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1/*
2 * OMAP4 SMP source file. It contains platform specific fucntions
3 * needed for the linux smp kernel.
4 *
5 * Copyright (C) 2009 Texas Instruments, Inc.
6 *
7 * Author:
8 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * Platform file needed for the OMAP4 SMP. This file is based on arm
11 * realview smp platform.
12 * * Copyright (c) 2002 ARM Limited.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18#include <linux/init.h>
19#include <linux/device.h>
20#include <linux/smp.h>
21#include <linux/io.h>
22
23#include <asm/cacheflush.h>
24#include <asm/hardware/gic.h>
25#include <asm/smp_scu.h>
26
27#include <mach/hardware.h>
28#include <mach/omap-secure.h>
29
30#include "iomap.h"
31#include "common.h"
32#include "clockdomain.h"
33
34/* SCU base address */
35static void __iomem *scu_base;
36
37static DEFINE_SPINLOCK(boot_lock);
38
39void __iomem *omap4_get_scu_base(void)
40{
41 return scu_base;
42}
43
44void __cpuinit platform_secondary_init(unsigned int cpu)
45{
46 /*
47 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
48 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
49 * init and for CPU1, a secure PPA API provided. CPU0 must be ON
50 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
51 * OMAP443X GP devices- SMP bit isn't accessible.
52 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
53 */
54 if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
55 omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
56 4, 0, 0, 0, 0, 0);
57
58 /*
59 * If any interrupts are already enabled for the primary
60 * core (e.g. timer irq), then they will not have been enabled
61 * for us: do so
62 */
63 gic_secondary_init(0);
64
65 /*
66 * Synchronise with the boot thread.
67 */
68 spin_lock(&boot_lock);
69 spin_unlock(&boot_lock);
70}
71
72int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
73{
74 static struct clockdomain *cpu1_clkdm;
75 static bool booted;
76 /*
77 * Set synchronisation state between this boot processor
78 * and the secondary one
79 */
80 spin_lock(&boot_lock);
81
82 /*
83 * Update the AuxCoreBoot0 with boot state for secondary core.
84 * omap_secondary_startup() routine will hold the secondary core till
85 * the AuxCoreBoot1 register is updated with cpu state
86 * A barrier is added to ensure that write buffer is drained
87 */
88 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
89 flush_cache_all();
90 smp_wmb();
91
92 if (!cpu1_clkdm)
93 cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
94
95 /*
96 * The SGI(Software Generated Interrupts) are not wakeup capable
97 * from low power states. This is known limitation on OMAP4 and
98 * needs to be worked around by using software forced clockdomain
99 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
100 * software force wakeup. The clockdomain is then put back to
101 * hardware supervised mode.
102 * More details can be found in OMAP4430 TRM - Version J
103 * Section :
104 * 4.3.4.2 Power States of CPU0 and CPU1
105 */
106 if (booted) {
107 clkdm_wakeup(cpu1_clkdm);
108 clkdm_allow_idle(cpu1_clkdm);
109 } else {
110 dsb_sev();
111 booted = true;
112 }
113
114 gic_raise_softirq(cpumask_of(cpu), 1);
115
116 /*
117 * Now the secondary core is starting up let it run its
118 * calibrations, then wait for it to finish
119 */
120 spin_unlock(&boot_lock);
121
122 return 0;
123}
124
125static void __init wakeup_secondary(void)
126{
127 /*
128 * Write the address of secondary startup routine into the
129 * AuxCoreBoot1 where ROM code will jump and start executing
130 * on secondary core once out of WFE
131 * A barrier is added to ensure that write buffer is drained
132 */
133 omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
134 smp_wmb();
135
136 /*
137 * Send a 'sev' to wake the secondary core from WFE.
138 * Drain the outstanding writes to memory
139 */
140 dsb_sev();
141 mb();
142}
143
144/*
145 * Initialise the CPU possible map early - this describes the CPUs
146 * which may be present or become present in the system.
147 */
148void __init smp_init_cpus(void)
149{
150 unsigned int i, ncores;
151
152 /*
153 * Currently we can't call ioremap here because
154 * SoC detection won't work until after init_early.
155 */
156 scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
157 BUG_ON(!scu_base);
158
159 ncores = scu_get_core_count(scu_base);
160
161 /* sanity check */
162 if (ncores > nr_cpu_ids) {
163 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
164 ncores, nr_cpu_ids);
165 ncores = nr_cpu_ids;
166 }
167
168 for (i = 0; i < ncores; i++)
169 set_cpu_possible(i, true);
170
171 set_smp_cross_call(gic_raise_softirq);
172}
173
174void __init platform_smp_prepare_cpus(unsigned int max_cpus)
175{
176
177 /*
178 * Initialise the SCU and wake up the secondary core using
179 * wakeup_secondary().
180 */
181 scu_enable(scu_base);
182 wakeup_secondary();
183}
1/*
2 * OMAP4 SMP source file. It contains platform specific fucntions
3 * needed for the linux smp kernel.
4 *
5 * Copyright (C) 2009 Texas Instruments, Inc.
6 *
7 * Author:
8 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * Platform file needed for the OMAP4 SMP. This file is based on arm
11 * realview smp platform.
12 * * Copyright (c) 2002 ARM Limited.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18#include <linux/init.h>
19#include <linux/device.h>
20#include <linux/smp.h>
21#include <linux/io.h>
22
23#include <asm/cacheflush.h>
24#include <asm/hardware/gic.h>
25#include <asm/smp_scu.h>
26#include <mach/hardware.h>
27#include <mach/omap4-common.h>
28
29/* SCU base address */
30static void __iomem *scu_base;
31
32static DEFINE_SPINLOCK(boot_lock);
33
34void __cpuinit platform_secondary_init(unsigned int cpu)
35{
36 /*
37 * If any interrupts are already enabled for the primary
38 * core (e.g. timer irq), then they will not have been enabled
39 * for us: do so
40 */
41 gic_secondary_init(0);
42
43 /*
44 * Synchronise with the boot thread.
45 */
46 spin_lock(&boot_lock);
47 spin_unlock(&boot_lock);
48}
49
50int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
51{
52 /*
53 * Set synchronisation state between this boot processor
54 * and the secondary one
55 */
56 spin_lock(&boot_lock);
57
58 /*
59 * Update the AuxCoreBoot0 with boot state for secondary core.
60 * omap_secondary_startup() routine will hold the secondary core till
61 * the AuxCoreBoot1 register is updated with cpu state
62 * A barrier is added to ensure that write buffer is drained
63 */
64 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
65 flush_cache_all();
66 smp_wmb();
67 gic_raise_softirq(cpumask_of(cpu), 1);
68
69 /*
70 * Now the secondary core is starting up let it run its
71 * calibrations, then wait for it to finish
72 */
73 spin_unlock(&boot_lock);
74
75 return 0;
76}
77
78static void __init wakeup_secondary(void)
79{
80 /*
81 * Write the address of secondary startup routine into the
82 * AuxCoreBoot1 where ROM code will jump and start executing
83 * on secondary core once out of WFE
84 * A barrier is added to ensure that write buffer is drained
85 */
86 omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
87 smp_wmb();
88
89 /*
90 * Send a 'sev' to wake the secondary core from WFE.
91 * Drain the outstanding writes to memory
92 */
93 dsb_sev();
94 mb();
95}
96
97/*
98 * Initialise the CPU possible map early - this describes the CPUs
99 * which may be present or become present in the system.
100 */
101void __init smp_init_cpus(void)
102{
103 unsigned int i, ncores;
104
105 /* Never released */
106 scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
107 BUG_ON(!scu_base);
108
109 ncores = scu_get_core_count(scu_base);
110
111 /* sanity check */
112 if (ncores > NR_CPUS) {
113 printk(KERN_WARNING
114 "OMAP4: no. of cores (%d) greater than configured "
115 "maximum of %d - clipping\n",
116 ncores, NR_CPUS);
117 ncores = NR_CPUS;
118 }
119
120 for (i = 0; i < ncores; i++)
121 set_cpu_possible(i, true);
122
123 set_smp_cross_call(gic_raise_softirq);
124}
125
126void __init platform_smp_prepare_cpus(unsigned int max_cpus)
127{
128
129 /*
130 * Initialise the SCU and wake up the secondary core using
131 * wakeup_secondary().
132 */
133 scu_enable(scu_base);
134 wakeup_secondary();
135}