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1/*
2 * Copyright 2008 Cavium Networks
3 *
4 * This file is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License, Version 2, as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/atomic.h>
14#include <mach/cns3xxx.h>
15#include <mach/pm.h>
16#include "core.h"
17
18void cns3xxx_pwr_clk_en(unsigned int block)
19{
20 u32 reg = __raw_readl(PM_CLK_GATE_REG);
21
22 reg |= (block & PM_CLK_GATE_REG_MASK);
23 __raw_writel(reg, PM_CLK_GATE_REG);
24}
25EXPORT_SYMBOL(cns3xxx_pwr_clk_en);
26
27void cns3xxx_pwr_clk_dis(unsigned int block)
28{
29 u32 reg = __raw_readl(PM_CLK_GATE_REG);
30
31 reg &= ~(block & PM_CLK_GATE_REG_MASK);
32 __raw_writel(reg, PM_CLK_GATE_REG);
33}
34EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);
35
36void cns3xxx_pwr_power_up(unsigned int block)
37{
38 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
39
40 reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
41 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
42
43 /* Wait for 300us for the PLL output clock locked. */
44 udelay(300);
45};
46EXPORT_SYMBOL(cns3xxx_pwr_power_up);
47
48void cns3xxx_pwr_power_down(unsigned int block)
49{
50 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
51
52 /* write '1' to power down */
53 reg |= (block & CNS3XXX_PWR_PLL_ALL);
54 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
55};
56EXPORT_SYMBOL(cns3xxx_pwr_power_down);
57
58static void cns3xxx_pwr_soft_rst_force(unsigned int block)
59{
60 u32 reg = __raw_readl(PM_SOFT_RST_REG);
61
62 /*
63 * bit 0, 28, 29 => program low to reset,
64 * the other else program low and then high
65 */
66 if (block & 0x30000001) {
67 reg &= ~(block & PM_SOFT_RST_REG_MASK);
68 } else {
69 reg &= ~(block & PM_SOFT_RST_REG_MASK);
70 __raw_writel(reg, PM_SOFT_RST_REG);
71 reg |= (block & PM_SOFT_RST_REG_MASK);
72 }
73
74 __raw_writel(reg, PM_SOFT_RST_REG);
75}
76EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force);
77
78void cns3xxx_pwr_soft_rst(unsigned int block)
79{
80 static unsigned int soft_reset;
81
82 if (soft_reset & block) {
83 /* SPI/I2C/GPIO use the same block, reset once. */
84 return;
85 } else {
86 soft_reset |= block;
87 }
88 cns3xxx_pwr_soft_rst_force(block);
89}
90EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
91
92void cns3xxx_restart(char mode, const char *cmd)
93{
94 /*
95 * To reset, we hit the on-board reset register
96 * in the system FPGA.
97 */
98 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
99}
100
101/*
102 * cns3xxx_cpu_clock - return CPU/L2 clock
103 * aclk: cpu clock/2
104 * hclk: cpu clock/4
105 * pclk: cpu clock/8
106 */
107int cns3xxx_cpu_clock(void)
108{
109 u32 reg = __raw_readl(PM_CLK_CTRL_REG);
110 int cpu;
111 int cpu_sel;
112 int div_sel;
113
114 cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
115 div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
116
117 cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
118
119 return cpu;
120}
121EXPORT_SYMBOL(cns3xxx_cpu_clock);
122
123atomic_t usb_pwr_ref = ATOMIC_INIT(0);
124EXPORT_SYMBOL(usb_pwr_ref);
1/*
2 * Copyright 2008 Cavium Networks
3 *
4 * This file is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License, Version 2, as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/init.h>
10#include <linux/module.h>
11#include <linux/io.h>
12#include <linux/delay.h>
13#include <linux/atomic.h>
14#include <mach/system.h>
15#include <mach/cns3xxx.h>
16#include <mach/pm.h>
17
18void cns3xxx_pwr_clk_en(unsigned int block)
19{
20 u32 reg = __raw_readl(PM_CLK_GATE_REG);
21
22 reg |= (block & PM_CLK_GATE_REG_MASK);
23 __raw_writel(reg, PM_CLK_GATE_REG);
24}
25EXPORT_SYMBOL(cns3xxx_pwr_clk_en);
26
27void cns3xxx_pwr_clk_dis(unsigned int block)
28{
29 u32 reg = __raw_readl(PM_CLK_GATE_REG);
30
31 reg &= ~(block & PM_CLK_GATE_REG_MASK);
32 __raw_writel(reg, PM_CLK_GATE_REG);
33}
34EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);
35
36void cns3xxx_pwr_power_up(unsigned int block)
37{
38 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
39
40 reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
41 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
42
43 /* Wait for 300us for the PLL output clock locked. */
44 udelay(300);
45};
46EXPORT_SYMBOL(cns3xxx_pwr_power_up);
47
48void cns3xxx_pwr_power_down(unsigned int block)
49{
50 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
51
52 /* write '1' to power down */
53 reg |= (block & CNS3XXX_PWR_PLL_ALL);
54 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
55};
56EXPORT_SYMBOL(cns3xxx_pwr_power_down);
57
58static void cns3xxx_pwr_soft_rst_force(unsigned int block)
59{
60 u32 reg = __raw_readl(PM_SOFT_RST_REG);
61
62 /*
63 * bit 0, 28, 29 => program low to reset,
64 * the other else program low and then high
65 */
66 if (block & 0x30000001) {
67 reg &= ~(block & PM_SOFT_RST_REG_MASK);
68 } else {
69 reg &= ~(block & PM_SOFT_RST_REG_MASK);
70 __raw_writel(reg, PM_SOFT_RST_REG);
71 reg |= (block & PM_SOFT_RST_REG_MASK);
72 }
73
74 __raw_writel(reg, PM_SOFT_RST_REG);
75}
76EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force);
77
78void cns3xxx_pwr_soft_rst(unsigned int block)
79{
80 static unsigned int soft_reset;
81
82 if (soft_reset & block) {
83 /* SPI/I2C/GPIO use the same block, reset once. */
84 return;
85 } else {
86 soft_reset |= block;
87 }
88 cns3xxx_pwr_soft_rst_force(block);
89}
90EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
91
92void arch_reset(char mode, const char *cmd)
93{
94 /*
95 * To reset, we hit the on-board reset register
96 * in the system FPGA.
97 */
98 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
99}
100
101/*
102 * cns3xxx_cpu_clock - return CPU/L2 clock
103 * aclk: cpu clock/2
104 * hclk: cpu clock/4
105 * pclk: cpu clock/8
106 */
107int cns3xxx_cpu_clock(void)
108{
109 u32 reg = __raw_readl(PM_CLK_CTRL_REG);
110 int cpu;
111 int cpu_sel;
112 int div_sel;
113
114 cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
115 div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
116
117 cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
118
119 return cpu;
120}
121EXPORT_SYMBOL(cns3xxx_cpu_clock);
122
123atomic_t usb_pwr_ref = ATOMIC_INIT(0);
124EXPORT_SYMBOL(usb_pwr_ref);