Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 | /* * drivers/irqchip/irq-crossbar.c * * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com * Author: Sricharan R <r.sricharan@ti.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * */ #include <linux/err.h> #include <linux/io.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/slab.h> #include <linux/irqchip/arm-gic.h> #define IRQ_FREE -1 #define GIC_IRQ_START 32 /* * @int_max: maximum number of supported interrupts * @irq_map: array of interrupts to crossbar number mapping * @crossbar_base: crossbar base address * @register_offsets: offsets for each irq number */ struct crossbar_device { uint int_max; uint *irq_map; void __iomem *crossbar_base; int *register_offsets; void (*write) (int, int); }; static struct crossbar_device *cb; static inline void crossbar_writel(int irq_no, int cb_no) { writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); } static inline void crossbar_writew(int irq_no, int cb_no) { writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); } static inline void crossbar_writeb(int irq_no, int cb_no) { writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); } static inline int allocate_free_irq(int cb_no) { int i; for (i = 0; i < cb->int_max; i++) { if (cb->irq_map[i] == IRQ_FREE) { cb->irq_map[i] = cb_no; return i; } } return -ENODEV; } static int crossbar_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]); return 0; } static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq) { irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq; if (hw > GIC_IRQ_START) cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE; } static int crossbar_domain_xlate(struct irq_domain *d, struct device_node *controller, const u32 *intspec, unsigned int intsize, unsigned long *out_hwirq, unsigned int *out_type) { unsigned long ret; ret = allocate_free_irq(intspec[1]); if (IS_ERR_VALUE(ret)) return ret; *out_hwirq = ret + GIC_IRQ_START; return 0; } const struct irq_domain_ops routable_irq_domain_ops = { .map = crossbar_domain_map, .unmap = crossbar_domain_unmap, .xlate = crossbar_domain_xlate }; static int __init crossbar_of_init(struct device_node *node) { int i, size, max, reserved = 0, entry; const __be32 *irqsr; cb = kzalloc(sizeof(*cb), GFP_KERNEL); if (!cb) return -ENOMEM; cb->crossbar_base = of_iomap(node, 0); if (!cb->crossbar_base) goto err1; of_property_read_u32(node, "ti,max-irqs", &max); cb->irq_map = kzalloc(max * sizeof(int), GFP_KERNEL); if (!cb->irq_map) goto err2; cb->int_max = max; for (i = 0; i < max; i++) cb->irq_map[i] = IRQ_FREE; /* Get and mark reserved irqs */ irqsr = of_get_property(node, "ti,irqs-reserved", &size); if (irqsr) { size /= sizeof(__be32); for (i = 0; i < size; i++) { of_property_read_u32_index(node, "ti,irqs-reserved", i, &entry); if (entry > max) { pr_err("Invalid reserved entry\n"); goto err3; } cb->irq_map[entry] = 0; } } cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL); if (!cb->register_offsets) goto err3; of_property_read_u32(node, "ti,reg-size", &size); switch (size) { case 1: cb->write = crossbar_writeb; break; case 2: cb->write = crossbar_writew; break; case 4: cb->write = crossbar_writel; break; default: pr_err("Invalid reg-size property\n"); goto err4; break; } /* * Register offsets are not linear because of the * reserved irqs. so find and store the offsets once. */ for (i = 0; i < max; i++) { if (!cb->irq_map[i]) continue; cb->register_offsets[i] = reserved; reserved += size; } register_routable_domain_ops(&routable_irq_domain_ops); return 0; err4: kfree(cb->register_offsets); err3: kfree(cb->irq_map); err2: iounmap(cb->crossbar_base); err1: kfree(cb); return -ENOMEM; } static const struct of_device_id crossbar_match[] __initconst = { { .compatible = "ti,irq-crossbar" }, {} }; int __init irqcrossbar_init(void) { struct device_node *np; np = of_find_matching_node(NULL, crossbar_match); if (!np) return -ENODEV; crossbar_of_init(np); return 0; } |