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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 | /* * Copyright 2013 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Ben Skeggs */ #include "nvc0.h" /******************************************************************************* * Perfmon object classes ******************************************************************************/ /******************************************************************************* * PPM context ******************************************************************************/ /******************************************************************************* * PPM engine/subdev functions ******************************************************************************/ static const struct nouveau_specdom nvc0_perfmon_hub[] = { {} }; static const struct nouveau_specdom nvc0_perfmon_gpc[] = { {} }; static const struct nouveau_specdom nvc0_perfmon_part[] = { {} }; static void nvc0_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, struct nouveau_perfctr *ctr) { struct nvc0_perfmon_priv *priv = (void *)ppm; struct nvc0_perfmon_cntr *cntr = (void *)ctr; u32 log = ctr->logic_op; u32 src = 0x00000000; int i; for (i = 0; i < 4 && ctr->signal[i]; i++) src |= (ctr->signal[i] - dom->signal) << (i * 8); nv_wr32(priv, dom->addr + 0x09c, 0x00040002); nv_wr32(priv, dom->addr + 0x100, 0x00000000); nv_wr32(priv, dom->addr + 0x040 + (cntr->base.slot * 0x08), src); nv_wr32(priv, dom->addr + 0x044 + (cntr->base.slot * 0x08), log); } static void nvc0_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, struct nouveau_perfctr *ctr) { struct nvc0_perfmon_priv *priv = (void *)ppm; struct nvc0_perfmon_cntr *cntr = (void *)ctr; switch (cntr->base.slot) { case 0: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x08c); break; case 1: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x088); break; case 2: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x080); break; case 3: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x090); break; } cntr->base.clk = nv_rd32(priv, dom->addr + 0x070); } static void nvc0_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom) { struct nvc0_perfmon_priv *priv = (void *)ppm; nv_wr32(priv, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27); nv_wr32(priv, dom->addr + 0x0ec, 0x00000011); } const struct nouveau_funcdom nvc0_perfctr_func = { .init = nvc0_perfctr_init, .read = nvc0_perfctr_read, .next = nvc0_perfctr_next, }; int nvc0_perfmon_fini(struct nouveau_object *object, bool suspend) { struct nvc0_perfmon_priv *priv = (void *)object; nv_mask(priv, 0x000200, 0x10000000, 0x00000000); nv_mask(priv, 0x000200, 0x10000000, 0x10000000); return nouveau_perfmon_fini(&priv->base, suspend); } static int nvc0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) { struct nvc0_perfmon_priv *priv; u32 mask; int ret; ret = nouveau_perfmon_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, nvc0_perfmon_pwr); if (ret) return ret; /* HUB */ ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200, nvc0_perfmon_hub); if (ret) return ret; /* GPC */ mask = (1 << nv_rd32(priv, 0x022430)) - 1; mask &= ~nv_rd32(priv, 0x022504); mask &= ~nv_rd32(priv, 0x022584); ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000, 0x1000, 0x200, nvc0_perfmon_gpc); if (ret) return ret; /* PART */ mask = (1 << nv_rd32(priv, 0x022438)) - 1; mask &= ~nv_rd32(priv, 0x022548); mask &= ~nv_rd32(priv, 0x0225c8); ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000, 0x1000, 0x200, nvc0_perfmon_part); if (ret) return ret; nv_engine(priv)->cclass = &nouveau_perfmon_cclass; nv_engine(priv)->sclass = nouveau_perfmon_sclass; priv->base.last = 7; return 0; } struct nouveau_oclass nvc0_perfmon_oclass = { .handle = NV_ENGINE(PERFMON, 0xc0), .ofuncs = &(struct nouveau_ofuncs) { .ctor = nvc0_perfmon_ctor, .dtor = _nouveau_perfmon_dtor, .init = _nouveau_perfmon_init, .fini = nvc0_perfmon_fini, }, }; |