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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 | /* * debugfs ops for the L1 cache * * Copyright (C) 2006 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ #include <linux/init.h> #include <linux/module.h> #include <linux/debugfs.h> #include <linux/seq_file.h> #include <asm/processor.h> #include <asm/uaccess.h> #include <asm/cache.h> #include <asm/io.h> enum cache_type { CACHE_TYPE_ICACHE, CACHE_TYPE_DCACHE, CACHE_TYPE_UNIFIED, }; static int cache_seq_show(struct seq_file *file, void *iter) { unsigned int cache_type = (unsigned int)file->private; struct cache_info *cache; unsigned int waysize, way; unsigned long ccr; unsigned long addrstart = 0; /* * Go uncached immediately so we don't skew the results any * more than we already are.. */ jump_to_uncached(); ccr = __raw_readl(SH_CCR); if ((ccr & CCR_CACHE_ENABLE) == 0) { back_to_cached(); seq_printf(file, "disabled\n"); return 0; } if (cache_type == CACHE_TYPE_DCACHE) { addrstart = CACHE_OC_ADDRESS_ARRAY; cache = ¤t_cpu_data.dcache; } else { addrstart = CACHE_IC_ADDRESS_ARRAY; cache = ¤t_cpu_data.icache; } waysize = cache->sets; /* * If the OC is already in RAM mode, we only have * half of the entries to consider.. */ if ((ccr & CCR_CACHE_ORA) && cache_type == CACHE_TYPE_DCACHE) waysize >>= 1; waysize <<= cache->entry_shift; for (way = 0; way < cache->ways; way++) { unsigned long addr; unsigned int line; seq_printf(file, "-----------------------------------------\n"); seq_printf(file, "Way %d\n", way); seq_printf(file, "-----------------------------------------\n"); for (addr = addrstart, line = 0; addr < addrstart + waysize; addr += cache->linesz, line++) { unsigned long data = __raw_readl(addr); /* Check the V bit, ignore invalid cachelines */ if ((data & 1) == 0) continue; /* U: Dirty, cache tag is 10 bits up */ seq_printf(file, "%3d: %c 0x%lx\n", line, data & 2 ? 'U' : ' ', data & 0x1ffffc00); } addrstart += cache->way_incr; } back_to_cached(); return 0; } static int cache_debugfs_open(struct inode *inode, struct file *file) { return single_open(file, cache_seq_show, inode->i_private); } static const struct file_operations cache_debugfs_fops = { .owner = THIS_MODULE, .open = cache_debugfs_open, .read = seq_read, .llseek = seq_lseek, .release = single_release, }; static int __init cache_debugfs_init(void) { struct dentry *dcache_dentry, *icache_dentry; dcache_dentry = debugfs_create_file("dcache", S_IRUSR, arch_debugfs_dir, (unsigned int *)CACHE_TYPE_DCACHE, &cache_debugfs_fops); if (!dcache_dentry) return -ENOMEM; icache_dentry = debugfs_create_file("icache", S_IRUSR, arch_debugfs_dir, (unsigned int *)CACHE_TYPE_ICACHE, &cache_debugfs_fops); if (!icache_dentry) { debugfs_remove(dcache_dentry); return -ENOMEM; } return 0; } module_init(cache_debugfs_init); MODULE_LICENSE("GPL v2"); |