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1/* linux/arch/arm/mach-s5p64x0/include/mach/irqs.h
2 *
3 * Copyright 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - IRQ definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_IRQS_H __FILE__
15
16#include <plat/irqs.h>
17
18/* VIC0 */
19
20#define IRQ_EINT0_3 S5P_IRQ_VIC0(0)
21#define IRQ_EINT4_11 S5P_IRQ_VIC0(1)
22#define IRQ_RTC_TIC S5P_IRQ_VIC0(2)
23#define IRQ_IIS1 S5P_IRQ_VIC0(3) /* for only S5P6450 */
24#define IRQ_IIS2 S5P_IRQ_VIC0(4) /* for only S5P6450 */
25#define IRQ_IIC1 S5P_IRQ_VIC0(5)
26#define IRQ_I2SV40 S5P_IRQ_VIC0(6)
27#define IRQ_GPS S5P_IRQ_VIC0(7) /* for only S5P6450 */
28
29#define IRQ_2D S5P_IRQ_VIC0(11)
30#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23)
31#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24)
32#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(25)
33#define IRQ_WDT S5P_IRQ_VIC0(26)
34#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(27)
35#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(28)
36#define IRQ_DISPCON0 S5P_IRQ_VIC0(29)
37#define IRQ_DISPCON1 S5P_IRQ_VIC0(30)
38#define IRQ_DISPCON2 S5P_IRQ_VIC0(31)
39
40/* VIC1 */
41
42#define IRQ_EINT12_15 S5P_IRQ_VIC1(0)
43#define IRQ_PCM0 S5P_IRQ_VIC1(2)
44#define IRQ_PCM1 S5P_IRQ_VIC1(3) /* for only S5P6450 */
45#define IRQ_PCM2 S5P_IRQ_VIC1(4) /* for only S5P6450 */
46#define IRQ_UART0 S5P_IRQ_VIC1(5)
47#define IRQ_UART1 S5P_IRQ_VIC1(6)
48#define IRQ_UART2 S5P_IRQ_VIC1(7)
49#define IRQ_UART3 S5P_IRQ_VIC1(8)
50#define IRQ_DMA0 S5P_IRQ_VIC1(9)
51#define IRQ_UART4 S5P_IRQ_VIC1(10) /* S5P6450 */
52#define IRQ_UART5 S5P_IRQ_VIC1(11) /* S5P6450 */
53#define IRQ_NFC S5P_IRQ_VIC1(13)
54#define IRQ_USI S5P_IRQ_VIC1(15) /* S5P6450 */
55#define IRQ_SPI0 S5P_IRQ_VIC1(16)
56#define IRQ_SPI1 S5P_IRQ_VIC1(17)
57#define IRQ_HSMMC2 S5P_IRQ_VIC1(17) /* Shared */
58#define IRQ_IIC S5P_IRQ_VIC1(18)
59#define IRQ_DISPCON3 S5P_IRQ_VIC1(19)
60#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21)
61#define IRQ_PMU S5P_IRQ_VIC1(23) /* S5P6440 */
62#define IRQ_HSMMC0 S5P_IRQ_VIC1(24)
63#define IRQ_HSMMC1 S5P_IRQ_VIC1(25)
64#define IRQ_OTG S5P_IRQ_VIC1(26)
65#define IRQ_DSI S5P_IRQ_VIC1(27)
66#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28)
67#define IRQ_TSI S5P_IRQ_VIC1(29)
68#define IRQ_PENDN S5P_IRQ_VIC1(30)
69#define IRQ_TC IRQ_PENDN
70#define IRQ_ADC S5P_IRQ_VIC1(31)
71
72/* UART interrupts, S5P6450 has 5 UARTs */
73#define IRQ_S5P_UART_BASE4 (96)
74#define IRQ_S5P_UART_BASE5 (100)
75
76#define IRQ_S5P_UART_RX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_RXD)
77#define IRQ_S5P_UART_TX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_TXD)
78#define IRQ_S5P_UART_ERR4 (IRQ_S5P_UART_BASE4 + UART_IRQ_ERR)
79
80#define IRQ_S5P_UART_RX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_RXD)
81#define IRQ_S5P_UART_TX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_TXD)
82#define IRQ_S5P_UART_ERR5 (IRQ_S5P_UART_BASE5 + UART_IRQ_ERR)
83
84/* S3C compatibilty defines */
85#define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4
86#define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5
87
88#define IRQ_I2S0 IRQ_I2SV40
89
90#define IRQ_LCD_FIFO IRQ_DISPCON0
91#define IRQ_LCD_VSYNC IRQ_DISPCON1
92#define IRQ_LCD_SYSTEM IRQ_DISPCON2
93
94/* S5P6450 EINT feature will be added */
95
96/*
97 * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
98 * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
99 * after the pair of VICs.
100 */
101
102#define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6)
103
104#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE)
105
106#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE)
107/*
108 * S5P6440 has 0-15 external interrupts in group 0. Only these can be used
109 * to wake up from sleep. If request is beyond this range, by mistake, a large
110 * return value for an irq number should be indication of something amiss.
111 */
112#define S5P_EINT_BASE2 (0xf0000000)
113
114/*
115 * Next the external interrupt groups. These are similar to the IRQ_EINT(x)
116 * that they are sourced from the GPIO pins but with a different scheme for
117 * priority and source indication.
118 *
119 * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
120 * interrupts, but for historical reasons they are kept apart from these
121 * next interrupts.
122 *
123 * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
124 * machine specific support files.
125 */
126
127/* Actually, #6 and #7 are missing in the EINT_GROUP1 */
128#define IRQ_EINT_GROUP1_NR (15)
129#define IRQ_EINT_GROUP2_NR (8)
130#define IRQ_EINT_GROUP5_NR (7)
131#define IRQ_EINT_GROUP6_NR (10)
132/* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */
133#define IRQ_EINT_GROUP8_NR (11)
134
135#define IRQ_EINT_GROUP_BASE S5P_EINT(16)
136#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0)
137#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
138#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
139#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
140#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
141
142#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x))
143
144/* Set the default NR_IRQS */
145
146#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
147
148#endif /* __ASM_ARCH_IRQS_H */