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1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/pci.h>
24#include <linux/irq.h>
25#include <linux/log2.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/slab.h>
29#include <linux/dmi.h>
30#include <linux/dma-mapping.h>
31
32#include "xhci.h"
33#include "xhci-trace.h"
34
35#define DRIVER_AUTHOR "Sarah Sharp"
36#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
37
38/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
39static int link_quirk;
40module_param(link_quirk, int, S_IRUGO | S_IWUSR);
41MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
42
43static unsigned int quirks;
44module_param(quirks, uint, S_IRUGO);
45MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
46
47/* TODO: copied from ehci-hcd.c - can this be refactored? */
48/*
49 * xhci_handshake - spin reading hc until handshake completes or fails
50 * @ptr: address of hc register to be read
51 * @mask: bits to look at in result of read
52 * @done: value of those bits when handshake succeeds
53 * @usec: timeout in microseconds
54 *
55 * Returns negative errno, or zero on success
56 *
57 * Success happens when the "mask" bits have the specified value (hardware
58 * handshake done). There are two failure modes: "usec" have passed (major
59 * hardware flakeout), or the register reads as all-ones (hardware removed).
60 */
61int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
62 u32 mask, u32 done, int usec)
63{
64 u32 result;
65
66 do {
67 result = readl(ptr);
68 if (result == ~(u32)0) /* card removed */
69 return -ENODEV;
70 result &= mask;
71 if (result == done)
72 return 0;
73 udelay(1);
74 usec--;
75 } while (usec > 0);
76 return -ETIMEDOUT;
77}
78
79/*
80 * Disable interrupts and begin the xHCI halting process.
81 */
82void xhci_quiesce(struct xhci_hcd *xhci)
83{
84 u32 halted;
85 u32 cmd;
86 u32 mask;
87
88 mask = ~(XHCI_IRQS);
89 halted = readl(&xhci->op_regs->status) & STS_HALT;
90 if (!halted)
91 mask &= ~CMD_RUN;
92
93 cmd = readl(&xhci->op_regs->command);
94 cmd &= mask;
95 writel(cmd, &xhci->op_regs->command);
96}
97
98/*
99 * Force HC into halt state.
100 *
101 * Disable any IRQs and clear the run/stop bit.
102 * HC will complete any current and actively pipelined transactions, and
103 * should halt within 16 ms of the run/stop bit being cleared.
104 * Read HC Halted bit in the status register to see when the HC is finished.
105 */
106int xhci_halt(struct xhci_hcd *xhci)
107{
108 int ret;
109 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
110 xhci_quiesce(xhci);
111
112 ret = xhci_handshake(xhci, &xhci->op_regs->status,
113 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
114 if (!ret) {
115 xhci->xhc_state |= XHCI_STATE_HALTED;
116 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
117 } else
118 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
119 XHCI_MAX_HALT_USEC);
120 return ret;
121}
122
123/*
124 * Set the run bit and wait for the host to be running.
125 */
126static int xhci_start(struct xhci_hcd *xhci)
127{
128 u32 temp;
129 int ret;
130
131 temp = readl(&xhci->op_regs->command);
132 temp |= (CMD_RUN);
133 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
134 temp);
135 writel(temp, &xhci->op_regs->command);
136
137 /*
138 * Wait for the HCHalted Status bit to be 0 to indicate the host is
139 * running.
140 */
141 ret = xhci_handshake(xhci, &xhci->op_regs->status,
142 STS_HALT, 0, XHCI_MAX_HALT_USEC);
143 if (ret == -ETIMEDOUT)
144 xhci_err(xhci, "Host took too long to start, "
145 "waited %u microseconds.\n",
146 XHCI_MAX_HALT_USEC);
147 if (!ret)
148 xhci->xhc_state &= ~XHCI_STATE_HALTED;
149 return ret;
150}
151
152/*
153 * Reset a halted HC.
154 *
155 * This resets pipelines, timers, counters, state machines, etc.
156 * Transactions will be terminated immediately, and operational registers
157 * will be set to their defaults.
158 */
159int xhci_reset(struct xhci_hcd *xhci)
160{
161 u32 command;
162 u32 state;
163 int ret, i;
164
165 state = readl(&xhci->op_regs->status);
166 if ((state & STS_HALT) == 0) {
167 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
168 return 0;
169 }
170
171 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
172 command = readl(&xhci->op_regs->command);
173 command |= CMD_RESET;
174 writel(command, &xhci->op_regs->command);
175
176 ret = xhci_handshake(xhci, &xhci->op_regs->command,
177 CMD_RESET, 0, 10 * 1000 * 1000);
178 if (ret)
179 return ret;
180
181 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
182 "Wait for controller to be ready for doorbell rings");
183 /*
184 * xHCI cannot write to any doorbells or operational registers other
185 * than status until the "Controller Not Ready" flag is cleared.
186 */
187 ret = xhci_handshake(xhci, &xhci->op_regs->status,
188 STS_CNR, 0, 10 * 1000 * 1000);
189
190 for (i = 0; i < 2; ++i) {
191 xhci->bus_state[i].port_c_suspend = 0;
192 xhci->bus_state[i].suspended_ports = 0;
193 xhci->bus_state[i].resuming_ports = 0;
194 }
195
196 return ret;
197}
198
199#ifdef CONFIG_PCI
200static int xhci_free_msi(struct xhci_hcd *xhci)
201{
202 int i;
203
204 if (!xhci->msix_entries)
205 return -EINVAL;
206
207 for (i = 0; i < xhci->msix_count; i++)
208 if (xhci->msix_entries[i].vector)
209 free_irq(xhci->msix_entries[i].vector,
210 xhci_to_hcd(xhci));
211 return 0;
212}
213
214/*
215 * Set up MSI
216 */
217static int xhci_setup_msi(struct xhci_hcd *xhci)
218{
219 int ret;
220 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
221
222 ret = pci_enable_msi(pdev);
223 if (ret) {
224 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
225 "failed to allocate MSI entry");
226 return ret;
227 }
228
229 ret = request_irq(pdev->irq, xhci_msi_irq,
230 0, "xhci_hcd", xhci_to_hcd(xhci));
231 if (ret) {
232 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
233 "disable MSI interrupt");
234 pci_disable_msi(pdev);
235 }
236
237 return ret;
238}
239
240/*
241 * Free IRQs
242 * free all IRQs request
243 */
244static void xhci_free_irq(struct xhci_hcd *xhci)
245{
246 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
247 int ret;
248
249 /* return if using legacy interrupt */
250 if (xhci_to_hcd(xhci)->irq > 0)
251 return;
252
253 ret = xhci_free_msi(xhci);
254 if (!ret)
255 return;
256 if (pdev->irq > 0)
257 free_irq(pdev->irq, xhci_to_hcd(xhci));
258
259 return;
260}
261
262/*
263 * Set up MSI-X
264 */
265static int xhci_setup_msix(struct xhci_hcd *xhci)
266{
267 int i, ret = 0;
268 struct usb_hcd *hcd = xhci_to_hcd(xhci);
269 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
270
271 /*
272 * calculate number of msi-x vectors supported.
273 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
274 * with max number of interrupters based on the xhci HCSPARAMS1.
275 * - num_online_cpus: maximum msi-x vectors per CPUs core.
276 * Add additional 1 vector to ensure always available interrupt.
277 */
278 xhci->msix_count = min(num_online_cpus() + 1,
279 HCS_MAX_INTRS(xhci->hcs_params1));
280
281 xhci->msix_entries =
282 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
283 GFP_KERNEL);
284 if (!xhci->msix_entries) {
285 xhci_err(xhci, "Failed to allocate MSI-X entries\n");
286 return -ENOMEM;
287 }
288
289 for (i = 0; i < xhci->msix_count; i++) {
290 xhci->msix_entries[i].entry = i;
291 xhci->msix_entries[i].vector = 0;
292 }
293
294 ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
295 if (ret) {
296 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
297 "Failed to enable MSI-X");
298 goto free_entries;
299 }
300
301 for (i = 0; i < xhci->msix_count; i++) {
302 ret = request_irq(xhci->msix_entries[i].vector,
303 xhci_msi_irq,
304 0, "xhci_hcd", xhci_to_hcd(xhci));
305 if (ret)
306 goto disable_msix;
307 }
308
309 hcd->msix_enabled = 1;
310 return ret;
311
312disable_msix:
313 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
314 xhci_free_irq(xhci);
315 pci_disable_msix(pdev);
316free_entries:
317 kfree(xhci->msix_entries);
318 xhci->msix_entries = NULL;
319 return ret;
320}
321
322/* Free any IRQs and disable MSI-X */
323static void xhci_cleanup_msix(struct xhci_hcd *xhci)
324{
325 struct usb_hcd *hcd = xhci_to_hcd(xhci);
326 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
327
328 if (xhci->quirks & XHCI_PLAT)
329 return;
330
331 xhci_free_irq(xhci);
332
333 if (xhci->msix_entries) {
334 pci_disable_msix(pdev);
335 kfree(xhci->msix_entries);
336 xhci->msix_entries = NULL;
337 } else {
338 pci_disable_msi(pdev);
339 }
340
341 hcd->msix_enabled = 0;
342 return;
343}
344
345static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
346{
347 int i;
348
349 if (xhci->msix_entries) {
350 for (i = 0; i < xhci->msix_count; i++)
351 synchronize_irq(xhci->msix_entries[i].vector);
352 }
353}
354
355static int xhci_try_enable_msi(struct usb_hcd *hcd)
356{
357 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
358 struct pci_dev *pdev;
359 int ret;
360
361 /* The xhci platform device has set up IRQs through usb_add_hcd. */
362 if (xhci->quirks & XHCI_PLAT)
363 return 0;
364
365 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
366 /*
367 * Some Fresco Logic host controllers advertise MSI, but fail to
368 * generate interrupts. Don't even try to enable MSI.
369 */
370 if (xhci->quirks & XHCI_BROKEN_MSI)
371 goto legacy_irq;
372
373 /* unregister the legacy interrupt */
374 if (hcd->irq)
375 free_irq(hcd->irq, hcd);
376 hcd->irq = 0;
377
378 ret = xhci_setup_msix(xhci);
379 if (ret)
380 /* fall back to msi*/
381 ret = xhci_setup_msi(xhci);
382
383 if (!ret)
384 /* hcd->irq is 0, we have MSI */
385 return 0;
386
387 if (!pdev->irq) {
388 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
389 return -EINVAL;
390 }
391
392 legacy_irq:
393 if (!strlen(hcd->irq_descr))
394 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
395 hcd->driver->description, hcd->self.busnum);
396
397 /* fall back to legacy interrupt*/
398 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
399 hcd->irq_descr, hcd);
400 if (ret) {
401 xhci_err(xhci, "request interrupt %d failed\n",
402 pdev->irq);
403 return ret;
404 }
405 hcd->irq = pdev->irq;
406 return 0;
407}
408
409#else
410
411static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
412{
413 return 0;
414}
415
416static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
417{
418}
419
420static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
421{
422}
423
424#endif
425
426static void compliance_mode_recovery(unsigned long arg)
427{
428 struct xhci_hcd *xhci;
429 struct usb_hcd *hcd;
430 u32 temp;
431 int i;
432
433 xhci = (struct xhci_hcd *)arg;
434
435 for (i = 0; i < xhci->num_usb3_ports; i++) {
436 temp = readl(xhci->usb3_ports[i]);
437 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
438 /*
439 * Compliance Mode Detected. Letting USB Core
440 * handle the Warm Reset
441 */
442 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
443 "Compliance mode detected->port %d",
444 i + 1);
445 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
446 "Attempting compliance mode recovery");
447 hcd = xhci->shared_hcd;
448
449 if (hcd->state == HC_STATE_SUSPENDED)
450 usb_hcd_resume_root_hub(hcd);
451
452 usb_hcd_poll_rh_status(hcd);
453 }
454 }
455
456 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
457 mod_timer(&xhci->comp_mode_recovery_timer,
458 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
459}
460
461/*
462 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
463 * that causes ports behind that hardware to enter compliance mode sometimes.
464 * The quirk creates a timer that polls every 2 seconds the link state of
465 * each host controller's port and recovers it by issuing a Warm reset
466 * if Compliance mode is detected, otherwise the port will become "dead" (no
467 * device connections or disconnections will be detected anymore). Becasue no
468 * status event is generated when entering compliance mode (per xhci spec),
469 * this quirk is needed on systems that have the failing hardware installed.
470 */
471static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
472{
473 xhci->port_status_u0 = 0;
474 init_timer(&xhci->comp_mode_recovery_timer);
475
476 xhci->comp_mode_recovery_timer.data = (unsigned long) xhci;
477 xhci->comp_mode_recovery_timer.function = compliance_mode_recovery;
478 xhci->comp_mode_recovery_timer.expires = jiffies +
479 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
480
481 set_timer_slack(&xhci->comp_mode_recovery_timer,
482 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
483 add_timer(&xhci->comp_mode_recovery_timer);
484 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
485 "Compliance mode recovery timer initialized");
486}
487
488/*
489 * This function identifies the systems that have installed the SN65LVPE502CP
490 * USB3.0 re-driver and that need the Compliance Mode Quirk.
491 * Systems:
492 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
493 */
494bool xhci_compliance_mode_recovery_timer_quirk_check(void)
495{
496 const char *dmi_product_name, *dmi_sys_vendor;
497
498 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
499 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
500 if (!dmi_product_name || !dmi_sys_vendor)
501 return false;
502
503 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
504 return false;
505
506 if (strstr(dmi_product_name, "Z420") ||
507 strstr(dmi_product_name, "Z620") ||
508 strstr(dmi_product_name, "Z820") ||
509 strstr(dmi_product_name, "Z1 Workstation"))
510 return true;
511
512 return false;
513}
514
515static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
516{
517 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
518}
519
520
521/*
522 * Initialize memory for HCD and xHC (one-time init).
523 *
524 * Program the PAGESIZE register, initialize the device context array, create
525 * device contexts (?), set up a command ring segment (or two?), create event
526 * ring (one for now).
527 */
528int xhci_init(struct usb_hcd *hcd)
529{
530 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
531 int retval = 0;
532
533 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
534 spin_lock_init(&xhci->lock);
535 if (xhci->hci_version == 0x95 && link_quirk) {
536 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
537 "QUIRK: Not clearing Link TRB chain bits.");
538 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
539 } else {
540 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
541 "xHCI doesn't need link TRB QUIRK");
542 }
543 retval = xhci_mem_init(xhci, GFP_KERNEL);
544 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
545
546 /* Initializing Compliance Mode Recovery Data If Needed */
547 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
548 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
549 compliance_mode_recovery_timer_init(xhci);
550 }
551
552 return retval;
553}
554
555/*-------------------------------------------------------------------------*/
556
557
558static int xhci_run_finished(struct xhci_hcd *xhci)
559{
560 if (xhci_start(xhci)) {
561 xhci_halt(xhci);
562 return -ENODEV;
563 }
564 xhci->shared_hcd->state = HC_STATE_RUNNING;
565 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
566
567 if (xhci->quirks & XHCI_NEC_HOST)
568 xhci_ring_cmd_db(xhci);
569
570 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
571 "Finished xhci_run for USB3 roothub");
572 return 0;
573}
574
575/*
576 * Start the HC after it was halted.
577 *
578 * This function is called by the USB core when the HC driver is added.
579 * Its opposite is xhci_stop().
580 *
581 * xhci_init() must be called once before this function can be called.
582 * Reset the HC, enable device slot contexts, program DCBAAP, and
583 * set command ring pointer and event ring pointer.
584 *
585 * Setup MSI-X vectors and enable interrupts.
586 */
587int xhci_run(struct usb_hcd *hcd)
588{
589 u32 temp;
590 u64 temp_64;
591 int ret;
592 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
593
594 /* Start the xHCI host controller running only after the USB 2.0 roothub
595 * is setup.
596 */
597
598 hcd->uses_new_polling = 1;
599 if (!usb_hcd_is_primary_hcd(hcd))
600 return xhci_run_finished(xhci);
601
602 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
603
604 ret = xhci_try_enable_msi(hcd);
605 if (ret)
606 return ret;
607
608 xhci_dbg(xhci, "Command ring memory map follows:\n");
609 xhci_debug_ring(xhci, xhci->cmd_ring);
610 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
611 xhci_dbg_cmd_ptrs(xhci);
612
613 xhci_dbg(xhci, "ERST memory map follows:\n");
614 xhci_dbg_erst(xhci, &xhci->erst);
615 xhci_dbg(xhci, "Event ring:\n");
616 xhci_debug_ring(xhci, xhci->event_ring);
617 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
618 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
619 temp_64 &= ~ERST_PTR_MASK;
620 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
621 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
622
623 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
624 "// Set the interrupt modulation register");
625 temp = readl(&xhci->ir_set->irq_control);
626 temp &= ~ER_IRQ_INTERVAL_MASK;
627 temp |= (u32) 160;
628 writel(temp, &xhci->ir_set->irq_control);
629
630 /* Set the HCD state before we enable the irqs */
631 temp = readl(&xhci->op_regs->command);
632 temp |= (CMD_EIE);
633 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
634 "// Enable interrupts, cmd = 0x%x.", temp);
635 writel(temp, &xhci->op_regs->command);
636
637 temp = readl(&xhci->ir_set->irq_pending);
638 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
639 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
640 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
641 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
642 xhci_print_ir_set(xhci, 0);
643
644 if (xhci->quirks & XHCI_NEC_HOST)
645 xhci_queue_vendor_command(xhci, 0, 0, 0,
646 TRB_TYPE(TRB_NEC_GET_FW));
647
648 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
649 "Finished xhci_run for USB2 roothub");
650 return 0;
651}
652
653static void xhci_only_stop_hcd(struct usb_hcd *hcd)
654{
655 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
656
657 spin_lock_irq(&xhci->lock);
658 xhci_halt(xhci);
659
660 /* The shared_hcd is going to be deallocated shortly (the USB core only
661 * calls this function when allocation fails in usb_add_hcd(), or
662 * usb_remove_hcd() is called). So we need to unset xHCI's pointer.
663 */
664 xhci->shared_hcd = NULL;
665 spin_unlock_irq(&xhci->lock);
666}
667
668/*
669 * Stop xHCI driver.
670 *
671 * This function is called by the USB core when the HC driver is removed.
672 * Its opposite is xhci_run().
673 *
674 * Disable device contexts, disable IRQs, and quiesce the HC.
675 * Reset the HC, finish any completed transactions, and cleanup memory.
676 */
677void xhci_stop(struct usb_hcd *hcd)
678{
679 u32 temp;
680 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
681
682 if (!usb_hcd_is_primary_hcd(hcd)) {
683 xhci_only_stop_hcd(xhci->shared_hcd);
684 return;
685 }
686
687 spin_lock_irq(&xhci->lock);
688 /* Make sure the xHC is halted for a USB3 roothub
689 * (xhci_stop() could be called as part of failed init).
690 */
691 xhci_halt(xhci);
692 xhci_reset(xhci);
693 spin_unlock_irq(&xhci->lock);
694
695 xhci_cleanup_msix(xhci);
696
697 /* Deleting Compliance Mode Recovery Timer */
698 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
699 (!(xhci_all_ports_seen_u0(xhci)))) {
700 del_timer_sync(&xhci->comp_mode_recovery_timer);
701 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
702 "%s: compliance mode recovery timer deleted",
703 __func__);
704 }
705
706 if (xhci->quirks & XHCI_AMD_PLL_FIX)
707 usb_amd_dev_put();
708
709 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
710 "// Disabling event ring interrupts");
711 temp = readl(&xhci->op_regs->status);
712 writel(temp & ~STS_EINT, &xhci->op_regs->status);
713 temp = readl(&xhci->ir_set->irq_pending);
714 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
715 xhci_print_ir_set(xhci, 0);
716
717 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
718 xhci_mem_cleanup(xhci);
719 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
720 "xhci_stop completed - status = %x",
721 readl(&xhci->op_regs->status));
722}
723
724/*
725 * Shutdown HC (not bus-specific)
726 *
727 * This is called when the machine is rebooting or halting. We assume that the
728 * machine will be powered off, and the HC's internal state will be reset.
729 * Don't bother to free memory.
730 *
731 * This will only ever be called with the main usb_hcd (the USB3 roothub).
732 */
733void xhci_shutdown(struct usb_hcd *hcd)
734{
735 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
736
737 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
738 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
739
740 spin_lock_irq(&xhci->lock);
741 xhci_halt(xhci);
742 /* Workaround for spurious wakeups at shutdown with HSW */
743 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
744 xhci_reset(xhci);
745 spin_unlock_irq(&xhci->lock);
746
747 xhci_cleanup_msix(xhci);
748
749 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
750 "xhci_shutdown completed - status = %x",
751 readl(&xhci->op_regs->status));
752
753 /* Yet another workaround for spurious wakeups at shutdown with HSW */
754 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
755 pci_set_power_state(to_pci_dev(hcd->self.controller), PCI_D3hot);
756}
757
758#ifdef CONFIG_PM
759static void xhci_save_registers(struct xhci_hcd *xhci)
760{
761 xhci->s3.command = readl(&xhci->op_regs->command);
762 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
763 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
764 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
765 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
766 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
767 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
768 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
769 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
770}
771
772static void xhci_restore_registers(struct xhci_hcd *xhci)
773{
774 writel(xhci->s3.command, &xhci->op_regs->command);
775 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
776 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
777 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
778 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
779 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
780 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
781 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
782 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
783}
784
785static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
786{
787 u64 val_64;
788
789 /* step 2: initialize command ring buffer */
790 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
791 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
792 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
793 xhci->cmd_ring->dequeue) &
794 (u64) ~CMD_RING_RSVD_BITS) |
795 xhci->cmd_ring->cycle_state;
796 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
797 "// Setting command ring address to 0x%llx",
798 (long unsigned long) val_64);
799 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
800}
801
802/*
803 * The whole command ring must be cleared to zero when we suspend the host.
804 *
805 * The host doesn't save the command ring pointer in the suspend well, so we
806 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
807 * aligned, because of the reserved bits in the command ring dequeue pointer
808 * register. Therefore, we can't just set the dequeue pointer back in the
809 * middle of the ring (TRBs are 16-byte aligned).
810 */
811static void xhci_clear_command_ring(struct xhci_hcd *xhci)
812{
813 struct xhci_ring *ring;
814 struct xhci_segment *seg;
815
816 ring = xhci->cmd_ring;
817 seg = ring->deq_seg;
818 do {
819 memset(seg->trbs, 0,
820 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
821 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
822 cpu_to_le32(~TRB_CYCLE);
823 seg = seg->next;
824 } while (seg != ring->deq_seg);
825
826 /* Reset the software enqueue and dequeue pointers */
827 ring->deq_seg = ring->first_seg;
828 ring->dequeue = ring->first_seg->trbs;
829 ring->enq_seg = ring->deq_seg;
830 ring->enqueue = ring->dequeue;
831
832 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
833 /*
834 * Ring is now zeroed, so the HW should look for change of ownership
835 * when the cycle bit is set to 1.
836 */
837 ring->cycle_state = 1;
838
839 /*
840 * Reset the hardware dequeue pointer.
841 * Yes, this will need to be re-written after resume, but we're paranoid
842 * and want to make sure the hardware doesn't access bogus memory
843 * because, say, the BIOS or an SMI started the host without changing
844 * the command ring pointers.
845 */
846 xhci_set_cmd_ring_deq(xhci);
847}
848
849/*
850 * Stop HC (not bus-specific)
851 *
852 * This is called when the machine transition into S3/S4 mode.
853 *
854 */
855int xhci_suspend(struct xhci_hcd *xhci)
856{
857 int rc = 0;
858 unsigned int delay = XHCI_MAX_HALT_USEC;
859 struct usb_hcd *hcd = xhci_to_hcd(xhci);
860 u32 command;
861
862 if (hcd->state != HC_STATE_SUSPENDED ||
863 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
864 return -EINVAL;
865
866 /* Don't poll the roothubs on bus suspend. */
867 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
868 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
869 del_timer_sync(&hcd->rh_timer);
870
871 spin_lock_irq(&xhci->lock);
872 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
873 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
874 /* step 1: stop endpoint */
875 /* skipped assuming that port suspend has done */
876
877 /* step 2: clear Run/Stop bit */
878 command = readl(&xhci->op_regs->command);
879 command &= ~CMD_RUN;
880 writel(command, &xhci->op_regs->command);
881
882 /* Some chips from Fresco Logic need an extraordinary delay */
883 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
884
885 if (xhci_handshake(xhci, &xhci->op_regs->status,
886 STS_HALT, STS_HALT, delay)) {
887 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
888 spin_unlock_irq(&xhci->lock);
889 return -ETIMEDOUT;
890 }
891 xhci_clear_command_ring(xhci);
892
893 /* step 3: save registers */
894 xhci_save_registers(xhci);
895
896 /* step 4: set CSS flag */
897 command = readl(&xhci->op_regs->command);
898 command |= CMD_CSS;
899 writel(command, &xhci->op_regs->command);
900 if (xhci_handshake(xhci, &xhci->op_regs->status,
901 STS_SAVE, 0, 10 * 1000)) {
902 xhci_warn(xhci, "WARN: xHC save state timeout\n");
903 spin_unlock_irq(&xhci->lock);
904 return -ETIMEDOUT;
905 }
906 spin_unlock_irq(&xhci->lock);
907
908 /*
909 * Deleting Compliance Mode Recovery Timer because the xHCI Host
910 * is about to be suspended.
911 */
912 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
913 (!(xhci_all_ports_seen_u0(xhci)))) {
914 del_timer_sync(&xhci->comp_mode_recovery_timer);
915 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
916 "%s: compliance mode recovery timer deleted",
917 __func__);
918 }
919
920 /* step 5: remove core well power */
921 /* synchronize irq when using MSI-X */
922 xhci_msix_sync_irqs(xhci);
923
924 return rc;
925}
926
927/*
928 * start xHC (not bus-specific)
929 *
930 * This is called when the machine transition from S3/S4 mode.
931 *
932 */
933int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
934{
935 u32 command, temp = 0;
936 struct usb_hcd *hcd = xhci_to_hcd(xhci);
937 struct usb_hcd *secondary_hcd;
938 int retval = 0;
939 bool comp_timer_running = false;
940
941 /* Wait a bit if either of the roothubs need to settle from the
942 * transition into bus suspend.
943 */
944 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
945 time_before(jiffies,
946 xhci->bus_state[1].next_statechange))
947 msleep(100);
948
949 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
950 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
951
952 spin_lock_irq(&xhci->lock);
953 if (xhci->quirks & XHCI_RESET_ON_RESUME)
954 hibernated = true;
955
956 if (!hibernated) {
957 /* step 1: restore register */
958 xhci_restore_registers(xhci);
959 /* step 2: initialize command ring buffer */
960 xhci_set_cmd_ring_deq(xhci);
961 /* step 3: restore state and start state*/
962 /* step 3: set CRS flag */
963 command = readl(&xhci->op_regs->command);
964 command |= CMD_CRS;
965 writel(command, &xhci->op_regs->command);
966 if (xhci_handshake(xhci, &xhci->op_regs->status,
967 STS_RESTORE, 0, 10 * 1000)) {
968 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
969 spin_unlock_irq(&xhci->lock);
970 return -ETIMEDOUT;
971 }
972 temp = readl(&xhci->op_regs->status);
973 }
974
975 /* If restore operation fails, re-initialize the HC during resume */
976 if ((temp & STS_SRE) || hibernated) {
977
978 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
979 !(xhci_all_ports_seen_u0(xhci))) {
980 del_timer_sync(&xhci->comp_mode_recovery_timer);
981 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
982 "Compliance Mode Recovery Timer deleted!");
983 }
984
985 /* Let the USB core know _both_ roothubs lost power. */
986 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
987 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
988
989 xhci_dbg(xhci, "Stop HCD\n");
990 xhci_halt(xhci);
991 xhci_reset(xhci);
992 spin_unlock_irq(&xhci->lock);
993 xhci_cleanup_msix(xhci);
994
995 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
996 temp = readl(&xhci->op_regs->status);
997 writel(temp & ~STS_EINT, &xhci->op_regs->status);
998 temp = readl(&xhci->ir_set->irq_pending);
999 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1000 xhci_print_ir_set(xhci, 0);
1001
1002 xhci_dbg(xhci, "cleaning up memory\n");
1003 xhci_mem_cleanup(xhci);
1004 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1005 readl(&xhci->op_regs->status));
1006
1007 /* USB core calls the PCI reinit and start functions twice:
1008 * first with the primary HCD, and then with the secondary HCD.
1009 * If we don't do the same, the host will never be started.
1010 */
1011 if (!usb_hcd_is_primary_hcd(hcd))
1012 secondary_hcd = hcd;
1013 else
1014 secondary_hcd = xhci->shared_hcd;
1015
1016 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1017 retval = xhci_init(hcd->primary_hcd);
1018 if (retval)
1019 return retval;
1020 comp_timer_running = true;
1021
1022 xhci_dbg(xhci, "Start the primary HCD\n");
1023 retval = xhci_run(hcd->primary_hcd);
1024 if (!retval) {
1025 xhci_dbg(xhci, "Start the secondary HCD\n");
1026 retval = xhci_run(secondary_hcd);
1027 }
1028 hcd->state = HC_STATE_SUSPENDED;
1029 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1030 goto done;
1031 }
1032
1033 /* step 4: set Run/Stop bit */
1034 command = readl(&xhci->op_regs->command);
1035 command |= CMD_RUN;
1036 writel(command, &xhci->op_regs->command);
1037 xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT,
1038 0, 250 * 1000);
1039
1040 /* step 5: walk topology and initialize portsc,
1041 * portpmsc and portli
1042 */
1043 /* this is done in bus_resume */
1044
1045 /* step 6: restart each of the previously
1046 * Running endpoints by ringing their doorbells
1047 */
1048
1049 spin_unlock_irq(&xhci->lock);
1050
1051 done:
1052 if (retval == 0) {
1053 usb_hcd_resume_root_hub(hcd);
1054 usb_hcd_resume_root_hub(xhci->shared_hcd);
1055 }
1056
1057 /*
1058 * If system is subject to the Quirk, Compliance Mode Timer needs to
1059 * be re-initialized Always after a system resume. Ports are subject
1060 * to suffer the Compliance Mode issue again. It doesn't matter if
1061 * ports have entered previously to U0 before system's suspension.
1062 */
1063 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1064 compliance_mode_recovery_timer_init(xhci);
1065
1066 /* Re-enable port polling. */
1067 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1068 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1069 usb_hcd_poll_rh_status(hcd);
1070
1071 return retval;
1072}
1073#endif /* CONFIG_PM */
1074
1075/*-------------------------------------------------------------------------*/
1076
1077/**
1078 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1079 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1080 * value to right shift 1 for the bitmask.
1081 *
1082 * Index = (epnum * 2) + direction - 1,
1083 * where direction = 0 for OUT, 1 for IN.
1084 * For control endpoints, the IN index is used (OUT index is unused), so
1085 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1086 */
1087unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1088{
1089 unsigned int index;
1090 if (usb_endpoint_xfer_control(desc))
1091 index = (unsigned int) (usb_endpoint_num(desc)*2);
1092 else
1093 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1094 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1095 return index;
1096}
1097
1098/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1099 * address from the XHCI endpoint index.
1100 */
1101unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1102{
1103 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1104 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1105 return direction | number;
1106}
1107
1108/* Find the flag for this endpoint (for use in the control context). Use the
1109 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1110 * bit 1, etc.
1111 */
1112unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1113{
1114 return 1 << (xhci_get_endpoint_index(desc) + 1);
1115}
1116
1117/* Find the flag for this endpoint (for use in the control context). Use the
1118 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1119 * bit 1, etc.
1120 */
1121unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1122{
1123 return 1 << (ep_index + 1);
1124}
1125
1126/* Compute the last valid endpoint context index. Basically, this is the
1127 * endpoint index plus one. For slot contexts with more than valid endpoint,
1128 * we find the most significant bit set in the added contexts flags.
1129 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1130 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1131 */
1132unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1133{
1134 return fls(added_ctxs) - 1;
1135}
1136
1137/* Returns 1 if the arguments are OK;
1138 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1139 */
1140static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1141 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1142 const char *func) {
1143 struct xhci_hcd *xhci;
1144 struct xhci_virt_device *virt_dev;
1145
1146 if (!hcd || (check_ep && !ep) || !udev) {
1147 pr_debug("xHCI %s called with invalid args\n", func);
1148 return -EINVAL;
1149 }
1150 if (!udev->parent) {
1151 pr_debug("xHCI %s called for root hub\n", func);
1152 return 0;
1153 }
1154
1155 xhci = hcd_to_xhci(hcd);
1156 if (check_virt_dev) {
1157 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1158 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1159 func);
1160 return -EINVAL;
1161 }
1162
1163 virt_dev = xhci->devs[udev->slot_id];
1164 if (virt_dev->udev != udev) {
1165 xhci_dbg(xhci, "xHCI %s called with udev and "
1166 "virt_dev does not match\n", func);
1167 return -EINVAL;
1168 }
1169 }
1170
1171 if (xhci->xhc_state & XHCI_STATE_HALTED)
1172 return -ENODEV;
1173
1174 return 1;
1175}
1176
1177static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1178 struct usb_device *udev, struct xhci_command *command,
1179 bool ctx_change, bool must_succeed);
1180
1181/*
1182 * Full speed devices may have a max packet size greater than 8 bytes, but the
1183 * USB core doesn't know that until it reads the first 8 bytes of the
1184 * descriptor. If the usb_device's max packet size changes after that point,
1185 * we need to issue an evaluate context command and wait on it.
1186 */
1187static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1188 unsigned int ep_index, struct urb *urb)
1189{
1190 struct xhci_container_ctx *in_ctx;
1191 struct xhci_container_ctx *out_ctx;
1192 struct xhci_input_control_ctx *ctrl_ctx;
1193 struct xhci_ep_ctx *ep_ctx;
1194 int max_packet_size;
1195 int hw_max_packet_size;
1196 int ret = 0;
1197
1198 out_ctx = xhci->devs[slot_id]->out_ctx;
1199 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1200 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1201 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1202 if (hw_max_packet_size != max_packet_size) {
1203 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1204 "Max Packet Size for ep 0 changed.");
1205 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1206 "Max packet size in usb_device = %d",
1207 max_packet_size);
1208 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1209 "Max packet size in xHCI HW = %d",
1210 hw_max_packet_size);
1211 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1212 "Issuing evaluate context command.");
1213
1214 /* Set up the input context flags for the command */
1215 /* FIXME: This won't work if a non-default control endpoint
1216 * changes max packet sizes.
1217 */
1218 in_ctx = xhci->devs[slot_id]->in_ctx;
1219 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1220 if (!ctrl_ctx) {
1221 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1222 __func__);
1223 return -ENOMEM;
1224 }
1225 /* Set up the modified control endpoint 0 */
1226 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1227 xhci->devs[slot_id]->out_ctx, ep_index);
1228
1229 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1230 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1231 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1232
1233 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1234 ctrl_ctx->drop_flags = 0;
1235
1236 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1237 xhci_dbg_ctx(xhci, in_ctx, ep_index);
1238 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1239 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1240
1241 ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
1242 true, false);
1243
1244 /* Clean up the input context for later use by bandwidth
1245 * functions.
1246 */
1247 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1248 }
1249 return ret;
1250}
1251
1252/*
1253 * non-error returns are a promise to giveback() the urb later
1254 * we drop ownership so next owner (or urb unlink) can get it
1255 */
1256int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1257{
1258 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1259 struct xhci_td *buffer;
1260 unsigned long flags;
1261 int ret = 0;
1262 unsigned int slot_id, ep_index;
1263 struct urb_priv *urb_priv;
1264 int size, i;
1265
1266 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1267 true, true, __func__) <= 0)
1268 return -EINVAL;
1269
1270 slot_id = urb->dev->slot_id;
1271 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1272
1273 if (!HCD_HW_ACCESSIBLE(hcd)) {
1274 if (!in_interrupt())
1275 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1276 ret = -ESHUTDOWN;
1277 goto exit;
1278 }
1279
1280 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1281 size = urb->number_of_packets;
1282 else
1283 size = 1;
1284
1285 urb_priv = kzalloc(sizeof(struct urb_priv) +
1286 size * sizeof(struct xhci_td *), mem_flags);
1287 if (!urb_priv)
1288 return -ENOMEM;
1289
1290 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1291 if (!buffer) {
1292 kfree(urb_priv);
1293 return -ENOMEM;
1294 }
1295
1296 for (i = 0; i < size; i++) {
1297 urb_priv->td[i] = buffer;
1298 buffer++;
1299 }
1300
1301 urb_priv->length = size;
1302 urb_priv->td_cnt = 0;
1303 urb->hcpriv = urb_priv;
1304
1305 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1306 /* Check to see if the max packet size for the default control
1307 * endpoint changed during FS device enumeration
1308 */
1309 if (urb->dev->speed == USB_SPEED_FULL) {
1310 ret = xhci_check_maxpacket(xhci, slot_id,
1311 ep_index, urb);
1312 if (ret < 0) {
1313 xhci_urb_free_priv(xhci, urb_priv);
1314 urb->hcpriv = NULL;
1315 return ret;
1316 }
1317 }
1318
1319 /* We have a spinlock and interrupts disabled, so we must pass
1320 * atomic context to this function, which may allocate memory.
1321 */
1322 spin_lock_irqsave(&xhci->lock, flags);
1323 if (xhci->xhc_state & XHCI_STATE_DYING)
1324 goto dying;
1325 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1326 slot_id, ep_index);
1327 if (ret)
1328 goto free_priv;
1329 spin_unlock_irqrestore(&xhci->lock, flags);
1330 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1331 spin_lock_irqsave(&xhci->lock, flags);
1332 if (xhci->xhc_state & XHCI_STATE_DYING)
1333 goto dying;
1334 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1335 EP_GETTING_STREAMS) {
1336 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1337 "is transitioning to using streams.\n");
1338 ret = -EINVAL;
1339 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1340 EP_GETTING_NO_STREAMS) {
1341 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1342 "is transitioning to "
1343 "not having streams.\n");
1344 ret = -EINVAL;
1345 } else {
1346 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1347 slot_id, ep_index);
1348 }
1349 if (ret)
1350 goto free_priv;
1351 spin_unlock_irqrestore(&xhci->lock, flags);
1352 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1353 spin_lock_irqsave(&xhci->lock, flags);
1354 if (xhci->xhc_state & XHCI_STATE_DYING)
1355 goto dying;
1356 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1357 slot_id, ep_index);
1358 if (ret)
1359 goto free_priv;
1360 spin_unlock_irqrestore(&xhci->lock, flags);
1361 } else {
1362 spin_lock_irqsave(&xhci->lock, flags);
1363 if (xhci->xhc_state & XHCI_STATE_DYING)
1364 goto dying;
1365 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1366 slot_id, ep_index);
1367 if (ret)
1368 goto free_priv;
1369 spin_unlock_irqrestore(&xhci->lock, flags);
1370 }
1371exit:
1372 return ret;
1373dying:
1374 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1375 "non-responsive xHCI host.\n",
1376 urb->ep->desc.bEndpointAddress, urb);
1377 ret = -ESHUTDOWN;
1378free_priv:
1379 xhci_urb_free_priv(xhci, urb_priv);
1380 urb->hcpriv = NULL;
1381 spin_unlock_irqrestore(&xhci->lock, flags);
1382 return ret;
1383}
1384
1385/* Get the right ring for the given URB.
1386 * If the endpoint supports streams, boundary check the URB's stream ID.
1387 * If the endpoint doesn't support streams, return the singular endpoint ring.
1388 */
1389static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1390 struct urb *urb)
1391{
1392 unsigned int slot_id;
1393 unsigned int ep_index;
1394 unsigned int stream_id;
1395 struct xhci_virt_ep *ep;
1396
1397 slot_id = urb->dev->slot_id;
1398 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1399 stream_id = urb->stream_id;
1400 ep = &xhci->devs[slot_id]->eps[ep_index];
1401 /* Common case: no streams */
1402 if (!(ep->ep_state & EP_HAS_STREAMS))
1403 return ep->ring;
1404
1405 if (stream_id == 0) {
1406 xhci_warn(xhci,
1407 "WARN: Slot ID %u, ep index %u has streams, "
1408 "but URB has no stream ID.\n",
1409 slot_id, ep_index);
1410 return NULL;
1411 }
1412
1413 if (stream_id < ep->stream_info->num_streams)
1414 return ep->stream_info->stream_rings[stream_id];
1415
1416 xhci_warn(xhci,
1417 "WARN: Slot ID %u, ep index %u has "
1418 "stream IDs 1 to %u allocated, "
1419 "but stream ID %u is requested.\n",
1420 slot_id, ep_index,
1421 ep->stream_info->num_streams - 1,
1422 stream_id);
1423 return NULL;
1424}
1425
1426/*
1427 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1428 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1429 * should pick up where it left off in the TD, unless a Set Transfer Ring
1430 * Dequeue Pointer is issued.
1431 *
1432 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1433 * the ring. Since the ring is a contiguous structure, they can't be physically
1434 * removed. Instead, there are two options:
1435 *
1436 * 1) If the HC is in the middle of processing the URB to be canceled, we
1437 * simply move the ring's dequeue pointer past those TRBs using the Set
1438 * Transfer Ring Dequeue Pointer command. This will be the common case,
1439 * when drivers timeout on the last submitted URB and attempt to cancel.
1440 *
1441 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1442 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1443 * HC will need to invalidate the any TRBs it has cached after the stop
1444 * endpoint command, as noted in the xHCI 0.95 errata.
1445 *
1446 * 3) The TD may have completed by the time the Stop Endpoint Command
1447 * completes, so software needs to handle that case too.
1448 *
1449 * This function should protect against the TD enqueueing code ringing the
1450 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1451 * It also needs to account for multiple cancellations on happening at the same
1452 * time for the same endpoint.
1453 *
1454 * Note that this function can be called in any context, or so says
1455 * usb_hcd_unlink_urb()
1456 */
1457int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1458{
1459 unsigned long flags;
1460 int ret, i;
1461 u32 temp;
1462 struct xhci_hcd *xhci;
1463 struct urb_priv *urb_priv;
1464 struct xhci_td *td;
1465 unsigned int ep_index;
1466 struct xhci_ring *ep_ring;
1467 struct xhci_virt_ep *ep;
1468
1469 xhci = hcd_to_xhci(hcd);
1470 spin_lock_irqsave(&xhci->lock, flags);
1471 /* Make sure the URB hasn't completed or been unlinked already */
1472 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1473 if (ret || !urb->hcpriv)
1474 goto done;
1475 temp = readl(&xhci->op_regs->status);
1476 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1477 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1478 "HW died, freeing TD.");
1479 urb_priv = urb->hcpriv;
1480 for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
1481 td = urb_priv->td[i];
1482 if (!list_empty(&td->td_list))
1483 list_del_init(&td->td_list);
1484 if (!list_empty(&td->cancelled_td_list))
1485 list_del_init(&td->cancelled_td_list);
1486 }
1487
1488 usb_hcd_unlink_urb_from_ep(hcd, urb);
1489 spin_unlock_irqrestore(&xhci->lock, flags);
1490 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1491 xhci_urb_free_priv(xhci, urb_priv);
1492 return ret;
1493 }
1494 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
1495 (xhci->xhc_state & XHCI_STATE_HALTED)) {
1496 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1497 "Ep 0x%x: URB %p to be canceled on "
1498 "non-responsive xHCI host.",
1499 urb->ep->desc.bEndpointAddress, urb);
1500 /* Let the stop endpoint command watchdog timer (which set this
1501 * state) finish cleaning up the endpoint TD lists. We must
1502 * have caught it in the middle of dropping a lock and giving
1503 * back an URB.
1504 */
1505 goto done;
1506 }
1507
1508 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1509 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1510 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1511 if (!ep_ring) {
1512 ret = -EINVAL;
1513 goto done;
1514 }
1515
1516 urb_priv = urb->hcpriv;
1517 i = urb_priv->td_cnt;
1518 if (i < urb_priv->length)
1519 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1520 "Cancel URB %p, dev %s, ep 0x%x, "
1521 "starting at offset 0x%llx",
1522 urb, urb->dev->devpath,
1523 urb->ep->desc.bEndpointAddress,
1524 (unsigned long long) xhci_trb_virt_to_dma(
1525 urb_priv->td[i]->start_seg,
1526 urb_priv->td[i]->first_trb));
1527
1528 for (; i < urb_priv->length; i++) {
1529 td = urb_priv->td[i];
1530 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1531 }
1532
1533 /* Queue a stop endpoint command, but only if this is
1534 * the first cancellation to be handled.
1535 */
1536 if (!(ep->ep_state & EP_HALT_PENDING)) {
1537 ep->ep_state |= EP_HALT_PENDING;
1538 ep->stop_cmds_pending++;
1539 ep->stop_cmd_timer.expires = jiffies +
1540 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1541 add_timer(&ep->stop_cmd_timer);
1542 xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0);
1543 xhci_ring_cmd_db(xhci);
1544 }
1545done:
1546 spin_unlock_irqrestore(&xhci->lock, flags);
1547 return ret;
1548}
1549
1550/* Drop an endpoint from a new bandwidth configuration for this device.
1551 * Only one call to this function is allowed per endpoint before
1552 * check_bandwidth() or reset_bandwidth() must be called.
1553 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1554 * add the endpoint to the schedule with possibly new parameters denoted by a
1555 * different endpoint descriptor in usb_host_endpoint.
1556 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1557 * not allowed.
1558 *
1559 * The USB core will not allow URBs to be queued to an endpoint that is being
1560 * disabled, so there's no need for mutual exclusion to protect
1561 * the xhci->devs[slot_id] structure.
1562 */
1563int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1564 struct usb_host_endpoint *ep)
1565{
1566 struct xhci_hcd *xhci;
1567 struct xhci_container_ctx *in_ctx, *out_ctx;
1568 struct xhci_input_control_ctx *ctrl_ctx;
1569 struct xhci_slot_ctx *slot_ctx;
1570 unsigned int last_ctx;
1571 unsigned int ep_index;
1572 struct xhci_ep_ctx *ep_ctx;
1573 u32 drop_flag;
1574 u32 new_add_flags, new_drop_flags, new_slot_info;
1575 int ret;
1576
1577 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1578 if (ret <= 0)
1579 return ret;
1580 xhci = hcd_to_xhci(hcd);
1581 if (xhci->xhc_state & XHCI_STATE_DYING)
1582 return -ENODEV;
1583
1584 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1585 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1586 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1587 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1588 __func__, drop_flag);
1589 return 0;
1590 }
1591
1592 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1593 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1594 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1595 if (!ctrl_ctx) {
1596 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1597 __func__);
1598 return 0;
1599 }
1600
1601 ep_index = xhci_get_endpoint_index(&ep->desc);
1602 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1603 /* If the HC already knows the endpoint is disabled,
1604 * or the HCD has noted it is disabled, ignore this request
1605 */
1606 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1607 cpu_to_le32(EP_STATE_DISABLED)) ||
1608 le32_to_cpu(ctrl_ctx->drop_flags) &
1609 xhci_get_endpoint_flag(&ep->desc)) {
1610 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1611 __func__, ep);
1612 return 0;
1613 }
1614
1615 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1616 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1617
1618 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1619 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1620
1621 last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags));
1622 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1623 /* Update the last valid endpoint context, if we deleted the last one */
1624 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) >
1625 LAST_CTX(last_ctx)) {
1626 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1627 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1628 }
1629 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1630
1631 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1632
1633 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1634 (unsigned int) ep->desc.bEndpointAddress,
1635 udev->slot_id,
1636 (unsigned int) new_drop_flags,
1637 (unsigned int) new_add_flags,
1638 (unsigned int) new_slot_info);
1639 return 0;
1640}
1641
1642/* Add an endpoint to a new possible bandwidth configuration for this device.
1643 * Only one call to this function is allowed per endpoint before
1644 * check_bandwidth() or reset_bandwidth() must be called.
1645 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1646 * add the endpoint to the schedule with possibly new parameters denoted by a
1647 * different endpoint descriptor in usb_host_endpoint.
1648 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1649 * not allowed.
1650 *
1651 * The USB core will not allow URBs to be queued to an endpoint until the
1652 * configuration or alt setting is installed in the device, so there's no need
1653 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1654 */
1655int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1656 struct usb_host_endpoint *ep)
1657{
1658 struct xhci_hcd *xhci;
1659 struct xhci_container_ctx *in_ctx, *out_ctx;
1660 unsigned int ep_index;
1661 struct xhci_slot_ctx *slot_ctx;
1662 struct xhci_input_control_ctx *ctrl_ctx;
1663 u32 added_ctxs;
1664 unsigned int last_ctx;
1665 u32 new_add_flags, new_drop_flags, new_slot_info;
1666 struct xhci_virt_device *virt_dev;
1667 int ret = 0;
1668
1669 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1670 if (ret <= 0) {
1671 /* So we won't queue a reset ep command for a root hub */
1672 ep->hcpriv = NULL;
1673 return ret;
1674 }
1675 xhci = hcd_to_xhci(hcd);
1676 if (xhci->xhc_state & XHCI_STATE_DYING)
1677 return -ENODEV;
1678
1679 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1680 last_ctx = xhci_last_valid_endpoint(added_ctxs);
1681 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1682 /* FIXME when we have to issue an evaluate endpoint command to
1683 * deal with ep0 max packet size changing once we get the
1684 * descriptors
1685 */
1686 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1687 __func__, added_ctxs);
1688 return 0;
1689 }
1690
1691 virt_dev = xhci->devs[udev->slot_id];
1692 in_ctx = virt_dev->in_ctx;
1693 out_ctx = virt_dev->out_ctx;
1694 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1695 if (!ctrl_ctx) {
1696 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1697 __func__);
1698 return 0;
1699 }
1700
1701 ep_index = xhci_get_endpoint_index(&ep->desc);
1702 /* If this endpoint is already in use, and the upper layers are trying
1703 * to add it again without dropping it, reject the addition.
1704 */
1705 if (virt_dev->eps[ep_index].ring &&
1706 !(le32_to_cpu(ctrl_ctx->drop_flags) &
1707 xhci_get_endpoint_flag(&ep->desc))) {
1708 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1709 "without dropping it.\n",
1710 (unsigned int) ep->desc.bEndpointAddress);
1711 return -EINVAL;
1712 }
1713
1714 /* If the HCD has already noted the endpoint is enabled,
1715 * ignore this request.
1716 */
1717 if (le32_to_cpu(ctrl_ctx->add_flags) &
1718 xhci_get_endpoint_flag(&ep->desc)) {
1719 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1720 __func__, ep);
1721 return 0;
1722 }
1723
1724 /*
1725 * Configuration and alternate setting changes must be done in
1726 * process context, not interrupt context (or so documenation
1727 * for usb_set_interface() and usb_set_configuration() claim).
1728 */
1729 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1730 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1731 __func__, ep->desc.bEndpointAddress);
1732 return -ENOMEM;
1733 }
1734
1735 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1736 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1737
1738 /* If xhci_endpoint_disable() was called for this endpoint, but the
1739 * xHC hasn't been notified yet through the check_bandwidth() call,
1740 * this re-adds a new state for the endpoint from the new endpoint
1741 * descriptors. We must drop and re-add this endpoint, so we leave the
1742 * drop flags alone.
1743 */
1744 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1745
1746 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1747 /* Update the last valid endpoint context, if we just added one past */
1748 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) <
1749 LAST_CTX(last_ctx)) {
1750 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1751 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1752 }
1753 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1754
1755 /* Store the usb_device pointer for later use */
1756 ep->hcpriv = udev;
1757
1758 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1759 (unsigned int) ep->desc.bEndpointAddress,
1760 udev->slot_id,
1761 (unsigned int) new_drop_flags,
1762 (unsigned int) new_add_flags,
1763 (unsigned int) new_slot_info);
1764 return 0;
1765}
1766
1767static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1768{
1769 struct xhci_input_control_ctx *ctrl_ctx;
1770 struct xhci_ep_ctx *ep_ctx;
1771 struct xhci_slot_ctx *slot_ctx;
1772 int i;
1773
1774 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1775 if (!ctrl_ctx) {
1776 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1777 __func__);
1778 return;
1779 }
1780
1781 /* When a device's add flag and drop flag are zero, any subsequent
1782 * configure endpoint command will leave that endpoint's state
1783 * untouched. Make sure we don't leave any old state in the input
1784 * endpoint contexts.
1785 */
1786 ctrl_ctx->drop_flags = 0;
1787 ctrl_ctx->add_flags = 0;
1788 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1789 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1790 /* Endpoint 0 is always valid */
1791 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1792 for (i = 1; i < 31; ++i) {
1793 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1794 ep_ctx->ep_info = 0;
1795 ep_ctx->ep_info2 = 0;
1796 ep_ctx->deq = 0;
1797 ep_ctx->tx_info = 0;
1798 }
1799}
1800
1801static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1802 struct usb_device *udev, u32 *cmd_status)
1803{
1804 int ret;
1805
1806 switch (*cmd_status) {
1807 case COMP_ENOMEM:
1808 dev_warn(&udev->dev, "Not enough host controller resources "
1809 "for new device state.\n");
1810 ret = -ENOMEM;
1811 /* FIXME: can we allocate more resources for the HC? */
1812 break;
1813 case COMP_BW_ERR:
1814 case COMP_2ND_BW_ERR:
1815 dev_warn(&udev->dev, "Not enough bandwidth "
1816 "for new device state.\n");
1817 ret = -ENOSPC;
1818 /* FIXME: can we go back to the old state? */
1819 break;
1820 case COMP_TRB_ERR:
1821 /* the HCD set up something wrong */
1822 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1823 "add flag = 1, "
1824 "and endpoint is not disabled.\n");
1825 ret = -EINVAL;
1826 break;
1827 case COMP_DEV_ERR:
1828 dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint "
1829 "configure command.\n");
1830 ret = -ENODEV;
1831 break;
1832 case COMP_SUCCESS:
1833 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1834 "Successful Endpoint Configure command");
1835 ret = 0;
1836 break;
1837 default:
1838 xhci_err(xhci, "ERROR: unexpected command completion "
1839 "code 0x%x.\n", *cmd_status);
1840 ret = -EINVAL;
1841 break;
1842 }
1843 return ret;
1844}
1845
1846static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1847 struct usb_device *udev, u32 *cmd_status)
1848{
1849 int ret;
1850 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1851
1852 switch (*cmd_status) {
1853 case COMP_EINVAL:
1854 dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
1855 "context command.\n");
1856 ret = -EINVAL;
1857 break;
1858 case COMP_EBADSLT:
1859 dev_warn(&udev->dev, "WARN: slot not enabled for"
1860 "evaluate context command.\n");
1861 ret = -EINVAL;
1862 break;
1863 case COMP_CTX_STATE:
1864 dev_warn(&udev->dev, "WARN: invalid context state for "
1865 "evaluate context command.\n");
1866 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1867 ret = -EINVAL;
1868 break;
1869 case COMP_DEV_ERR:
1870 dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate "
1871 "context command.\n");
1872 ret = -ENODEV;
1873 break;
1874 case COMP_MEL_ERR:
1875 /* Max Exit Latency too large error */
1876 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1877 ret = -EINVAL;
1878 break;
1879 case COMP_SUCCESS:
1880 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1881 "Successful evaluate context command");
1882 ret = 0;
1883 break;
1884 default:
1885 xhci_err(xhci, "ERROR: unexpected command completion "
1886 "code 0x%x.\n", *cmd_status);
1887 ret = -EINVAL;
1888 break;
1889 }
1890 return ret;
1891}
1892
1893static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1894 struct xhci_input_control_ctx *ctrl_ctx)
1895{
1896 u32 valid_add_flags;
1897 u32 valid_drop_flags;
1898
1899 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1900 * (bit 1). The default control endpoint is added during the Address
1901 * Device command and is never removed until the slot is disabled.
1902 */
1903 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1904 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1905
1906 /* Use hweight32 to count the number of ones in the add flags, or
1907 * number of endpoints added. Don't count endpoints that are changed
1908 * (both added and dropped).
1909 */
1910 return hweight32(valid_add_flags) -
1911 hweight32(valid_add_flags & valid_drop_flags);
1912}
1913
1914static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1915 struct xhci_input_control_ctx *ctrl_ctx)
1916{
1917 u32 valid_add_flags;
1918 u32 valid_drop_flags;
1919
1920 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
1921 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
1922
1923 return hweight32(valid_drop_flags) -
1924 hweight32(valid_add_flags & valid_drop_flags);
1925}
1926
1927/*
1928 * We need to reserve the new number of endpoints before the configure endpoint
1929 * command completes. We can't subtract the dropped endpoints from the number
1930 * of active endpoints until the command completes because we can oversubscribe
1931 * the host in this case:
1932 *
1933 * - the first configure endpoint command drops more endpoints than it adds
1934 * - a second configure endpoint command that adds more endpoints is queued
1935 * - the first configure endpoint command fails, so the config is unchanged
1936 * - the second command may succeed, even though there isn't enough resources
1937 *
1938 * Must be called with xhci->lock held.
1939 */
1940static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
1941 struct xhci_input_control_ctx *ctrl_ctx)
1942{
1943 u32 added_eps;
1944
1945 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
1946 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1947 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1948 "Not enough ep ctxs: "
1949 "%u active, need to add %u, limit is %u.",
1950 xhci->num_active_eps, added_eps,
1951 xhci->limit_active_eps);
1952 return -ENOMEM;
1953 }
1954 xhci->num_active_eps += added_eps;
1955 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1956 "Adding %u ep ctxs, %u now active.", added_eps,
1957 xhci->num_active_eps);
1958 return 0;
1959}
1960
1961/*
1962 * The configure endpoint was failed by the xHC for some other reason, so we
1963 * need to revert the resources that failed configuration would have used.
1964 *
1965 * Must be called with xhci->lock held.
1966 */
1967static void xhci_free_host_resources(struct xhci_hcd *xhci,
1968 struct xhci_input_control_ctx *ctrl_ctx)
1969{
1970 u32 num_failed_eps;
1971
1972 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
1973 xhci->num_active_eps -= num_failed_eps;
1974 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1975 "Removing %u failed ep ctxs, %u now active.",
1976 num_failed_eps,
1977 xhci->num_active_eps);
1978}
1979
1980/*
1981 * Now that the command has completed, clean up the active endpoint count by
1982 * subtracting out the endpoints that were dropped (but not changed).
1983 *
1984 * Must be called with xhci->lock held.
1985 */
1986static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
1987 struct xhci_input_control_ctx *ctrl_ctx)
1988{
1989 u32 num_dropped_eps;
1990
1991 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
1992 xhci->num_active_eps -= num_dropped_eps;
1993 if (num_dropped_eps)
1994 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1995 "Removing %u dropped ep ctxs, %u now active.",
1996 num_dropped_eps,
1997 xhci->num_active_eps);
1998}
1999
2000static unsigned int xhci_get_block_size(struct usb_device *udev)
2001{
2002 switch (udev->speed) {
2003 case USB_SPEED_LOW:
2004 case USB_SPEED_FULL:
2005 return FS_BLOCK;
2006 case USB_SPEED_HIGH:
2007 return HS_BLOCK;
2008 case USB_SPEED_SUPER:
2009 return SS_BLOCK;
2010 case USB_SPEED_UNKNOWN:
2011 case USB_SPEED_WIRELESS:
2012 default:
2013 /* Should never happen */
2014 return 1;
2015 }
2016}
2017
2018static unsigned int
2019xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2020{
2021 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2022 return LS_OVERHEAD;
2023 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2024 return FS_OVERHEAD;
2025 return HS_OVERHEAD;
2026}
2027
2028/* If we are changing a LS/FS device under a HS hub,
2029 * make sure (if we are activating a new TT) that the HS bus has enough
2030 * bandwidth for this new TT.
2031 */
2032static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2033 struct xhci_virt_device *virt_dev,
2034 int old_active_eps)
2035{
2036 struct xhci_interval_bw_table *bw_table;
2037 struct xhci_tt_bw_info *tt_info;
2038
2039 /* Find the bandwidth table for the root port this TT is attached to. */
2040 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2041 tt_info = virt_dev->tt_info;
2042 /* If this TT already had active endpoints, the bandwidth for this TT
2043 * has already been added. Removing all periodic endpoints (and thus
2044 * making the TT enactive) will only decrease the bandwidth used.
2045 */
2046 if (old_active_eps)
2047 return 0;
2048 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2049 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2050 return -ENOMEM;
2051 return 0;
2052 }
2053 /* Not sure why we would have no new active endpoints...
2054 *
2055 * Maybe because of an Evaluate Context change for a hub update or a
2056 * control endpoint 0 max packet size change?
2057 * FIXME: skip the bandwidth calculation in that case.
2058 */
2059 return 0;
2060}
2061
2062static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2063 struct xhci_virt_device *virt_dev)
2064{
2065 unsigned int bw_reserved;
2066
2067 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2068 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2069 return -ENOMEM;
2070
2071 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2072 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2073 return -ENOMEM;
2074
2075 return 0;
2076}
2077
2078/*
2079 * This algorithm is a very conservative estimate of the worst-case scheduling
2080 * scenario for any one interval. The hardware dynamically schedules the
2081 * packets, so we can't tell which microframe could be the limiting factor in
2082 * the bandwidth scheduling. This only takes into account periodic endpoints.
2083 *
2084 * Obviously, we can't solve an NP complete problem to find the minimum worst
2085 * case scenario. Instead, we come up with an estimate that is no less than
2086 * the worst case bandwidth used for any one microframe, but may be an
2087 * over-estimate.
2088 *
2089 * We walk the requirements for each endpoint by interval, starting with the
2090 * smallest interval, and place packets in the schedule where there is only one
2091 * possible way to schedule packets for that interval. In order to simplify
2092 * this algorithm, we record the largest max packet size for each interval, and
2093 * assume all packets will be that size.
2094 *
2095 * For interval 0, we obviously must schedule all packets for each interval.
2096 * The bandwidth for interval 0 is just the amount of data to be transmitted
2097 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2098 * the number of packets).
2099 *
2100 * For interval 1, we have two possible microframes to schedule those packets
2101 * in. For this algorithm, if we can schedule the same number of packets for
2102 * each possible scheduling opportunity (each microframe), we will do so. The
2103 * remaining number of packets will be saved to be transmitted in the gaps in
2104 * the next interval's scheduling sequence.
2105 *
2106 * As we move those remaining packets to be scheduled with interval 2 packets,
2107 * we have to double the number of remaining packets to transmit. This is
2108 * because the intervals are actually powers of 2, and we would be transmitting
2109 * the previous interval's packets twice in this interval. We also have to be
2110 * sure that when we look at the largest max packet size for this interval, we
2111 * also look at the largest max packet size for the remaining packets and take
2112 * the greater of the two.
2113 *
2114 * The algorithm continues to evenly distribute packets in each scheduling
2115 * opportunity, and push the remaining packets out, until we get to the last
2116 * interval. Then those packets and their associated overhead are just added
2117 * to the bandwidth used.
2118 */
2119static int xhci_check_bw_table(struct xhci_hcd *xhci,
2120 struct xhci_virt_device *virt_dev,
2121 int old_active_eps)
2122{
2123 unsigned int bw_reserved;
2124 unsigned int max_bandwidth;
2125 unsigned int bw_used;
2126 unsigned int block_size;
2127 struct xhci_interval_bw_table *bw_table;
2128 unsigned int packet_size = 0;
2129 unsigned int overhead = 0;
2130 unsigned int packets_transmitted = 0;
2131 unsigned int packets_remaining = 0;
2132 unsigned int i;
2133
2134 if (virt_dev->udev->speed == USB_SPEED_SUPER)
2135 return xhci_check_ss_bw(xhci, virt_dev);
2136
2137 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2138 max_bandwidth = HS_BW_LIMIT;
2139 /* Convert percent of bus BW reserved to blocks reserved */
2140 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2141 } else {
2142 max_bandwidth = FS_BW_LIMIT;
2143 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2144 }
2145
2146 bw_table = virt_dev->bw_table;
2147 /* We need to translate the max packet size and max ESIT payloads into
2148 * the units the hardware uses.
2149 */
2150 block_size = xhci_get_block_size(virt_dev->udev);
2151
2152 /* If we are manipulating a LS/FS device under a HS hub, double check
2153 * that the HS bus has enough bandwidth if we are activing a new TT.
2154 */
2155 if (virt_dev->tt_info) {
2156 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2157 "Recalculating BW for rootport %u",
2158 virt_dev->real_port);
2159 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2160 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2161 "newly activated TT.\n");
2162 return -ENOMEM;
2163 }
2164 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2165 "Recalculating BW for TT slot %u port %u",
2166 virt_dev->tt_info->slot_id,
2167 virt_dev->tt_info->ttport);
2168 } else {
2169 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2170 "Recalculating BW for rootport %u",
2171 virt_dev->real_port);
2172 }
2173
2174 /* Add in how much bandwidth will be used for interval zero, or the
2175 * rounded max ESIT payload + number of packets * largest overhead.
2176 */
2177 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2178 bw_table->interval_bw[0].num_packets *
2179 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2180
2181 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2182 unsigned int bw_added;
2183 unsigned int largest_mps;
2184 unsigned int interval_overhead;
2185
2186 /*
2187 * How many packets could we transmit in this interval?
2188 * If packets didn't fit in the previous interval, we will need
2189 * to transmit that many packets twice within this interval.
2190 */
2191 packets_remaining = 2 * packets_remaining +
2192 bw_table->interval_bw[i].num_packets;
2193
2194 /* Find the largest max packet size of this or the previous
2195 * interval.
2196 */
2197 if (list_empty(&bw_table->interval_bw[i].endpoints))
2198 largest_mps = 0;
2199 else {
2200 struct xhci_virt_ep *virt_ep;
2201 struct list_head *ep_entry;
2202
2203 ep_entry = bw_table->interval_bw[i].endpoints.next;
2204 virt_ep = list_entry(ep_entry,
2205 struct xhci_virt_ep, bw_endpoint_list);
2206 /* Convert to blocks, rounding up */
2207 largest_mps = DIV_ROUND_UP(
2208 virt_ep->bw_info.max_packet_size,
2209 block_size);
2210 }
2211 if (largest_mps > packet_size)
2212 packet_size = largest_mps;
2213
2214 /* Use the larger overhead of this or the previous interval. */
2215 interval_overhead = xhci_get_largest_overhead(
2216 &bw_table->interval_bw[i]);
2217 if (interval_overhead > overhead)
2218 overhead = interval_overhead;
2219
2220 /* How many packets can we evenly distribute across
2221 * (1 << (i + 1)) possible scheduling opportunities?
2222 */
2223 packets_transmitted = packets_remaining >> (i + 1);
2224
2225 /* Add in the bandwidth used for those scheduled packets */
2226 bw_added = packets_transmitted * (overhead + packet_size);
2227
2228 /* How many packets do we have remaining to transmit? */
2229 packets_remaining = packets_remaining % (1 << (i + 1));
2230
2231 /* What largest max packet size should those packets have? */
2232 /* If we've transmitted all packets, don't carry over the
2233 * largest packet size.
2234 */
2235 if (packets_remaining == 0) {
2236 packet_size = 0;
2237 overhead = 0;
2238 } else if (packets_transmitted > 0) {
2239 /* Otherwise if we do have remaining packets, and we've
2240 * scheduled some packets in this interval, take the
2241 * largest max packet size from endpoints with this
2242 * interval.
2243 */
2244 packet_size = largest_mps;
2245 overhead = interval_overhead;
2246 }
2247 /* Otherwise carry over packet_size and overhead from the last
2248 * time we had a remainder.
2249 */
2250 bw_used += bw_added;
2251 if (bw_used > max_bandwidth) {
2252 xhci_warn(xhci, "Not enough bandwidth. "
2253 "Proposed: %u, Max: %u\n",
2254 bw_used, max_bandwidth);
2255 return -ENOMEM;
2256 }
2257 }
2258 /*
2259 * Ok, we know we have some packets left over after even-handedly
2260 * scheduling interval 15. We don't know which microframes they will
2261 * fit into, so we over-schedule and say they will be scheduled every
2262 * microframe.
2263 */
2264 if (packets_remaining > 0)
2265 bw_used += overhead + packet_size;
2266
2267 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2268 unsigned int port_index = virt_dev->real_port - 1;
2269
2270 /* OK, we're manipulating a HS device attached to a
2271 * root port bandwidth domain. Include the number of active TTs
2272 * in the bandwidth used.
2273 */
2274 bw_used += TT_HS_OVERHEAD *
2275 xhci->rh_bw[port_index].num_active_tts;
2276 }
2277
2278 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2279 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2280 "Available: %u " "percent",
2281 bw_used, max_bandwidth, bw_reserved,
2282 (max_bandwidth - bw_used - bw_reserved) * 100 /
2283 max_bandwidth);
2284
2285 bw_used += bw_reserved;
2286 if (bw_used > max_bandwidth) {
2287 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2288 bw_used, max_bandwidth);
2289 return -ENOMEM;
2290 }
2291
2292 bw_table->bw_used = bw_used;
2293 return 0;
2294}
2295
2296static bool xhci_is_async_ep(unsigned int ep_type)
2297{
2298 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2299 ep_type != ISOC_IN_EP &&
2300 ep_type != INT_IN_EP);
2301}
2302
2303static bool xhci_is_sync_in_ep(unsigned int ep_type)
2304{
2305 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2306}
2307
2308static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2309{
2310 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2311
2312 if (ep_bw->ep_interval == 0)
2313 return SS_OVERHEAD_BURST +
2314 (ep_bw->mult * ep_bw->num_packets *
2315 (SS_OVERHEAD + mps));
2316 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2317 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2318 1 << ep_bw->ep_interval);
2319
2320}
2321
2322void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2323 struct xhci_bw_info *ep_bw,
2324 struct xhci_interval_bw_table *bw_table,
2325 struct usb_device *udev,
2326 struct xhci_virt_ep *virt_ep,
2327 struct xhci_tt_bw_info *tt_info)
2328{
2329 struct xhci_interval_bw *interval_bw;
2330 int normalized_interval;
2331
2332 if (xhci_is_async_ep(ep_bw->type))
2333 return;
2334
2335 if (udev->speed == USB_SPEED_SUPER) {
2336 if (xhci_is_sync_in_ep(ep_bw->type))
2337 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2338 xhci_get_ss_bw_consumed(ep_bw);
2339 else
2340 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2341 xhci_get_ss_bw_consumed(ep_bw);
2342 return;
2343 }
2344
2345 /* SuperSpeed endpoints never get added to intervals in the table, so
2346 * this check is only valid for HS/FS/LS devices.
2347 */
2348 if (list_empty(&virt_ep->bw_endpoint_list))
2349 return;
2350 /* For LS/FS devices, we need to translate the interval expressed in
2351 * microframes to frames.
2352 */
2353 if (udev->speed == USB_SPEED_HIGH)
2354 normalized_interval = ep_bw->ep_interval;
2355 else
2356 normalized_interval = ep_bw->ep_interval - 3;
2357
2358 if (normalized_interval == 0)
2359 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2360 interval_bw = &bw_table->interval_bw[normalized_interval];
2361 interval_bw->num_packets -= ep_bw->num_packets;
2362 switch (udev->speed) {
2363 case USB_SPEED_LOW:
2364 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2365 break;
2366 case USB_SPEED_FULL:
2367 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2368 break;
2369 case USB_SPEED_HIGH:
2370 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2371 break;
2372 case USB_SPEED_SUPER:
2373 case USB_SPEED_UNKNOWN:
2374 case USB_SPEED_WIRELESS:
2375 /* Should never happen because only LS/FS/HS endpoints will get
2376 * added to the endpoint list.
2377 */
2378 return;
2379 }
2380 if (tt_info)
2381 tt_info->active_eps -= 1;
2382 list_del_init(&virt_ep->bw_endpoint_list);
2383}
2384
2385static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2386 struct xhci_bw_info *ep_bw,
2387 struct xhci_interval_bw_table *bw_table,
2388 struct usb_device *udev,
2389 struct xhci_virt_ep *virt_ep,
2390 struct xhci_tt_bw_info *tt_info)
2391{
2392 struct xhci_interval_bw *interval_bw;
2393 struct xhci_virt_ep *smaller_ep;
2394 int normalized_interval;
2395
2396 if (xhci_is_async_ep(ep_bw->type))
2397 return;
2398
2399 if (udev->speed == USB_SPEED_SUPER) {
2400 if (xhci_is_sync_in_ep(ep_bw->type))
2401 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2402 xhci_get_ss_bw_consumed(ep_bw);
2403 else
2404 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2405 xhci_get_ss_bw_consumed(ep_bw);
2406 return;
2407 }
2408
2409 /* For LS/FS devices, we need to translate the interval expressed in
2410 * microframes to frames.
2411 */
2412 if (udev->speed == USB_SPEED_HIGH)
2413 normalized_interval = ep_bw->ep_interval;
2414 else
2415 normalized_interval = ep_bw->ep_interval - 3;
2416
2417 if (normalized_interval == 0)
2418 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2419 interval_bw = &bw_table->interval_bw[normalized_interval];
2420 interval_bw->num_packets += ep_bw->num_packets;
2421 switch (udev->speed) {
2422 case USB_SPEED_LOW:
2423 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2424 break;
2425 case USB_SPEED_FULL:
2426 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2427 break;
2428 case USB_SPEED_HIGH:
2429 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2430 break;
2431 case USB_SPEED_SUPER:
2432 case USB_SPEED_UNKNOWN:
2433 case USB_SPEED_WIRELESS:
2434 /* Should never happen because only LS/FS/HS endpoints will get
2435 * added to the endpoint list.
2436 */
2437 return;
2438 }
2439
2440 if (tt_info)
2441 tt_info->active_eps += 1;
2442 /* Insert the endpoint into the list, largest max packet size first. */
2443 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2444 bw_endpoint_list) {
2445 if (ep_bw->max_packet_size >=
2446 smaller_ep->bw_info.max_packet_size) {
2447 /* Add the new ep before the smaller endpoint */
2448 list_add_tail(&virt_ep->bw_endpoint_list,
2449 &smaller_ep->bw_endpoint_list);
2450 return;
2451 }
2452 }
2453 /* Add the new endpoint at the end of the list. */
2454 list_add_tail(&virt_ep->bw_endpoint_list,
2455 &interval_bw->endpoints);
2456}
2457
2458void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2459 struct xhci_virt_device *virt_dev,
2460 int old_active_eps)
2461{
2462 struct xhci_root_port_bw_info *rh_bw_info;
2463 if (!virt_dev->tt_info)
2464 return;
2465
2466 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2467 if (old_active_eps == 0 &&
2468 virt_dev->tt_info->active_eps != 0) {
2469 rh_bw_info->num_active_tts += 1;
2470 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2471 } else if (old_active_eps != 0 &&
2472 virt_dev->tt_info->active_eps == 0) {
2473 rh_bw_info->num_active_tts -= 1;
2474 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2475 }
2476}
2477
2478static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2479 struct xhci_virt_device *virt_dev,
2480 struct xhci_container_ctx *in_ctx)
2481{
2482 struct xhci_bw_info ep_bw_info[31];
2483 int i;
2484 struct xhci_input_control_ctx *ctrl_ctx;
2485 int old_active_eps = 0;
2486
2487 if (virt_dev->tt_info)
2488 old_active_eps = virt_dev->tt_info->active_eps;
2489
2490 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
2491 if (!ctrl_ctx) {
2492 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2493 __func__);
2494 return -ENOMEM;
2495 }
2496
2497 for (i = 0; i < 31; i++) {
2498 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2499 continue;
2500
2501 /* Make a copy of the BW info in case we need to revert this */
2502 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2503 sizeof(ep_bw_info[i]));
2504 /* Drop the endpoint from the interval table if the endpoint is
2505 * being dropped or changed.
2506 */
2507 if (EP_IS_DROPPED(ctrl_ctx, i))
2508 xhci_drop_ep_from_interval_table(xhci,
2509 &virt_dev->eps[i].bw_info,
2510 virt_dev->bw_table,
2511 virt_dev->udev,
2512 &virt_dev->eps[i],
2513 virt_dev->tt_info);
2514 }
2515 /* Overwrite the information stored in the endpoints' bw_info */
2516 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2517 for (i = 0; i < 31; i++) {
2518 /* Add any changed or added endpoints to the interval table */
2519 if (EP_IS_ADDED(ctrl_ctx, i))
2520 xhci_add_ep_to_interval_table(xhci,
2521 &virt_dev->eps[i].bw_info,
2522 virt_dev->bw_table,
2523 virt_dev->udev,
2524 &virt_dev->eps[i],
2525 virt_dev->tt_info);
2526 }
2527
2528 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2529 /* Ok, this fits in the bandwidth we have.
2530 * Update the number of active TTs.
2531 */
2532 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2533 return 0;
2534 }
2535
2536 /* We don't have enough bandwidth for this, revert the stored info. */
2537 for (i = 0; i < 31; i++) {
2538 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2539 continue;
2540
2541 /* Drop the new copies of any added or changed endpoints from
2542 * the interval table.
2543 */
2544 if (EP_IS_ADDED(ctrl_ctx, i)) {
2545 xhci_drop_ep_from_interval_table(xhci,
2546 &virt_dev->eps[i].bw_info,
2547 virt_dev->bw_table,
2548 virt_dev->udev,
2549 &virt_dev->eps[i],
2550 virt_dev->tt_info);
2551 }
2552 /* Revert the endpoint back to its old information */
2553 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2554 sizeof(ep_bw_info[i]));
2555 /* Add any changed or dropped endpoints back into the table */
2556 if (EP_IS_DROPPED(ctrl_ctx, i))
2557 xhci_add_ep_to_interval_table(xhci,
2558 &virt_dev->eps[i].bw_info,
2559 virt_dev->bw_table,
2560 virt_dev->udev,
2561 &virt_dev->eps[i],
2562 virt_dev->tt_info);
2563 }
2564 return -ENOMEM;
2565}
2566
2567
2568/* Issue a configure endpoint command or evaluate context command
2569 * and wait for it to finish.
2570 */
2571static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2572 struct usb_device *udev,
2573 struct xhci_command *command,
2574 bool ctx_change, bool must_succeed)
2575{
2576 int ret;
2577 int timeleft;
2578 unsigned long flags;
2579 struct xhci_container_ctx *in_ctx;
2580 struct xhci_input_control_ctx *ctrl_ctx;
2581 struct completion *cmd_completion;
2582 u32 *cmd_status;
2583 struct xhci_virt_device *virt_dev;
2584 union xhci_trb *cmd_trb;
2585
2586 spin_lock_irqsave(&xhci->lock, flags);
2587 virt_dev = xhci->devs[udev->slot_id];
2588
2589 if (command)
2590 in_ctx = command->in_ctx;
2591 else
2592 in_ctx = virt_dev->in_ctx;
2593 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
2594 if (!ctrl_ctx) {
2595 spin_unlock_irqrestore(&xhci->lock, flags);
2596 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2597 __func__);
2598 return -ENOMEM;
2599 }
2600
2601 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2602 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2603 spin_unlock_irqrestore(&xhci->lock, flags);
2604 xhci_warn(xhci, "Not enough host resources, "
2605 "active endpoint contexts = %u\n",
2606 xhci->num_active_eps);
2607 return -ENOMEM;
2608 }
2609 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2610 xhci_reserve_bandwidth(xhci, virt_dev, in_ctx)) {
2611 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2612 xhci_free_host_resources(xhci, ctrl_ctx);
2613 spin_unlock_irqrestore(&xhci->lock, flags);
2614 xhci_warn(xhci, "Not enough bandwidth\n");
2615 return -ENOMEM;
2616 }
2617
2618 if (command) {
2619 cmd_completion = command->completion;
2620 cmd_status = &command->status;
2621 command->command_trb = xhci_find_next_enqueue(xhci->cmd_ring);
2622 list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
2623 } else {
2624 cmd_completion = &virt_dev->cmd_completion;
2625 cmd_status = &virt_dev->cmd_status;
2626 }
2627 init_completion(cmd_completion);
2628
2629 cmd_trb = xhci_find_next_enqueue(xhci->cmd_ring);
2630 if (!ctx_change)
2631 ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
2632 udev->slot_id, must_succeed);
2633 else
2634 ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
2635 udev->slot_id, must_succeed);
2636 if (ret < 0) {
2637 if (command)
2638 list_del(&command->cmd_list);
2639 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2640 xhci_free_host_resources(xhci, ctrl_ctx);
2641 spin_unlock_irqrestore(&xhci->lock, flags);
2642 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2643 "FIXME allocate a new ring segment");
2644 return -ENOMEM;
2645 }
2646 xhci_ring_cmd_db(xhci);
2647 spin_unlock_irqrestore(&xhci->lock, flags);
2648
2649 /* Wait for the configure endpoint command to complete */
2650 timeleft = wait_for_completion_interruptible_timeout(
2651 cmd_completion,
2652 XHCI_CMD_DEFAULT_TIMEOUT);
2653 if (timeleft <= 0) {
2654 xhci_warn(xhci, "%s while waiting for %s command\n",
2655 timeleft == 0 ? "Timeout" : "Signal",
2656 ctx_change == 0 ?
2657 "configure endpoint" :
2658 "evaluate context");
2659 /* cancel the configure endpoint command */
2660 ret = xhci_cancel_cmd(xhci, command, cmd_trb);
2661 if (ret < 0)
2662 return ret;
2663 return -ETIME;
2664 }
2665
2666 if (!ctx_change)
2667 ret = xhci_configure_endpoint_result(xhci, udev, cmd_status);
2668 else
2669 ret = xhci_evaluate_context_result(xhci, udev, cmd_status);
2670
2671 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2672 spin_lock_irqsave(&xhci->lock, flags);
2673 /* If the command failed, remove the reserved resources.
2674 * Otherwise, clean up the estimate to include dropped eps.
2675 */
2676 if (ret)
2677 xhci_free_host_resources(xhci, ctrl_ctx);
2678 else
2679 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2680 spin_unlock_irqrestore(&xhci->lock, flags);
2681 }
2682 return ret;
2683}
2684
2685static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2686 struct xhci_virt_device *vdev, int i)
2687{
2688 struct xhci_virt_ep *ep = &vdev->eps[i];
2689
2690 if (ep->ep_state & EP_HAS_STREAMS) {
2691 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2692 xhci_get_endpoint_address(i));
2693 xhci_free_stream_info(xhci, ep->stream_info);
2694 ep->stream_info = NULL;
2695 ep->ep_state &= ~EP_HAS_STREAMS;
2696 }
2697}
2698
2699/* Called after one or more calls to xhci_add_endpoint() or
2700 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2701 * to call xhci_reset_bandwidth().
2702 *
2703 * Since we are in the middle of changing either configuration or
2704 * installing a new alt setting, the USB core won't allow URBs to be
2705 * enqueued for any endpoint on the old config or interface. Nothing
2706 * else should be touching the xhci->devs[slot_id] structure, so we
2707 * don't need to take the xhci->lock for manipulating that.
2708 */
2709int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2710{
2711 int i;
2712 int ret = 0;
2713 struct xhci_hcd *xhci;
2714 struct xhci_virt_device *virt_dev;
2715 struct xhci_input_control_ctx *ctrl_ctx;
2716 struct xhci_slot_ctx *slot_ctx;
2717
2718 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2719 if (ret <= 0)
2720 return ret;
2721 xhci = hcd_to_xhci(hcd);
2722 if (xhci->xhc_state & XHCI_STATE_DYING)
2723 return -ENODEV;
2724
2725 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2726 virt_dev = xhci->devs[udev->slot_id];
2727
2728 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2729 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
2730 if (!ctrl_ctx) {
2731 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2732 __func__);
2733 return -ENOMEM;
2734 }
2735 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2736 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2737 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2738
2739 /* Don't issue the command if there's no endpoints to update. */
2740 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2741 ctrl_ctx->drop_flags == 0)
2742 return 0;
2743
2744 xhci_dbg(xhci, "New Input Control Context:\n");
2745 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2746 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2747 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2748
2749 ret = xhci_configure_endpoint(xhci, udev, NULL,
2750 false, false);
2751 if (ret) {
2752 /* Callee should call reset_bandwidth() */
2753 return ret;
2754 }
2755
2756 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2757 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2758 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2759
2760 /* Free any rings that were dropped, but not changed. */
2761 for (i = 1; i < 31; ++i) {
2762 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2763 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2764 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2765 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2766 }
2767 }
2768 xhci_zero_in_ctx(xhci, virt_dev);
2769 /*
2770 * Install any rings for completely new endpoints or changed endpoints,
2771 * and free or cache any old rings from changed endpoints.
2772 */
2773 for (i = 1; i < 31; ++i) {
2774 if (!virt_dev->eps[i].new_ring)
2775 continue;
2776 /* Only cache or free the old ring if it exists.
2777 * It may not if this is the first add of an endpoint.
2778 */
2779 if (virt_dev->eps[i].ring) {
2780 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2781 }
2782 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2783 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2784 virt_dev->eps[i].new_ring = NULL;
2785 }
2786
2787 return ret;
2788}
2789
2790void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2791{
2792 struct xhci_hcd *xhci;
2793 struct xhci_virt_device *virt_dev;
2794 int i, ret;
2795
2796 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2797 if (ret <= 0)
2798 return;
2799 xhci = hcd_to_xhci(hcd);
2800
2801 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2802 virt_dev = xhci->devs[udev->slot_id];
2803 /* Free any rings allocated for added endpoints */
2804 for (i = 0; i < 31; ++i) {
2805 if (virt_dev->eps[i].new_ring) {
2806 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2807 virt_dev->eps[i].new_ring = NULL;
2808 }
2809 }
2810 xhci_zero_in_ctx(xhci, virt_dev);
2811}
2812
2813static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2814 struct xhci_container_ctx *in_ctx,
2815 struct xhci_container_ctx *out_ctx,
2816 struct xhci_input_control_ctx *ctrl_ctx,
2817 u32 add_flags, u32 drop_flags)
2818{
2819 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2820 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2821 xhci_slot_copy(xhci, in_ctx, out_ctx);
2822 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2823
2824 xhci_dbg(xhci, "Input Context:\n");
2825 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2826}
2827
2828static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2829 unsigned int slot_id, unsigned int ep_index,
2830 struct xhci_dequeue_state *deq_state)
2831{
2832 struct xhci_input_control_ctx *ctrl_ctx;
2833 struct xhci_container_ctx *in_ctx;
2834 struct xhci_ep_ctx *ep_ctx;
2835 u32 added_ctxs;
2836 dma_addr_t addr;
2837
2838 in_ctx = xhci->devs[slot_id]->in_ctx;
2839 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
2840 if (!ctrl_ctx) {
2841 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2842 __func__);
2843 return;
2844 }
2845
2846 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2847 xhci->devs[slot_id]->out_ctx, ep_index);
2848 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2849 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2850 deq_state->new_deq_ptr);
2851 if (addr == 0) {
2852 xhci_warn(xhci, "WARN Cannot submit config ep after "
2853 "reset ep command\n");
2854 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2855 deq_state->new_deq_seg,
2856 deq_state->new_deq_ptr);
2857 return;
2858 }
2859 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2860
2861 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2862 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2863 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2864 added_ctxs, added_ctxs);
2865}
2866
2867void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2868 struct usb_device *udev, unsigned int ep_index)
2869{
2870 struct xhci_dequeue_state deq_state;
2871 struct xhci_virt_ep *ep;
2872
2873 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2874 "Cleaning up stalled endpoint ring");
2875 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2876 /* We need to move the HW's dequeue pointer past this TD,
2877 * or it will attempt to resend it on the next doorbell ring.
2878 */
2879 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2880 ep_index, ep->stopped_stream, ep->stopped_td,
2881 &deq_state);
2882
2883 /* HW with the reset endpoint quirk will use the saved dequeue state to
2884 * issue a configure endpoint command later.
2885 */
2886 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2887 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2888 "Queueing new dequeue state");
2889 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2890 ep_index, ep->stopped_stream, &deq_state);
2891 } else {
2892 /* Better hope no one uses the input context between now and the
2893 * reset endpoint completion!
2894 * XXX: No idea how this hardware will react when stream rings
2895 * are enabled.
2896 */
2897 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2898 "Setting up input context for "
2899 "configure endpoint command");
2900 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2901 ep_index, &deq_state);
2902 }
2903}
2904
2905/* Deal with stalled endpoints. The core should have sent the control message
2906 * to clear the halt condition. However, we need to make the xHCI hardware
2907 * reset its sequence number, since a device will expect a sequence number of
2908 * zero after the halt condition is cleared.
2909 * Context: in_interrupt
2910 */
2911void xhci_endpoint_reset(struct usb_hcd *hcd,
2912 struct usb_host_endpoint *ep)
2913{
2914 struct xhci_hcd *xhci;
2915 struct usb_device *udev;
2916 unsigned int ep_index;
2917 unsigned long flags;
2918 int ret;
2919 struct xhci_virt_ep *virt_ep;
2920
2921 xhci = hcd_to_xhci(hcd);
2922 udev = (struct usb_device *) ep->hcpriv;
2923 /* Called with a root hub endpoint (or an endpoint that wasn't added
2924 * with xhci_add_endpoint()
2925 */
2926 if (!ep->hcpriv)
2927 return;
2928 ep_index = xhci_get_endpoint_index(&ep->desc);
2929 virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2930 if (!virt_ep->stopped_td) {
2931 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2932 "Endpoint 0x%x not halted, refusing to reset.",
2933 ep->desc.bEndpointAddress);
2934 return;
2935 }
2936 if (usb_endpoint_xfer_control(&ep->desc)) {
2937 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2938 "Control endpoint stall already handled.");
2939 return;
2940 }
2941
2942 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2943 "Queueing reset endpoint command");
2944 spin_lock_irqsave(&xhci->lock, flags);
2945 ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index);
2946 /*
2947 * Can't change the ring dequeue pointer until it's transitioned to the
2948 * stopped state, which is only upon a successful reset endpoint
2949 * command. Better hope that last command worked!
2950 */
2951 if (!ret) {
2952 xhci_cleanup_stalled_ring(xhci, udev, ep_index);
2953 kfree(virt_ep->stopped_td);
2954 xhci_ring_cmd_db(xhci);
2955 }
2956 virt_ep->stopped_td = NULL;
2957 virt_ep->stopped_stream = 0;
2958 spin_unlock_irqrestore(&xhci->lock, flags);
2959
2960 if (ret)
2961 xhci_warn(xhci, "FIXME allocate a new ring segment\n");
2962}
2963
2964static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2965 struct usb_device *udev, struct usb_host_endpoint *ep,
2966 unsigned int slot_id)
2967{
2968 int ret;
2969 unsigned int ep_index;
2970 unsigned int ep_state;
2971
2972 if (!ep)
2973 return -EINVAL;
2974 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
2975 if (ret <= 0)
2976 return -EINVAL;
2977 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
2978 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2979 " descriptor for ep 0x%x does not support streams\n",
2980 ep->desc.bEndpointAddress);
2981 return -EINVAL;
2982 }
2983
2984 ep_index = xhci_get_endpoint_index(&ep->desc);
2985 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2986 if (ep_state & EP_HAS_STREAMS ||
2987 ep_state & EP_GETTING_STREAMS) {
2988 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2989 "already has streams set up.\n",
2990 ep->desc.bEndpointAddress);
2991 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2992 "dynamic stream context array reallocation.\n");
2993 return -EINVAL;
2994 }
2995 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2996 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
2997 "endpoint 0x%x; URBs are pending.\n",
2998 ep->desc.bEndpointAddress);
2999 return -EINVAL;
3000 }
3001 return 0;
3002}
3003
3004static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3005 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3006{
3007 unsigned int max_streams;
3008
3009 /* The stream context array size must be a power of two */
3010 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3011 /*
3012 * Find out how many primary stream array entries the host controller
3013 * supports. Later we may use secondary stream arrays (similar to 2nd
3014 * level page entries), but that's an optional feature for xHCI host
3015 * controllers. xHCs must support at least 4 stream IDs.
3016 */
3017 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3018 if (*num_stream_ctxs > max_streams) {
3019 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3020 max_streams);
3021 *num_stream_ctxs = max_streams;
3022 *num_streams = max_streams;
3023 }
3024}
3025
3026/* Returns an error code if one of the endpoint already has streams.
3027 * This does not change any data structures, it only checks and gathers
3028 * information.
3029 */
3030static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3031 struct usb_device *udev,
3032 struct usb_host_endpoint **eps, unsigned int num_eps,
3033 unsigned int *num_streams, u32 *changed_ep_bitmask)
3034{
3035 unsigned int max_streams;
3036 unsigned int endpoint_flag;
3037 int i;
3038 int ret;
3039
3040 for (i = 0; i < num_eps; i++) {
3041 ret = xhci_check_streams_endpoint(xhci, udev,
3042 eps[i], udev->slot_id);
3043 if (ret < 0)
3044 return ret;
3045
3046 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3047 if (max_streams < (*num_streams - 1)) {
3048 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3049 eps[i]->desc.bEndpointAddress,
3050 max_streams);
3051 *num_streams = max_streams+1;
3052 }
3053
3054 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3055 if (*changed_ep_bitmask & endpoint_flag)
3056 return -EINVAL;
3057 *changed_ep_bitmask |= endpoint_flag;
3058 }
3059 return 0;
3060}
3061
3062static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3063 struct usb_device *udev,
3064 struct usb_host_endpoint **eps, unsigned int num_eps)
3065{
3066 u32 changed_ep_bitmask = 0;
3067 unsigned int slot_id;
3068 unsigned int ep_index;
3069 unsigned int ep_state;
3070 int i;
3071
3072 slot_id = udev->slot_id;
3073 if (!xhci->devs[slot_id])
3074 return 0;
3075
3076 for (i = 0; i < num_eps; i++) {
3077 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3078 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3079 /* Are streams already being freed for the endpoint? */
3080 if (ep_state & EP_GETTING_NO_STREAMS) {
3081 xhci_warn(xhci, "WARN Can't disable streams for "
3082 "endpoint 0x%x, "
3083 "streams are being disabled already\n",
3084 eps[i]->desc.bEndpointAddress);
3085 return 0;
3086 }
3087 /* Are there actually any streams to free? */
3088 if (!(ep_state & EP_HAS_STREAMS) &&
3089 !(ep_state & EP_GETTING_STREAMS)) {
3090 xhci_warn(xhci, "WARN Can't disable streams for "
3091 "endpoint 0x%x, "
3092 "streams are already disabled!\n",
3093 eps[i]->desc.bEndpointAddress);
3094 xhci_warn(xhci, "WARN xhci_free_streams() called "
3095 "with non-streams endpoint\n");
3096 return 0;
3097 }
3098 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3099 }
3100 return changed_ep_bitmask;
3101}
3102
3103/*
3104 * The USB device drivers use this function (though the HCD interface in USB
3105 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3106 * coordinate mass storage command queueing across multiple endpoints (basically
3107 * a stream ID == a task ID).
3108 *
3109 * Setting up streams involves allocating the same size stream context array
3110 * for each endpoint and issuing a configure endpoint command for all endpoints.
3111 *
3112 * Don't allow the call to succeed if one endpoint only supports one stream
3113 * (which means it doesn't support streams at all).
3114 *
3115 * Drivers may get less stream IDs than they asked for, if the host controller
3116 * hardware or endpoints claim they can't support the number of requested
3117 * stream IDs.
3118 */
3119int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3120 struct usb_host_endpoint **eps, unsigned int num_eps,
3121 unsigned int num_streams, gfp_t mem_flags)
3122{
3123 int i, ret;
3124 struct xhci_hcd *xhci;
3125 struct xhci_virt_device *vdev;
3126 struct xhci_command *config_cmd;
3127 struct xhci_input_control_ctx *ctrl_ctx;
3128 unsigned int ep_index;
3129 unsigned int num_stream_ctxs;
3130 unsigned long flags;
3131 u32 changed_ep_bitmask = 0;
3132
3133 if (!eps)
3134 return -EINVAL;
3135
3136 /* Add one to the number of streams requested to account for
3137 * stream 0 that is reserved for xHCI usage.
3138 */
3139 num_streams += 1;
3140 xhci = hcd_to_xhci(hcd);
3141 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3142 num_streams);
3143
3144 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3145 if (HCC_MAX_PSA(xhci->hcc_params) < 4) {
3146 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3147 return -ENOSYS;
3148 }
3149
3150 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3151 if (!config_cmd) {
3152 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3153 return -ENOMEM;
3154 }
3155 ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
3156 if (!ctrl_ctx) {
3157 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3158 __func__);
3159 xhci_free_command(xhci, config_cmd);
3160 return -ENOMEM;
3161 }
3162
3163 /* Check to make sure all endpoints are not already configured for
3164 * streams. While we're at it, find the maximum number of streams that
3165 * all the endpoints will support and check for duplicate endpoints.
3166 */
3167 spin_lock_irqsave(&xhci->lock, flags);
3168 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3169 num_eps, &num_streams, &changed_ep_bitmask);
3170 if (ret < 0) {
3171 xhci_free_command(xhci, config_cmd);
3172 spin_unlock_irqrestore(&xhci->lock, flags);
3173 return ret;
3174 }
3175 if (num_streams <= 1) {
3176 xhci_warn(xhci, "WARN: endpoints can't handle "
3177 "more than one stream.\n");
3178 xhci_free_command(xhci, config_cmd);
3179 spin_unlock_irqrestore(&xhci->lock, flags);
3180 return -EINVAL;
3181 }
3182 vdev = xhci->devs[udev->slot_id];
3183 /* Mark each endpoint as being in transition, so
3184 * xhci_urb_enqueue() will reject all URBs.
3185 */
3186 for (i = 0; i < num_eps; i++) {
3187 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3188 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3189 }
3190 spin_unlock_irqrestore(&xhci->lock, flags);
3191
3192 /* Setup internal data structures and allocate HW data structures for
3193 * streams (but don't install the HW structures in the input context
3194 * until we're sure all memory allocation succeeded).
3195 */
3196 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3197 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3198 num_stream_ctxs, num_streams);
3199
3200 for (i = 0; i < num_eps; i++) {
3201 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3202 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3203 num_stream_ctxs,
3204 num_streams, mem_flags);
3205 if (!vdev->eps[ep_index].stream_info)
3206 goto cleanup;
3207 /* Set maxPstreams in endpoint context and update deq ptr to
3208 * point to stream context array. FIXME
3209 */
3210 }
3211
3212 /* Set up the input context for a configure endpoint command. */
3213 for (i = 0; i < num_eps; i++) {
3214 struct xhci_ep_ctx *ep_ctx;
3215
3216 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3217 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3218
3219 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3220 vdev->out_ctx, ep_index);
3221 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3222 vdev->eps[ep_index].stream_info);
3223 }
3224 /* Tell the HW to drop its old copy of the endpoint context info
3225 * and add the updated copy from the input context.
3226 */
3227 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3228 vdev->out_ctx, ctrl_ctx,
3229 changed_ep_bitmask, changed_ep_bitmask);
3230
3231 /* Issue and wait for the configure endpoint command */
3232 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3233 false, false);
3234
3235 /* xHC rejected the configure endpoint command for some reason, so we
3236 * leave the old ring intact and free our internal streams data
3237 * structure.
3238 */
3239 if (ret < 0)
3240 goto cleanup;
3241
3242 spin_lock_irqsave(&xhci->lock, flags);
3243 for (i = 0; i < num_eps; i++) {
3244 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3245 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3246 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3247 udev->slot_id, ep_index);
3248 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3249 }
3250 xhci_free_command(xhci, config_cmd);
3251 spin_unlock_irqrestore(&xhci->lock, flags);
3252
3253 /* Subtract 1 for stream 0, which drivers can't use */
3254 return num_streams - 1;
3255
3256cleanup:
3257 /* If it didn't work, free the streams! */
3258 for (i = 0; i < num_eps; i++) {
3259 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3260 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3261 vdev->eps[ep_index].stream_info = NULL;
3262 /* FIXME Unset maxPstreams in endpoint context and
3263 * update deq ptr to point to normal string ring.
3264 */
3265 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3266 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3267 xhci_endpoint_zero(xhci, vdev, eps[i]);
3268 }
3269 xhci_free_command(xhci, config_cmd);
3270 return -ENOMEM;
3271}
3272
3273/* Transition the endpoint from using streams to being a "normal" endpoint
3274 * without streams.
3275 *
3276 * Modify the endpoint context state, submit a configure endpoint command,
3277 * and free all endpoint rings for streams if that completes successfully.
3278 */
3279int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3280 struct usb_host_endpoint **eps, unsigned int num_eps,
3281 gfp_t mem_flags)
3282{
3283 int i, ret;
3284 struct xhci_hcd *xhci;
3285 struct xhci_virt_device *vdev;
3286 struct xhci_command *command;
3287 struct xhci_input_control_ctx *ctrl_ctx;
3288 unsigned int ep_index;
3289 unsigned long flags;
3290 u32 changed_ep_bitmask;
3291
3292 xhci = hcd_to_xhci(hcd);
3293 vdev = xhci->devs[udev->slot_id];
3294
3295 /* Set up a configure endpoint command to remove the streams rings */
3296 spin_lock_irqsave(&xhci->lock, flags);
3297 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3298 udev, eps, num_eps);
3299 if (changed_ep_bitmask == 0) {
3300 spin_unlock_irqrestore(&xhci->lock, flags);
3301 return -EINVAL;
3302 }
3303
3304 /* Use the xhci_command structure from the first endpoint. We may have
3305 * allocated too many, but the driver may call xhci_free_streams() for
3306 * each endpoint it grouped into one call to xhci_alloc_streams().
3307 */
3308 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3309 command = vdev->eps[ep_index].stream_info->free_streams_command;
3310 ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx);
3311 if (!ctrl_ctx) {
3312 spin_unlock_irqrestore(&xhci->lock, flags);
3313 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3314 __func__);
3315 return -EINVAL;
3316 }
3317
3318 for (i = 0; i < num_eps; i++) {
3319 struct xhci_ep_ctx *ep_ctx;
3320
3321 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3322 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3323 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3324 EP_GETTING_NO_STREAMS;
3325
3326 xhci_endpoint_copy(xhci, command->in_ctx,
3327 vdev->out_ctx, ep_index);
3328 xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx,
3329 &vdev->eps[ep_index]);
3330 }
3331 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3332 vdev->out_ctx, ctrl_ctx,
3333 changed_ep_bitmask, changed_ep_bitmask);
3334 spin_unlock_irqrestore(&xhci->lock, flags);
3335
3336 /* Issue and wait for the configure endpoint command,
3337 * which must succeed.
3338 */
3339 ret = xhci_configure_endpoint(xhci, udev, command,
3340 false, true);
3341
3342 /* xHC rejected the configure endpoint command for some reason, so we
3343 * leave the streams rings intact.
3344 */
3345 if (ret < 0)
3346 return ret;
3347
3348 spin_lock_irqsave(&xhci->lock, flags);
3349 for (i = 0; i < num_eps; i++) {
3350 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3351 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3352 vdev->eps[ep_index].stream_info = NULL;
3353 /* FIXME Unset maxPstreams in endpoint context and
3354 * update deq ptr to point to normal string ring.
3355 */
3356 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3357 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3358 }
3359 spin_unlock_irqrestore(&xhci->lock, flags);
3360
3361 return 0;
3362}
3363
3364/*
3365 * Deletes endpoint resources for endpoints that were active before a Reset
3366 * Device command, or a Disable Slot command. The Reset Device command leaves
3367 * the control endpoint intact, whereas the Disable Slot command deletes it.
3368 *
3369 * Must be called with xhci->lock held.
3370 */
3371void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3372 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3373{
3374 int i;
3375 unsigned int num_dropped_eps = 0;
3376 unsigned int drop_flags = 0;
3377
3378 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3379 if (virt_dev->eps[i].ring) {
3380 drop_flags |= 1 << i;
3381 num_dropped_eps++;
3382 }
3383 }
3384 xhci->num_active_eps -= num_dropped_eps;
3385 if (num_dropped_eps)
3386 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3387 "Dropped %u ep ctxs, flags = 0x%x, "
3388 "%u now active.",
3389 num_dropped_eps, drop_flags,
3390 xhci->num_active_eps);
3391}
3392
3393/*
3394 * This submits a Reset Device Command, which will set the device state to 0,
3395 * set the device address to 0, and disable all the endpoints except the default
3396 * control endpoint. The USB core should come back and call
3397 * xhci_address_device(), and then re-set up the configuration. If this is
3398 * called because of a usb_reset_and_verify_device(), then the old alternate
3399 * settings will be re-installed through the normal bandwidth allocation
3400 * functions.
3401 *
3402 * Wait for the Reset Device command to finish. Remove all structures
3403 * associated with the endpoints that were disabled. Clear the input device
3404 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3405 *
3406 * If the virt_dev to be reset does not exist or does not match the udev,
3407 * it means the device is lost, possibly due to the xHC restore error and
3408 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3409 * re-allocate the device.
3410 */
3411int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3412{
3413 int ret, i;
3414 unsigned long flags;
3415 struct xhci_hcd *xhci;
3416 unsigned int slot_id;
3417 struct xhci_virt_device *virt_dev;
3418 struct xhci_command *reset_device_cmd;
3419 int timeleft;
3420 int last_freed_endpoint;
3421 struct xhci_slot_ctx *slot_ctx;
3422 int old_active_eps = 0;
3423
3424 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3425 if (ret <= 0)
3426 return ret;
3427 xhci = hcd_to_xhci(hcd);
3428 slot_id = udev->slot_id;
3429 virt_dev = xhci->devs[slot_id];
3430 if (!virt_dev) {
3431 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3432 "not exist. Re-allocate the device\n", slot_id);
3433 ret = xhci_alloc_dev(hcd, udev);
3434 if (ret == 1)
3435 return 0;
3436 else
3437 return -EINVAL;
3438 }
3439
3440 if (virt_dev->udev != udev) {
3441 /* If the virt_dev and the udev does not match, this virt_dev
3442 * may belong to another udev.
3443 * Re-allocate the device.
3444 */
3445 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3446 "not match the udev. Re-allocate the device\n",
3447 slot_id);
3448 ret = xhci_alloc_dev(hcd, udev);
3449 if (ret == 1)
3450 return 0;
3451 else
3452 return -EINVAL;
3453 }
3454
3455 /* If device is not setup, there is no point in resetting it */
3456 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3457 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3458 SLOT_STATE_DISABLED)
3459 return 0;
3460
3461 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3462 /* Allocate the command structure that holds the struct completion.
3463 * Assume we're in process context, since the normal device reset
3464 * process has to wait for the device anyway. Storage devices are
3465 * reset as part of error handling, so use GFP_NOIO instead of
3466 * GFP_KERNEL.
3467 */
3468 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3469 if (!reset_device_cmd) {
3470 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3471 return -ENOMEM;
3472 }
3473
3474 /* Attempt to submit the Reset Device command to the command ring */
3475 spin_lock_irqsave(&xhci->lock, flags);
3476 reset_device_cmd->command_trb = xhci_find_next_enqueue(xhci->cmd_ring);
3477
3478 list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list);
3479 ret = xhci_queue_reset_device(xhci, slot_id);
3480 if (ret) {
3481 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3482 list_del(&reset_device_cmd->cmd_list);
3483 spin_unlock_irqrestore(&xhci->lock, flags);
3484 goto command_cleanup;
3485 }
3486 xhci_ring_cmd_db(xhci);
3487 spin_unlock_irqrestore(&xhci->lock, flags);
3488
3489 /* Wait for the Reset Device command to finish */
3490 timeleft = wait_for_completion_interruptible_timeout(
3491 reset_device_cmd->completion,
3492 XHCI_CMD_DEFAULT_TIMEOUT);
3493 if (timeleft <= 0) {
3494 xhci_warn(xhci, "%s while waiting for reset device command\n",
3495 timeleft == 0 ? "Timeout" : "Signal");
3496 spin_lock_irqsave(&xhci->lock, flags);
3497 /* The timeout might have raced with the event ring handler, so
3498 * only delete from the list if the item isn't poisoned.
3499 */
3500 if (reset_device_cmd->cmd_list.next != LIST_POISON1)
3501 list_del(&reset_device_cmd->cmd_list);
3502 spin_unlock_irqrestore(&xhci->lock, flags);
3503 ret = -ETIME;
3504 goto command_cleanup;
3505 }
3506
3507 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3508 * unless we tried to reset a slot ID that wasn't enabled,
3509 * or the device wasn't in the addressed or configured state.
3510 */
3511 ret = reset_device_cmd->status;
3512 switch (ret) {
3513 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3514 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3515 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3516 slot_id,
3517 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3518 xhci_dbg(xhci, "Not freeing device rings.\n");
3519 /* Don't treat this as an error. May change my mind later. */
3520 ret = 0;
3521 goto command_cleanup;
3522 case COMP_SUCCESS:
3523 xhci_dbg(xhci, "Successful reset device command.\n");
3524 break;
3525 default:
3526 if (xhci_is_vendor_info_code(xhci, ret))
3527 break;
3528 xhci_warn(xhci, "Unknown completion code %u for "
3529 "reset device command.\n", ret);
3530 ret = -EINVAL;
3531 goto command_cleanup;
3532 }
3533
3534 /* Free up host controller endpoint resources */
3535 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3536 spin_lock_irqsave(&xhci->lock, flags);
3537 /* Don't delete the default control endpoint resources */
3538 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3539 spin_unlock_irqrestore(&xhci->lock, flags);
3540 }
3541
3542 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3543 last_freed_endpoint = 1;
3544 for (i = 1; i < 31; ++i) {
3545 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3546
3547 if (ep->ep_state & EP_HAS_STREAMS) {
3548 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3549 xhci_get_endpoint_address(i));
3550 xhci_free_stream_info(xhci, ep->stream_info);
3551 ep->stream_info = NULL;
3552 ep->ep_state &= ~EP_HAS_STREAMS;
3553 }
3554
3555 if (ep->ring) {
3556 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3557 last_freed_endpoint = i;
3558 }
3559 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3560 xhci_drop_ep_from_interval_table(xhci,
3561 &virt_dev->eps[i].bw_info,
3562 virt_dev->bw_table,
3563 udev,
3564 &virt_dev->eps[i],
3565 virt_dev->tt_info);
3566 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3567 }
3568 /* If necessary, update the number of active TTs on this root port */
3569 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3570
3571 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3572 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3573 ret = 0;
3574
3575command_cleanup:
3576 xhci_free_command(xhci, reset_device_cmd);
3577 return ret;
3578}
3579
3580/*
3581 * At this point, the struct usb_device is about to go away, the device has
3582 * disconnected, and all traffic has been stopped and the endpoints have been
3583 * disabled. Free any HC data structures associated with that device.
3584 */
3585void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3586{
3587 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3588 struct xhci_virt_device *virt_dev;
3589 unsigned long flags;
3590 u32 state;
3591 int i, ret;
3592
3593#ifndef CONFIG_USB_DEFAULT_PERSIST
3594 /*
3595 * We called pm_runtime_get_noresume when the device was attached.
3596 * Decrement the counter here to allow controller to runtime suspend
3597 * if no devices remain.
3598 */
3599 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3600 pm_runtime_put_noidle(hcd->self.controller);
3601#endif
3602
3603 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3604 /* If the host is halted due to driver unload, we still need to free the
3605 * device.
3606 */
3607 if (ret <= 0 && ret != -ENODEV)
3608 return;
3609
3610 virt_dev = xhci->devs[udev->slot_id];
3611
3612 /* Stop any wayward timer functions (which may grab the lock) */
3613 for (i = 0; i < 31; ++i) {
3614 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3615 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3616 }
3617
3618 spin_lock_irqsave(&xhci->lock, flags);
3619 /* Don't disable the slot if the host controller is dead. */
3620 state = readl(&xhci->op_regs->status);
3621 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3622 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3623 xhci_free_virt_device(xhci, udev->slot_id);
3624 spin_unlock_irqrestore(&xhci->lock, flags);
3625 return;
3626 }
3627
3628 if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
3629 spin_unlock_irqrestore(&xhci->lock, flags);
3630 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3631 return;
3632 }
3633 xhci_ring_cmd_db(xhci);
3634 spin_unlock_irqrestore(&xhci->lock, flags);
3635 /*
3636 * Event command completion handler will free any data structures
3637 * associated with the slot. XXX Can free sleep?
3638 */
3639}
3640
3641/*
3642 * Checks if we have enough host controller resources for the default control
3643 * endpoint.
3644 *
3645 * Must be called with xhci->lock held.
3646 */
3647static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3648{
3649 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3650 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3651 "Not enough ep ctxs: "
3652 "%u active, need to add 1, limit is %u.",
3653 xhci->num_active_eps, xhci->limit_active_eps);
3654 return -ENOMEM;
3655 }
3656 xhci->num_active_eps += 1;
3657 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3658 "Adding 1 ep ctx, %u now active.",
3659 xhci->num_active_eps);
3660 return 0;
3661}
3662
3663
3664/*
3665 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3666 * timed out, or allocating memory failed. Returns 1 on success.
3667 */
3668int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3669{
3670 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3671 unsigned long flags;
3672 int timeleft;
3673 int ret;
3674 union xhci_trb *cmd_trb;
3675
3676 spin_lock_irqsave(&xhci->lock, flags);
3677 cmd_trb = xhci_find_next_enqueue(xhci->cmd_ring);
3678 ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
3679 if (ret) {
3680 spin_unlock_irqrestore(&xhci->lock, flags);
3681 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3682 return 0;
3683 }
3684 xhci_ring_cmd_db(xhci);
3685 spin_unlock_irqrestore(&xhci->lock, flags);
3686
3687 /* XXX: how much time for xHC slot assignment? */
3688 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
3689 XHCI_CMD_DEFAULT_TIMEOUT);
3690 if (timeleft <= 0) {
3691 xhci_warn(xhci, "%s while waiting for a slot\n",
3692 timeleft == 0 ? "Timeout" : "Signal");
3693 /* cancel the enable slot request */
3694 return xhci_cancel_cmd(xhci, NULL, cmd_trb);
3695 }
3696
3697 if (!xhci->slot_id) {
3698 xhci_err(xhci, "Error while assigning device slot ID\n");
3699 return 0;
3700 }
3701
3702 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3703 spin_lock_irqsave(&xhci->lock, flags);
3704 ret = xhci_reserve_host_control_ep_resources(xhci);
3705 if (ret) {
3706 spin_unlock_irqrestore(&xhci->lock, flags);
3707 xhci_warn(xhci, "Not enough host resources, "
3708 "active endpoint contexts = %u\n",
3709 xhci->num_active_eps);
3710 goto disable_slot;
3711 }
3712 spin_unlock_irqrestore(&xhci->lock, flags);
3713 }
3714 /* Use GFP_NOIO, since this function can be called from
3715 * xhci_discover_or_reset_device(), which may be called as part of
3716 * mass storage driver error handling.
3717 */
3718 if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) {
3719 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3720 goto disable_slot;
3721 }
3722 udev->slot_id = xhci->slot_id;
3723
3724#ifndef CONFIG_USB_DEFAULT_PERSIST
3725 /*
3726 * If resetting upon resume, we can't put the controller into runtime
3727 * suspend if there is a device attached.
3728 */
3729 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3730 pm_runtime_get_noresume(hcd->self.controller);
3731#endif
3732
3733 /* Is this a LS or FS device under a HS hub? */
3734 /* Hub or peripherial? */
3735 return 1;
3736
3737disable_slot:
3738 /* Disable slot, if we can do it without mem alloc */
3739 spin_lock_irqsave(&xhci->lock, flags);
3740 if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
3741 xhci_ring_cmd_db(xhci);
3742 spin_unlock_irqrestore(&xhci->lock, flags);
3743 return 0;
3744}
3745
3746/*
3747 * Issue an Address Device command and optionally send a corresponding
3748 * SetAddress request to the device.
3749 * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
3750 * we should only issue and wait on one address command at the same time.
3751 */
3752static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3753 enum xhci_setup_dev setup)
3754{
3755 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3756 unsigned long flags;
3757 int timeleft;
3758 struct xhci_virt_device *virt_dev;
3759 int ret = 0;
3760 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3761 struct xhci_slot_ctx *slot_ctx;
3762 struct xhci_input_control_ctx *ctrl_ctx;
3763 u64 temp_64;
3764 union xhci_trb *cmd_trb;
3765
3766 if (!udev->slot_id) {
3767 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3768 "Bad Slot ID %d", udev->slot_id);
3769 return -EINVAL;
3770 }
3771
3772 virt_dev = xhci->devs[udev->slot_id];
3773
3774 if (WARN_ON(!virt_dev)) {
3775 /*
3776 * In plug/unplug torture test with an NEC controller,
3777 * a zero-dereference was observed once due to virt_dev = 0.
3778 * Print useful debug rather than crash if it is observed again!
3779 */
3780 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3781 udev->slot_id);
3782 return -EINVAL;
3783 }
3784
3785 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3786 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
3787 if (!ctrl_ctx) {
3788 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3789 __func__);
3790 return -EINVAL;
3791 }
3792 /*
3793 * If this is the first Set Address since device plug-in or
3794 * virt_device realloaction after a resume with an xHCI power loss,
3795 * then set up the slot context.
3796 */
3797 if (!slot_ctx->dev_info)
3798 xhci_setup_addressable_virt_dev(xhci, udev);
3799 /* Otherwise, update the control endpoint ring enqueue pointer. */
3800 else
3801 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3802 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3803 ctrl_ctx->drop_flags = 0;
3804
3805 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3806 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3807 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3808 le32_to_cpu(slot_ctx->dev_info) >> 27);
3809
3810 spin_lock_irqsave(&xhci->lock, flags);
3811 cmd_trb = xhci_find_next_enqueue(xhci->cmd_ring);
3812 ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
3813 udev->slot_id, setup);
3814 if (ret) {
3815 spin_unlock_irqrestore(&xhci->lock, flags);
3816 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3817 "FIXME: allocate a command ring segment");
3818 return ret;
3819 }
3820 xhci_ring_cmd_db(xhci);
3821 spin_unlock_irqrestore(&xhci->lock, flags);
3822
3823 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3824 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
3825 XHCI_CMD_DEFAULT_TIMEOUT);
3826 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3827 * the SetAddress() "recovery interval" required by USB and aborting the
3828 * command on a timeout.
3829 */
3830 if (timeleft <= 0) {
3831 xhci_warn(xhci, "%s while waiting for setup %s command\n",
3832 timeleft == 0 ? "Timeout" : "Signal", act);
3833 /* cancel the address device command */
3834 ret = xhci_cancel_cmd(xhci, NULL, cmd_trb);
3835 if (ret < 0)
3836 return ret;
3837 return -ETIME;
3838 }
3839
3840 switch (virt_dev->cmd_status) {
3841 case COMP_CTX_STATE:
3842 case COMP_EBADSLT:
3843 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
3844 act, udev->slot_id);
3845 ret = -EINVAL;
3846 break;
3847 case COMP_TX_ERR:
3848 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
3849 ret = -EPROTO;
3850 break;
3851 case COMP_DEV_ERR:
3852 dev_warn(&udev->dev,
3853 "ERROR: Incompatible device for setup %s command\n", act);
3854 ret = -ENODEV;
3855 break;
3856 case COMP_SUCCESS:
3857 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3858 "Successful setup %s command", act);
3859 break;
3860 default:
3861 xhci_err(xhci,
3862 "ERROR: unexpected setup %s command completion code 0x%x.\n",
3863 act, virt_dev->cmd_status);
3864 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3865 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3866 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
3867 ret = -EINVAL;
3868 break;
3869 }
3870 if (ret) {
3871 return ret;
3872 }
3873 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3874 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3875 "Op regs DCBAA ptr = %#016llx", temp_64);
3876 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3877 "Slot ID %d dcbaa entry @%p = %#016llx",
3878 udev->slot_id,
3879 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3880 (unsigned long long)
3881 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3882 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3883 "Output Context DMA address = %#08llx",
3884 (unsigned long long)virt_dev->out_ctx->dma);
3885 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3886 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3887 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3888 le32_to_cpu(slot_ctx->dev_info) >> 27);
3889 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3890 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3891 /*
3892 * USB core uses address 1 for the roothubs, so we add one to the
3893 * address given back to us by the HC.
3894 */
3895 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3896 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
3897 le32_to_cpu(slot_ctx->dev_info) >> 27);
3898 /* Zero the input context control for later use */
3899 ctrl_ctx->add_flags = 0;
3900 ctrl_ctx->drop_flags = 0;
3901
3902 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3903 "Internal device address = %d",
3904 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
3905
3906 return 0;
3907}
3908
3909int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3910{
3911 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
3912}
3913
3914int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
3915{
3916 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
3917}
3918
3919/*
3920 * Transfer the port index into real index in the HW port status
3921 * registers. Caculate offset between the port's PORTSC register
3922 * and port status base. Divide the number of per port register
3923 * to get the real index. The raw port number bases 1.
3924 */
3925int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
3926{
3927 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3928 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
3929 __le32 __iomem *addr;
3930 int raw_port;
3931
3932 if (hcd->speed != HCD_USB3)
3933 addr = xhci->usb2_ports[port1 - 1];
3934 else
3935 addr = xhci->usb3_ports[port1 - 1];
3936
3937 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
3938 return raw_port;
3939}
3940
3941/*
3942 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
3943 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
3944 */
3945static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
3946 struct usb_device *udev, u16 max_exit_latency)
3947{
3948 struct xhci_virt_device *virt_dev;
3949 struct xhci_command *command;
3950 struct xhci_input_control_ctx *ctrl_ctx;
3951 struct xhci_slot_ctx *slot_ctx;
3952 unsigned long flags;
3953 int ret;
3954
3955 spin_lock_irqsave(&xhci->lock, flags);
3956 if (max_exit_latency == xhci->devs[udev->slot_id]->current_mel) {
3957 spin_unlock_irqrestore(&xhci->lock, flags);
3958 return 0;
3959 }
3960
3961 /* Attempt to issue an Evaluate Context command to change the MEL. */
3962 virt_dev = xhci->devs[udev->slot_id];
3963 command = xhci->lpm_command;
3964 ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx);
3965 if (!ctrl_ctx) {
3966 spin_unlock_irqrestore(&xhci->lock, flags);
3967 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3968 __func__);
3969 return -ENOMEM;
3970 }
3971
3972 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
3973 spin_unlock_irqrestore(&xhci->lock, flags);
3974
3975 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3976 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
3977 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
3978 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
3979
3980 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
3981 "Set up evaluate context for LPM MEL change.");
3982 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
3983 xhci_dbg_ctx(xhci, command->in_ctx, 0);
3984
3985 /* Issue and wait for the evaluate context command. */
3986 ret = xhci_configure_endpoint(xhci, udev, command,
3987 true, true);
3988 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
3989 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
3990
3991 if (!ret) {
3992 spin_lock_irqsave(&xhci->lock, flags);
3993 virt_dev->current_mel = max_exit_latency;
3994 spin_unlock_irqrestore(&xhci->lock, flags);
3995 }
3996 return ret;
3997}
3998
3999#ifdef CONFIG_PM_RUNTIME
4000
4001/* BESL to HIRD Encoding array for USB2 LPM */
4002static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4003 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4004
4005/* Calculate HIRD/BESL for USB2 PORTPMSC*/
4006static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4007 struct usb_device *udev)
4008{
4009 int u2del, besl, besl_host;
4010 int besl_device = 0;
4011 u32 field;
4012
4013 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4014 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4015
4016 if (field & USB_BESL_SUPPORT) {
4017 for (besl_host = 0; besl_host < 16; besl_host++) {
4018 if (xhci_besl_encoding[besl_host] >= u2del)
4019 break;
4020 }
4021 /* Use baseline BESL value as default */
4022 if (field & USB_BESL_BASELINE_VALID)
4023 besl_device = USB_GET_BESL_BASELINE(field);
4024 else if (field & USB_BESL_DEEP_VALID)
4025 besl_device = USB_GET_BESL_DEEP(field);
4026 } else {
4027 if (u2del <= 50)
4028 besl_host = 0;
4029 else
4030 besl_host = (u2del - 51) / 75 + 1;
4031 }
4032
4033 besl = besl_host + besl_device;
4034 if (besl > 15)
4035 besl = 15;
4036
4037 return besl;
4038}
4039
4040/* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4041static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4042{
4043 u32 field;
4044 int l1;
4045 int besld = 0;
4046 int hirdm = 0;
4047
4048 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4049
4050 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4051 l1 = udev->l1_params.timeout / 256;
4052
4053 /* device has preferred BESLD */
4054 if (field & USB_BESL_DEEP_VALID) {
4055 besld = USB_GET_BESL_DEEP(field);
4056 hirdm = 1;
4057 }
4058
4059 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4060}
4061
4062int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4063 struct usb_device *udev, int enable)
4064{
4065 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4066 __le32 __iomem **port_array;
4067 __le32 __iomem *pm_addr, *hlpm_addr;
4068 u32 pm_val, hlpm_val, field;
4069 unsigned int port_num;
4070 unsigned long flags;
4071 int hird, exit_latency;
4072 int ret;
4073
4074 if (hcd->speed == HCD_USB3 || !xhci->hw_lpm_support ||
4075 !udev->lpm_capable)
4076 return -EPERM;
4077
4078 if (!udev->parent || udev->parent->parent ||
4079 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4080 return -EPERM;
4081
4082 if (udev->usb2_hw_lpm_capable != 1)
4083 return -EPERM;
4084
4085 spin_lock_irqsave(&xhci->lock, flags);
4086
4087 port_array = xhci->usb2_ports;
4088 port_num = udev->portnum - 1;
4089 pm_addr = port_array[port_num] + PORTPMSC;
4090 pm_val = readl(pm_addr);
4091 hlpm_addr = port_array[port_num] + PORTHLPMC;
4092 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4093
4094 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4095 enable ? "enable" : "disable", port_num);
4096
4097 if (enable) {
4098 /* Host supports BESL timeout instead of HIRD */
4099 if (udev->usb2_hw_lpm_besl_capable) {
4100 /* if device doesn't have a preferred BESL value use a
4101 * default one which works with mixed HIRD and BESL
4102 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4103 */
4104 if ((field & USB_BESL_SUPPORT) &&
4105 (field & USB_BESL_BASELINE_VALID))
4106 hird = USB_GET_BESL_BASELINE(field);
4107 else
4108 hird = udev->l1_params.besl;
4109
4110 exit_latency = xhci_besl_encoding[hird];
4111 spin_unlock_irqrestore(&xhci->lock, flags);
4112
4113 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4114 * input context for link powermanagement evaluate
4115 * context commands. It is protected by hcd->bandwidth
4116 * mutex and is shared by all devices. We need to set
4117 * the max ext latency in USB 2 BESL LPM as well, so
4118 * use the same mutex and xhci_change_max_exit_latency()
4119 */
4120 mutex_lock(hcd->bandwidth_mutex);
4121 ret = xhci_change_max_exit_latency(xhci, udev,
4122 exit_latency);
4123 mutex_unlock(hcd->bandwidth_mutex);
4124
4125 if (ret < 0)
4126 return ret;
4127 spin_lock_irqsave(&xhci->lock, flags);
4128
4129 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4130 writel(hlpm_val, hlpm_addr);
4131 /* flush write */
4132 readl(hlpm_addr);
4133 } else {
4134 hird = xhci_calculate_hird_besl(xhci, udev);
4135 }
4136
4137 pm_val &= ~PORT_HIRD_MASK;
4138 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4139 writel(pm_val, pm_addr);
4140 pm_val = readl(pm_addr);
4141 pm_val |= PORT_HLE;
4142 writel(pm_val, pm_addr);
4143 /* flush write */
4144 readl(pm_addr);
4145 } else {
4146 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4147 writel(pm_val, pm_addr);
4148 /* flush write */
4149 readl(pm_addr);
4150 if (udev->usb2_hw_lpm_besl_capable) {
4151 spin_unlock_irqrestore(&xhci->lock, flags);
4152 mutex_lock(hcd->bandwidth_mutex);
4153 xhci_change_max_exit_latency(xhci, udev, 0);
4154 mutex_unlock(hcd->bandwidth_mutex);
4155 return 0;
4156 }
4157 }
4158
4159 spin_unlock_irqrestore(&xhci->lock, flags);
4160 return 0;
4161}
4162
4163/* check if a usb2 port supports a given extened capability protocol
4164 * only USB2 ports extended protocol capability values are cached.
4165 * Return 1 if capability is supported
4166 */
4167static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4168 unsigned capability)
4169{
4170 u32 port_offset, port_count;
4171 int i;
4172
4173 for (i = 0; i < xhci->num_ext_caps; i++) {
4174 if (xhci->ext_caps[i] & capability) {
4175 /* port offsets starts at 1 */
4176 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4177 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4178 if (port >= port_offset &&
4179 port < port_offset + port_count)
4180 return 1;
4181 }
4182 }
4183 return 0;
4184}
4185
4186int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4187{
4188 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4189 int portnum = udev->portnum - 1;
4190
4191 if (hcd->speed == HCD_USB3 || !xhci->sw_lpm_support ||
4192 !udev->lpm_capable)
4193 return 0;
4194
4195 /* we only support lpm for non-hub device connected to root hub yet */
4196 if (!udev->parent || udev->parent->parent ||
4197 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4198 return 0;
4199
4200 if (xhci->hw_lpm_support == 1 &&
4201 xhci_check_usb2_port_capability(
4202 xhci, portnum, XHCI_HLC)) {
4203 udev->usb2_hw_lpm_capable = 1;
4204 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4205 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4206 if (xhci_check_usb2_port_capability(xhci, portnum,
4207 XHCI_BLC))
4208 udev->usb2_hw_lpm_besl_capable = 1;
4209 }
4210
4211 return 0;
4212}
4213
4214#else
4215
4216int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4217 struct usb_device *udev, int enable)
4218{
4219 return 0;
4220}
4221
4222int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4223{
4224 return 0;
4225}
4226
4227#endif /* CONFIG_PM_RUNTIME */
4228
4229/*---------------------- USB 3.0 Link PM functions ------------------------*/
4230
4231#ifdef CONFIG_PM
4232/* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4233static unsigned long long xhci_service_interval_to_ns(
4234 struct usb_endpoint_descriptor *desc)
4235{
4236 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4237}
4238
4239static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4240 enum usb3_link_state state)
4241{
4242 unsigned long long sel;
4243 unsigned long long pel;
4244 unsigned int max_sel_pel;
4245 char *state_name;
4246
4247 switch (state) {
4248 case USB3_LPM_U1:
4249 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4250 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4251 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4252 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4253 state_name = "U1";
4254 break;
4255 case USB3_LPM_U2:
4256 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4257 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4258 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4259 state_name = "U2";
4260 break;
4261 default:
4262 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4263 __func__);
4264 return USB3_LPM_DISABLED;
4265 }
4266
4267 if (sel <= max_sel_pel && pel <= max_sel_pel)
4268 return USB3_LPM_DEVICE_INITIATED;
4269
4270 if (sel > max_sel_pel)
4271 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4272 "due to long SEL %llu ms\n",
4273 state_name, sel);
4274 else
4275 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4276 "due to long PEL %llu ms\n",
4277 state_name, pel);
4278 return USB3_LPM_DISABLED;
4279}
4280
4281/* Returns the hub-encoded U1 timeout value.
4282 * The U1 timeout should be the maximum of the following values:
4283 * - For control endpoints, U1 system exit latency (SEL) * 3
4284 * - For bulk endpoints, U1 SEL * 5
4285 * - For interrupt endpoints:
4286 * - Notification EPs, U1 SEL * 3
4287 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4288 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4289 */
4290static u16 xhci_calculate_intel_u1_timeout(struct usb_device *udev,
4291 struct usb_endpoint_descriptor *desc)
4292{
4293 unsigned long long timeout_ns;
4294 int ep_type;
4295 int intr_type;
4296
4297 ep_type = usb_endpoint_type(desc);
4298 switch (ep_type) {
4299 case USB_ENDPOINT_XFER_CONTROL:
4300 timeout_ns = udev->u1_params.sel * 3;
4301 break;
4302 case USB_ENDPOINT_XFER_BULK:
4303 timeout_ns = udev->u1_params.sel * 5;
4304 break;
4305 case USB_ENDPOINT_XFER_INT:
4306 intr_type = usb_endpoint_interrupt_type(desc);
4307 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4308 timeout_ns = udev->u1_params.sel * 3;
4309 break;
4310 }
4311 /* Otherwise the calculation is the same as isoc eps */
4312 case USB_ENDPOINT_XFER_ISOC:
4313 timeout_ns = xhci_service_interval_to_ns(desc);
4314 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4315 if (timeout_ns < udev->u1_params.sel * 2)
4316 timeout_ns = udev->u1_params.sel * 2;
4317 break;
4318 default:
4319 return 0;
4320 }
4321
4322 /* The U1 timeout is encoded in 1us intervals. */
4323 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4324 /* Don't return a timeout of zero, because that's USB3_LPM_DISABLED. */
4325 if (timeout_ns == USB3_LPM_DISABLED)
4326 timeout_ns++;
4327
4328 /* If the necessary timeout value is bigger than what we can set in the
4329 * USB 3.0 hub, we have to disable hub-initiated U1.
4330 */
4331 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4332 return timeout_ns;
4333 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4334 "due to long timeout %llu ms\n", timeout_ns);
4335 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4336}
4337
4338/* Returns the hub-encoded U2 timeout value.
4339 * The U2 timeout should be the maximum of:
4340 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4341 * - largest bInterval of any active periodic endpoint (to avoid going
4342 * into lower power link states between intervals).
4343 * - the U2 Exit Latency of the device
4344 */
4345static u16 xhci_calculate_intel_u2_timeout(struct usb_device *udev,
4346 struct usb_endpoint_descriptor *desc)
4347{
4348 unsigned long long timeout_ns;
4349 unsigned long long u2_del_ns;
4350
4351 timeout_ns = 10 * 1000 * 1000;
4352
4353 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4354 (xhci_service_interval_to_ns(desc) > timeout_ns))
4355 timeout_ns = xhci_service_interval_to_ns(desc);
4356
4357 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4358 if (u2_del_ns > timeout_ns)
4359 timeout_ns = u2_del_ns;
4360
4361 /* The U2 timeout is encoded in 256us intervals */
4362 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4363 /* If the necessary timeout value is bigger than what we can set in the
4364 * USB 3.0 hub, we have to disable hub-initiated U2.
4365 */
4366 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4367 return timeout_ns;
4368 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4369 "due to long timeout %llu ms\n", timeout_ns);
4370 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4371}
4372
4373static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4374 struct usb_device *udev,
4375 struct usb_endpoint_descriptor *desc,
4376 enum usb3_link_state state,
4377 u16 *timeout)
4378{
4379 if (state == USB3_LPM_U1) {
4380 if (xhci->quirks & XHCI_INTEL_HOST)
4381 return xhci_calculate_intel_u1_timeout(udev, desc);
4382 } else {
4383 if (xhci->quirks & XHCI_INTEL_HOST)
4384 return xhci_calculate_intel_u2_timeout(udev, desc);
4385 }
4386
4387 return USB3_LPM_DISABLED;
4388}
4389
4390static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4391 struct usb_device *udev,
4392 struct usb_endpoint_descriptor *desc,
4393 enum usb3_link_state state,
4394 u16 *timeout)
4395{
4396 u16 alt_timeout;
4397
4398 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4399 desc, state, timeout);
4400
4401 /* If we found we can't enable hub-initiated LPM, or
4402 * the U1 or U2 exit latency was too high to allow
4403 * device-initiated LPM as well, just stop searching.
4404 */
4405 if (alt_timeout == USB3_LPM_DISABLED ||
4406 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4407 *timeout = alt_timeout;
4408 return -E2BIG;
4409 }
4410 if (alt_timeout > *timeout)
4411 *timeout = alt_timeout;
4412 return 0;
4413}
4414
4415static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4416 struct usb_device *udev,
4417 struct usb_host_interface *alt,
4418 enum usb3_link_state state,
4419 u16 *timeout)
4420{
4421 int j;
4422
4423 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4424 if (xhci_update_timeout_for_endpoint(xhci, udev,
4425 &alt->endpoint[j].desc, state, timeout))
4426 return -E2BIG;
4427 continue;
4428 }
4429 return 0;
4430}
4431
4432static int xhci_check_intel_tier_policy(struct usb_device *udev,
4433 enum usb3_link_state state)
4434{
4435 struct usb_device *parent;
4436 unsigned int num_hubs;
4437
4438 if (state == USB3_LPM_U2)
4439 return 0;
4440
4441 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4442 for (parent = udev->parent, num_hubs = 0; parent->parent;
4443 parent = parent->parent)
4444 num_hubs++;
4445
4446 if (num_hubs < 2)
4447 return 0;
4448
4449 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4450 " below second-tier hub.\n");
4451 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4452 "to decrease power consumption.\n");
4453 return -E2BIG;
4454}
4455
4456static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4457 struct usb_device *udev,
4458 enum usb3_link_state state)
4459{
4460 if (xhci->quirks & XHCI_INTEL_HOST)
4461 return xhci_check_intel_tier_policy(udev, state);
4462 return -EINVAL;
4463}
4464
4465/* Returns the U1 or U2 timeout that should be enabled.
4466 * If the tier check or timeout setting functions return with a non-zero exit
4467 * code, that means the timeout value has been finalized and we shouldn't look
4468 * at any more endpoints.
4469 */
4470static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4471 struct usb_device *udev, enum usb3_link_state state)
4472{
4473 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4474 struct usb_host_config *config;
4475 char *state_name;
4476 int i;
4477 u16 timeout = USB3_LPM_DISABLED;
4478
4479 if (state == USB3_LPM_U1)
4480 state_name = "U1";
4481 else if (state == USB3_LPM_U2)
4482 state_name = "U2";
4483 else {
4484 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4485 state);
4486 return timeout;
4487 }
4488
4489 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4490 return timeout;
4491
4492 /* Gather some information about the currently installed configuration
4493 * and alternate interface settings.
4494 */
4495 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4496 state, &timeout))
4497 return timeout;
4498
4499 config = udev->actconfig;
4500 if (!config)
4501 return timeout;
4502
4503 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4504 struct usb_driver *driver;
4505 struct usb_interface *intf = config->interface[i];
4506
4507 if (!intf)
4508 continue;
4509
4510 /* Check if any currently bound drivers want hub-initiated LPM
4511 * disabled.
4512 */
4513 if (intf->dev.driver) {
4514 driver = to_usb_driver(intf->dev.driver);
4515 if (driver && driver->disable_hub_initiated_lpm) {
4516 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4517 "at request of driver %s\n",
4518 state_name, driver->name);
4519 return xhci_get_timeout_no_hub_lpm(udev, state);
4520 }
4521 }
4522
4523 /* Not sure how this could happen... */
4524 if (!intf->cur_altsetting)
4525 continue;
4526
4527 if (xhci_update_timeout_for_interface(xhci, udev,
4528 intf->cur_altsetting,
4529 state, &timeout))
4530 return timeout;
4531 }
4532 return timeout;
4533}
4534
4535static int calculate_max_exit_latency(struct usb_device *udev,
4536 enum usb3_link_state state_changed,
4537 u16 hub_encoded_timeout)
4538{
4539 unsigned long long u1_mel_us = 0;
4540 unsigned long long u2_mel_us = 0;
4541 unsigned long long mel_us = 0;
4542 bool disabling_u1;
4543 bool disabling_u2;
4544 bool enabling_u1;
4545 bool enabling_u2;
4546
4547 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4548 hub_encoded_timeout == USB3_LPM_DISABLED);
4549 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4550 hub_encoded_timeout == USB3_LPM_DISABLED);
4551
4552 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4553 hub_encoded_timeout != USB3_LPM_DISABLED);
4554 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4555 hub_encoded_timeout != USB3_LPM_DISABLED);
4556
4557 /* If U1 was already enabled and we're not disabling it,
4558 * or we're going to enable U1, account for the U1 max exit latency.
4559 */
4560 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4561 enabling_u1)
4562 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4563 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4564 enabling_u2)
4565 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4566
4567 if (u1_mel_us > u2_mel_us)
4568 mel_us = u1_mel_us;
4569 else
4570 mel_us = u2_mel_us;
4571 /* xHCI host controller max exit latency field is only 16 bits wide. */
4572 if (mel_us > MAX_EXIT) {
4573 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4574 "is too big.\n", mel_us);
4575 return -E2BIG;
4576 }
4577 return mel_us;
4578}
4579
4580/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4581int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4582 struct usb_device *udev, enum usb3_link_state state)
4583{
4584 struct xhci_hcd *xhci;
4585 u16 hub_encoded_timeout;
4586 int mel;
4587 int ret;
4588
4589 xhci = hcd_to_xhci(hcd);
4590 /* The LPM timeout values are pretty host-controller specific, so don't
4591 * enable hub-initiated timeouts unless the vendor has provided
4592 * information about their timeout algorithm.
4593 */
4594 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4595 !xhci->devs[udev->slot_id])
4596 return USB3_LPM_DISABLED;
4597
4598 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4599 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4600 if (mel < 0) {
4601 /* Max Exit Latency is too big, disable LPM. */
4602 hub_encoded_timeout = USB3_LPM_DISABLED;
4603 mel = 0;
4604 }
4605
4606 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4607 if (ret)
4608 return ret;
4609 return hub_encoded_timeout;
4610}
4611
4612int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4613 struct usb_device *udev, enum usb3_link_state state)
4614{
4615 struct xhci_hcd *xhci;
4616 u16 mel;
4617 int ret;
4618
4619 xhci = hcd_to_xhci(hcd);
4620 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4621 !xhci->devs[udev->slot_id])
4622 return 0;
4623
4624 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4625 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4626 if (ret)
4627 return ret;
4628 return 0;
4629}
4630#else /* CONFIG_PM */
4631
4632int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4633 struct usb_device *udev, enum usb3_link_state state)
4634{
4635 return USB3_LPM_DISABLED;
4636}
4637
4638int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4639 struct usb_device *udev, enum usb3_link_state state)
4640{
4641 return 0;
4642}
4643#endif /* CONFIG_PM */
4644
4645/*-------------------------------------------------------------------------*/
4646
4647/* Once a hub descriptor is fetched for a device, we need to update the xHC's
4648 * internal data structures for the device.
4649 */
4650int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4651 struct usb_tt *tt, gfp_t mem_flags)
4652{
4653 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4654 struct xhci_virt_device *vdev;
4655 struct xhci_command *config_cmd;
4656 struct xhci_input_control_ctx *ctrl_ctx;
4657 struct xhci_slot_ctx *slot_ctx;
4658 unsigned long flags;
4659 unsigned think_time;
4660 int ret;
4661
4662 /* Ignore root hubs */
4663 if (!hdev->parent)
4664 return 0;
4665
4666 vdev = xhci->devs[hdev->slot_id];
4667 if (!vdev) {
4668 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4669 return -EINVAL;
4670 }
4671 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4672 if (!config_cmd) {
4673 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4674 return -ENOMEM;
4675 }
4676 ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
4677 if (!ctrl_ctx) {
4678 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4679 __func__);
4680 xhci_free_command(xhci, config_cmd);
4681 return -ENOMEM;
4682 }
4683
4684 spin_lock_irqsave(&xhci->lock, flags);
4685 if (hdev->speed == USB_SPEED_HIGH &&
4686 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4687 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4688 xhci_free_command(xhci, config_cmd);
4689 spin_unlock_irqrestore(&xhci->lock, flags);
4690 return -ENOMEM;
4691 }
4692
4693 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4694 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4695 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4696 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4697 if (tt->multi)
4698 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4699 if (xhci->hci_version > 0x95) {
4700 xhci_dbg(xhci, "xHCI version %x needs hub "
4701 "TT think time and number of ports\n",
4702 (unsigned int) xhci->hci_version);
4703 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4704 /* Set TT think time - convert from ns to FS bit times.
4705 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4706 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4707 *
4708 * xHCI 1.0: this field shall be 0 if the device is not a
4709 * High-spped hub.
4710 */
4711 think_time = tt->think_time;
4712 if (think_time != 0)
4713 think_time = (think_time / 666) - 1;
4714 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4715 slot_ctx->tt_info |=
4716 cpu_to_le32(TT_THINK_TIME(think_time));
4717 } else {
4718 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4719 "TT think time or number of ports\n",
4720 (unsigned int) xhci->hci_version);
4721 }
4722 slot_ctx->dev_state = 0;
4723 spin_unlock_irqrestore(&xhci->lock, flags);
4724
4725 xhci_dbg(xhci, "Set up %s for hub device.\n",
4726 (xhci->hci_version > 0x95) ?
4727 "configure endpoint" : "evaluate context");
4728 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4729 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4730
4731 /* Issue and wait for the configure endpoint or
4732 * evaluate context command.
4733 */
4734 if (xhci->hci_version > 0x95)
4735 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4736 false, false);
4737 else
4738 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4739 true, false);
4740
4741 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4742 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4743
4744 xhci_free_command(xhci, config_cmd);
4745 return ret;
4746}
4747
4748int xhci_get_frame(struct usb_hcd *hcd)
4749{
4750 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4751 /* EHCI mods by the periodic size. Why? */
4752 return readl(&xhci->run_regs->microframe_index) >> 3;
4753}
4754
4755int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4756{
4757 struct xhci_hcd *xhci;
4758 struct device *dev = hcd->self.controller;
4759 int retval;
4760
4761 /* Accept arbitrarily long scatter-gather lists */
4762 hcd->self.sg_tablesize = ~0;
4763
4764 /* support to build packet from discontinuous buffers */
4765 hcd->self.no_sg_constraint = 1;
4766
4767 /* XHCI controllers don't stop the ep queue on short packets :| */
4768 hcd->self.no_stop_on_short = 1;
4769
4770 if (usb_hcd_is_primary_hcd(hcd)) {
4771 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
4772 if (!xhci)
4773 return -ENOMEM;
4774 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
4775 xhci->main_hcd = hcd;
4776 /* Mark the first roothub as being USB 2.0.
4777 * The xHCI driver will register the USB 3.0 roothub.
4778 */
4779 hcd->speed = HCD_USB2;
4780 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4781 /*
4782 * USB 2.0 roothub under xHCI has an integrated TT,
4783 * (rate matching hub) as opposed to having an OHCI/UHCI
4784 * companion controller.
4785 */
4786 hcd->has_tt = 1;
4787 } else {
4788 /* xHCI private pointer was set in xhci_pci_probe for the second
4789 * registered roothub.
4790 */
4791 return 0;
4792 }
4793
4794 xhci->cap_regs = hcd->regs;
4795 xhci->op_regs = hcd->regs +
4796 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
4797 xhci->run_regs = hcd->regs +
4798 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4799 /* Cache read-only capability registers */
4800 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
4801 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
4802 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
4803 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
4804 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4805 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
4806 xhci_print_registers(xhci);
4807
4808 xhci->quirks = quirks;
4809
4810 get_quirks(dev, xhci);
4811
4812 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4813 * success event after a short transfer. This quirk will ignore such
4814 * spurious event.
4815 */
4816 if (xhci->hci_version > 0x96)
4817 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4818
4819 /* Make sure the HC is halted. */
4820 retval = xhci_halt(xhci);
4821 if (retval)
4822 goto error;
4823
4824 xhci_dbg(xhci, "Resetting HCD\n");
4825 /* Reset the internal HC memory state and registers. */
4826 retval = xhci_reset(xhci);
4827 if (retval)
4828 goto error;
4829 xhci_dbg(xhci, "Reset complete\n");
4830
4831 /* Set dma_mask and coherent_dma_mask to 64-bits,
4832 * if xHC supports 64-bit addressing */
4833 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
4834 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
4835 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4836 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
4837 }
4838
4839 xhci_dbg(xhci, "Calling HCD init\n");
4840 /* Initialize HCD and host controller data structures. */
4841 retval = xhci_init(hcd);
4842 if (retval)
4843 goto error;
4844 xhci_dbg(xhci, "Called HCD init\n");
4845 return 0;
4846error:
4847 kfree(xhci);
4848 return retval;
4849}
4850
4851MODULE_DESCRIPTION(DRIVER_DESC);
4852MODULE_AUTHOR(DRIVER_AUTHOR);
4853MODULE_LICENSE("GPL");
4854
4855static int __init xhci_hcd_init(void)
4856{
4857 int retval;
4858
4859 retval = xhci_register_pci();
4860 if (retval < 0) {
4861 pr_debug("Problem registering PCI driver.\n");
4862 return retval;
4863 }
4864 retval = xhci_register_plat();
4865 if (retval < 0) {
4866 pr_debug("Problem registering platform driver.\n");
4867 goto unreg_pci;
4868 }
4869 /*
4870 * Check the compiler generated sizes of structures that must be laid
4871 * out in specific ways for hardware access.
4872 */
4873 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
4874 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
4875 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
4876 /* xhci_device_control has eight fields, and also
4877 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
4878 */
4879 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
4880 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
4881 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
4882 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
4883 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
4884 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
4885 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
4886 return 0;
4887unreg_pci:
4888 xhci_unregister_pci();
4889 return retval;
4890}
4891module_init(xhci_hcd_init);
4892
4893static void __exit xhci_hcd_cleanup(void)
4894{
4895 xhci_unregister_pci();
4896 xhci_unregister_plat();
4897}
4898module_exit(xhci_hcd_cleanup);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11#include <linux/pci.h>
12#include <linux/iommu.h>
13#include <linux/iopoll.h>
14#include <linux/irq.h>
15#include <linux/log2.h>
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/slab.h>
19#include <linux/dmi.h>
20#include <linux/dma-mapping.h>
21
22#include "xhci.h"
23#include "xhci-trace.h"
24#include "xhci-debugfs.h"
25#include "xhci-dbgcap.h"
26
27#define DRIVER_AUTHOR "Sarah Sharp"
28#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29
30#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31
32/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
33static int link_quirk;
34module_param(link_quirk, int, S_IRUGO | S_IWUSR);
35MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
36
37static unsigned long long quirks;
38module_param(quirks, ullong, S_IRUGO);
39MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
40
41static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
42{
43 struct xhci_segment *seg = ring->first_seg;
44
45 if (!td || !td->start_seg)
46 return false;
47 do {
48 if (seg == td->start_seg)
49 return true;
50 seg = seg->next;
51 } while (seg && seg != ring->first_seg);
52
53 return false;
54}
55
56/*
57 * xhci_handshake - spin reading hc until handshake completes or fails
58 * @ptr: address of hc register to be read
59 * @mask: bits to look at in result of read
60 * @done: value of those bits when handshake succeeds
61 * @usec: timeout in microseconds
62 *
63 * Returns negative errno, or zero on success
64 *
65 * Success happens when the "mask" bits have the specified value (hardware
66 * handshake done). There are two failure modes: "usec" have passed (major
67 * hardware flakeout), or the register reads as all-ones (hardware removed).
68 */
69int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
70{
71 u32 result;
72 int ret;
73
74 ret = readl_poll_timeout_atomic(ptr, result,
75 (result & mask) == done ||
76 result == U32_MAX,
77 1, timeout_us);
78 if (result == U32_MAX) /* card removed */
79 return -ENODEV;
80
81 return ret;
82}
83
84/*
85 * xhci_handshake_check_state - same as xhci_handshake but takes an additional
86 * exit_state parameter, and bails out with an error immediately when xhc_state
87 * has exit_state flag set.
88 */
89int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr,
90 u32 mask, u32 done, int usec, unsigned int exit_state)
91{
92 u32 result;
93 int ret;
94
95 ret = readl_poll_timeout_atomic(ptr, result,
96 (result & mask) == done ||
97 result == U32_MAX ||
98 xhci->xhc_state & exit_state,
99 1, usec);
100
101 if (result == U32_MAX || xhci->xhc_state & exit_state)
102 return -ENODEV;
103
104 return ret;
105}
106
107/*
108 * Disable interrupts and begin the xHCI halting process.
109 */
110void xhci_quiesce(struct xhci_hcd *xhci)
111{
112 u32 halted;
113 u32 cmd;
114 u32 mask;
115
116 mask = ~(XHCI_IRQS);
117 halted = readl(&xhci->op_regs->status) & STS_HALT;
118 if (!halted)
119 mask &= ~CMD_RUN;
120
121 cmd = readl(&xhci->op_regs->command);
122 cmd &= mask;
123 writel(cmd, &xhci->op_regs->command);
124}
125
126/*
127 * Force HC into halt state.
128 *
129 * Disable any IRQs and clear the run/stop bit.
130 * HC will complete any current and actively pipelined transactions, and
131 * should halt within 16 ms of the run/stop bit being cleared.
132 * Read HC Halted bit in the status register to see when the HC is finished.
133 */
134int xhci_halt(struct xhci_hcd *xhci)
135{
136 int ret;
137
138 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
139 xhci_quiesce(xhci);
140
141 ret = xhci_handshake(&xhci->op_regs->status,
142 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
143 if (ret) {
144 xhci_warn(xhci, "Host halt failed, %d\n", ret);
145 return ret;
146 }
147
148 xhci->xhc_state |= XHCI_STATE_HALTED;
149 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
150
151 return ret;
152}
153
154/*
155 * Set the run bit and wait for the host to be running.
156 */
157int xhci_start(struct xhci_hcd *xhci)
158{
159 u32 temp;
160 int ret;
161
162 temp = readl(&xhci->op_regs->command);
163 temp |= (CMD_RUN);
164 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
165 temp);
166 writel(temp, &xhci->op_regs->command);
167
168 /*
169 * Wait for the HCHalted Status bit to be 0 to indicate the host is
170 * running.
171 */
172 ret = xhci_handshake(&xhci->op_regs->status,
173 STS_HALT, 0, XHCI_MAX_HALT_USEC);
174 if (ret == -ETIMEDOUT)
175 xhci_err(xhci, "Host took too long to start, "
176 "waited %u microseconds.\n",
177 XHCI_MAX_HALT_USEC);
178 if (!ret) {
179 /* clear state flags. Including dying, halted or removing */
180 xhci->xhc_state = 0;
181 xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
182 }
183
184 return ret;
185}
186
187/*
188 * Reset a halted HC.
189 *
190 * This resets pipelines, timers, counters, state machines, etc.
191 * Transactions will be terminated immediately, and operational registers
192 * will be set to their defaults.
193 */
194int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
195{
196 u32 command;
197 u32 state;
198 int ret;
199
200 state = readl(&xhci->op_regs->status);
201
202 if (state == ~(u32)0) {
203 xhci_warn(xhci, "Host not accessible, reset failed.\n");
204 return -ENODEV;
205 }
206
207 if ((state & STS_HALT) == 0) {
208 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
209 return 0;
210 }
211
212 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
213 command = readl(&xhci->op_regs->command);
214 command |= CMD_RESET;
215 writel(command, &xhci->op_regs->command);
216
217 /* Existing Intel xHCI controllers require a delay of 1 mS,
218 * after setting the CMD_RESET bit, and before accessing any
219 * HC registers. This allows the HC to complete the
220 * reset operation and be ready for HC register access.
221 * Without this delay, the subsequent HC register access,
222 * may result in a system hang very rarely.
223 */
224 if (xhci->quirks & XHCI_INTEL_HOST)
225 udelay(1000);
226
227 ret = xhci_handshake_check_state(xhci, &xhci->op_regs->command,
228 CMD_RESET, 0, timeout_us, XHCI_STATE_REMOVING);
229 if (ret)
230 return ret;
231
232 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
233 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
234
235 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
236 "Wait for controller to be ready for doorbell rings");
237 /*
238 * xHCI cannot write to any doorbells or operational registers other
239 * than status until the "Controller Not Ready" flag is cleared.
240 */
241 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
242
243 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
244 xhci->usb2_rhub.bus_state.suspended_ports = 0;
245 xhci->usb2_rhub.bus_state.resuming_ports = 0;
246 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
247 xhci->usb3_rhub.bus_state.suspended_ports = 0;
248 xhci->usb3_rhub.bus_state.resuming_ports = 0;
249
250 return ret;
251}
252
253static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
254{
255 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
256 struct iommu_domain *domain;
257 int err, i;
258 u64 val;
259 u32 intrs;
260
261 /*
262 * Some Renesas controllers get into a weird state if they are
263 * reset while programmed with 64bit addresses (they will preserve
264 * the top half of the address in internal, non visible
265 * registers). You end up with half the address coming from the
266 * kernel, and the other half coming from the firmware. Also,
267 * changing the programming leads to extra accesses even if the
268 * controller is supposed to be halted. The controller ends up with
269 * a fatal fault, and is then ripe for being properly reset.
270 *
271 * Special care is taken to only apply this if the device is behind
272 * an iommu. Doing anything when there is no iommu is definitely
273 * unsafe...
274 */
275 domain = iommu_get_domain_for_dev(dev);
276 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !domain ||
277 domain->type == IOMMU_DOMAIN_IDENTITY)
278 return;
279
280 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
281
282 /* Clear HSEIE so that faults do not get signaled */
283 val = readl(&xhci->op_regs->command);
284 val &= ~CMD_HSEIE;
285 writel(val, &xhci->op_regs->command);
286
287 /* Clear HSE (aka FATAL) */
288 val = readl(&xhci->op_regs->status);
289 val |= STS_FATAL;
290 writel(val, &xhci->op_regs->status);
291
292 /* Now zero the registers, and brace for impact */
293 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
294 if (upper_32_bits(val))
295 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
296 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
297 if (upper_32_bits(val))
298 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
299
300 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
301 ARRAY_SIZE(xhci->run_regs->ir_set));
302
303 for (i = 0; i < intrs; i++) {
304 struct xhci_intr_reg __iomem *ir;
305
306 ir = &xhci->run_regs->ir_set[i];
307 val = xhci_read_64(xhci, &ir->erst_base);
308 if (upper_32_bits(val))
309 xhci_write_64(xhci, 0, &ir->erst_base);
310 val= xhci_read_64(xhci, &ir->erst_dequeue);
311 if (upper_32_bits(val))
312 xhci_write_64(xhci, 0, &ir->erst_dequeue);
313 }
314
315 /* Wait for the fault to appear. It will be cleared on reset */
316 err = xhci_handshake(&xhci->op_regs->status,
317 STS_FATAL, STS_FATAL,
318 XHCI_MAX_HALT_USEC);
319 if (!err)
320 xhci_info(xhci, "Fault detected\n");
321}
322
323static int xhci_enable_interrupter(struct xhci_interrupter *ir)
324{
325 u32 iman;
326
327 if (!ir || !ir->ir_set)
328 return -EINVAL;
329
330 iman = readl(&ir->ir_set->irq_pending);
331 writel(ER_IRQ_ENABLE(iman), &ir->ir_set->irq_pending);
332
333 return 0;
334}
335
336static int xhci_disable_interrupter(struct xhci_interrupter *ir)
337{
338 u32 iman;
339
340 if (!ir || !ir->ir_set)
341 return -EINVAL;
342
343 iman = readl(&ir->ir_set->irq_pending);
344 writel(ER_IRQ_DISABLE(iman), &ir->ir_set->irq_pending);
345
346 return 0;
347}
348
349/* interrupt moderation interval imod_interval in nanoseconds */
350static int xhci_set_interrupter_moderation(struct xhci_interrupter *ir,
351 u32 imod_interval)
352{
353 u32 imod;
354
355 if (!ir || !ir->ir_set || imod_interval > U16_MAX * 250)
356 return -EINVAL;
357
358 imod = readl(&ir->ir_set->irq_control);
359 imod &= ~ER_IRQ_INTERVAL_MASK;
360 imod |= (imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
361 writel(imod, &ir->ir_set->irq_control);
362
363 return 0;
364}
365
366static void compliance_mode_recovery(struct timer_list *t)
367{
368 struct xhci_hcd *xhci;
369 struct usb_hcd *hcd;
370 struct xhci_hub *rhub;
371 u32 temp;
372 int i;
373
374 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
375 rhub = &xhci->usb3_rhub;
376 hcd = rhub->hcd;
377
378 if (!hcd)
379 return;
380
381 for (i = 0; i < rhub->num_ports; i++) {
382 temp = readl(rhub->ports[i]->addr);
383 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
384 /*
385 * Compliance Mode Detected. Letting USB Core
386 * handle the Warm Reset
387 */
388 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
389 "Compliance mode detected->port %d",
390 i + 1);
391 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
392 "Attempting compliance mode recovery");
393
394 if (hcd->state == HC_STATE_SUSPENDED)
395 usb_hcd_resume_root_hub(hcd);
396
397 usb_hcd_poll_rh_status(hcd);
398 }
399 }
400
401 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
402 mod_timer(&xhci->comp_mode_recovery_timer,
403 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
404}
405
406/*
407 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
408 * that causes ports behind that hardware to enter compliance mode sometimes.
409 * The quirk creates a timer that polls every 2 seconds the link state of
410 * each host controller's port and recovers it by issuing a Warm reset
411 * if Compliance mode is detected, otherwise the port will become "dead" (no
412 * device connections or disconnections will be detected anymore). Becasue no
413 * status event is generated when entering compliance mode (per xhci spec),
414 * this quirk is needed on systems that have the failing hardware installed.
415 */
416static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
417{
418 xhci->port_status_u0 = 0;
419 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
420 0);
421 xhci->comp_mode_recovery_timer.expires = jiffies +
422 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
423
424 add_timer(&xhci->comp_mode_recovery_timer);
425 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
426 "Compliance mode recovery timer initialized");
427}
428
429/*
430 * This function identifies the systems that have installed the SN65LVPE502CP
431 * USB3.0 re-driver and that need the Compliance Mode Quirk.
432 * Systems:
433 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
434 */
435static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
436{
437 const char *dmi_product_name, *dmi_sys_vendor;
438
439 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
440 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
441 if (!dmi_product_name || !dmi_sys_vendor)
442 return false;
443
444 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
445 return false;
446
447 if (strstr(dmi_product_name, "Z420") ||
448 strstr(dmi_product_name, "Z620") ||
449 strstr(dmi_product_name, "Z820") ||
450 strstr(dmi_product_name, "Z1 Workstation"))
451 return true;
452
453 return false;
454}
455
456static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
457{
458 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
459}
460
461
462/*
463 * Initialize memory for HCD and xHC (one-time init).
464 *
465 * Program the PAGESIZE register, initialize the device context array, create
466 * device contexts (?), set up a command ring segment (or two?), create event
467 * ring (one for now).
468 */
469static int xhci_init(struct usb_hcd *hcd)
470{
471 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
472 int retval;
473
474 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
475 spin_lock_init(&xhci->lock);
476 if (xhci->hci_version == 0x95 && link_quirk) {
477 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
478 "QUIRK: Not clearing Link TRB chain bits.");
479 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
480 } else {
481 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
482 "xHCI doesn't need link TRB QUIRK");
483 }
484 retval = xhci_mem_init(xhci, GFP_KERNEL);
485 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
486
487 /* Initializing Compliance Mode Recovery Data If Needed */
488 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
489 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
490 compliance_mode_recovery_timer_init(xhci);
491 }
492
493 return retval;
494}
495
496/*-------------------------------------------------------------------------*/
497
498static int xhci_run_finished(struct xhci_hcd *xhci)
499{
500 struct xhci_interrupter *ir = xhci->interrupters[0];
501 unsigned long flags;
502 u32 temp;
503
504 /*
505 * Enable interrupts before starting the host (xhci 4.2 and 5.5.2).
506 * Protect the short window before host is running with a lock
507 */
508 spin_lock_irqsave(&xhci->lock, flags);
509
510 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable interrupts");
511 temp = readl(&xhci->op_regs->command);
512 temp |= (CMD_EIE);
513 writel(temp, &xhci->op_regs->command);
514
515 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Enable primary interrupter");
516 xhci_enable_interrupter(ir);
517
518 if (xhci_start(xhci)) {
519 xhci_halt(xhci);
520 spin_unlock_irqrestore(&xhci->lock, flags);
521 return -ENODEV;
522 }
523
524 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
525
526 if (xhci->quirks & XHCI_NEC_HOST)
527 xhci_ring_cmd_db(xhci);
528
529 spin_unlock_irqrestore(&xhci->lock, flags);
530
531 return 0;
532}
533
534/*
535 * Start the HC after it was halted.
536 *
537 * This function is called by the USB core when the HC driver is added.
538 * Its opposite is xhci_stop().
539 *
540 * xhci_init() must be called once before this function can be called.
541 * Reset the HC, enable device slot contexts, program DCBAAP, and
542 * set command ring pointer and event ring pointer.
543 *
544 * Setup MSI-X vectors and enable interrupts.
545 */
546int xhci_run(struct usb_hcd *hcd)
547{
548 u64 temp_64;
549 int ret;
550 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
551 struct xhci_interrupter *ir = xhci->interrupters[0];
552 /* Start the xHCI host controller running only after the USB 2.0 roothub
553 * is setup.
554 */
555
556 hcd->uses_new_polling = 1;
557 if (hcd->msi_enabled)
558 ir->ip_autoclear = true;
559
560 if (!usb_hcd_is_primary_hcd(hcd))
561 return xhci_run_finished(xhci);
562
563 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
564
565 temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
566 temp_64 &= ERST_PTR_MASK;
567 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
568 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
569
570 xhci_set_interrupter_moderation(ir, xhci->imod_interval);
571
572 if (xhci->quirks & XHCI_NEC_HOST) {
573 struct xhci_command *command;
574
575 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
576 if (!command)
577 return -ENOMEM;
578
579 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
580 TRB_TYPE(TRB_NEC_GET_FW));
581 if (ret)
582 xhci_free_command(xhci, command);
583 }
584 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
585 "Finished %s for main hcd", __func__);
586
587 xhci_create_dbc_dev(xhci);
588
589 xhci_debugfs_init(xhci);
590
591 if (xhci_has_one_roothub(xhci))
592 return xhci_run_finished(xhci);
593
594 set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
595
596 return 0;
597}
598EXPORT_SYMBOL_GPL(xhci_run);
599
600/*
601 * Stop xHCI driver.
602 *
603 * This function is called by the USB core when the HC driver is removed.
604 * Its opposite is xhci_run().
605 *
606 * Disable device contexts, disable IRQs, and quiesce the HC.
607 * Reset the HC, finish any completed transactions, and cleanup memory.
608 */
609void xhci_stop(struct usb_hcd *hcd)
610{
611 u32 temp;
612 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
613 struct xhci_interrupter *ir = xhci->interrupters[0];
614
615 mutex_lock(&xhci->mutex);
616
617 /* Only halt host and free memory after both hcds are removed */
618 if (!usb_hcd_is_primary_hcd(hcd)) {
619 mutex_unlock(&xhci->mutex);
620 return;
621 }
622
623 xhci_remove_dbc_dev(xhci);
624
625 spin_lock_irq(&xhci->lock);
626 xhci->xhc_state |= XHCI_STATE_HALTED;
627 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
628 xhci_halt(xhci);
629 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
630 spin_unlock_irq(&xhci->lock);
631
632 /* Deleting Compliance Mode Recovery Timer */
633 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
634 (!(xhci_all_ports_seen_u0(xhci)))) {
635 del_timer_sync(&xhci->comp_mode_recovery_timer);
636 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
637 "%s: compliance mode recovery timer deleted",
638 __func__);
639 }
640
641 if (xhci->quirks & XHCI_AMD_PLL_FIX)
642 usb_amd_dev_put();
643
644 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
645 "// Disabling event ring interrupts");
646 temp = readl(&xhci->op_regs->status);
647 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
648 xhci_disable_interrupter(ir);
649
650 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
651 xhci_mem_cleanup(xhci);
652 xhci_debugfs_exit(xhci);
653 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
654 "xhci_stop completed - status = %x",
655 readl(&xhci->op_regs->status));
656 mutex_unlock(&xhci->mutex);
657}
658EXPORT_SYMBOL_GPL(xhci_stop);
659
660/*
661 * Shutdown HC (not bus-specific)
662 *
663 * This is called when the machine is rebooting or halting. We assume that the
664 * machine will be powered off, and the HC's internal state will be reset.
665 * Don't bother to free memory.
666 *
667 * This will only ever be called with the main usb_hcd (the USB3 roothub).
668 */
669void xhci_shutdown(struct usb_hcd *hcd)
670{
671 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
672
673 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
674 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
675
676 /* Don't poll the roothubs after shutdown. */
677 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
678 __func__, hcd->self.busnum);
679 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
680 del_timer_sync(&hcd->rh_timer);
681
682 if (xhci->shared_hcd) {
683 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
684 del_timer_sync(&xhci->shared_hcd->rh_timer);
685 }
686
687 spin_lock_irq(&xhci->lock);
688 xhci_halt(xhci);
689
690 /*
691 * Workaround for spurious wakeps at shutdown with HSW, and for boot
692 * firmware delay in ADL-P PCH if port are left in U3 at shutdown
693 */
694 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP ||
695 xhci->quirks & XHCI_RESET_TO_DEFAULT)
696 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
697
698 spin_unlock_irq(&xhci->lock);
699
700 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
701 "xhci_shutdown completed - status = %x",
702 readl(&xhci->op_regs->status));
703}
704EXPORT_SYMBOL_GPL(xhci_shutdown);
705
706#ifdef CONFIG_PM
707static void xhci_save_registers(struct xhci_hcd *xhci)
708{
709 struct xhci_interrupter *ir;
710 unsigned int i;
711
712 xhci->s3.command = readl(&xhci->op_regs->command);
713 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
714 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
715 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
716
717 /* save both primary and all secondary interrupters */
718 /* fixme, shold we lock to prevent race with remove secondary interrupter? */
719 for (i = 0; i < xhci->max_interrupters; i++) {
720 ir = xhci->interrupters[i];
721 if (!ir)
722 continue;
723
724 ir->s3_erst_size = readl(&ir->ir_set->erst_size);
725 ir->s3_erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
726 ir->s3_erst_dequeue = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);
727 ir->s3_irq_pending = readl(&ir->ir_set->irq_pending);
728 ir->s3_irq_control = readl(&ir->ir_set->irq_control);
729 }
730}
731
732static void xhci_restore_registers(struct xhci_hcd *xhci)
733{
734 struct xhci_interrupter *ir;
735 unsigned int i;
736
737 writel(xhci->s3.command, &xhci->op_regs->command);
738 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
739 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
740 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
741
742 /* FIXME should we lock to protect against freeing of interrupters */
743 for (i = 0; i < xhci->max_interrupters; i++) {
744 ir = xhci->interrupters[i];
745 if (!ir)
746 continue;
747
748 writel(ir->s3_erst_size, &ir->ir_set->erst_size);
749 xhci_write_64(xhci, ir->s3_erst_base, &ir->ir_set->erst_base);
750 xhci_write_64(xhci, ir->s3_erst_dequeue, &ir->ir_set->erst_dequeue);
751 writel(ir->s3_irq_pending, &ir->ir_set->irq_pending);
752 writel(ir->s3_irq_control, &ir->ir_set->irq_control);
753 }
754}
755
756static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
757{
758 u64 val_64;
759
760 /* step 2: initialize command ring buffer */
761 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
762 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
763 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
764 xhci->cmd_ring->dequeue) &
765 (u64) ~CMD_RING_RSVD_BITS) |
766 xhci->cmd_ring->cycle_state;
767 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
768 "// Setting command ring address to 0x%llx",
769 (long unsigned long) val_64);
770 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
771}
772
773/*
774 * The whole command ring must be cleared to zero when we suspend the host.
775 *
776 * The host doesn't save the command ring pointer in the suspend well, so we
777 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
778 * aligned, because of the reserved bits in the command ring dequeue pointer
779 * register. Therefore, we can't just set the dequeue pointer back in the
780 * middle of the ring (TRBs are 16-byte aligned).
781 */
782static void xhci_clear_command_ring(struct xhci_hcd *xhci)
783{
784 struct xhci_ring *ring;
785 struct xhci_segment *seg;
786
787 ring = xhci->cmd_ring;
788 seg = ring->deq_seg;
789 do {
790 memset(seg->trbs, 0,
791 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
792 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
793 cpu_to_le32(~TRB_CYCLE);
794 seg = seg->next;
795 } while (seg != ring->deq_seg);
796
797 xhci_initialize_ring_info(ring, 1);
798 /*
799 * Reset the hardware dequeue pointer.
800 * Yes, this will need to be re-written after resume, but we're paranoid
801 * and want to make sure the hardware doesn't access bogus memory
802 * because, say, the BIOS or an SMI started the host without changing
803 * the command ring pointers.
804 */
805 xhci_set_cmd_ring_deq(xhci);
806}
807
808/*
809 * Disable port wake bits if do_wakeup is not set.
810 *
811 * Also clear a possible internal port wake state left hanging for ports that
812 * detected termination but never successfully enumerated (trained to 0U).
813 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
814 * at enumeration clears this wake, force one here as well for unconnected ports
815 */
816
817static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
818 struct xhci_hub *rhub,
819 bool do_wakeup)
820{
821 unsigned long flags;
822 u32 t1, t2, portsc;
823 int i;
824
825 spin_lock_irqsave(&xhci->lock, flags);
826
827 for (i = 0; i < rhub->num_ports; i++) {
828 portsc = readl(rhub->ports[i]->addr);
829 t1 = xhci_port_state_to_neutral(portsc);
830 t2 = t1;
831
832 /* clear wake bits if do_wake is not set */
833 if (!do_wakeup)
834 t2 &= ~PORT_WAKE_BITS;
835
836 /* Don't touch csc bit if connected or connect change is set */
837 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
838 t2 |= PORT_CSC;
839
840 if (t1 != t2) {
841 writel(t2, rhub->ports[i]->addr);
842 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
843 rhub->hcd->self.busnum, i + 1, portsc, t2);
844 }
845 }
846 spin_unlock_irqrestore(&xhci->lock, flags);
847}
848
849static bool xhci_pending_portevent(struct xhci_hcd *xhci)
850{
851 struct xhci_port **ports;
852 int port_index;
853 u32 status;
854 u32 portsc;
855
856 status = readl(&xhci->op_regs->status);
857 if (status & STS_EINT)
858 return true;
859 /*
860 * Checking STS_EINT is not enough as there is a lag between a change
861 * bit being set and the Port Status Change Event that it generated
862 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
863 */
864
865 port_index = xhci->usb2_rhub.num_ports;
866 ports = xhci->usb2_rhub.ports;
867 while (port_index--) {
868 portsc = readl(ports[port_index]->addr);
869 if (portsc & PORT_CHANGE_MASK ||
870 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
871 return true;
872 }
873 port_index = xhci->usb3_rhub.num_ports;
874 ports = xhci->usb3_rhub.ports;
875 while (port_index--) {
876 portsc = readl(ports[port_index]->addr);
877 if (portsc & (PORT_CHANGE_MASK | PORT_CAS) ||
878 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
879 return true;
880 }
881 return false;
882}
883
884/*
885 * Stop HC (not bus-specific)
886 *
887 * This is called when the machine transition into S3/S4 mode.
888 *
889 */
890int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
891{
892 int rc = 0;
893 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
894 struct usb_hcd *hcd = xhci_to_hcd(xhci);
895 u32 command;
896 u32 res;
897
898 if (!hcd->state)
899 return 0;
900
901 if (hcd->state != HC_STATE_SUSPENDED ||
902 (xhci->shared_hcd && xhci->shared_hcd->state != HC_STATE_SUSPENDED))
903 return -EINVAL;
904
905 /* Clear root port wake on bits if wakeup not allowed. */
906 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
907 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
908
909 if (!HCD_HW_ACCESSIBLE(hcd))
910 return 0;
911
912 xhci_dbc_suspend(xhci);
913
914 /* Don't poll the roothubs on bus suspend. */
915 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
916 __func__, hcd->self.busnum);
917 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
918 del_timer_sync(&hcd->rh_timer);
919 if (xhci->shared_hcd) {
920 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
921 del_timer_sync(&xhci->shared_hcd->rh_timer);
922 }
923
924 if (xhci->quirks & XHCI_SUSPEND_DELAY)
925 usleep_range(1000, 1500);
926
927 spin_lock_irq(&xhci->lock);
928 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
929 if (xhci->shared_hcd)
930 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
931 /* step 1: stop endpoint */
932 /* skipped assuming that port suspend has done */
933
934 /* step 2: clear Run/Stop bit */
935 command = readl(&xhci->op_regs->command);
936 command &= ~CMD_RUN;
937 writel(command, &xhci->op_regs->command);
938
939 /* Some chips from Fresco Logic need an extraordinary delay */
940 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
941
942 if (xhci_handshake(&xhci->op_regs->status,
943 STS_HALT, STS_HALT, delay)) {
944 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
945 spin_unlock_irq(&xhci->lock);
946 return -ETIMEDOUT;
947 }
948 xhci_clear_command_ring(xhci);
949
950 /* step 3: save registers */
951 xhci_save_registers(xhci);
952
953 /* step 4: set CSS flag */
954 command = readl(&xhci->op_regs->command);
955 command |= CMD_CSS;
956 writel(command, &xhci->op_regs->command);
957 xhci->broken_suspend = 0;
958 if (xhci_handshake(&xhci->op_regs->status,
959 STS_SAVE, 0, 20 * 1000)) {
960 /*
961 * AMD SNPS xHC 3.0 occasionally does not clear the
962 * SSS bit of USBSTS and when driver tries to poll
963 * to see if the xHC clears BIT(8) which never happens
964 * and driver assumes that controller is not responding
965 * and times out. To workaround this, its good to check
966 * if SRE and HCE bits are not set (as per xhci
967 * Section 5.4.2) and bypass the timeout.
968 */
969 res = readl(&xhci->op_regs->status);
970 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
971 (((res & STS_SRE) == 0) &&
972 ((res & STS_HCE) == 0))) {
973 xhci->broken_suspend = 1;
974 } else {
975 xhci_warn(xhci, "WARN: xHC save state timeout\n");
976 spin_unlock_irq(&xhci->lock);
977 return -ETIMEDOUT;
978 }
979 }
980 spin_unlock_irq(&xhci->lock);
981
982 /*
983 * Deleting Compliance Mode Recovery Timer because the xHCI Host
984 * is about to be suspended.
985 */
986 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
987 (!(xhci_all_ports_seen_u0(xhci)))) {
988 del_timer_sync(&xhci->comp_mode_recovery_timer);
989 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
990 "%s: compliance mode recovery timer deleted",
991 __func__);
992 }
993
994 return rc;
995}
996EXPORT_SYMBOL_GPL(xhci_suspend);
997
998/*
999 * start xHC (not bus-specific)
1000 *
1001 * This is called when the machine transition from S3/S4 mode.
1002 *
1003 */
1004int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg)
1005{
1006 bool hibernated = (msg.event == PM_EVENT_RESTORE);
1007 u32 command, temp = 0;
1008 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1009 int retval = 0;
1010 bool comp_timer_running = false;
1011 bool pending_portevent = false;
1012 bool suspended_usb3_devs = false;
1013 bool reinit_xhc = false;
1014
1015 if (!hcd->state)
1016 return 0;
1017
1018 /* Wait a bit if either of the roothubs need to settle from the
1019 * transition into bus suspend.
1020 */
1021
1022 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1023 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1024 msleep(100);
1025
1026 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1027 if (xhci->shared_hcd)
1028 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1029
1030 spin_lock_irq(&xhci->lock);
1031
1032 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1033 reinit_xhc = true;
1034
1035 if (!reinit_xhc) {
1036 /*
1037 * Some controllers might lose power during suspend, so wait
1038 * for controller not ready bit to clear, just as in xHC init.
1039 */
1040 retval = xhci_handshake(&xhci->op_regs->status,
1041 STS_CNR, 0, 10 * 1000 * 1000);
1042 if (retval) {
1043 xhci_warn(xhci, "Controller not ready at resume %d\n",
1044 retval);
1045 spin_unlock_irq(&xhci->lock);
1046 return retval;
1047 }
1048 /* step 1: restore register */
1049 xhci_restore_registers(xhci);
1050 /* step 2: initialize command ring buffer */
1051 xhci_set_cmd_ring_deq(xhci);
1052 /* step 3: restore state and start state*/
1053 /* step 3: set CRS flag */
1054 command = readl(&xhci->op_regs->command);
1055 command |= CMD_CRS;
1056 writel(command, &xhci->op_regs->command);
1057 /*
1058 * Some controllers take up to 55+ ms to complete the controller
1059 * restore so setting the timeout to 100ms. Xhci specification
1060 * doesn't mention any timeout value.
1061 */
1062 if (xhci_handshake(&xhci->op_regs->status,
1063 STS_RESTORE, 0, 100 * 1000)) {
1064 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1065 spin_unlock_irq(&xhci->lock);
1066 return -ETIMEDOUT;
1067 }
1068 }
1069
1070 temp = readl(&xhci->op_regs->status);
1071
1072 /* re-initialize the HC on Restore Error, or Host Controller Error */
1073 if ((temp & (STS_SRE | STS_HCE)) &&
1074 !(xhci->xhc_state & XHCI_STATE_REMOVING)) {
1075 reinit_xhc = true;
1076 if (!xhci->broken_suspend)
1077 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1078 }
1079
1080 if (reinit_xhc) {
1081 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1082 !(xhci_all_ports_seen_u0(xhci))) {
1083 del_timer_sync(&xhci->comp_mode_recovery_timer);
1084 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1085 "Compliance Mode Recovery Timer deleted!");
1086 }
1087
1088 /* Let the USB core know _both_ roothubs lost power. */
1089 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1090 if (xhci->shared_hcd)
1091 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1092
1093 xhci_dbg(xhci, "Stop HCD\n");
1094 xhci_halt(xhci);
1095 xhci_zero_64b_regs(xhci);
1096 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1097 spin_unlock_irq(&xhci->lock);
1098 if (retval)
1099 return retval;
1100
1101 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1102 temp = readl(&xhci->op_regs->status);
1103 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1104 xhci_disable_interrupter(xhci->interrupters[0]);
1105
1106 xhci_dbg(xhci, "cleaning up memory\n");
1107 xhci_mem_cleanup(xhci);
1108 xhci_debugfs_exit(xhci);
1109 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1110 readl(&xhci->op_regs->status));
1111
1112 /* USB core calls the PCI reinit and start functions twice:
1113 * first with the primary HCD, and then with the secondary HCD.
1114 * If we don't do the same, the host will never be started.
1115 */
1116 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1117 retval = xhci_init(hcd);
1118 if (retval)
1119 return retval;
1120 comp_timer_running = true;
1121
1122 xhci_dbg(xhci, "Start the primary HCD\n");
1123 retval = xhci_run(hcd);
1124 if (!retval && xhci->shared_hcd) {
1125 xhci_dbg(xhci, "Start the secondary HCD\n");
1126 retval = xhci_run(xhci->shared_hcd);
1127 }
1128
1129 hcd->state = HC_STATE_SUSPENDED;
1130 if (xhci->shared_hcd)
1131 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1132 goto done;
1133 }
1134
1135 /* step 4: set Run/Stop bit */
1136 command = readl(&xhci->op_regs->command);
1137 command |= CMD_RUN;
1138 writel(command, &xhci->op_regs->command);
1139 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1140 0, 250 * 1000);
1141
1142 /* step 5: walk topology and initialize portsc,
1143 * portpmsc and portli
1144 */
1145 /* this is done in bus_resume */
1146
1147 /* step 6: restart each of the previously
1148 * Running endpoints by ringing their doorbells
1149 */
1150
1151 spin_unlock_irq(&xhci->lock);
1152
1153 xhci_dbc_resume(xhci);
1154
1155 done:
1156 if (retval == 0) {
1157 /*
1158 * Resume roothubs only if there are pending events.
1159 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1160 * the first wake signalling failed, give it that chance if
1161 * there are suspended USB 3 devices.
1162 */
1163 if (xhci->usb3_rhub.bus_state.suspended_ports ||
1164 xhci->usb3_rhub.bus_state.bus_suspended)
1165 suspended_usb3_devs = true;
1166
1167 pending_portevent = xhci_pending_portevent(xhci);
1168
1169 if (suspended_usb3_devs && !pending_portevent &&
1170 msg.event == PM_EVENT_AUTO_RESUME) {
1171 msleep(120);
1172 pending_portevent = xhci_pending_portevent(xhci);
1173 }
1174
1175 if (pending_portevent) {
1176 if (xhci->shared_hcd)
1177 usb_hcd_resume_root_hub(xhci->shared_hcd);
1178 usb_hcd_resume_root_hub(hcd);
1179 }
1180 }
1181 /*
1182 * If system is subject to the Quirk, Compliance Mode Timer needs to
1183 * be re-initialized Always after a system resume. Ports are subject
1184 * to suffer the Compliance Mode issue again. It doesn't matter if
1185 * ports have entered previously to U0 before system's suspension.
1186 */
1187 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1188 compliance_mode_recovery_timer_init(xhci);
1189
1190 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1191 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1192
1193 /* Re-enable port polling. */
1194 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1195 __func__, hcd->self.busnum);
1196 if (xhci->shared_hcd) {
1197 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1198 usb_hcd_poll_rh_status(xhci->shared_hcd);
1199 }
1200 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1201 usb_hcd_poll_rh_status(hcd);
1202
1203 return retval;
1204}
1205EXPORT_SYMBOL_GPL(xhci_resume);
1206#endif /* CONFIG_PM */
1207
1208/*-------------------------------------------------------------------------*/
1209
1210static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1211{
1212 void *temp;
1213 int ret = 0;
1214 unsigned int buf_len;
1215 enum dma_data_direction dir;
1216
1217 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1218 buf_len = urb->transfer_buffer_length;
1219
1220 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1221 dev_to_node(hcd->self.sysdev));
1222 if (!temp)
1223 return -ENOMEM;
1224
1225 if (usb_urb_dir_out(urb))
1226 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1227 temp, buf_len, 0);
1228
1229 urb->transfer_buffer = temp;
1230 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1231 urb->transfer_buffer,
1232 urb->transfer_buffer_length,
1233 dir);
1234
1235 if (dma_mapping_error(hcd->self.sysdev,
1236 urb->transfer_dma)) {
1237 ret = -EAGAIN;
1238 kfree(temp);
1239 } else {
1240 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1241 }
1242
1243 return ret;
1244}
1245
1246static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1247 struct urb *urb)
1248{
1249 bool ret = false;
1250 unsigned int i;
1251 unsigned int len = 0;
1252 unsigned int trb_size;
1253 unsigned int max_pkt;
1254 struct scatterlist *sg;
1255 struct scatterlist *tail_sg;
1256
1257 tail_sg = urb->sg;
1258 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1259
1260 if (!urb->num_sgs)
1261 return ret;
1262
1263 if (urb->dev->speed >= USB_SPEED_SUPER)
1264 trb_size = TRB_CACHE_SIZE_SS;
1265 else
1266 trb_size = TRB_CACHE_SIZE_HS;
1267
1268 if (urb->transfer_buffer_length != 0 &&
1269 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1270 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1271 len = len + sg->length;
1272 if (i > trb_size - 2) {
1273 len = len - tail_sg->length;
1274 if (len < max_pkt) {
1275 ret = true;
1276 break;
1277 }
1278
1279 tail_sg = sg_next(tail_sg);
1280 }
1281 }
1282 }
1283 return ret;
1284}
1285
1286static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1287{
1288 unsigned int len;
1289 unsigned int buf_len;
1290 enum dma_data_direction dir;
1291
1292 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1293
1294 buf_len = urb->transfer_buffer_length;
1295
1296 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1297 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1298 dma_unmap_single(hcd->self.sysdev,
1299 urb->transfer_dma,
1300 urb->transfer_buffer_length,
1301 dir);
1302
1303 if (usb_urb_dir_in(urb)) {
1304 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1305 urb->transfer_buffer,
1306 buf_len,
1307 0);
1308 if (len != buf_len) {
1309 xhci_dbg(hcd_to_xhci(hcd),
1310 "Copy from tmp buf to urb sg list failed\n");
1311 urb->actual_length = len;
1312 }
1313 }
1314 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1315 kfree(urb->transfer_buffer);
1316 urb->transfer_buffer = NULL;
1317}
1318
1319/*
1320 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1321 * we'll copy the actual data into the TRB address register. This is limited to
1322 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1323 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1324 */
1325static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1326 gfp_t mem_flags)
1327{
1328 struct xhci_hcd *xhci;
1329
1330 xhci = hcd_to_xhci(hcd);
1331
1332 if (xhci_urb_suitable_for_idt(urb))
1333 return 0;
1334
1335 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1336 if (xhci_urb_temp_buffer_required(hcd, urb))
1337 return xhci_map_temp_buffer(hcd, urb);
1338 }
1339 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1340}
1341
1342static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1343{
1344 struct xhci_hcd *xhci;
1345 bool unmap_temp_buf = false;
1346
1347 xhci = hcd_to_xhci(hcd);
1348
1349 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1350 unmap_temp_buf = true;
1351
1352 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1353 xhci_unmap_temp_buf(hcd, urb);
1354 else
1355 usb_hcd_unmap_urb_for_dma(hcd, urb);
1356}
1357
1358/**
1359 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1360 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1361 * value to right shift 1 for the bitmask.
1362 *
1363 * Index = (epnum * 2) + direction - 1,
1364 * where direction = 0 for OUT, 1 for IN.
1365 * For control endpoints, the IN index is used (OUT index is unused), so
1366 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1367 */
1368unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1369{
1370 unsigned int index;
1371 if (usb_endpoint_xfer_control(desc))
1372 index = (unsigned int) (usb_endpoint_num(desc)*2);
1373 else
1374 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1375 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1376 return index;
1377}
1378EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1379
1380/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1381 * address from the XHCI endpoint index.
1382 */
1383static unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1384{
1385 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1386 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1387 return direction | number;
1388}
1389
1390/* Find the flag for this endpoint (for use in the control context). Use the
1391 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1392 * bit 1, etc.
1393 */
1394static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1395{
1396 return 1 << (xhci_get_endpoint_index(desc) + 1);
1397}
1398
1399/* Compute the last valid endpoint context index. Basically, this is the
1400 * endpoint index plus one. For slot contexts with more than valid endpoint,
1401 * we find the most significant bit set in the added contexts flags.
1402 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1403 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1404 */
1405unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1406{
1407 return fls(added_ctxs) - 1;
1408}
1409
1410/* Returns 1 if the arguments are OK;
1411 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1412 */
1413static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1414 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1415 const char *func) {
1416 struct xhci_hcd *xhci;
1417 struct xhci_virt_device *virt_dev;
1418
1419 if (!hcd || (check_ep && !ep) || !udev) {
1420 pr_debug("xHCI %s called with invalid args\n", func);
1421 return -EINVAL;
1422 }
1423 if (!udev->parent) {
1424 pr_debug("xHCI %s called for root hub\n", func);
1425 return 0;
1426 }
1427
1428 xhci = hcd_to_xhci(hcd);
1429 if (check_virt_dev) {
1430 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1431 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1432 func);
1433 return -EINVAL;
1434 }
1435
1436 virt_dev = xhci->devs[udev->slot_id];
1437 if (virt_dev->udev != udev) {
1438 xhci_dbg(xhci, "xHCI %s called with udev and "
1439 "virt_dev does not match\n", func);
1440 return -EINVAL;
1441 }
1442 }
1443
1444 if (xhci->xhc_state & XHCI_STATE_HALTED)
1445 return -ENODEV;
1446
1447 return 1;
1448}
1449
1450static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1451 struct usb_device *udev, struct xhci_command *command,
1452 bool ctx_change, bool must_succeed);
1453
1454/*
1455 * Full speed devices may have a max packet size greater than 8 bytes, but the
1456 * USB core doesn't know that until it reads the first 8 bytes of the
1457 * descriptor. If the usb_device's max packet size changes after that point,
1458 * we need to issue an evaluate context command and wait on it.
1459 */
1460static int xhci_check_ep0_maxpacket(struct xhci_hcd *xhci, struct xhci_virt_device *vdev)
1461{
1462 struct xhci_input_control_ctx *ctrl_ctx;
1463 struct xhci_ep_ctx *ep_ctx;
1464 struct xhci_command *command;
1465 int max_packet_size;
1466 int hw_max_packet_size;
1467 int ret = 0;
1468
1469 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, 0);
1470 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1471 max_packet_size = usb_endpoint_maxp(&vdev->udev->ep0.desc);
1472
1473 if (hw_max_packet_size == max_packet_size)
1474 return 0;
1475
1476 switch (max_packet_size) {
1477 case 8: case 16: case 32: case 64: case 9:
1478 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1479 "Max Packet Size for ep 0 changed.");
1480 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1481 "Max packet size in usb_device = %d",
1482 max_packet_size);
1483 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1484 "Max packet size in xHCI HW = %d",
1485 hw_max_packet_size);
1486 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1487 "Issuing evaluate context command.");
1488
1489 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
1490 if (!command)
1491 return -ENOMEM;
1492
1493 command->in_ctx = vdev->in_ctx;
1494 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1495 if (!ctrl_ctx) {
1496 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1497 __func__);
1498 ret = -ENOMEM;
1499 break;
1500 }
1501 /* Set up the modified control endpoint 0 */
1502 xhci_endpoint_copy(xhci, vdev->in_ctx, vdev->out_ctx, 0);
1503
1504 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, 0);
1505 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1506 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1507 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1508
1509 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1510 ctrl_ctx->drop_flags = 0;
1511
1512 ret = xhci_configure_endpoint(xhci, vdev->udev, command,
1513 true, false);
1514 /* Clean up the input context for later use by bandwidth functions */
1515 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1516 break;
1517 default:
1518 dev_dbg(&vdev->udev->dev, "incorrect max packet size %d for ep0\n",
1519 max_packet_size);
1520 return -EINVAL;
1521 }
1522
1523 kfree(command->completion);
1524 kfree(command);
1525
1526 return ret;
1527}
1528
1529/*
1530 * non-error returns are a promise to giveback() the urb later
1531 * we drop ownership so next owner (or urb unlink) can get it
1532 */
1533static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1534{
1535 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1536 unsigned long flags;
1537 int ret = 0;
1538 unsigned int slot_id, ep_index;
1539 unsigned int *ep_state;
1540 struct urb_priv *urb_priv;
1541 int num_tds;
1542
1543 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1544
1545 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1546 num_tds = urb->number_of_packets;
1547 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1548 urb->transfer_buffer_length > 0 &&
1549 urb->transfer_flags & URB_ZERO_PACKET &&
1550 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1551 num_tds = 2;
1552 else
1553 num_tds = 1;
1554
1555 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1556 if (!urb_priv)
1557 return -ENOMEM;
1558
1559 urb_priv->num_tds = num_tds;
1560 urb_priv->num_tds_done = 0;
1561 urb->hcpriv = urb_priv;
1562
1563 trace_xhci_urb_enqueue(urb);
1564
1565 spin_lock_irqsave(&xhci->lock, flags);
1566
1567 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1568 true, true, __func__);
1569 if (ret <= 0) {
1570 ret = ret ? ret : -EINVAL;
1571 goto free_priv;
1572 }
1573
1574 slot_id = urb->dev->slot_id;
1575
1576 if (!HCD_HW_ACCESSIBLE(hcd)) {
1577 ret = -ESHUTDOWN;
1578 goto free_priv;
1579 }
1580
1581 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1582 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1583 ret = -ENODEV;
1584 goto free_priv;
1585 }
1586
1587 if (xhci->xhc_state & XHCI_STATE_DYING) {
1588 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1589 urb->ep->desc.bEndpointAddress, urb);
1590 ret = -ESHUTDOWN;
1591 goto free_priv;
1592 }
1593
1594 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1595
1596 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1597 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1598 *ep_state);
1599 ret = -EINVAL;
1600 goto free_priv;
1601 }
1602 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1603 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1604 ret = -EINVAL;
1605 goto free_priv;
1606 }
1607
1608 switch (usb_endpoint_type(&urb->ep->desc)) {
1609
1610 case USB_ENDPOINT_XFER_CONTROL:
1611 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1612 slot_id, ep_index);
1613 break;
1614 case USB_ENDPOINT_XFER_BULK:
1615 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1616 slot_id, ep_index);
1617 break;
1618 case USB_ENDPOINT_XFER_INT:
1619 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1620 slot_id, ep_index);
1621 break;
1622 case USB_ENDPOINT_XFER_ISOC:
1623 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1624 slot_id, ep_index);
1625 }
1626
1627 if (ret) {
1628free_priv:
1629 xhci_urb_free_priv(urb_priv);
1630 urb->hcpriv = NULL;
1631 }
1632 spin_unlock_irqrestore(&xhci->lock, flags);
1633 return ret;
1634}
1635
1636/*
1637 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1638 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1639 * should pick up where it left off in the TD, unless a Set Transfer Ring
1640 * Dequeue Pointer is issued.
1641 *
1642 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1643 * the ring. Since the ring is a contiguous structure, they can't be physically
1644 * removed. Instead, there are two options:
1645 *
1646 * 1) If the HC is in the middle of processing the URB to be canceled, we
1647 * simply move the ring's dequeue pointer past those TRBs using the Set
1648 * Transfer Ring Dequeue Pointer command. This will be the common case,
1649 * when drivers timeout on the last submitted URB and attempt to cancel.
1650 *
1651 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1652 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1653 * HC will need to invalidate the any TRBs it has cached after the stop
1654 * endpoint command, as noted in the xHCI 0.95 errata.
1655 *
1656 * 3) The TD may have completed by the time the Stop Endpoint Command
1657 * completes, so software needs to handle that case too.
1658 *
1659 * This function should protect against the TD enqueueing code ringing the
1660 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1661 * It also needs to account for multiple cancellations on happening at the same
1662 * time for the same endpoint.
1663 *
1664 * Note that this function can be called in any context, or so says
1665 * usb_hcd_unlink_urb()
1666 */
1667static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1668{
1669 unsigned long flags;
1670 int ret, i;
1671 u32 temp;
1672 struct xhci_hcd *xhci;
1673 struct urb_priv *urb_priv;
1674 struct xhci_td *td;
1675 unsigned int ep_index;
1676 struct xhci_ring *ep_ring;
1677 struct xhci_virt_ep *ep;
1678 struct xhci_command *command;
1679 struct xhci_virt_device *vdev;
1680
1681 xhci = hcd_to_xhci(hcd);
1682 spin_lock_irqsave(&xhci->lock, flags);
1683
1684 trace_xhci_urb_dequeue(urb);
1685
1686 /* Make sure the URB hasn't completed or been unlinked already */
1687 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1688 if (ret)
1689 goto done;
1690
1691 /* give back URB now if we can't queue it for cancel */
1692 vdev = xhci->devs[urb->dev->slot_id];
1693 urb_priv = urb->hcpriv;
1694 if (!vdev || !urb_priv)
1695 goto err_giveback;
1696
1697 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1698 ep = &vdev->eps[ep_index];
1699 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1700 if (!ep || !ep_ring)
1701 goto err_giveback;
1702
1703 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1704 temp = readl(&xhci->op_regs->status);
1705 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1706 xhci_hc_died(xhci);
1707 goto done;
1708 }
1709
1710 /*
1711 * check ring is not re-allocated since URB was enqueued. If it is, then
1712 * make sure none of the ring related pointers in this URB private data
1713 * are touched, such as td_list, otherwise we overwrite freed data
1714 */
1715 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1716 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1717 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1718 td = &urb_priv->td[i];
1719 if (!list_empty(&td->cancelled_td_list))
1720 list_del_init(&td->cancelled_td_list);
1721 }
1722 goto err_giveback;
1723 }
1724
1725 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1726 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1727 "HC halted, freeing TD manually.");
1728 for (i = urb_priv->num_tds_done;
1729 i < urb_priv->num_tds;
1730 i++) {
1731 td = &urb_priv->td[i];
1732 if (!list_empty(&td->td_list))
1733 list_del_init(&td->td_list);
1734 if (!list_empty(&td->cancelled_td_list))
1735 list_del_init(&td->cancelled_td_list);
1736 }
1737 goto err_giveback;
1738 }
1739
1740 i = urb_priv->num_tds_done;
1741 if (i < urb_priv->num_tds)
1742 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1743 "Cancel URB %p, dev %s, ep 0x%x, "
1744 "starting at offset 0x%llx",
1745 urb, urb->dev->devpath,
1746 urb->ep->desc.bEndpointAddress,
1747 (unsigned long long) xhci_trb_virt_to_dma(
1748 urb_priv->td[i].start_seg,
1749 urb_priv->td[i].first_trb));
1750
1751 for (; i < urb_priv->num_tds; i++) {
1752 td = &urb_priv->td[i];
1753 /* TD can already be on cancelled list if ep halted on it */
1754 if (list_empty(&td->cancelled_td_list)) {
1755 td->cancel_status = TD_DIRTY;
1756 list_add_tail(&td->cancelled_td_list,
1757 &ep->cancelled_td_list);
1758 }
1759 }
1760
1761 /* Queue a stop endpoint command, but only if this is
1762 * the first cancellation to be handled.
1763 */
1764 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1765 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1766 if (!command) {
1767 ret = -ENOMEM;
1768 goto done;
1769 }
1770 ep->ep_state |= EP_STOP_CMD_PENDING;
1771 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1772 ep_index, 0);
1773 xhci_ring_cmd_db(xhci);
1774 }
1775done:
1776 spin_unlock_irqrestore(&xhci->lock, flags);
1777 return ret;
1778
1779err_giveback:
1780 if (urb_priv)
1781 xhci_urb_free_priv(urb_priv);
1782 usb_hcd_unlink_urb_from_ep(hcd, urb);
1783 spin_unlock_irqrestore(&xhci->lock, flags);
1784 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1785 return ret;
1786}
1787
1788/* Drop an endpoint from a new bandwidth configuration for this device.
1789 * Only one call to this function is allowed per endpoint before
1790 * check_bandwidth() or reset_bandwidth() must be called.
1791 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1792 * add the endpoint to the schedule with possibly new parameters denoted by a
1793 * different endpoint descriptor in usb_host_endpoint.
1794 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1795 * not allowed.
1796 *
1797 * The USB core will not allow URBs to be queued to an endpoint that is being
1798 * disabled, so there's no need for mutual exclusion to protect
1799 * the xhci->devs[slot_id] structure.
1800 */
1801int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1802 struct usb_host_endpoint *ep)
1803{
1804 struct xhci_hcd *xhci;
1805 struct xhci_container_ctx *in_ctx, *out_ctx;
1806 struct xhci_input_control_ctx *ctrl_ctx;
1807 unsigned int ep_index;
1808 struct xhci_ep_ctx *ep_ctx;
1809 u32 drop_flag;
1810 u32 new_add_flags, new_drop_flags;
1811 int ret;
1812
1813 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1814 if (ret <= 0)
1815 return ret;
1816 xhci = hcd_to_xhci(hcd);
1817 if (xhci->xhc_state & XHCI_STATE_DYING)
1818 return -ENODEV;
1819
1820 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1821 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1822 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1823 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1824 __func__, drop_flag);
1825 return 0;
1826 }
1827
1828 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1829 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1830 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1831 if (!ctrl_ctx) {
1832 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1833 __func__);
1834 return 0;
1835 }
1836
1837 ep_index = xhci_get_endpoint_index(&ep->desc);
1838 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1839 /* If the HC already knows the endpoint is disabled,
1840 * or the HCD has noted it is disabled, ignore this request
1841 */
1842 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1843 le32_to_cpu(ctrl_ctx->drop_flags) &
1844 xhci_get_endpoint_flag(&ep->desc)) {
1845 /* Do not warn when called after a usb_device_reset */
1846 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1847 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1848 __func__, ep);
1849 return 0;
1850 }
1851
1852 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1853 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1854
1855 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1856 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1857
1858 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1859
1860 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1861
1862 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1863 (unsigned int) ep->desc.bEndpointAddress,
1864 udev->slot_id,
1865 (unsigned int) new_drop_flags,
1866 (unsigned int) new_add_flags);
1867 return 0;
1868}
1869EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
1870
1871/* Add an endpoint to a new possible bandwidth configuration for this device.
1872 * Only one call to this function is allowed per endpoint before
1873 * check_bandwidth() or reset_bandwidth() must be called.
1874 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1875 * add the endpoint to the schedule with possibly new parameters denoted by a
1876 * different endpoint descriptor in usb_host_endpoint.
1877 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1878 * not allowed.
1879 *
1880 * The USB core will not allow URBs to be queued to an endpoint until the
1881 * configuration or alt setting is installed in the device, so there's no need
1882 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1883 */
1884int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1885 struct usb_host_endpoint *ep)
1886{
1887 struct xhci_hcd *xhci;
1888 struct xhci_container_ctx *in_ctx;
1889 unsigned int ep_index;
1890 struct xhci_input_control_ctx *ctrl_ctx;
1891 struct xhci_ep_ctx *ep_ctx;
1892 u32 added_ctxs;
1893 u32 new_add_flags, new_drop_flags;
1894 struct xhci_virt_device *virt_dev;
1895 int ret = 0;
1896
1897 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1898 if (ret <= 0) {
1899 /* So we won't queue a reset ep command for a root hub */
1900 ep->hcpriv = NULL;
1901 return ret;
1902 }
1903 xhci = hcd_to_xhci(hcd);
1904 if (xhci->xhc_state & XHCI_STATE_DYING)
1905 return -ENODEV;
1906
1907 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1908 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1909 /* FIXME when we have to issue an evaluate endpoint command to
1910 * deal with ep0 max packet size changing once we get the
1911 * descriptors
1912 */
1913 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1914 __func__, added_ctxs);
1915 return 0;
1916 }
1917
1918 virt_dev = xhci->devs[udev->slot_id];
1919 in_ctx = virt_dev->in_ctx;
1920 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1921 if (!ctrl_ctx) {
1922 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1923 __func__);
1924 return 0;
1925 }
1926
1927 ep_index = xhci_get_endpoint_index(&ep->desc);
1928 /* If this endpoint is already in use, and the upper layers are trying
1929 * to add it again without dropping it, reject the addition.
1930 */
1931 if (virt_dev->eps[ep_index].ring &&
1932 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1933 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1934 "without dropping it.\n",
1935 (unsigned int) ep->desc.bEndpointAddress);
1936 return -EINVAL;
1937 }
1938
1939 /* If the HCD has already noted the endpoint is enabled,
1940 * ignore this request.
1941 */
1942 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1943 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1944 __func__, ep);
1945 return 0;
1946 }
1947
1948 /*
1949 * Configuration and alternate setting changes must be done in
1950 * process context, not interrupt context (or so documenation
1951 * for usb_set_interface() and usb_set_configuration() claim).
1952 */
1953 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1954 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1955 __func__, ep->desc.bEndpointAddress);
1956 return -ENOMEM;
1957 }
1958
1959 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1960 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1961
1962 /* If xhci_endpoint_disable() was called for this endpoint, but the
1963 * xHC hasn't been notified yet through the check_bandwidth() call,
1964 * this re-adds a new state for the endpoint from the new endpoint
1965 * descriptors. We must drop and re-add this endpoint, so we leave the
1966 * drop flags alone.
1967 */
1968 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1969
1970 /* Store the usb_device pointer for later use */
1971 ep->hcpriv = udev;
1972
1973 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1974 trace_xhci_add_endpoint(ep_ctx);
1975
1976 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1977 (unsigned int) ep->desc.bEndpointAddress,
1978 udev->slot_id,
1979 (unsigned int) new_drop_flags,
1980 (unsigned int) new_add_flags);
1981 return 0;
1982}
1983EXPORT_SYMBOL_GPL(xhci_add_endpoint);
1984
1985static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1986{
1987 struct xhci_input_control_ctx *ctrl_ctx;
1988 struct xhci_ep_ctx *ep_ctx;
1989 struct xhci_slot_ctx *slot_ctx;
1990 int i;
1991
1992 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1993 if (!ctrl_ctx) {
1994 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1995 __func__);
1996 return;
1997 }
1998
1999 /* When a device's add flag and drop flag are zero, any subsequent
2000 * configure endpoint command will leave that endpoint's state
2001 * untouched. Make sure we don't leave any old state in the input
2002 * endpoint contexts.
2003 */
2004 ctrl_ctx->drop_flags = 0;
2005 ctrl_ctx->add_flags = 0;
2006 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2007 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2008 /* Endpoint 0 is always valid */
2009 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2010 for (i = 1; i < 31; i++) {
2011 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2012 ep_ctx->ep_info = 0;
2013 ep_ctx->ep_info2 = 0;
2014 ep_ctx->deq = 0;
2015 ep_ctx->tx_info = 0;
2016 }
2017}
2018
2019static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2020 struct usb_device *udev, u32 *cmd_status)
2021{
2022 int ret;
2023
2024 switch (*cmd_status) {
2025 case COMP_COMMAND_ABORTED:
2026 case COMP_COMMAND_RING_STOPPED:
2027 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2028 ret = -ETIME;
2029 break;
2030 case COMP_RESOURCE_ERROR:
2031 dev_warn(&udev->dev,
2032 "Not enough host controller resources for new device state.\n");
2033 ret = -ENOMEM;
2034 /* FIXME: can we allocate more resources for the HC? */
2035 break;
2036 case COMP_BANDWIDTH_ERROR:
2037 case COMP_SECONDARY_BANDWIDTH_ERROR:
2038 dev_warn(&udev->dev,
2039 "Not enough bandwidth for new device state.\n");
2040 ret = -ENOSPC;
2041 /* FIXME: can we go back to the old state? */
2042 break;
2043 case COMP_TRB_ERROR:
2044 /* the HCD set up something wrong */
2045 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2046 "add flag = 1, "
2047 "and endpoint is not disabled.\n");
2048 ret = -EINVAL;
2049 break;
2050 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2051 dev_warn(&udev->dev,
2052 "ERROR: Incompatible device for endpoint configure command.\n");
2053 ret = -ENODEV;
2054 break;
2055 case COMP_SUCCESS:
2056 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2057 "Successful Endpoint Configure command");
2058 ret = 0;
2059 break;
2060 default:
2061 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2062 *cmd_status);
2063 ret = -EINVAL;
2064 break;
2065 }
2066 return ret;
2067}
2068
2069static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2070 struct usb_device *udev, u32 *cmd_status)
2071{
2072 int ret;
2073
2074 switch (*cmd_status) {
2075 case COMP_COMMAND_ABORTED:
2076 case COMP_COMMAND_RING_STOPPED:
2077 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2078 ret = -ETIME;
2079 break;
2080 case COMP_PARAMETER_ERROR:
2081 dev_warn(&udev->dev,
2082 "WARN: xHCI driver setup invalid evaluate context command.\n");
2083 ret = -EINVAL;
2084 break;
2085 case COMP_SLOT_NOT_ENABLED_ERROR:
2086 dev_warn(&udev->dev,
2087 "WARN: slot not enabled for evaluate context command.\n");
2088 ret = -EINVAL;
2089 break;
2090 case COMP_CONTEXT_STATE_ERROR:
2091 dev_warn(&udev->dev,
2092 "WARN: invalid context state for evaluate context command.\n");
2093 ret = -EINVAL;
2094 break;
2095 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2096 dev_warn(&udev->dev,
2097 "ERROR: Incompatible device for evaluate context command.\n");
2098 ret = -ENODEV;
2099 break;
2100 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2101 /* Max Exit Latency too large error */
2102 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2103 ret = -EINVAL;
2104 break;
2105 case COMP_SUCCESS:
2106 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2107 "Successful evaluate context command");
2108 ret = 0;
2109 break;
2110 default:
2111 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2112 *cmd_status);
2113 ret = -EINVAL;
2114 break;
2115 }
2116 return ret;
2117}
2118
2119static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2120 struct xhci_input_control_ctx *ctrl_ctx)
2121{
2122 u32 valid_add_flags;
2123 u32 valid_drop_flags;
2124
2125 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2126 * (bit 1). The default control endpoint is added during the Address
2127 * Device command and is never removed until the slot is disabled.
2128 */
2129 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2130 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2131
2132 /* Use hweight32 to count the number of ones in the add flags, or
2133 * number of endpoints added. Don't count endpoints that are changed
2134 * (both added and dropped).
2135 */
2136 return hweight32(valid_add_flags) -
2137 hweight32(valid_add_flags & valid_drop_flags);
2138}
2139
2140static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2141 struct xhci_input_control_ctx *ctrl_ctx)
2142{
2143 u32 valid_add_flags;
2144 u32 valid_drop_flags;
2145
2146 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2147 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2148
2149 return hweight32(valid_drop_flags) -
2150 hweight32(valid_add_flags & valid_drop_flags);
2151}
2152
2153/*
2154 * We need to reserve the new number of endpoints before the configure endpoint
2155 * command completes. We can't subtract the dropped endpoints from the number
2156 * of active endpoints until the command completes because we can oversubscribe
2157 * the host in this case:
2158 *
2159 * - the first configure endpoint command drops more endpoints than it adds
2160 * - a second configure endpoint command that adds more endpoints is queued
2161 * - the first configure endpoint command fails, so the config is unchanged
2162 * - the second command may succeed, even though there isn't enough resources
2163 *
2164 * Must be called with xhci->lock held.
2165 */
2166static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2167 struct xhci_input_control_ctx *ctrl_ctx)
2168{
2169 u32 added_eps;
2170
2171 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2172 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2173 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2174 "Not enough ep ctxs: "
2175 "%u active, need to add %u, limit is %u.",
2176 xhci->num_active_eps, added_eps,
2177 xhci->limit_active_eps);
2178 return -ENOMEM;
2179 }
2180 xhci->num_active_eps += added_eps;
2181 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2182 "Adding %u ep ctxs, %u now active.", added_eps,
2183 xhci->num_active_eps);
2184 return 0;
2185}
2186
2187/*
2188 * The configure endpoint was failed by the xHC for some other reason, so we
2189 * need to revert the resources that failed configuration would have used.
2190 *
2191 * Must be called with xhci->lock held.
2192 */
2193static void xhci_free_host_resources(struct xhci_hcd *xhci,
2194 struct xhci_input_control_ctx *ctrl_ctx)
2195{
2196 u32 num_failed_eps;
2197
2198 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2199 xhci->num_active_eps -= num_failed_eps;
2200 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2201 "Removing %u failed ep ctxs, %u now active.",
2202 num_failed_eps,
2203 xhci->num_active_eps);
2204}
2205
2206/*
2207 * Now that the command has completed, clean up the active endpoint count by
2208 * subtracting out the endpoints that were dropped (but not changed).
2209 *
2210 * Must be called with xhci->lock held.
2211 */
2212static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2213 struct xhci_input_control_ctx *ctrl_ctx)
2214{
2215 u32 num_dropped_eps;
2216
2217 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2218 xhci->num_active_eps -= num_dropped_eps;
2219 if (num_dropped_eps)
2220 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2221 "Removing %u dropped ep ctxs, %u now active.",
2222 num_dropped_eps,
2223 xhci->num_active_eps);
2224}
2225
2226static unsigned int xhci_get_block_size(struct usb_device *udev)
2227{
2228 switch (udev->speed) {
2229 case USB_SPEED_LOW:
2230 case USB_SPEED_FULL:
2231 return FS_BLOCK;
2232 case USB_SPEED_HIGH:
2233 return HS_BLOCK;
2234 case USB_SPEED_SUPER:
2235 case USB_SPEED_SUPER_PLUS:
2236 return SS_BLOCK;
2237 case USB_SPEED_UNKNOWN:
2238 default:
2239 /* Should never happen */
2240 return 1;
2241 }
2242}
2243
2244static unsigned int
2245xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2246{
2247 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2248 return LS_OVERHEAD;
2249 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2250 return FS_OVERHEAD;
2251 return HS_OVERHEAD;
2252}
2253
2254/* If we are changing a LS/FS device under a HS hub,
2255 * make sure (if we are activating a new TT) that the HS bus has enough
2256 * bandwidth for this new TT.
2257 */
2258static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2259 struct xhci_virt_device *virt_dev,
2260 int old_active_eps)
2261{
2262 struct xhci_interval_bw_table *bw_table;
2263 struct xhci_tt_bw_info *tt_info;
2264
2265 /* Find the bandwidth table for the root port this TT is attached to. */
2266 bw_table = &xhci->rh_bw[virt_dev->rhub_port->hw_portnum].bw_table;
2267 tt_info = virt_dev->tt_info;
2268 /* If this TT already had active endpoints, the bandwidth for this TT
2269 * has already been added. Removing all periodic endpoints (and thus
2270 * making the TT enactive) will only decrease the bandwidth used.
2271 */
2272 if (old_active_eps)
2273 return 0;
2274 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2275 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2276 return -ENOMEM;
2277 return 0;
2278 }
2279 /* Not sure why we would have no new active endpoints...
2280 *
2281 * Maybe because of an Evaluate Context change for a hub update or a
2282 * control endpoint 0 max packet size change?
2283 * FIXME: skip the bandwidth calculation in that case.
2284 */
2285 return 0;
2286}
2287
2288static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2289 struct xhci_virt_device *virt_dev)
2290{
2291 unsigned int bw_reserved;
2292
2293 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2294 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2295 return -ENOMEM;
2296
2297 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2298 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2299 return -ENOMEM;
2300
2301 return 0;
2302}
2303
2304/*
2305 * This algorithm is a very conservative estimate of the worst-case scheduling
2306 * scenario for any one interval. The hardware dynamically schedules the
2307 * packets, so we can't tell which microframe could be the limiting factor in
2308 * the bandwidth scheduling. This only takes into account periodic endpoints.
2309 *
2310 * Obviously, we can't solve an NP complete problem to find the minimum worst
2311 * case scenario. Instead, we come up with an estimate that is no less than
2312 * the worst case bandwidth used for any one microframe, but may be an
2313 * over-estimate.
2314 *
2315 * We walk the requirements for each endpoint by interval, starting with the
2316 * smallest interval, and place packets in the schedule where there is only one
2317 * possible way to schedule packets for that interval. In order to simplify
2318 * this algorithm, we record the largest max packet size for each interval, and
2319 * assume all packets will be that size.
2320 *
2321 * For interval 0, we obviously must schedule all packets for each interval.
2322 * The bandwidth for interval 0 is just the amount of data to be transmitted
2323 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2324 * the number of packets).
2325 *
2326 * For interval 1, we have two possible microframes to schedule those packets
2327 * in. For this algorithm, if we can schedule the same number of packets for
2328 * each possible scheduling opportunity (each microframe), we will do so. The
2329 * remaining number of packets will be saved to be transmitted in the gaps in
2330 * the next interval's scheduling sequence.
2331 *
2332 * As we move those remaining packets to be scheduled with interval 2 packets,
2333 * we have to double the number of remaining packets to transmit. This is
2334 * because the intervals are actually powers of 2, and we would be transmitting
2335 * the previous interval's packets twice in this interval. We also have to be
2336 * sure that when we look at the largest max packet size for this interval, we
2337 * also look at the largest max packet size for the remaining packets and take
2338 * the greater of the two.
2339 *
2340 * The algorithm continues to evenly distribute packets in each scheduling
2341 * opportunity, and push the remaining packets out, until we get to the last
2342 * interval. Then those packets and their associated overhead are just added
2343 * to the bandwidth used.
2344 */
2345static int xhci_check_bw_table(struct xhci_hcd *xhci,
2346 struct xhci_virt_device *virt_dev,
2347 int old_active_eps)
2348{
2349 unsigned int bw_reserved;
2350 unsigned int max_bandwidth;
2351 unsigned int bw_used;
2352 unsigned int block_size;
2353 struct xhci_interval_bw_table *bw_table;
2354 unsigned int packet_size = 0;
2355 unsigned int overhead = 0;
2356 unsigned int packets_transmitted = 0;
2357 unsigned int packets_remaining = 0;
2358 unsigned int i;
2359
2360 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2361 return xhci_check_ss_bw(xhci, virt_dev);
2362
2363 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2364 max_bandwidth = HS_BW_LIMIT;
2365 /* Convert percent of bus BW reserved to blocks reserved */
2366 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2367 } else {
2368 max_bandwidth = FS_BW_LIMIT;
2369 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2370 }
2371
2372 bw_table = virt_dev->bw_table;
2373 /* We need to translate the max packet size and max ESIT payloads into
2374 * the units the hardware uses.
2375 */
2376 block_size = xhci_get_block_size(virt_dev->udev);
2377
2378 /* If we are manipulating a LS/FS device under a HS hub, double check
2379 * that the HS bus has enough bandwidth if we are activing a new TT.
2380 */
2381 if (virt_dev->tt_info) {
2382 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2383 "Recalculating BW for rootport %u",
2384 virt_dev->rhub_port->hw_portnum + 1);
2385 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2386 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2387 "newly activated TT.\n");
2388 return -ENOMEM;
2389 }
2390 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2391 "Recalculating BW for TT slot %u port %u",
2392 virt_dev->tt_info->slot_id,
2393 virt_dev->tt_info->ttport);
2394 } else {
2395 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2396 "Recalculating BW for rootport %u",
2397 virt_dev->rhub_port->hw_portnum + 1);
2398 }
2399
2400 /* Add in how much bandwidth will be used for interval zero, or the
2401 * rounded max ESIT payload + number of packets * largest overhead.
2402 */
2403 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2404 bw_table->interval_bw[0].num_packets *
2405 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2406
2407 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2408 unsigned int bw_added;
2409 unsigned int largest_mps;
2410 unsigned int interval_overhead;
2411
2412 /*
2413 * How many packets could we transmit in this interval?
2414 * If packets didn't fit in the previous interval, we will need
2415 * to transmit that many packets twice within this interval.
2416 */
2417 packets_remaining = 2 * packets_remaining +
2418 bw_table->interval_bw[i].num_packets;
2419
2420 /* Find the largest max packet size of this or the previous
2421 * interval.
2422 */
2423 if (list_empty(&bw_table->interval_bw[i].endpoints))
2424 largest_mps = 0;
2425 else {
2426 struct xhci_virt_ep *virt_ep;
2427 struct list_head *ep_entry;
2428
2429 ep_entry = bw_table->interval_bw[i].endpoints.next;
2430 virt_ep = list_entry(ep_entry,
2431 struct xhci_virt_ep, bw_endpoint_list);
2432 /* Convert to blocks, rounding up */
2433 largest_mps = DIV_ROUND_UP(
2434 virt_ep->bw_info.max_packet_size,
2435 block_size);
2436 }
2437 if (largest_mps > packet_size)
2438 packet_size = largest_mps;
2439
2440 /* Use the larger overhead of this or the previous interval. */
2441 interval_overhead = xhci_get_largest_overhead(
2442 &bw_table->interval_bw[i]);
2443 if (interval_overhead > overhead)
2444 overhead = interval_overhead;
2445
2446 /* How many packets can we evenly distribute across
2447 * (1 << (i + 1)) possible scheduling opportunities?
2448 */
2449 packets_transmitted = packets_remaining >> (i + 1);
2450
2451 /* Add in the bandwidth used for those scheduled packets */
2452 bw_added = packets_transmitted * (overhead + packet_size);
2453
2454 /* How many packets do we have remaining to transmit? */
2455 packets_remaining = packets_remaining % (1 << (i + 1));
2456
2457 /* What largest max packet size should those packets have? */
2458 /* If we've transmitted all packets, don't carry over the
2459 * largest packet size.
2460 */
2461 if (packets_remaining == 0) {
2462 packet_size = 0;
2463 overhead = 0;
2464 } else if (packets_transmitted > 0) {
2465 /* Otherwise if we do have remaining packets, and we've
2466 * scheduled some packets in this interval, take the
2467 * largest max packet size from endpoints with this
2468 * interval.
2469 */
2470 packet_size = largest_mps;
2471 overhead = interval_overhead;
2472 }
2473 /* Otherwise carry over packet_size and overhead from the last
2474 * time we had a remainder.
2475 */
2476 bw_used += bw_added;
2477 if (bw_used > max_bandwidth) {
2478 xhci_warn(xhci, "Not enough bandwidth. "
2479 "Proposed: %u, Max: %u\n",
2480 bw_used, max_bandwidth);
2481 return -ENOMEM;
2482 }
2483 }
2484 /*
2485 * Ok, we know we have some packets left over after even-handedly
2486 * scheduling interval 15. We don't know which microframes they will
2487 * fit into, so we over-schedule and say they will be scheduled every
2488 * microframe.
2489 */
2490 if (packets_remaining > 0)
2491 bw_used += overhead + packet_size;
2492
2493 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2494 /* OK, we're manipulating a HS device attached to a
2495 * root port bandwidth domain. Include the number of active TTs
2496 * in the bandwidth used.
2497 */
2498 bw_used += TT_HS_OVERHEAD *
2499 xhci->rh_bw[virt_dev->rhub_port->hw_portnum].num_active_tts;
2500 }
2501
2502 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2503 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2504 "Available: %u " "percent",
2505 bw_used, max_bandwidth, bw_reserved,
2506 (max_bandwidth - bw_used - bw_reserved) * 100 /
2507 max_bandwidth);
2508
2509 bw_used += bw_reserved;
2510 if (bw_used > max_bandwidth) {
2511 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2512 bw_used, max_bandwidth);
2513 return -ENOMEM;
2514 }
2515
2516 bw_table->bw_used = bw_used;
2517 return 0;
2518}
2519
2520static bool xhci_is_async_ep(unsigned int ep_type)
2521{
2522 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2523 ep_type != ISOC_IN_EP &&
2524 ep_type != INT_IN_EP);
2525}
2526
2527static bool xhci_is_sync_in_ep(unsigned int ep_type)
2528{
2529 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2530}
2531
2532static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2533{
2534 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2535
2536 if (ep_bw->ep_interval == 0)
2537 return SS_OVERHEAD_BURST +
2538 (ep_bw->mult * ep_bw->num_packets *
2539 (SS_OVERHEAD + mps));
2540 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2541 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2542 1 << ep_bw->ep_interval);
2543
2544}
2545
2546static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2547 struct xhci_bw_info *ep_bw,
2548 struct xhci_interval_bw_table *bw_table,
2549 struct usb_device *udev,
2550 struct xhci_virt_ep *virt_ep,
2551 struct xhci_tt_bw_info *tt_info)
2552{
2553 struct xhci_interval_bw *interval_bw;
2554 int normalized_interval;
2555
2556 if (xhci_is_async_ep(ep_bw->type))
2557 return;
2558
2559 if (udev->speed >= USB_SPEED_SUPER) {
2560 if (xhci_is_sync_in_ep(ep_bw->type))
2561 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2562 xhci_get_ss_bw_consumed(ep_bw);
2563 else
2564 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2565 xhci_get_ss_bw_consumed(ep_bw);
2566 return;
2567 }
2568
2569 /* SuperSpeed endpoints never get added to intervals in the table, so
2570 * this check is only valid for HS/FS/LS devices.
2571 */
2572 if (list_empty(&virt_ep->bw_endpoint_list))
2573 return;
2574 /* For LS/FS devices, we need to translate the interval expressed in
2575 * microframes to frames.
2576 */
2577 if (udev->speed == USB_SPEED_HIGH)
2578 normalized_interval = ep_bw->ep_interval;
2579 else
2580 normalized_interval = ep_bw->ep_interval - 3;
2581
2582 if (normalized_interval == 0)
2583 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2584 interval_bw = &bw_table->interval_bw[normalized_interval];
2585 interval_bw->num_packets -= ep_bw->num_packets;
2586 switch (udev->speed) {
2587 case USB_SPEED_LOW:
2588 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2589 break;
2590 case USB_SPEED_FULL:
2591 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2592 break;
2593 case USB_SPEED_HIGH:
2594 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2595 break;
2596 default:
2597 /* Should never happen because only LS/FS/HS endpoints will get
2598 * added to the endpoint list.
2599 */
2600 return;
2601 }
2602 if (tt_info)
2603 tt_info->active_eps -= 1;
2604 list_del_init(&virt_ep->bw_endpoint_list);
2605}
2606
2607static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2608 struct xhci_bw_info *ep_bw,
2609 struct xhci_interval_bw_table *bw_table,
2610 struct usb_device *udev,
2611 struct xhci_virt_ep *virt_ep,
2612 struct xhci_tt_bw_info *tt_info)
2613{
2614 struct xhci_interval_bw *interval_bw;
2615 struct xhci_virt_ep *smaller_ep;
2616 int normalized_interval;
2617
2618 if (xhci_is_async_ep(ep_bw->type))
2619 return;
2620
2621 if (udev->speed == USB_SPEED_SUPER) {
2622 if (xhci_is_sync_in_ep(ep_bw->type))
2623 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2624 xhci_get_ss_bw_consumed(ep_bw);
2625 else
2626 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2627 xhci_get_ss_bw_consumed(ep_bw);
2628 return;
2629 }
2630
2631 /* For LS/FS devices, we need to translate the interval expressed in
2632 * microframes to frames.
2633 */
2634 if (udev->speed == USB_SPEED_HIGH)
2635 normalized_interval = ep_bw->ep_interval;
2636 else
2637 normalized_interval = ep_bw->ep_interval - 3;
2638
2639 if (normalized_interval == 0)
2640 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2641 interval_bw = &bw_table->interval_bw[normalized_interval];
2642 interval_bw->num_packets += ep_bw->num_packets;
2643 switch (udev->speed) {
2644 case USB_SPEED_LOW:
2645 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2646 break;
2647 case USB_SPEED_FULL:
2648 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2649 break;
2650 case USB_SPEED_HIGH:
2651 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2652 break;
2653 default:
2654 /* Should never happen because only LS/FS/HS endpoints will get
2655 * added to the endpoint list.
2656 */
2657 return;
2658 }
2659
2660 if (tt_info)
2661 tt_info->active_eps += 1;
2662 /* Insert the endpoint into the list, largest max packet size first. */
2663 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2664 bw_endpoint_list) {
2665 if (ep_bw->max_packet_size >=
2666 smaller_ep->bw_info.max_packet_size) {
2667 /* Add the new ep before the smaller endpoint */
2668 list_add_tail(&virt_ep->bw_endpoint_list,
2669 &smaller_ep->bw_endpoint_list);
2670 return;
2671 }
2672 }
2673 /* Add the new endpoint at the end of the list. */
2674 list_add_tail(&virt_ep->bw_endpoint_list,
2675 &interval_bw->endpoints);
2676}
2677
2678void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2679 struct xhci_virt_device *virt_dev,
2680 int old_active_eps)
2681{
2682 struct xhci_root_port_bw_info *rh_bw_info;
2683 if (!virt_dev->tt_info)
2684 return;
2685
2686 rh_bw_info = &xhci->rh_bw[virt_dev->rhub_port->hw_portnum];
2687 if (old_active_eps == 0 &&
2688 virt_dev->tt_info->active_eps != 0) {
2689 rh_bw_info->num_active_tts += 1;
2690 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2691 } else if (old_active_eps != 0 &&
2692 virt_dev->tt_info->active_eps == 0) {
2693 rh_bw_info->num_active_tts -= 1;
2694 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2695 }
2696}
2697
2698static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2699 struct xhci_virt_device *virt_dev,
2700 struct xhci_container_ctx *in_ctx)
2701{
2702 struct xhci_bw_info ep_bw_info[31];
2703 int i;
2704 struct xhci_input_control_ctx *ctrl_ctx;
2705 int old_active_eps = 0;
2706
2707 if (virt_dev->tt_info)
2708 old_active_eps = virt_dev->tt_info->active_eps;
2709
2710 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2711 if (!ctrl_ctx) {
2712 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2713 __func__);
2714 return -ENOMEM;
2715 }
2716
2717 for (i = 0; i < 31; i++) {
2718 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2719 continue;
2720
2721 /* Make a copy of the BW info in case we need to revert this */
2722 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2723 sizeof(ep_bw_info[i]));
2724 /* Drop the endpoint from the interval table if the endpoint is
2725 * being dropped or changed.
2726 */
2727 if (EP_IS_DROPPED(ctrl_ctx, i))
2728 xhci_drop_ep_from_interval_table(xhci,
2729 &virt_dev->eps[i].bw_info,
2730 virt_dev->bw_table,
2731 virt_dev->udev,
2732 &virt_dev->eps[i],
2733 virt_dev->tt_info);
2734 }
2735 /* Overwrite the information stored in the endpoints' bw_info */
2736 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2737 for (i = 0; i < 31; i++) {
2738 /* Add any changed or added endpoints to the interval table */
2739 if (EP_IS_ADDED(ctrl_ctx, i))
2740 xhci_add_ep_to_interval_table(xhci,
2741 &virt_dev->eps[i].bw_info,
2742 virt_dev->bw_table,
2743 virt_dev->udev,
2744 &virt_dev->eps[i],
2745 virt_dev->tt_info);
2746 }
2747
2748 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2749 /* Ok, this fits in the bandwidth we have.
2750 * Update the number of active TTs.
2751 */
2752 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2753 return 0;
2754 }
2755
2756 /* We don't have enough bandwidth for this, revert the stored info. */
2757 for (i = 0; i < 31; i++) {
2758 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2759 continue;
2760
2761 /* Drop the new copies of any added or changed endpoints from
2762 * the interval table.
2763 */
2764 if (EP_IS_ADDED(ctrl_ctx, i)) {
2765 xhci_drop_ep_from_interval_table(xhci,
2766 &virt_dev->eps[i].bw_info,
2767 virt_dev->bw_table,
2768 virt_dev->udev,
2769 &virt_dev->eps[i],
2770 virt_dev->tt_info);
2771 }
2772 /* Revert the endpoint back to its old information */
2773 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2774 sizeof(ep_bw_info[i]));
2775 /* Add any changed or dropped endpoints back into the table */
2776 if (EP_IS_DROPPED(ctrl_ctx, i))
2777 xhci_add_ep_to_interval_table(xhci,
2778 &virt_dev->eps[i].bw_info,
2779 virt_dev->bw_table,
2780 virt_dev->udev,
2781 &virt_dev->eps[i],
2782 virt_dev->tt_info);
2783 }
2784 return -ENOMEM;
2785}
2786
2787
2788/* Issue a configure endpoint command or evaluate context command
2789 * and wait for it to finish.
2790 */
2791static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2792 struct usb_device *udev,
2793 struct xhci_command *command,
2794 bool ctx_change, bool must_succeed)
2795{
2796 int ret;
2797 unsigned long flags;
2798 struct xhci_input_control_ctx *ctrl_ctx;
2799 struct xhci_virt_device *virt_dev;
2800 struct xhci_slot_ctx *slot_ctx;
2801
2802 if (!command)
2803 return -EINVAL;
2804
2805 spin_lock_irqsave(&xhci->lock, flags);
2806
2807 if (xhci->xhc_state & XHCI_STATE_DYING) {
2808 spin_unlock_irqrestore(&xhci->lock, flags);
2809 return -ESHUTDOWN;
2810 }
2811
2812 virt_dev = xhci->devs[udev->slot_id];
2813
2814 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2815 if (!ctrl_ctx) {
2816 spin_unlock_irqrestore(&xhci->lock, flags);
2817 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2818 __func__);
2819 return -ENOMEM;
2820 }
2821
2822 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2823 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2824 spin_unlock_irqrestore(&xhci->lock, flags);
2825 xhci_warn(xhci, "Not enough host resources, "
2826 "active endpoint contexts = %u\n",
2827 xhci->num_active_eps);
2828 return -ENOMEM;
2829 }
2830 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2831 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2832 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2833 xhci_free_host_resources(xhci, ctrl_ctx);
2834 spin_unlock_irqrestore(&xhci->lock, flags);
2835 xhci_warn(xhci, "Not enough bandwidth\n");
2836 return -ENOMEM;
2837 }
2838
2839 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2840
2841 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2842 trace_xhci_configure_endpoint(slot_ctx);
2843
2844 if (!ctx_change)
2845 ret = xhci_queue_configure_endpoint(xhci, command,
2846 command->in_ctx->dma,
2847 udev->slot_id, must_succeed);
2848 else
2849 ret = xhci_queue_evaluate_context(xhci, command,
2850 command->in_ctx->dma,
2851 udev->slot_id, must_succeed);
2852 if (ret < 0) {
2853 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2854 xhci_free_host_resources(xhci, ctrl_ctx);
2855 spin_unlock_irqrestore(&xhci->lock, flags);
2856 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2857 "FIXME allocate a new ring segment");
2858 return -ENOMEM;
2859 }
2860 xhci_ring_cmd_db(xhci);
2861 spin_unlock_irqrestore(&xhci->lock, flags);
2862
2863 /* Wait for the configure endpoint command to complete */
2864 wait_for_completion(command->completion);
2865
2866 if (!ctx_change)
2867 ret = xhci_configure_endpoint_result(xhci, udev,
2868 &command->status);
2869 else
2870 ret = xhci_evaluate_context_result(xhci, udev,
2871 &command->status);
2872
2873 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2874 spin_lock_irqsave(&xhci->lock, flags);
2875 /* If the command failed, remove the reserved resources.
2876 * Otherwise, clean up the estimate to include dropped eps.
2877 */
2878 if (ret)
2879 xhci_free_host_resources(xhci, ctrl_ctx);
2880 else
2881 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2882 spin_unlock_irqrestore(&xhci->lock, flags);
2883 }
2884 return ret;
2885}
2886
2887static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2888 struct xhci_virt_device *vdev, int i)
2889{
2890 struct xhci_virt_ep *ep = &vdev->eps[i];
2891
2892 if (ep->ep_state & EP_HAS_STREAMS) {
2893 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2894 xhci_get_endpoint_address(i));
2895 xhci_free_stream_info(xhci, ep->stream_info);
2896 ep->stream_info = NULL;
2897 ep->ep_state &= ~EP_HAS_STREAMS;
2898 }
2899}
2900
2901/* Called after one or more calls to xhci_add_endpoint() or
2902 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2903 * to call xhci_reset_bandwidth().
2904 *
2905 * Since we are in the middle of changing either configuration or
2906 * installing a new alt setting, the USB core won't allow URBs to be
2907 * enqueued for any endpoint on the old config or interface. Nothing
2908 * else should be touching the xhci->devs[slot_id] structure, so we
2909 * don't need to take the xhci->lock for manipulating that.
2910 */
2911int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2912{
2913 int i;
2914 int ret = 0;
2915 struct xhci_hcd *xhci;
2916 struct xhci_virt_device *virt_dev;
2917 struct xhci_input_control_ctx *ctrl_ctx;
2918 struct xhci_slot_ctx *slot_ctx;
2919 struct xhci_command *command;
2920
2921 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2922 if (ret <= 0)
2923 return ret;
2924 xhci = hcd_to_xhci(hcd);
2925 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2926 (xhci->xhc_state & XHCI_STATE_REMOVING))
2927 return -ENODEV;
2928
2929 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2930 virt_dev = xhci->devs[udev->slot_id];
2931
2932 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2933 if (!command)
2934 return -ENOMEM;
2935
2936 command->in_ctx = virt_dev->in_ctx;
2937
2938 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2939 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2940 if (!ctrl_ctx) {
2941 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2942 __func__);
2943 ret = -ENOMEM;
2944 goto command_cleanup;
2945 }
2946 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2947 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2948 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2949
2950 /* Don't issue the command if there's no endpoints to update. */
2951 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2952 ctrl_ctx->drop_flags == 0) {
2953 ret = 0;
2954 goto command_cleanup;
2955 }
2956 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2957 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2958 for (i = 31; i >= 1; i--) {
2959 __le32 le32 = cpu_to_le32(BIT(i));
2960
2961 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2962 || (ctrl_ctx->add_flags & le32) || i == 1) {
2963 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2964 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2965 break;
2966 }
2967 }
2968
2969 ret = xhci_configure_endpoint(xhci, udev, command,
2970 false, false);
2971 if (ret)
2972 /* Callee should call reset_bandwidth() */
2973 goto command_cleanup;
2974
2975 /* Free any rings that were dropped, but not changed. */
2976 for (i = 1; i < 31; i++) {
2977 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2978 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2979 xhci_free_endpoint_ring(xhci, virt_dev, i);
2980 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2981 }
2982 }
2983 xhci_zero_in_ctx(xhci, virt_dev);
2984 /*
2985 * Install any rings for completely new endpoints or changed endpoints,
2986 * and free any old rings from changed endpoints.
2987 */
2988 for (i = 1; i < 31; i++) {
2989 if (!virt_dev->eps[i].new_ring)
2990 continue;
2991 /* Only free the old ring if it exists.
2992 * It may not if this is the first add of an endpoint.
2993 */
2994 if (virt_dev->eps[i].ring) {
2995 xhci_free_endpoint_ring(xhci, virt_dev, i);
2996 }
2997 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2998 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2999 virt_dev->eps[i].new_ring = NULL;
3000 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3001 }
3002command_cleanup:
3003 kfree(command->completion);
3004 kfree(command);
3005
3006 return ret;
3007}
3008EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3009
3010void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3011{
3012 struct xhci_hcd *xhci;
3013 struct xhci_virt_device *virt_dev;
3014 int i, ret;
3015
3016 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3017 if (ret <= 0)
3018 return;
3019 xhci = hcd_to_xhci(hcd);
3020
3021 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3022 virt_dev = xhci->devs[udev->slot_id];
3023 /* Free any rings allocated for added endpoints */
3024 for (i = 0; i < 31; i++) {
3025 if (virt_dev->eps[i].new_ring) {
3026 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3027 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3028 virt_dev->eps[i].new_ring = NULL;
3029 }
3030 }
3031 xhci_zero_in_ctx(xhci, virt_dev);
3032}
3033EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3034
3035static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3036 struct xhci_container_ctx *in_ctx,
3037 struct xhci_container_ctx *out_ctx,
3038 struct xhci_input_control_ctx *ctrl_ctx,
3039 u32 add_flags, u32 drop_flags)
3040{
3041 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3042 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3043 xhci_slot_copy(xhci, in_ctx, out_ctx);
3044 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3045}
3046
3047static void xhci_endpoint_disable(struct usb_hcd *hcd,
3048 struct usb_host_endpoint *host_ep)
3049{
3050 struct xhci_hcd *xhci;
3051 struct xhci_virt_device *vdev;
3052 struct xhci_virt_ep *ep;
3053 struct usb_device *udev;
3054 unsigned long flags;
3055 unsigned int ep_index;
3056
3057 xhci = hcd_to_xhci(hcd);
3058rescan:
3059 spin_lock_irqsave(&xhci->lock, flags);
3060
3061 udev = (struct usb_device *)host_ep->hcpriv;
3062 if (!udev || !udev->slot_id)
3063 goto done;
3064
3065 vdev = xhci->devs[udev->slot_id];
3066 if (!vdev)
3067 goto done;
3068
3069 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3070 ep = &vdev->eps[ep_index];
3071
3072 /* wait for hub_tt_work to finish clearing hub TT */
3073 if (ep->ep_state & EP_CLEARING_TT) {
3074 spin_unlock_irqrestore(&xhci->lock, flags);
3075 schedule_timeout_uninterruptible(1);
3076 goto rescan;
3077 }
3078
3079 if (ep->ep_state)
3080 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3081 ep->ep_state);
3082done:
3083 host_ep->hcpriv = NULL;
3084 spin_unlock_irqrestore(&xhci->lock, flags);
3085}
3086
3087/*
3088 * Called after usb core issues a clear halt control message.
3089 * The host side of the halt should already be cleared by a reset endpoint
3090 * command issued when the STALL event was received.
3091 *
3092 * The reset endpoint command may only be issued to endpoints in the halted
3093 * state. For software that wishes to reset the data toggle or sequence number
3094 * of an endpoint that isn't in the halted state this function will issue a
3095 * configure endpoint command with the Drop and Add bits set for the target
3096 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3097 *
3098 * vdev may be lost due to xHC restore error and re-initialization during S3/S4
3099 * resume. A new vdev will be allocated later by xhci_discover_or_reset_device()
3100 */
3101
3102static void xhci_endpoint_reset(struct usb_hcd *hcd,
3103 struct usb_host_endpoint *host_ep)
3104{
3105 struct xhci_hcd *xhci;
3106 struct usb_device *udev;
3107 struct xhci_virt_device *vdev;
3108 struct xhci_virt_ep *ep;
3109 struct xhci_input_control_ctx *ctrl_ctx;
3110 struct xhci_command *stop_cmd, *cfg_cmd;
3111 unsigned int ep_index;
3112 unsigned long flags;
3113 u32 ep_flag;
3114 int err;
3115
3116 xhci = hcd_to_xhci(hcd);
3117 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3118
3119 /*
3120 * Usb core assumes a max packet value for ep0 on FS devices until the
3121 * real value is read from the descriptor. Core resets Ep0 if values
3122 * mismatch. Reconfigure the xhci ep0 endpoint context here in that case
3123 */
3124 if (usb_endpoint_xfer_control(&host_ep->desc) && ep_index == 0) {
3125
3126 udev = container_of(host_ep, struct usb_device, ep0);
3127 if (udev->speed != USB_SPEED_FULL || !udev->slot_id)
3128 return;
3129
3130 vdev = xhci->devs[udev->slot_id];
3131 if (!vdev || vdev->udev != udev)
3132 return;
3133
3134 xhci_check_ep0_maxpacket(xhci, vdev);
3135
3136 /* Nothing else should be done here for ep0 during ep reset */
3137 return;
3138 }
3139
3140 if (!host_ep->hcpriv)
3141 return;
3142 udev = (struct usb_device *) host_ep->hcpriv;
3143 vdev = xhci->devs[udev->slot_id];
3144
3145 if (!udev->slot_id || !vdev)
3146 return;
3147
3148 ep = &vdev->eps[ep_index];
3149
3150 /* Bail out if toggle is already being cleared by a endpoint reset */
3151 spin_lock_irqsave(&xhci->lock, flags);
3152 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3153 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3154 spin_unlock_irqrestore(&xhci->lock, flags);
3155 return;
3156 }
3157 spin_unlock_irqrestore(&xhci->lock, flags);
3158 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3159 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3160 usb_endpoint_xfer_isoc(&host_ep->desc))
3161 return;
3162
3163 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3164
3165 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3166 return;
3167
3168 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3169 if (!stop_cmd)
3170 return;
3171
3172 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3173 if (!cfg_cmd)
3174 goto cleanup;
3175
3176 spin_lock_irqsave(&xhci->lock, flags);
3177
3178 /* block queuing new trbs and ringing ep doorbell */
3179 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3180
3181 /*
3182 * Make sure endpoint ring is empty before resetting the toggle/seq.
3183 * Driver is required to synchronously cancel all transfer request.
3184 * Stop the endpoint to force xHC to update the output context
3185 */
3186
3187 if (!list_empty(&ep->ring->td_list)) {
3188 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3189 spin_unlock_irqrestore(&xhci->lock, flags);
3190 xhci_free_command(xhci, cfg_cmd);
3191 goto cleanup;
3192 }
3193
3194 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3195 ep_index, 0);
3196 if (err < 0) {
3197 spin_unlock_irqrestore(&xhci->lock, flags);
3198 xhci_free_command(xhci, cfg_cmd);
3199 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3200 __func__, err);
3201 goto cleanup;
3202 }
3203
3204 xhci_ring_cmd_db(xhci);
3205 spin_unlock_irqrestore(&xhci->lock, flags);
3206
3207 wait_for_completion(stop_cmd->completion);
3208
3209 spin_lock_irqsave(&xhci->lock, flags);
3210
3211 /* config ep command clears toggle if add and drop ep flags are set */
3212 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3213 if (!ctrl_ctx) {
3214 spin_unlock_irqrestore(&xhci->lock, flags);
3215 xhci_free_command(xhci, cfg_cmd);
3216 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3217 __func__);
3218 goto cleanup;
3219 }
3220
3221 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3222 ctrl_ctx, ep_flag, ep_flag);
3223 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3224
3225 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3226 udev->slot_id, false);
3227 if (err < 0) {
3228 spin_unlock_irqrestore(&xhci->lock, flags);
3229 xhci_free_command(xhci, cfg_cmd);
3230 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3231 __func__, err);
3232 goto cleanup;
3233 }
3234
3235 xhci_ring_cmd_db(xhci);
3236 spin_unlock_irqrestore(&xhci->lock, flags);
3237
3238 wait_for_completion(cfg_cmd->completion);
3239
3240 xhci_free_command(xhci, cfg_cmd);
3241cleanup:
3242 xhci_free_command(xhci, stop_cmd);
3243 spin_lock_irqsave(&xhci->lock, flags);
3244 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3245 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3246 spin_unlock_irqrestore(&xhci->lock, flags);
3247}
3248
3249static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3250 struct usb_device *udev, struct usb_host_endpoint *ep,
3251 unsigned int slot_id)
3252{
3253 int ret;
3254 unsigned int ep_index;
3255 unsigned int ep_state;
3256
3257 if (!ep)
3258 return -EINVAL;
3259 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3260 if (ret <= 0)
3261 return ret ? ret : -EINVAL;
3262 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3263 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3264 " descriptor for ep 0x%x does not support streams\n",
3265 ep->desc.bEndpointAddress);
3266 return -EINVAL;
3267 }
3268
3269 ep_index = xhci_get_endpoint_index(&ep->desc);
3270 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3271 if (ep_state & EP_HAS_STREAMS ||
3272 ep_state & EP_GETTING_STREAMS) {
3273 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3274 "already has streams set up.\n",
3275 ep->desc.bEndpointAddress);
3276 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3277 "dynamic stream context array reallocation.\n");
3278 return -EINVAL;
3279 }
3280 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3281 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3282 "endpoint 0x%x; URBs are pending.\n",
3283 ep->desc.bEndpointAddress);
3284 return -EINVAL;
3285 }
3286 return 0;
3287}
3288
3289static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3290 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3291{
3292 unsigned int max_streams;
3293
3294 /* The stream context array size must be a power of two */
3295 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3296 /*
3297 * Find out how many primary stream array entries the host controller
3298 * supports. Later we may use secondary stream arrays (similar to 2nd
3299 * level page entries), but that's an optional feature for xHCI host
3300 * controllers. xHCs must support at least 4 stream IDs.
3301 */
3302 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3303 if (*num_stream_ctxs > max_streams) {
3304 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3305 max_streams);
3306 *num_stream_ctxs = max_streams;
3307 *num_streams = max_streams;
3308 }
3309}
3310
3311/* Returns an error code if one of the endpoint already has streams.
3312 * This does not change any data structures, it only checks and gathers
3313 * information.
3314 */
3315static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3316 struct usb_device *udev,
3317 struct usb_host_endpoint **eps, unsigned int num_eps,
3318 unsigned int *num_streams, u32 *changed_ep_bitmask)
3319{
3320 unsigned int max_streams;
3321 unsigned int endpoint_flag;
3322 int i;
3323 int ret;
3324
3325 for (i = 0; i < num_eps; i++) {
3326 ret = xhci_check_streams_endpoint(xhci, udev,
3327 eps[i], udev->slot_id);
3328 if (ret < 0)
3329 return ret;
3330
3331 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3332 if (max_streams < (*num_streams - 1)) {
3333 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3334 eps[i]->desc.bEndpointAddress,
3335 max_streams);
3336 *num_streams = max_streams+1;
3337 }
3338
3339 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3340 if (*changed_ep_bitmask & endpoint_flag)
3341 return -EINVAL;
3342 *changed_ep_bitmask |= endpoint_flag;
3343 }
3344 return 0;
3345}
3346
3347static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3348 struct usb_device *udev,
3349 struct usb_host_endpoint **eps, unsigned int num_eps)
3350{
3351 u32 changed_ep_bitmask = 0;
3352 unsigned int slot_id;
3353 unsigned int ep_index;
3354 unsigned int ep_state;
3355 int i;
3356
3357 slot_id = udev->slot_id;
3358 if (!xhci->devs[slot_id])
3359 return 0;
3360
3361 for (i = 0; i < num_eps; i++) {
3362 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3363 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3364 /* Are streams already being freed for the endpoint? */
3365 if (ep_state & EP_GETTING_NO_STREAMS) {
3366 xhci_warn(xhci, "WARN Can't disable streams for "
3367 "endpoint 0x%x, "
3368 "streams are being disabled already\n",
3369 eps[i]->desc.bEndpointAddress);
3370 return 0;
3371 }
3372 /* Are there actually any streams to free? */
3373 if (!(ep_state & EP_HAS_STREAMS) &&
3374 !(ep_state & EP_GETTING_STREAMS)) {
3375 xhci_warn(xhci, "WARN Can't disable streams for "
3376 "endpoint 0x%x, "
3377 "streams are already disabled!\n",
3378 eps[i]->desc.bEndpointAddress);
3379 xhci_warn(xhci, "WARN xhci_free_streams() called "
3380 "with non-streams endpoint\n");
3381 return 0;
3382 }
3383 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3384 }
3385 return changed_ep_bitmask;
3386}
3387
3388/*
3389 * The USB device drivers use this function (through the HCD interface in USB
3390 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3391 * coordinate mass storage command queueing across multiple endpoints (basically
3392 * a stream ID == a task ID).
3393 *
3394 * Setting up streams involves allocating the same size stream context array
3395 * for each endpoint and issuing a configure endpoint command for all endpoints.
3396 *
3397 * Don't allow the call to succeed if one endpoint only supports one stream
3398 * (which means it doesn't support streams at all).
3399 *
3400 * Drivers may get less stream IDs than they asked for, if the host controller
3401 * hardware or endpoints claim they can't support the number of requested
3402 * stream IDs.
3403 */
3404static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3405 struct usb_host_endpoint **eps, unsigned int num_eps,
3406 unsigned int num_streams, gfp_t mem_flags)
3407{
3408 int i, ret;
3409 struct xhci_hcd *xhci;
3410 struct xhci_virt_device *vdev;
3411 struct xhci_command *config_cmd;
3412 struct xhci_input_control_ctx *ctrl_ctx;
3413 unsigned int ep_index;
3414 unsigned int num_stream_ctxs;
3415 unsigned int max_packet;
3416 unsigned long flags;
3417 u32 changed_ep_bitmask = 0;
3418
3419 if (!eps)
3420 return -EINVAL;
3421
3422 /* Add one to the number of streams requested to account for
3423 * stream 0 that is reserved for xHCI usage.
3424 */
3425 num_streams += 1;
3426 xhci = hcd_to_xhci(hcd);
3427 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3428 num_streams);
3429
3430 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3431 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3432 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3433 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3434 return -ENOSYS;
3435 }
3436
3437 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3438 if (!config_cmd)
3439 return -ENOMEM;
3440
3441 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3442 if (!ctrl_ctx) {
3443 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3444 __func__);
3445 xhci_free_command(xhci, config_cmd);
3446 return -ENOMEM;
3447 }
3448
3449 /* Check to make sure all endpoints are not already configured for
3450 * streams. While we're at it, find the maximum number of streams that
3451 * all the endpoints will support and check for duplicate endpoints.
3452 */
3453 spin_lock_irqsave(&xhci->lock, flags);
3454 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3455 num_eps, &num_streams, &changed_ep_bitmask);
3456 if (ret < 0) {
3457 xhci_free_command(xhci, config_cmd);
3458 spin_unlock_irqrestore(&xhci->lock, flags);
3459 return ret;
3460 }
3461 if (num_streams <= 1) {
3462 xhci_warn(xhci, "WARN: endpoints can't handle "
3463 "more than one stream.\n");
3464 xhci_free_command(xhci, config_cmd);
3465 spin_unlock_irqrestore(&xhci->lock, flags);
3466 return -EINVAL;
3467 }
3468 vdev = xhci->devs[udev->slot_id];
3469 /* Mark each endpoint as being in transition, so
3470 * xhci_urb_enqueue() will reject all URBs.
3471 */
3472 for (i = 0; i < num_eps; i++) {
3473 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3474 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3475 }
3476 spin_unlock_irqrestore(&xhci->lock, flags);
3477
3478 /* Setup internal data structures and allocate HW data structures for
3479 * streams (but don't install the HW structures in the input context
3480 * until we're sure all memory allocation succeeded).
3481 */
3482 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3483 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3484 num_stream_ctxs, num_streams);
3485
3486 for (i = 0; i < num_eps; i++) {
3487 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3488 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3489 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3490 num_stream_ctxs,
3491 num_streams,
3492 max_packet, mem_flags);
3493 if (!vdev->eps[ep_index].stream_info)
3494 goto cleanup;
3495 /* Set maxPstreams in endpoint context and update deq ptr to
3496 * point to stream context array. FIXME
3497 */
3498 }
3499
3500 /* Set up the input context for a configure endpoint command. */
3501 for (i = 0; i < num_eps; i++) {
3502 struct xhci_ep_ctx *ep_ctx;
3503
3504 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3505 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3506
3507 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3508 vdev->out_ctx, ep_index);
3509 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3510 vdev->eps[ep_index].stream_info);
3511 }
3512 /* Tell the HW to drop its old copy of the endpoint context info
3513 * and add the updated copy from the input context.
3514 */
3515 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3516 vdev->out_ctx, ctrl_ctx,
3517 changed_ep_bitmask, changed_ep_bitmask);
3518
3519 /* Issue and wait for the configure endpoint command */
3520 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3521 false, false);
3522
3523 /* xHC rejected the configure endpoint command for some reason, so we
3524 * leave the old ring intact and free our internal streams data
3525 * structure.
3526 */
3527 if (ret < 0)
3528 goto cleanup;
3529
3530 spin_lock_irqsave(&xhci->lock, flags);
3531 for (i = 0; i < num_eps; i++) {
3532 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3533 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3534 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3535 udev->slot_id, ep_index);
3536 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3537 }
3538 xhci_free_command(xhci, config_cmd);
3539 spin_unlock_irqrestore(&xhci->lock, flags);
3540
3541 for (i = 0; i < num_eps; i++) {
3542 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3543 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3544 }
3545 /* Subtract 1 for stream 0, which drivers can't use */
3546 return num_streams - 1;
3547
3548cleanup:
3549 /* If it didn't work, free the streams! */
3550 for (i = 0; i < num_eps; i++) {
3551 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3552 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3553 vdev->eps[ep_index].stream_info = NULL;
3554 /* FIXME Unset maxPstreams in endpoint context and
3555 * update deq ptr to point to normal string ring.
3556 */
3557 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3558 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3559 xhci_endpoint_zero(xhci, vdev, eps[i]);
3560 }
3561 xhci_free_command(xhci, config_cmd);
3562 return -ENOMEM;
3563}
3564
3565/* Transition the endpoint from using streams to being a "normal" endpoint
3566 * without streams.
3567 *
3568 * Modify the endpoint context state, submit a configure endpoint command,
3569 * and free all endpoint rings for streams if that completes successfully.
3570 */
3571static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3572 struct usb_host_endpoint **eps, unsigned int num_eps,
3573 gfp_t mem_flags)
3574{
3575 int i, ret;
3576 struct xhci_hcd *xhci;
3577 struct xhci_virt_device *vdev;
3578 struct xhci_command *command;
3579 struct xhci_input_control_ctx *ctrl_ctx;
3580 unsigned int ep_index;
3581 unsigned long flags;
3582 u32 changed_ep_bitmask;
3583
3584 xhci = hcd_to_xhci(hcd);
3585 vdev = xhci->devs[udev->slot_id];
3586
3587 /* Set up a configure endpoint command to remove the streams rings */
3588 spin_lock_irqsave(&xhci->lock, flags);
3589 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3590 udev, eps, num_eps);
3591 if (changed_ep_bitmask == 0) {
3592 spin_unlock_irqrestore(&xhci->lock, flags);
3593 return -EINVAL;
3594 }
3595
3596 /* Use the xhci_command structure from the first endpoint. We may have
3597 * allocated too many, but the driver may call xhci_free_streams() for
3598 * each endpoint it grouped into one call to xhci_alloc_streams().
3599 */
3600 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3601 command = vdev->eps[ep_index].stream_info->free_streams_command;
3602 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3603 if (!ctrl_ctx) {
3604 spin_unlock_irqrestore(&xhci->lock, flags);
3605 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3606 __func__);
3607 return -EINVAL;
3608 }
3609
3610 for (i = 0; i < num_eps; i++) {
3611 struct xhci_ep_ctx *ep_ctx;
3612
3613 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3614 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3615 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3616 EP_GETTING_NO_STREAMS;
3617
3618 xhci_endpoint_copy(xhci, command->in_ctx,
3619 vdev->out_ctx, ep_index);
3620 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3621 &vdev->eps[ep_index]);
3622 }
3623 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3624 vdev->out_ctx, ctrl_ctx,
3625 changed_ep_bitmask, changed_ep_bitmask);
3626 spin_unlock_irqrestore(&xhci->lock, flags);
3627
3628 /* Issue and wait for the configure endpoint command,
3629 * which must succeed.
3630 */
3631 ret = xhci_configure_endpoint(xhci, udev, command,
3632 false, true);
3633
3634 /* xHC rejected the configure endpoint command for some reason, so we
3635 * leave the streams rings intact.
3636 */
3637 if (ret < 0)
3638 return ret;
3639
3640 spin_lock_irqsave(&xhci->lock, flags);
3641 for (i = 0; i < num_eps; i++) {
3642 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3643 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3644 vdev->eps[ep_index].stream_info = NULL;
3645 /* FIXME Unset maxPstreams in endpoint context and
3646 * update deq ptr to point to normal string ring.
3647 */
3648 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3649 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3650 }
3651 spin_unlock_irqrestore(&xhci->lock, flags);
3652
3653 return 0;
3654}
3655
3656/*
3657 * Deletes endpoint resources for endpoints that were active before a Reset
3658 * Device command, or a Disable Slot command. The Reset Device command leaves
3659 * the control endpoint intact, whereas the Disable Slot command deletes it.
3660 *
3661 * Must be called with xhci->lock held.
3662 */
3663void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3664 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3665{
3666 int i;
3667 unsigned int num_dropped_eps = 0;
3668 unsigned int drop_flags = 0;
3669
3670 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3671 if (virt_dev->eps[i].ring) {
3672 drop_flags |= 1 << i;
3673 num_dropped_eps++;
3674 }
3675 }
3676 xhci->num_active_eps -= num_dropped_eps;
3677 if (num_dropped_eps)
3678 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3679 "Dropped %u ep ctxs, flags = 0x%x, "
3680 "%u now active.",
3681 num_dropped_eps, drop_flags,
3682 xhci->num_active_eps);
3683}
3684
3685/*
3686 * This submits a Reset Device Command, which will set the device state to 0,
3687 * set the device address to 0, and disable all the endpoints except the default
3688 * control endpoint. The USB core should come back and call
3689 * xhci_address_device(), and then re-set up the configuration. If this is
3690 * called because of a usb_reset_and_verify_device(), then the old alternate
3691 * settings will be re-installed through the normal bandwidth allocation
3692 * functions.
3693 *
3694 * Wait for the Reset Device command to finish. Remove all structures
3695 * associated with the endpoints that were disabled. Clear the input device
3696 * structure? Reset the control endpoint 0 max packet size?
3697 *
3698 * If the virt_dev to be reset does not exist or does not match the udev,
3699 * it means the device is lost, possibly due to the xHC restore error and
3700 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3701 * re-allocate the device.
3702 */
3703static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3704 struct usb_device *udev)
3705{
3706 int ret, i;
3707 unsigned long flags;
3708 struct xhci_hcd *xhci;
3709 unsigned int slot_id;
3710 struct xhci_virt_device *virt_dev;
3711 struct xhci_command *reset_device_cmd;
3712 struct xhci_slot_ctx *slot_ctx;
3713 int old_active_eps = 0;
3714
3715 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3716 if (ret <= 0)
3717 return ret;
3718 xhci = hcd_to_xhci(hcd);
3719 slot_id = udev->slot_id;
3720 virt_dev = xhci->devs[slot_id];
3721 if (!virt_dev) {
3722 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3723 "not exist. Re-allocate the device\n", slot_id);
3724 ret = xhci_alloc_dev(hcd, udev);
3725 if (ret == 1)
3726 return 0;
3727 else
3728 return -EINVAL;
3729 }
3730
3731 if (virt_dev->tt_info)
3732 old_active_eps = virt_dev->tt_info->active_eps;
3733
3734 if (virt_dev->udev != udev) {
3735 /* If the virt_dev and the udev does not match, this virt_dev
3736 * may belong to another udev.
3737 * Re-allocate the device.
3738 */
3739 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3740 "not match the udev. Re-allocate the device\n",
3741 slot_id);
3742 ret = xhci_alloc_dev(hcd, udev);
3743 if (ret == 1)
3744 return 0;
3745 else
3746 return -EINVAL;
3747 }
3748
3749 /* If device is not setup, there is no point in resetting it */
3750 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3751 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3752 SLOT_STATE_DISABLED)
3753 return 0;
3754
3755 trace_xhci_discover_or_reset_device(slot_ctx);
3756
3757 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3758 /* Allocate the command structure that holds the struct completion.
3759 * Assume we're in process context, since the normal device reset
3760 * process has to wait for the device anyway. Storage devices are
3761 * reset as part of error handling, so use GFP_NOIO instead of
3762 * GFP_KERNEL.
3763 */
3764 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3765 if (!reset_device_cmd) {
3766 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3767 return -ENOMEM;
3768 }
3769
3770 /* Attempt to submit the Reset Device command to the command ring */
3771 spin_lock_irqsave(&xhci->lock, flags);
3772
3773 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3774 if (ret) {
3775 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3776 spin_unlock_irqrestore(&xhci->lock, flags);
3777 goto command_cleanup;
3778 }
3779 xhci_ring_cmd_db(xhci);
3780 spin_unlock_irqrestore(&xhci->lock, flags);
3781
3782 /* Wait for the Reset Device command to finish */
3783 wait_for_completion(reset_device_cmd->completion);
3784
3785 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3786 * unless we tried to reset a slot ID that wasn't enabled,
3787 * or the device wasn't in the addressed or configured state.
3788 */
3789 ret = reset_device_cmd->status;
3790 switch (ret) {
3791 case COMP_COMMAND_ABORTED:
3792 case COMP_COMMAND_RING_STOPPED:
3793 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3794 ret = -ETIME;
3795 goto command_cleanup;
3796 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3797 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3798 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3799 slot_id,
3800 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3801 xhci_dbg(xhci, "Not freeing device rings.\n");
3802 /* Don't treat this as an error. May change my mind later. */
3803 ret = 0;
3804 goto command_cleanup;
3805 case COMP_SUCCESS:
3806 xhci_dbg(xhci, "Successful reset device command.\n");
3807 break;
3808 default:
3809 if (xhci_is_vendor_info_code(xhci, ret))
3810 break;
3811 xhci_warn(xhci, "Unknown completion code %u for "
3812 "reset device command.\n", ret);
3813 ret = -EINVAL;
3814 goto command_cleanup;
3815 }
3816
3817 /* Free up host controller endpoint resources */
3818 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3819 spin_lock_irqsave(&xhci->lock, flags);
3820 /* Don't delete the default control endpoint resources */
3821 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3822 spin_unlock_irqrestore(&xhci->lock, flags);
3823 }
3824
3825 /* Everything but endpoint 0 is disabled, so free the rings. */
3826 for (i = 1; i < 31; i++) {
3827 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3828
3829 if (ep->ep_state & EP_HAS_STREAMS) {
3830 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3831 xhci_get_endpoint_address(i));
3832 xhci_free_stream_info(xhci, ep->stream_info);
3833 ep->stream_info = NULL;
3834 ep->ep_state &= ~EP_HAS_STREAMS;
3835 }
3836
3837 if (ep->ring) {
3838 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3839 xhci_free_endpoint_ring(xhci, virt_dev, i);
3840 }
3841 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3842 xhci_drop_ep_from_interval_table(xhci,
3843 &virt_dev->eps[i].bw_info,
3844 virt_dev->bw_table,
3845 udev,
3846 &virt_dev->eps[i],
3847 virt_dev->tt_info);
3848 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3849 }
3850 /* If necessary, update the number of active TTs on this root port */
3851 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3852 virt_dev->flags = 0;
3853 ret = 0;
3854
3855command_cleanup:
3856 xhci_free_command(xhci, reset_device_cmd);
3857 return ret;
3858}
3859
3860/*
3861 * At this point, the struct usb_device is about to go away, the device has
3862 * disconnected, and all traffic has been stopped and the endpoints have been
3863 * disabled. Free any HC data structures associated with that device.
3864 */
3865static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3866{
3867 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3868 struct xhci_virt_device *virt_dev;
3869 struct xhci_slot_ctx *slot_ctx;
3870 unsigned long flags;
3871 int i, ret;
3872
3873 /*
3874 * We called pm_runtime_get_noresume when the device was attached.
3875 * Decrement the counter here to allow controller to runtime suspend
3876 * if no devices remain.
3877 */
3878 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3879 pm_runtime_put_noidle(hcd->self.controller);
3880
3881 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3882 /* If the host is halted due to driver unload, we still need to free the
3883 * device.
3884 */
3885 if (ret <= 0 && ret != -ENODEV)
3886 return;
3887
3888 virt_dev = xhci->devs[udev->slot_id];
3889 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3890 trace_xhci_free_dev(slot_ctx);
3891
3892 /* Stop any wayward timer functions (which may grab the lock) */
3893 for (i = 0; i < 31; i++)
3894 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3895 virt_dev->udev = NULL;
3896 xhci_disable_slot(xhci, udev->slot_id);
3897
3898 spin_lock_irqsave(&xhci->lock, flags);
3899 xhci_free_virt_device(xhci, udev->slot_id);
3900 spin_unlock_irqrestore(&xhci->lock, flags);
3901
3902}
3903
3904int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3905{
3906 struct xhci_command *command;
3907 unsigned long flags;
3908 u32 state;
3909 int ret;
3910
3911 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3912 if (!command)
3913 return -ENOMEM;
3914
3915 xhci_debugfs_remove_slot(xhci, slot_id);
3916
3917 spin_lock_irqsave(&xhci->lock, flags);
3918 /* Don't disable the slot if the host controller is dead. */
3919 state = readl(&xhci->op_regs->status);
3920 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3921 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3922 spin_unlock_irqrestore(&xhci->lock, flags);
3923 kfree(command);
3924 return -ENODEV;
3925 }
3926
3927 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3928 slot_id);
3929 if (ret) {
3930 spin_unlock_irqrestore(&xhci->lock, flags);
3931 kfree(command);
3932 return ret;
3933 }
3934 xhci_ring_cmd_db(xhci);
3935 spin_unlock_irqrestore(&xhci->lock, flags);
3936
3937 wait_for_completion(command->completion);
3938
3939 if (command->status != COMP_SUCCESS)
3940 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
3941 slot_id, command->status);
3942
3943 xhci_free_command(xhci, command);
3944
3945 return 0;
3946}
3947
3948/*
3949 * Checks if we have enough host controller resources for the default control
3950 * endpoint.
3951 *
3952 * Must be called with xhci->lock held.
3953 */
3954static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3955{
3956 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3957 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3958 "Not enough ep ctxs: "
3959 "%u active, need to add 1, limit is %u.",
3960 xhci->num_active_eps, xhci->limit_active_eps);
3961 return -ENOMEM;
3962 }
3963 xhci->num_active_eps += 1;
3964 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3965 "Adding 1 ep ctx, %u now active.",
3966 xhci->num_active_eps);
3967 return 0;
3968}
3969
3970
3971/*
3972 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3973 * timed out, or allocating memory failed. Returns 1 on success.
3974 */
3975int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3976{
3977 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3978 struct xhci_virt_device *vdev;
3979 struct xhci_slot_ctx *slot_ctx;
3980 unsigned long flags;
3981 int ret, slot_id;
3982 struct xhci_command *command;
3983
3984 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3985 if (!command)
3986 return 0;
3987
3988 spin_lock_irqsave(&xhci->lock, flags);
3989 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3990 if (ret) {
3991 spin_unlock_irqrestore(&xhci->lock, flags);
3992 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3993 xhci_free_command(xhci, command);
3994 return 0;
3995 }
3996 xhci_ring_cmd_db(xhci);
3997 spin_unlock_irqrestore(&xhci->lock, flags);
3998
3999 wait_for_completion(command->completion);
4000 slot_id = command->slot_id;
4001
4002 if (!slot_id || command->status != COMP_SUCCESS) {
4003 xhci_err(xhci, "Error while assigning device slot ID: %s\n",
4004 xhci_trb_comp_code_string(command->status));
4005 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4006 HCS_MAX_SLOTS(
4007 readl(&xhci->cap_regs->hcs_params1)));
4008 xhci_free_command(xhci, command);
4009 return 0;
4010 }
4011
4012 xhci_free_command(xhci, command);
4013
4014 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4015 spin_lock_irqsave(&xhci->lock, flags);
4016 ret = xhci_reserve_host_control_ep_resources(xhci);
4017 if (ret) {
4018 spin_unlock_irqrestore(&xhci->lock, flags);
4019 xhci_warn(xhci, "Not enough host resources, "
4020 "active endpoint contexts = %u\n",
4021 xhci->num_active_eps);
4022 goto disable_slot;
4023 }
4024 spin_unlock_irqrestore(&xhci->lock, flags);
4025 }
4026 /* Use GFP_NOIO, since this function can be called from
4027 * xhci_discover_or_reset_device(), which may be called as part of
4028 * mass storage driver error handling.
4029 */
4030 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4031 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4032 goto disable_slot;
4033 }
4034 vdev = xhci->devs[slot_id];
4035 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4036 trace_xhci_alloc_dev(slot_ctx);
4037
4038 udev->slot_id = slot_id;
4039
4040 xhci_debugfs_create_slot(xhci, slot_id);
4041
4042 /*
4043 * If resetting upon resume, we can't put the controller into runtime
4044 * suspend if there is a device attached.
4045 */
4046 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4047 pm_runtime_get_noresume(hcd->self.controller);
4048
4049 /* Is this a LS or FS device under a HS hub? */
4050 /* Hub or peripherial? */
4051 return 1;
4052
4053disable_slot:
4054 xhci_disable_slot(xhci, udev->slot_id);
4055 xhci_free_virt_device(xhci, udev->slot_id);
4056
4057 return 0;
4058}
4059
4060/**
4061 * xhci_setup_device - issues an Address Device command to assign a unique
4062 * USB bus address.
4063 * @hcd: USB host controller data structure.
4064 * @udev: USB dev structure representing the connected device.
4065 * @setup: Enum specifying setup mode: address only or with context.
4066 * @timeout_ms: Max wait time (ms) for the command operation to complete.
4067 *
4068 * Return: 0 if successful; otherwise, negative error code.
4069 */
4070static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4071 enum xhci_setup_dev setup, unsigned int timeout_ms)
4072{
4073 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4074 unsigned long flags;
4075 struct xhci_virt_device *virt_dev;
4076 int ret = 0;
4077 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4078 struct xhci_slot_ctx *slot_ctx;
4079 struct xhci_input_control_ctx *ctrl_ctx;
4080 u64 temp_64;
4081 struct xhci_command *command = NULL;
4082
4083 mutex_lock(&xhci->mutex);
4084
4085 if (xhci->xhc_state) { /* dying, removing or halted */
4086 ret = -ESHUTDOWN;
4087 goto out;
4088 }
4089
4090 if (!udev->slot_id) {
4091 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4092 "Bad Slot ID %d", udev->slot_id);
4093 ret = -EINVAL;
4094 goto out;
4095 }
4096
4097 virt_dev = xhci->devs[udev->slot_id];
4098
4099 if (WARN_ON(!virt_dev)) {
4100 /*
4101 * In plug/unplug torture test with an NEC controller,
4102 * a zero-dereference was observed once due to virt_dev = 0.
4103 * Print useful debug rather than crash if it is observed again!
4104 */
4105 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4106 udev->slot_id);
4107 ret = -EINVAL;
4108 goto out;
4109 }
4110 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4111 trace_xhci_setup_device_slot(slot_ctx);
4112
4113 if (setup == SETUP_CONTEXT_ONLY) {
4114 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4115 SLOT_STATE_DEFAULT) {
4116 xhci_dbg(xhci, "Slot already in default state\n");
4117 goto out;
4118 }
4119 }
4120
4121 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4122 if (!command) {
4123 ret = -ENOMEM;
4124 goto out;
4125 }
4126
4127 command->in_ctx = virt_dev->in_ctx;
4128 command->timeout_ms = timeout_ms;
4129
4130 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4131 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4132 if (!ctrl_ctx) {
4133 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4134 __func__);
4135 ret = -EINVAL;
4136 goto out;
4137 }
4138 /*
4139 * If this is the first Set Address since device plug-in or
4140 * virt_device realloaction after a resume with an xHCI power loss,
4141 * then set up the slot context.
4142 */
4143 if (!slot_ctx->dev_info)
4144 xhci_setup_addressable_virt_dev(xhci, udev);
4145 /* Otherwise, update the control endpoint ring enqueue pointer. */
4146 else
4147 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4148 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4149 ctrl_ctx->drop_flags = 0;
4150
4151 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4152 le32_to_cpu(slot_ctx->dev_info) >> 27);
4153
4154 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4155 spin_lock_irqsave(&xhci->lock, flags);
4156 trace_xhci_setup_device(virt_dev);
4157 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4158 udev->slot_id, setup);
4159 if (ret) {
4160 spin_unlock_irqrestore(&xhci->lock, flags);
4161 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4162 "FIXME: allocate a command ring segment");
4163 goto out;
4164 }
4165 xhci_ring_cmd_db(xhci);
4166 spin_unlock_irqrestore(&xhci->lock, flags);
4167
4168 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4169 wait_for_completion(command->completion);
4170
4171 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4172 * the SetAddress() "recovery interval" required by USB and aborting the
4173 * command on a timeout.
4174 */
4175 switch (command->status) {
4176 case COMP_COMMAND_ABORTED:
4177 case COMP_COMMAND_RING_STOPPED:
4178 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4179 ret = -ETIME;
4180 break;
4181 case COMP_CONTEXT_STATE_ERROR:
4182 case COMP_SLOT_NOT_ENABLED_ERROR:
4183 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4184 act, udev->slot_id);
4185 ret = -EINVAL;
4186 break;
4187 case COMP_USB_TRANSACTION_ERROR:
4188 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4189
4190 mutex_unlock(&xhci->mutex);
4191 ret = xhci_disable_slot(xhci, udev->slot_id);
4192 xhci_free_virt_device(xhci, udev->slot_id);
4193 if (!ret)
4194 xhci_alloc_dev(hcd, udev);
4195 kfree(command->completion);
4196 kfree(command);
4197 return -EPROTO;
4198 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4199 dev_warn(&udev->dev,
4200 "ERROR: Incompatible device for setup %s command\n", act);
4201 ret = -ENODEV;
4202 break;
4203 case COMP_SUCCESS:
4204 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4205 "Successful setup %s command", act);
4206 break;
4207 default:
4208 xhci_err(xhci,
4209 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4210 act, command->status);
4211 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4212 ret = -EINVAL;
4213 break;
4214 }
4215 if (ret)
4216 goto out;
4217 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4218 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4219 "Op regs DCBAA ptr = %#016llx", temp_64);
4220 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4221 "Slot ID %d dcbaa entry @%p = %#016llx",
4222 udev->slot_id,
4223 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4224 (unsigned long long)
4225 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4226 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4227 "Output Context DMA address = %#08llx",
4228 (unsigned long long)virt_dev->out_ctx->dma);
4229 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4230 le32_to_cpu(slot_ctx->dev_info) >> 27);
4231 /*
4232 * USB core uses address 1 for the roothubs, so we add one to the
4233 * address given back to us by the HC.
4234 */
4235 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4236 le32_to_cpu(slot_ctx->dev_info) >> 27);
4237 /* Zero the input context control for later use */
4238 ctrl_ctx->add_flags = 0;
4239 ctrl_ctx->drop_flags = 0;
4240 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4241 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4242
4243 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4244 "Internal device address = %d",
4245 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4246out:
4247 mutex_unlock(&xhci->mutex);
4248 if (command) {
4249 kfree(command->completion);
4250 kfree(command);
4251 }
4252 return ret;
4253}
4254
4255static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev,
4256 unsigned int timeout_ms)
4257{
4258 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS, timeout_ms);
4259}
4260
4261static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4262{
4263 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY,
4264 XHCI_CMD_DEFAULT_TIMEOUT);
4265}
4266
4267/*
4268 * Transfer the port index into real index in the HW port status
4269 * registers. Caculate offset between the port's PORTSC register
4270 * and port status base. Divide the number of per port register
4271 * to get the real index. The raw port number bases 1.
4272 */
4273int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4274{
4275 struct xhci_hub *rhub;
4276
4277 rhub = xhci_get_rhub(hcd);
4278 return rhub->ports[port1 - 1]->hw_portnum + 1;
4279}
4280
4281/*
4282 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4283 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4284 */
4285static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4286 struct usb_device *udev, u16 max_exit_latency)
4287{
4288 struct xhci_virt_device *virt_dev;
4289 struct xhci_command *command;
4290 struct xhci_input_control_ctx *ctrl_ctx;
4291 struct xhci_slot_ctx *slot_ctx;
4292 unsigned long flags;
4293 int ret;
4294
4295 command = xhci_alloc_command_with_ctx(xhci, true, GFP_KERNEL);
4296 if (!command)
4297 return -ENOMEM;
4298
4299 spin_lock_irqsave(&xhci->lock, flags);
4300
4301 virt_dev = xhci->devs[udev->slot_id];
4302
4303 /*
4304 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4305 * xHC was re-initialized. Exit latency will be set later after
4306 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4307 */
4308
4309 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4310 spin_unlock_irqrestore(&xhci->lock, flags);
4311 xhci_free_command(xhci, command);
4312 return 0;
4313 }
4314
4315 /* Attempt to issue an Evaluate Context command to change the MEL. */
4316 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4317 if (!ctrl_ctx) {
4318 spin_unlock_irqrestore(&xhci->lock, flags);
4319 xhci_free_command(xhci, command);
4320 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4321 __func__);
4322 return -ENOMEM;
4323 }
4324
4325 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4326 spin_unlock_irqrestore(&xhci->lock, flags);
4327
4328 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4329 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4330 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4331 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4332 slot_ctx->dev_state = 0;
4333
4334 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4335 "Set up evaluate context for LPM MEL change.");
4336
4337 /* Issue and wait for the evaluate context command. */
4338 ret = xhci_configure_endpoint(xhci, udev, command,
4339 true, true);
4340
4341 if (!ret) {
4342 spin_lock_irqsave(&xhci->lock, flags);
4343 virt_dev->current_mel = max_exit_latency;
4344 spin_unlock_irqrestore(&xhci->lock, flags);
4345 }
4346
4347 xhci_free_command(xhci, command);
4348
4349 return ret;
4350}
4351
4352#ifdef CONFIG_PM
4353
4354/* BESL to HIRD Encoding array for USB2 LPM */
4355static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4356 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4357
4358/* Calculate HIRD/BESL for USB2 PORTPMSC*/
4359static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4360 struct usb_device *udev)
4361{
4362 int u2del, besl, besl_host;
4363 int besl_device = 0;
4364 u32 field;
4365
4366 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4367 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4368
4369 if (field & USB_BESL_SUPPORT) {
4370 for (besl_host = 0; besl_host < 16; besl_host++) {
4371 if (xhci_besl_encoding[besl_host] >= u2del)
4372 break;
4373 }
4374 /* Use baseline BESL value as default */
4375 if (field & USB_BESL_BASELINE_VALID)
4376 besl_device = USB_GET_BESL_BASELINE(field);
4377 else if (field & USB_BESL_DEEP_VALID)
4378 besl_device = USB_GET_BESL_DEEP(field);
4379 } else {
4380 if (u2del <= 50)
4381 besl_host = 0;
4382 else
4383 besl_host = (u2del - 51) / 75 + 1;
4384 }
4385
4386 besl = besl_host + besl_device;
4387 if (besl > 15)
4388 besl = 15;
4389
4390 return besl;
4391}
4392
4393/* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4394static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4395{
4396 u32 field;
4397 int l1;
4398 int besld = 0;
4399 int hirdm = 0;
4400
4401 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4402
4403 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4404 l1 = udev->l1_params.timeout / 256;
4405
4406 /* device has preferred BESLD */
4407 if (field & USB_BESL_DEEP_VALID) {
4408 besld = USB_GET_BESL_DEEP(field);
4409 hirdm = 1;
4410 }
4411
4412 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4413}
4414
4415static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4416 struct usb_device *udev, int enable)
4417{
4418 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4419 struct xhci_port **ports;
4420 __le32 __iomem *pm_addr, *hlpm_addr;
4421 u32 pm_val, hlpm_val, field;
4422 unsigned int port_num;
4423 unsigned long flags;
4424 int hird, exit_latency;
4425 int ret;
4426
4427 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4428 return -EPERM;
4429
4430 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4431 !udev->lpm_capable)
4432 return -EPERM;
4433
4434 if (!udev->parent || udev->parent->parent ||
4435 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4436 return -EPERM;
4437
4438 if (udev->usb2_hw_lpm_capable != 1)
4439 return -EPERM;
4440
4441 spin_lock_irqsave(&xhci->lock, flags);
4442
4443 ports = xhci->usb2_rhub.ports;
4444 port_num = udev->portnum - 1;
4445 pm_addr = ports[port_num]->addr + PORTPMSC;
4446 pm_val = readl(pm_addr);
4447 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4448
4449 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4450 enable ? "enable" : "disable", port_num + 1);
4451
4452 if (enable) {
4453 /* Host supports BESL timeout instead of HIRD */
4454 if (udev->usb2_hw_lpm_besl_capable) {
4455 /* if device doesn't have a preferred BESL value use a
4456 * default one which works with mixed HIRD and BESL
4457 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4458 */
4459 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4460 if ((field & USB_BESL_SUPPORT) &&
4461 (field & USB_BESL_BASELINE_VALID))
4462 hird = USB_GET_BESL_BASELINE(field);
4463 else
4464 hird = udev->l1_params.besl;
4465
4466 exit_latency = xhci_besl_encoding[hird];
4467 spin_unlock_irqrestore(&xhci->lock, flags);
4468
4469 ret = xhci_change_max_exit_latency(xhci, udev,
4470 exit_latency);
4471 if (ret < 0)
4472 return ret;
4473 spin_lock_irqsave(&xhci->lock, flags);
4474
4475 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4476 writel(hlpm_val, hlpm_addr);
4477 /* flush write */
4478 readl(hlpm_addr);
4479 } else {
4480 hird = xhci_calculate_hird_besl(xhci, udev);
4481 }
4482
4483 pm_val &= ~PORT_HIRD_MASK;
4484 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4485 writel(pm_val, pm_addr);
4486 pm_val = readl(pm_addr);
4487 pm_val |= PORT_HLE;
4488 writel(pm_val, pm_addr);
4489 /* flush write */
4490 readl(pm_addr);
4491 } else {
4492 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4493 writel(pm_val, pm_addr);
4494 /* flush write */
4495 readl(pm_addr);
4496 if (udev->usb2_hw_lpm_besl_capable) {
4497 spin_unlock_irqrestore(&xhci->lock, flags);
4498 xhci_change_max_exit_latency(xhci, udev, 0);
4499 readl_poll_timeout(ports[port_num]->addr, pm_val,
4500 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4501 100, 10000);
4502 return 0;
4503 }
4504 }
4505
4506 spin_unlock_irqrestore(&xhci->lock, flags);
4507 return 0;
4508}
4509
4510/* check if a usb2 port supports a given extened capability protocol
4511 * only USB2 ports extended protocol capability values are cached.
4512 * Return 1 if capability is supported
4513 */
4514static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4515 unsigned capability)
4516{
4517 u32 port_offset, port_count;
4518 int i;
4519
4520 for (i = 0; i < xhci->num_ext_caps; i++) {
4521 if (xhci->ext_caps[i] & capability) {
4522 /* port offsets starts at 1 */
4523 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4524 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4525 if (port >= port_offset &&
4526 port < port_offset + port_count)
4527 return 1;
4528 }
4529 }
4530 return 0;
4531}
4532
4533static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4534{
4535 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4536 int portnum = udev->portnum - 1;
4537
4538 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4539 return 0;
4540
4541 /* we only support lpm for non-hub device connected to root hub yet */
4542 if (!udev->parent || udev->parent->parent ||
4543 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4544 return 0;
4545
4546 if (xhci->hw_lpm_support == 1 &&
4547 xhci_check_usb2_port_capability(
4548 xhci, portnum, XHCI_HLC)) {
4549 udev->usb2_hw_lpm_capable = 1;
4550 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4551 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4552 if (xhci_check_usb2_port_capability(xhci, portnum,
4553 XHCI_BLC))
4554 udev->usb2_hw_lpm_besl_capable = 1;
4555 }
4556
4557 return 0;
4558}
4559
4560/*---------------------- USB 3.0 Link PM functions ------------------------*/
4561
4562/* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4563static unsigned long long xhci_service_interval_to_ns(
4564 struct usb_endpoint_descriptor *desc)
4565{
4566 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4567}
4568
4569static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4570 enum usb3_link_state state)
4571{
4572 unsigned long long sel;
4573 unsigned long long pel;
4574 unsigned int max_sel_pel;
4575 char *state_name;
4576
4577 switch (state) {
4578 case USB3_LPM_U1:
4579 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4580 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4581 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4582 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4583 state_name = "U1";
4584 break;
4585 case USB3_LPM_U2:
4586 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4587 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4588 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4589 state_name = "U2";
4590 break;
4591 default:
4592 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4593 __func__);
4594 return USB3_LPM_DISABLED;
4595 }
4596
4597 if (sel <= max_sel_pel && pel <= max_sel_pel)
4598 return USB3_LPM_DEVICE_INITIATED;
4599
4600 if (sel > max_sel_pel)
4601 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4602 "due to long SEL %llu ms\n",
4603 state_name, sel);
4604 else
4605 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4606 "due to long PEL %llu ms\n",
4607 state_name, pel);
4608 return USB3_LPM_DISABLED;
4609}
4610
4611/* The U1 timeout should be the maximum of the following values:
4612 * - For control endpoints, U1 system exit latency (SEL) * 3
4613 * - For bulk endpoints, U1 SEL * 5
4614 * - For interrupt endpoints:
4615 * - Notification EPs, U1 SEL * 3
4616 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4617 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4618 */
4619static unsigned long long xhci_calculate_intel_u1_timeout(
4620 struct usb_device *udev,
4621 struct usb_endpoint_descriptor *desc)
4622{
4623 unsigned long long timeout_ns;
4624 int ep_type;
4625 int intr_type;
4626
4627 ep_type = usb_endpoint_type(desc);
4628 switch (ep_type) {
4629 case USB_ENDPOINT_XFER_CONTROL:
4630 timeout_ns = udev->u1_params.sel * 3;
4631 break;
4632 case USB_ENDPOINT_XFER_BULK:
4633 timeout_ns = udev->u1_params.sel * 5;
4634 break;
4635 case USB_ENDPOINT_XFER_INT:
4636 intr_type = usb_endpoint_interrupt_type(desc);
4637 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4638 timeout_ns = udev->u1_params.sel * 3;
4639 break;
4640 }
4641 /* Otherwise the calculation is the same as isoc eps */
4642 fallthrough;
4643 case USB_ENDPOINT_XFER_ISOC:
4644 timeout_ns = xhci_service_interval_to_ns(desc);
4645 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4646 if (timeout_ns < udev->u1_params.sel * 2)
4647 timeout_ns = udev->u1_params.sel * 2;
4648 break;
4649 default:
4650 return 0;
4651 }
4652
4653 return timeout_ns;
4654}
4655
4656/* Returns the hub-encoded U1 timeout value. */
4657static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4658 struct usb_device *udev,
4659 struct usb_endpoint_descriptor *desc)
4660{
4661 unsigned long long timeout_ns;
4662
4663 /* Prevent U1 if service interval is shorter than U1 exit latency */
4664 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4665 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4666 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4667 return USB3_LPM_DISABLED;
4668 }
4669 }
4670
4671 if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
4672 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4673 else
4674 timeout_ns = udev->u1_params.sel;
4675
4676 /* The U1 timeout is encoded in 1us intervals.
4677 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4678 */
4679 if (timeout_ns == USB3_LPM_DISABLED)
4680 timeout_ns = 1;
4681 else
4682 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4683
4684 /* If the necessary timeout value is bigger than what we can set in the
4685 * USB 3.0 hub, we have to disable hub-initiated U1.
4686 */
4687 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4688 return timeout_ns;
4689 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4690 "due to long timeout %llu ms\n", timeout_ns);
4691 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4692}
4693
4694/* The U2 timeout should be the maximum of:
4695 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4696 * - largest bInterval of any active periodic endpoint (to avoid going
4697 * into lower power link states between intervals).
4698 * - the U2 Exit Latency of the device
4699 */
4700static unsigned long long xhci_calculate_intel_u2_timeout(
4701 struct usb_device *udev,
4702 struct usb_endpoint_descriptor *desc)
4703{
4704 unsigned long long timeout_ns;
4705 unsigned long long u2_del_ns;
4706
4707 timeout_ns = 10 * 1000 * 1000;
4708
4709 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4710 (xhci_service_interval_to_ns(desc) > timeout_ns))
4711 timeout_ns = xhci_service_interval_to_ns(desc);
4712
4713 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4714 if (u2_del_ns > timeout_ns)
4715 timeout_ns = u2_del_ns;
4716
4717 return timeout_ns;
4718}
4719
4720/* Returns the hub-encoded U2 timeout value. */
4721static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4722 struct usb_device *udev,
4723 struct usb_endpoint_descriptor *desc)
4724{
4725 unsigned long long timeout_ns;
4726
4727 /* Prevent U2 if service interval is shorter than U2 exit latency */
4728 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4729 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4730 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4731 return USB3_LPM_DISABLED;
4732 }
4733 }
4734
4735 if (xhci->quirks & (XHCI_INTEL_HOST | XHCI_ZHAOXIN_HOST))
4736 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4737 else
4738 timeout_ns = udev->u2_params.sel;
4739
4740 /* The U2 timeout is encoded in 256us intervals */
4741 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4742 /* If the necessary timeout value is bigger than what we can set in the
4743 * USB 3.0 hub, we have to disable hub-initiated U2.
4744 */
4745 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4746 return timeout_ns;
4747 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4748 "due to long timeout %llu ms\n", timeout_ns);
4749 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4750}
4751
4752static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4753 struct usb_device *udev,
4754 struct usb_endpoint_descriptor *desc,
4755 enum usb3_link_state state,
4756 u16 *timeout)
4757{
4758 if (state == USB3_LPM_U1)
4759 return xhci_calculate_u1_timeout(xhci, udev, desc);
4760 else if (state == USB3_LPM_U2)
4761 return xhci_calculate_u2_timeout(xhci, udev, desc);
4762
4763 return USB3_LPM_DISABLED;
4764}
4765
4766static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4767 struct usb_device *udev,
4768 struct usb_endpoint_descriptor *desc,
4769 enum usb3_link_state state,
4770 u16 *timeout)
4771{
4772 u16 alt_timeout;
4773
4774 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4775 desc, state, timeout);
4776
4777 /* If we found we can't enable hub-initiated LPM, and
4778 * the U1 or U2 exit latency was too high to allow
4779 * device-initiated LPM as well, then we will disable LPM
4780 * for this device, so stop searching any further.
4781 */
4782 if (alt_timeout == USB3_LPM_DISABLED) {
4783 *timeout = alt_timeout;
4784 return -E2BIG;
4785 }
4786 if (alt_timeout > *timeout)
4787 *timeout = alt_timeout;
4788 return 0;
4789}
4790
4791static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4792 struct usb_device *udev,
4793 struct usb_host_interface *alt,
4794 enum usb3_link_state state,
4795 u16 *timeout)
4796{
4797 int j;
4798
4799 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4800 if (xhci_update_timeout_for_endpoint(xhci, udev,
4801 &alt->endpoint[j].desc, state, timeout))
4802 return -E2BIG;
4803 }
4804 return 0;
4805}
4806
4807static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4808 struct usb_device *udev,
4809 enum usb3_link_state state)
4810{
4811 struct usb_device *parent = udev->parent;
4812 int tier = 1; /* roothub is tier1 */
4813
4814 while (parent) {
4815 parent = parent->parent;
4816 tier++;
4817 }
4818
4819 if (xhci->quirks & XHCI_INTEL_HOST && tier > 3)
4820 goto fail;
4821 if (xhci->quirks & XHCI_ZHAOXIN_HOST && tier > 2)
4822 goto fail;
4823
4824 return 0;
4825fail:
4826 dev_dbg(&udev->dev, "Tier policy prevents U1/U2 LPM states for devices at tier %d\n",
4827 tier);
4828 return -E2BIG;
4829}
4830
4831/* Returns the U1 or U2 timeout that should be enabled.
4832 * If the tier check or timeout setting functions return with a non-zero exit
4833 * code, that means the timeout value has been finalized and we shouldn't look
4834 * at any more endpoints.
4835 */
4836static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4837 struct usb_device *udev, enum usb3_link_state state)
4838{
4839 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4840 struct usb_host_config *config;
4841 char *state_name;
4842 int i;
4843 u16 timeout = USB3_LPM_DISABLED;
4844
4845 if (state == USB3_LPM_U1)
4846 state_name = "U1";
4847 else if (state == USB3_LPM_U2)
4848 state_name = "U2";
4849 else {
4850 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4851 state);
4852 return timeout;
4853 }
4854
4855 /* Gather some information about the currently installed configuration
4856 * and alternate interface settings.
4857 */
4858 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4859 state, &timeout))
4860 return timeout;
4861
4862 config = udev->actconfig;
4863 if (!config)
4864 return timeout;
4865
4866 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4867 struct usb_driver *driver;
4868 struct usb_interface *intf = config->interface[i];
4869
4870 if (!intf)
4871 continue;
4872
4873 /* Check if any currently bound drivers want hub-initiated LPM
4874 * disabled.
4875 */
4876 if (intf->dev.driver) {
4877 driver = to_usb_driver(intf->dev.driver);
4878 if (driver && driver->disable_hub_initiated_lpm) {
4879 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4880 state_name, driver->name);
4881 timeout = xhci_get_timeout_no_hub_lpm(udev,
4882 state);
4883 if (timeout == USB3_LPM_DISABLED)
4884 return timeout;
4885 }
4886 }
4887
4888 /* Not sure how this could happen... */
4889 if (!intf->cur_altsetting)
4890 continue;
4891
4892 if (xhci_update_timeout_for_interface(xhci, udev,
4893 intf->cur_altsetting,
4894 state, &timeout))
4895 return timeout;
4896 }
4897 return timeout;
4898}
4899
4900static int calculate_max_exit_latency(struct usb_device *udev,
4901 enum usb3_link_state state_changed,
4902 u16 hub_encoded_timeout)
4903{
4904 unsigned long long u1_mel_us = 0;
4905 unsigned long long u2_mel_us = 0;
4906 unsigned long long mel_us = 0;
4907 bool disabling_u1;
4908 bool disabling_u2;
4909 bool enabling_u1;
4910 bool enabling_u2;
4911
4912 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4913 hub_encoded_timeout == USB3_LPM_DISABLED);
4914 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4915 hub_encoded_timeout == USB3_LPM_DISABLED);
4916
4917 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4918 hub_encoded_timeout != USB3_LPM_DISABLED);
4919 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4920 hub_encoded_timeout != USB3_LPM_DISABLED);
4921
4922 /* If U1 was already enabled and we're not disabling it,
4923 * or we're going to enable U1, account for the U1 max exit latency.
4924 */
4925 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4926 enabling_u1)
4927 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4928 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4929 enabling_u2)
4930 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4931
4932 mel_us = max(u1_mel_us, u2_mel_us);
4933
4934 /* xHCI host controller max exit latency field is only 16 bits wide. */
4935 if (mel_us > MAX_EXIT) {
4936 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4937 "is too big.\n", mel_us);
4938 return -E2BIG;
4939 }
4940 return mel_us;
4941}
4942
4943/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4944static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4945 struct usb_device *udev, enum usb3_link_state state)
4946{
4947 struct xhci_hcd *xhci;
4948 struct xhci_port *port;
4949 u16 hub_encoded_timeout;
4950 int mel;
4951 int ret;
4952
4953 xhci = hcd_to_xhci(hcd);
4954 /* The LPM timeout values are pretty host-controller specific, so don't
4955 * enable hub-initiated timeouts unless the vendor has provided
4956 * information about their timeout algorithm.
4957 */
4958 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4959 !xhci->devs[udev->slot_id])
4960 return USB3_LPM_DISABLED;
4961
4962 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4963 return USB3_LPM_DISABLED;
4964
4965 /* If connected to root port then check port can handle lpm */
4966 if (udev->parent && !udev->parent->parent) {
4967 port = xhci->usb3_rhub.ports[udev->portnum - 1];
4968 if (port->lpm_incapable)
4969 return USB3_LPM_DISABLED;
4970 }
4971
4972 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4973 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4974 if (mel < 0) {
4975 /* Max Exit Latency is too big, disable LPM. */
4976 hub_encoded_timeout = USB3_LPM_DISABLED;
4977 mel = 0;
4978 }
4979
4980 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4981 if (ret)
4982 return ret;
4983 return hub_encoded_timeout;
4984}
4985
4986static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4987 struct usb_device *udev, enum usb3_link_state state)
4988{
4989 struct xhci_hcd *xhci;
4990 u16 mel;
4991
4992 xhci = hcd_to_xhci(hcd);
4993 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4994 !xhci->devs[udev->slot_id])
4995 return 0;
4996
4997 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4998 return xhci_change_max_exit_latency(xhci, udev, mel);
4999}
5000#else /* CONFIG_PM */
5001
5002static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5003 struct usb_device *udev, int enable)
5004{
5005 return 0;
5006}
5007
5008static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5009{
5010 return 0;
5011}
5012
5013static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5014 struct usb_device *udev, enum usb3_link_state state)
5015{
5016 return USB3_LPM_DISABLED;
5017}
5018
5019static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5020 struct usb_device *udev, enum usb3_link_state state)
5021{
5022 return 0;
5023}
5024#endif /* CONFIG_PM */
5025
5026/*-------------------------------------------------------------------------*/
5027
5028/* Once a hub descriptor is fetched for a device, we need to update the xHC's
5029 * internal data structures for the device.
5030 */
5031int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5032 struct usb_tt *tt, gfp_t mem_flags)
5033{
5034 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5035 struct xhci_virt_device *vdev;
5036 struct xhci_command *config_cmd;
5037 struct xhci_input_control_ctx *ctrl_ctx;
5038 struct xhci_slot_ctx *slot_ctx;
5039 unsigned long flags;
5040 unsigned think_time;
5041 int ret;
5042
5043 /* Ignore root hubs */
5044 if (!hdev->parent)
5045 return 0;
5046
5047 vdev = xhci->devs[hdev->slot_id];
5048 if (!vdev) {
5049 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5050 return -EINVAL;
5051 }
5052
5053 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5054 if (!config_cmd)
5055 return -ENOMEM;
5056
5057 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5058 if (!ctrl_ctx) {
5059 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5060 __func__);
5061 xhci_free_command(xhci, config_cmd);
5062 return -ENOMEM;
5063 }
5064
5065 spin_lock_irqsave(&xhci->lock, flags);
5066 if (hdev->speed == USB_SPEED_HIGH &&
5067 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5068 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5069 xhci_free_command(xhci, config_cmd);
5070 spin_unlock_irqrestore(&xhci->lock, flags);
5071 return -ENOMEM;
5072 }
5073
5074 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5075 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5076 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5077 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5078 /*
5079 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5080 * but it may be already set to 1 when setup an xHCI virtual
5081 * device, so clear it anyway.
5082 */
5083 if (tt->multi)
5084 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5085 else if (hdev->speed == USB_SPEED_FULL)
5086 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5087
5088 if (xhci->hci_version > 0x95) {
5089 xhci_dbg(xhci, "xHCI version %x needs hub "
5090 "TT think time and number of ports\n",
5091 (unsigned int) xhci->hci_version);
5092 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5093 /* Set TT think time - convert from ns to FS bit times.
5094 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5095 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5096 *
5097 * xHCI 1.0: this field shall be 0 if the device is not a
5098 * High-spped hub.
5099 */
5100 think_time = tt->think_time;
5101 if (think_time != 0)
5102 think_time = (think_time / 666) - 1;
5103 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5104 slot_ctx->tt_info |=
5105 cpu_to_le32(TT_THINK_TIME(think_time));
5106 } else {
5107 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5108 "TT think time or number of ports\n",
5109 (unsigned int) xhci->hci_version);
5110 }
5111 slot_ctx->dev_state = 0;
5112 spin_unlock_irqrestore(&xhci->lock, flags);
5113
5114 xhci_dbg(xhci, "Set up %s for hub device.\n",
5115 (xhci->hci_version > 0x95) ?
5116 "configure endpoint" : "evaluate context");
5117
5118 /* Issue and wait for the configure endpoint or
5119 * evaluate context command.
5120 */
5121 if (xhci->hci_version > 0x95)
5122 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5123 false, false);
5124 else
5125 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5126 true, false);
5127
5128 xhci_free_command(xhci, config_cmd);
5129 return ret;
5130}
5131EXPORT_SYMBOL_GPL(xhci_update_hub_device);
5132
5133static int xhci_get_frame(struct usb_hcd *hcd)
5134{
5135 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5136 /* EHCI mods by the periodic size. Why? */
5137 return readl(&xhci->run_regs->microframe_index) >> 3;
5138}
5139
5140static void xhci_hcd_init_usb2_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5141{
5142 xhci->usb2_rhub.hcd = hcd;
5143 hcd->speed = HCD_USB2;
5144 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5145 /*
5146 * USB 2.0 roothub under xHCI has an integrated TT,
5147 * (rate matching hub) as opposed to having an OHCI/UHCI
5148 * companion controller.
5149 */
5150 hcd->has_tt = 1;
5151}
5152
5153static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5154{
5155 unsigned int minor_rev;
5156
5157 /*
5158 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5159 * should return 0x31 for sbrn, or that the minor revision
5160 * is a two digit BCD containig minor and sub-minor numbers.
5161 * This was later clarified in xHCI 1.2.
5162 *
5163 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5164 * minor revision set to 0x1 instead of 0x10.
5165 */
5166 if (xhci->usb3_rhub.min_rev == 0x1)
5167 minor_rev = 1;
5168 else
5169 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5170
5171 switch (minor_rev) {
5172 case 2:
5173 hcd->speed = HCD_USB32;
5174 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5175 hcd->self.root_hub->rx_lanes = 2;
5176 hcd->self.root_hub->tx_lanes = 2;
5177 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5178 break;
5179 case 1:
5180 hcd->speed = HCD_USB31;
5181 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5182 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5183 break;
5184 }
5185 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5186 minor_rev, minor_rev ? "Enhanced " : "");
5187
5188 xhci->usb3_rhub.hcd = hcd;
5189}
5190
5191int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5192{
5193 struct xhci_hcd *xhci;
5194 /*
5195 * TODO: Check with DWC3 clients for sysdev according to
5196 * quirks
5197 */
5198 struct device *dev = hcd->self.sysdev;
5199 int retval;
5200
5201 /* Accept arbitrarily long scatter-gather lists */
5202 hcd->self.sg_tablesize = ~0;
5203
5204 /* support to build packet from discontinuous buffers */
5205 hcd->self.no_sg_constraint = 1;
5206
5207 /* XHCI controllers don't stop the ep queue on short packets :| */
5208 hcd->self.no_stop_on_short = 1;
5209
5210 xhci = hcd_to_xhci(hcd);
5211
5212 if (!usb_hcd_is_primary_hcd(hcd)) {
5213 xhci_hcd_init_usb3_data(xhci, hcd);
5214 return 0;
5215 }
5216
5217 mutex_init(&xhci->mutex);
5218 xhci->main_hcd = hcd;
5219 xhci->cap_regs = hcd->regs;
5220 xhci->op_regs = hcd->regs +
5221 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5222 xhci->run_regs = hcd->regs +
5223 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5224 /* Cache read-only capability registers */
5225 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5226 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5227 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5228 xhci->hci_version = HC_VERSION(readl(&xhci->cap_regs->hc_capbase));
5229 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5230 if (xhci->hci_version > 0x100)
5231 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5232
5233 /* xhci-plat or xhci-pci might have set max_interrupters already */
5234 if ((!xhci->max_interrupters) ||
5235 xhci->max_interrupters > HCS_MAX_INTRS(xhci->hcs_params1))
5236 xhci->max_interrupters = HCS_MAX_INTRS(xhci->hcs_params1);
5237
5238 xhci->quirks |= quirks;
5239
5240 if (get_quirks)
5241 get_quirks(dev, xhci);
5242
5243 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5244 * success event after a short transfer. This quirk will ignore such
5245 * spurious event.
5246 */
5247 if (xhci->hci_version > 0x96)
5248 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5249
5250 /* Make sure the HC is halted. */
5251 retval = xhci_halt(xhci);
5252 if (retval)
5253 return retval;
5254
5255 xhci_zero_64b_regs(xhci);
5256
5257 xhci_dbg(xhci, "Resetting HCD\n");
5258 /* Reset the internal HC memory state and registers. */
5259 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5260 if (retval)
5261 return retval;
5262 xhci_dbg(xhci, "Reset complete\n");
5263
5264 /*
5265 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5266 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5267 * address memory pointers actually. So, this driver clears the AC64
5268 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5269 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5270 */
5271 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5272 xhci->hcc_params &= ~BIT(0);
5273
5274 /* Set dma_mask and coherent_dma_mask to 64-bits,
5275 * if xHC supports 64-bit addressing */
5276 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5277 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5278 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5279 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5280 } else {
5281 /*
5282 * This is to avoid error in cases where a 32-bit USB
5283 * controller is used on a 64-bit capable system.
5284 */
5285 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5286 if (retval)
5287 return retval;
5288 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5289 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5290 }
5291
5292 xhci_dbg(xhci, "Calling HCD init\n");
5293 /* Initialize HCD and host controller data structures. */
5294 retval = xhci_init(hcd);
5295 if (retval)
5296 return retval;
5297 xhci_dbg(xhci, "Called HCD init\n");
5298
5299 if (xhci_hcd_is_usb3(hcd))
5300 xhci_hcd_init_usb3_data(xhci, hcd);
5301 else
5302 xhci_hcd_init_usb2_data(xhci, hcd);
5303
5304 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5305 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5306
5307 return 0;
5308}
5309EXPORT_SYMBOL_GPL(xhci_gen_setup);
5310
5311static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5312 struct usb_host_endpoint *ep)
5313{
5314 struct xhci_hcd *xhci;
5315 struct usb_device *udev;
5316 unsigned int slot_id;
5317 unsigned int ep_index;
5318 unsigned long flags;
5319
5320 xhci = hcd_to_xhci(hcd);
5321
5322 spin_lock_irqsave(&xhci->lock, flags);
5323 udev = (struct usb_device *)ep->hcpriv;
5324 slot_id = udev->slot_id;
5325 ep_index = xhci_get_endpoint_index(&ep->desc);
5326
5327 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5328 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5329 spin_unlock_irqrestore(&xhci->lock, flags);
5330}
5331
5332static const struct hc_driver xhci_hc_driver = {
5333 .description = "xhci-hcd",
5334 .product_desc = "xHCI Host Controller",
5335 .hcd_priv_size = sizeof(struct xhci_hcd),
5336
5337 /*
5338 * generic hardware linkage
5339 */
5340 .irq = xhci_irq,
5341 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5342 HCD_BH,
5343
5344 /*
5345 * basic lifecycle operations
5346 */
5347 .reset = NULL, /* set in xhci_init_driver() */
5348 .start = xhci_run,
5349 .stop = xhci_stop,
5350 .shutdown = xhci_shutdown,
5351
5352 /*
5353 * managing i/o requests and associated device resources
5354 */
5355 .map_urb_for_dma = xhci_map_urb_for_dma,
5356 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5357 .urb_enqueue = xhci_urb_enqueue,
5358 .urb_dequeue = xhci_urb_dequeue,
5359 .alloc_dev = xhci_alloc_dev,
5360 .free_dev = xhci_free_dev,
5361 .alloc_streams = xhci_alloc_streams,
5362 .free_streams = xhci_free_streams,
5363 .add_endpoint = xhci_add_endpoint,
5364 .drop_endpoint = xhci_drop_endpoint,
5365 .endpoint_disable = xhci_endpoint_disable,
5366 .endpoint_reset = xhci_endpoint_reset,
5367 .check_bandwidth = xhci_check_bandwidth,
5368 .reset_bandwidth = xhci_reset_bandwidth,
5369 .address_device = xhci_address_device,
5370 .enable_device = xhci_enable_device,
5371 .update_hub_device = xhci_update_hub_device,
5372 .reset_device = xhci_discover_or_reset_device,
5373
5374 /*
5375 * scheduling support
5376 */
5377 .get_frame_number = xhci_get_frame,
5378
5379 /*
5380 * root hub support
5381 */
5382 .hub_control = xhci_hub_control,
5383 .hub_status_data = xhci_hub_status_data,
5384 .bus_suspend = xhci_bus_suspend,
5385 .bus_resume = xhci_bus_resume,
5386 .get_resuming_ports = xhci_get_resuming_ports,
5387
5388 /*
5389 * call back when device connected and addressed
5390 */
5391 .update_device = xhci_update_device,
5392 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5393 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5394 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5395 .find_raw_port_number = xhci_find_raw_port_number,
5396 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5397};
5398
5399void xhci_init_driver(struct hc_driver *drv,
5400 const struct xhci_driver_overrides *over)
5401{
5402 BUG_ON(!over);
5403
5404 /* Copy the generic table to drv then apply the overrides */
5405 *drv = xhci_hc_driver;
5406
5407 if (over) {
5408 drv->hcd_priv_size += over->extra_priv_size;
5409 if (over->reset)
5410 drv->reset = over->reset;
5411 if (over->start)
5412 drv->start = over->start;
5413 if (over->add_endpoint)
5414 drv->add_endpoint = over->add_endpoint;
5415 if (over->drop_endpoint)
5416 drv->drop_endpoint = over->drop_endpoint;
5417 if (over->check_bandwidth)
5418 drv->check_bandwidth = over->check_bandwidth;
5419 if (over->reset_bandwidth)
5420 drv->reset_bandwidth = over->reset_bandwidth;
5421 if (over->update_hub_device)
5422 drv->update_hub_device = over->update_hub_device;
5423 if (over->hub_control)
5424 drv->hub_control = over->hub_control;
5425 }
5426}
5427EXPORT_SYMBOL_GPL(xhci_init_driver);
5428
5429MODULE_DESCRIPTION(DRIVER_DESC);
5430MODULE_AUTHOR(DRIVER_AUTHOR);
5431MODULE_LICENSE("GPL");
5432
5433static int __init xhci_hcd_init(void)
5434{
5435 /*
5436 * Check the compiler generated sizes of structures that must be laid
5437 * out in specific ways for hardware access.
5438 */
5439 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5440 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5441 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5442 /* xhci_device_control has eight fields, and also
5443 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5444 */
5445 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5446 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5447 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5448 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5449 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5450 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5451 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5452
5453 if (usb_disabled())
5454 return -ENODEV;
5455
5456 xhci_debugfs_create_root();
5457 xhci_dbc_init();
5458
5459 return 0;
5460}
5461
5462/*
5463 * If an init function is provided, an exit function must also be provided
5464 * to allow module unload.
5465 */
5466static void __exit xhci_hcd_fini(void)
5467{
5468 xhci_debugfs_remove_root();
5469 xhci_dbc_exit();
5470}
5471
5472module_init(xhci_hcd_init);
5473module_exit(xhci_hcd_fini);