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1// SPDX-License-Identifier: GPL-2.0-only
2// Copyright (c) 2019 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
3/*
4 * +----------------------+
5 * GMAC1----RGMII----|--MAC0 |
6 * \---MDIO1----|--REGs |----MDIO3----\
7 * | | | +------+
8 * | | +--| |
9 * | MAC1-|----RMII--M-----| PHY0 |-o P0
10 * | | | | +------+
11 * | | | +--| |
12 * | MAC2-|----RMII--------| PHY1 |-o P1
13 * | | | | +------+
14 * | | | +--| |
15 * | MAC3-|----RMII--------| PHY2 |-o P2
16 * | | | | +------+
17 * | | | +--| |
18 * | MAC4-|----RMII--------| PHY3 |-o P3
19 * | | | | +------+
20 * | | | +--| |
21 * | MAC5-|--+-RMII--M-----|-PHY4-|-o P4
22 * | | | | +------+
23 * +----------------------+ | \--CFG_SW_PHY_SWAP
24 * GMAC0---------------RMII--------------------/ \-CFG_SW_PHY_ADDR_SWAP
25 * \---MDIO0--NC
26 *
27 * GMAC0 and MAC5 are connected together and use same PHY. Depending on
28 * configuration it can be PHY4 (default) or PHY0. Only GMAC0 or MAC5 can be
29 * used at same time. If GMAC0 is used (default) then MAC5 should be disabled.
30 *
31 * CFG_SW_PHY_SWAP - swap connections of PHY0 and PHY4. If this bit is not set
32 * PHY4 is connected to GMAC0/MAC5 bundle and PHY0 is connected to MAC1. If this
33 * bit is set, PHY4 is connected to MAC1 and PHY0 is connected to GMAC0/MAC5
34 * bundle.
35 *
36 * CFG_SW_PHY_ADDR_SWAP - swap addresses of PHY0 and PHY4
37 *
38 * CFG_SW_PHY_SWAP and CFG_SW_PHY_ADDR_SWAP are part of SoC specific register
39 * set and not related to switch internal registers.
40 */
41
42#include <linux/bitfield.h>
43#include <linux/module.h>
44#include <linux/of_irq.h>
45#include <linux/of_mdio.h>
46#include <linux/regmap.h>
47#include <linux/reset.h>
48#include <net/dsa.h>
49
50#define AR9331_SW_NAME "ar9331_switch"
51#define AR9331_SW_PORTS 6
52
53/* dummy reg to change page */
54#define AR9331_SW_REG_PAGE 0x40000
55
56/* Global Interrupt */
57#define AR9331_SW_REG_GINT 0x10
58#define AR9331_SW_REG_GINT_MASK 0x14
59#define AR9331_SW_GINT_PHY_INT BIT(2)
60
61#define AR9331_SW_REG_FLOOD_MASK 0x2c
62#define AR9331_SW_FLOOD_MASK_BROAD_TO_CPU BIT(26)
63
64#define AR9331_SW_REG_GLOBAL_CTRL 0x30
65#define AR9331_SW_GLOBAL_CTRL_MFS_M GENMASK(13, 0)
66
67#define AR9331_SW_REG_MDIO_CTRL 0x98
68#define AR9331_SW_MDIO_CTRL_BUSY BIT(31)
69#define AR9331_SW_MDIO_CTRL_MASTER_EN BIT(30)
70#define AR9331_SW_MDIO_CTRL_CMD_READ BIT(27)
71#define AR9331_SW_MDIO_CTRL_PHY_ADDR_M GENMASK(25, 21)
72#define AR9331_SW_MDIO_CTRL_REG_ADDR_M GENMASK(20, 16)
73#define AR9331_SW_MDIO_CTRL_DATA_M GENMASK(16, 0)
74
75#define AR9331_SW_REG_PORT_STATUS(_port) (0x100 + (_port) * 0x100)
76
77/* FLOW_LINK_EN - enable mac flow control config auto-neg with phy.
78 * If not set, mac can be config by software.
79 */
80#define AR9331_SW_PORT_STATUS_FLOW_LINK_EN BIT(12)
81
82/* LINK_EN - If set, MAC is configured from PHY link status.
83 * If not set, MAC should be configured by software.
84 */
85#define AR9331_SW_PORT_STATUS_LINK_EN BIT(9)
86#define AR9331_SW_PORT_STATUS_DUPLEX_MODE BIT(6)
87#define AR9331_SW_PORT_STATUS_RX_FLOW_EN BIT(5)
88#define AR9331_SW_PORT_STATUS_TX_FLOW_EN BIT(4)
89#define AR9331_SW_PORT_STATUS_RXMAC BIT(3)
90#define AR9331_SW_PORT_STATUS_TXMAC BIT(2)
91#define AR9331_SW_PORT_STATUS_SPEED_M GENMASK(1, 0)
92#define AR9331_SW_PORT_STATUS_SPEED_1000 2
93#define AR9331_SW_PORT_STATUS_SPEED_100 1
94#define AR9331_SW_PORT_STATUS_SPEED_10 0
95
96#define AR9331_SW_PORT_STATUS_MAC_MASK \
97 (AR9331_SW_PORT_STATUS_TXMAC | AR9331_SW_PORT_STATUS_RXMAC)
98
99#define AR9331_SW_PORT_STATUS_LINK_MASK \
100 (AR9331_SW_PORT_STATUS_DUPLEX_MODE | \
101 AR9331_SW_PORT_STATUS_RX_FLOW_EN | AR9331_SW_PORT_STATUS_TX_FLOW_EN | \
102 AR9331_SW_PORT_STATUS_SPEED_M)
103
104#define AR9331_SW_REG_PORT_CTRL(_port) (0x104 + (_port) * 0x100)
105#define AR9331_SW_PORT_CTRL_HEAD_EN BIT(11)
106#define AR9331_SW_PORT_CTRL_PORT_STATE GENMASK(2, 0)
107#define AR9331_SW_PORT_CTRL_PORT_STATE_DISABLED 0
108#define AR9331_SW_PORT_CTRL_PORT_STATE_BLOCKING 1
109#define AR9331_SW_PORT_CTRL_PORT_STATE_LISTENING 2
110#define AR9331_SW_PORT_CTRL_PORT_STATE_LEARNING 3
111#define AR9331_SW_PORT_CTRL_PORT_STATE_FORWARD 4
112
113#define AR9331_SW_REG_PORT_VLAN(_port) (0x108 + (_port) * 0x100)
114#define AR9331_SW_PORT_VLAN_8021Q_MODE GENMASK(31, 30)
115#define AR9331_SW_8021Q_MODE_SECURE 3
116#define AR9331_SW_8021Q_MODE_CHECK 2
117#define AR9331_SW_8021Q_MODE_FALLBACK 1
118#define AR9331_SW_8021Q_MODE_NONE 0
119#define AR9331_SW_PORT_VLAN_PORT_VID_MEMBER GENMASK(25, 16)
120
121/* MIB registers */
122#define AR9331_MIB_COUNTER(x) (0x20000 + ((x) * 0x100))
123
124/* Phy bypass mode
125 * ------------------------------------------------------------------------
126 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |
127 *
128 * real | start | OP | PhyAddr | Reg Addr | TA |
129 * atheros| start | OP | 2'b00 |PhyAdd[2:0]| Reg Addr[4:0] | TA |
130 *
131 *
132 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |
133 * real | Data |
134 * atheros| Data |
135 *
136 * ------------------------------------------------------------------------
137 * Page address mode
138 * ------------------------------------------------------------------------
139 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |
140 * real | start | OP | PhyAddr | Reg Addr | TA |
141 * atheros| start | OP | 2'b11 | 8'b0 | TA |
142 *
143 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |
144 * real | Data |
145 * atheros| | Page [9:0] |
146 */
147/* In case of Page Address mode, Bit[18:9] of 32 bit register address should be
148 * written to bits[9:0] of mdio data register.
149 */
150#define AR9331_SW_ADDR_PAGE GENMASK(18, 9)
151
152/* ------------------------------------------------------------------------
153 * Normal register access mode
154 * ------------------------------------------------------------------------
155 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 |
156 * real | start | OP | PhyAddr | Reg Addr | TA |
157 * atheros| start | OP | 2'b10 | low_addr[7:0] | TA |
158 *
159 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 |
160 * real | Data |
161 * atheros| Data |
162 * ------------------------------------------------------------------------
163 */
164#define AR9331_SW_LOW_ADDR_PHY GENMASK(8, 6)
165#define AR9331_SW_LOW_ADDR_REG GENMASK(5, 1)
166
167#define AR9331_SW_MDIO_PHY_MODE_M GENMASK(4, 3)
168#define AR9331_SW_MDIO_PHY_MODE_PAGE 3
169#define AR9331_SW_MDIO_PHY_MODE_REG 2
170#define AR9331_SW_MDIO_PHY_MODE_BYPASS 0
171#define AR9331_SW_MDIO_PHY_ADDR_M GENMASK(2, 0)
172
173/* Empirical determined values */
174#define AR9331_SW_MDIO_POLL_SLEEP_US 1
175#define AR9331_SW_MDIO_POLL_TIMEOUT_US 20
176
177/* The interval should be small enough to avoid overflow of 32bit MIBs */
178/*
179 * FIXME: until we can read MIBs from stats64 call directly (i.e. sleep
180 * there), we have to poll stats more frequently then it is actually needed.
181 * For overflow protection, normally, 100 sec interval should have been OK.
182 */
183#define STATS_INTERVAL_JIFFIES (3 * HZ)
184
185struct ar9331_sw_stats_raw {
186 u32 rxbroad; /* 0x00 */
187 u32 rxpause; /* 0x04 */
188 u32 rxmulti; /* 0x08 */
189 u32 rxfcserr; /* 0x0c */
190 u32 rxalignerr; /* 0x10 */
191 u32 rxrunt; /* 0x14 */
192 u32 rxfragment; /* 0x18 */
193 u32 rx64byte; /* 0x1c */
194 u32 rx128byte; /* 0x20 */
195 u32 rx256byte; /* 0x24 */
196 u32 rx512byte; /* 0x28 */
197 u32 rx1024byte; /* 0x2c */
198 u32 rx1518byte; /* 0x30 */
199 u32 rxmaxbyte; /* 0x34 */
200 u32 rxtoolong; /* 0x38 */
201 u32 rxgoodbyte; /* 0x3c */
202 u32 rxgoodbyte_hi;
203 u32 rxbadbyte; /* 0x44 */
204 u32 rxbadbyte_hi;
205 u32 rxoverflow; /* 0x4c */
206 u32 filtered; /* 0x50 */
207 u32 txbroad; /* 0x54 */
208 u32 txpause; /* 0x58 */
209 u32 txmulti; /* 0x5c */
210 u32 txunderrun; /* 0x60 */
211 u32 tx64byte; /* 0x64 */
212 u32 tx128byte; /* 0x68 */
213 u32 tx256byte; /* 0x6c */
214 u32 tx512byte; /* 0x70 */
215 u32 tx1024byte; /* 0x74 */
216 u32 tx1518byte; /* 0x78 */
217 u32 txmaxbyte; /* 0x7c */
218 u32 txoversize; /* 0x80 */
219 u32 txbyte; /* 0x84 */
220 u32 txbyte_hi;
221 u32 txcollision; /* 0x8c */
222 u32 txabortcol; /* 0x90 */
223 u32 txmulticol; /* 0x94 */
224 u32 txsinglecol; /* 0x98 */
225 u32 txexcdefer; /* 0x9c */
226 u32 txdefer; /* 0xa0 */
227 u32 txlatecol; /* 0xa4 */
228};
229
230struct ar9331_sw_port {
231 int idx;
232 struct delayed_work mib_read;
233 struct rtnl_link_stats64 stats;
234 struct ethtool_pause_stats pause_stats;
235 struct spinlock stats_lock;
236};
237
238struct ar9331_sw_priv {
239 struct device *dev;
240 struct dsa_switch ds;
241 struct dsa_switch_ops ops;
242 struct irq_domain *irqdomain;
243 u32 irq_mask;
244 struct mutex lock_irq;
245 struct mii_bus *mbus; /* mdio master */
246 struct mii_bus *sbus; /* mdio slave */
247 struct regmap *regmap;
248 struct reset_control *sw_reset;
249 struct ar9331_sw_port port[AR9331_SW_PORTS];
250};
251
252static struct ar9331_sw_priv *ar9331_sw_port_to_priv(struct ar9331_sw_port *port)
253{
254 struct ar9331_sw_port *p = port - port->idx;
255
256 return (struct ar9331_sw_priv *)((void *)p -
257 offsetof(struct ar9331_sw_priv, port));
258}
259
260/* Warning: switch reset will reset last AR9331_SW_MDIO_PHY_MODE_PAGE request
261 * If some kind of optimization is used, the request should be repeated.
262 */
263static int ar9331_sw_reset(struct ar9331_sw_priv *priv)
264{
265 int ret;
266
267 ret = reset_control_assert(priv->sw_reset);
268 if (ret)
269 goto error;
270
271 /* AR9331 doc do not provide any information about proper reset
272 * sequence. The AR8136 (the closes switch to the AR9331) doc says:
273 * reset duration should be greater than 10ms. So, let's use this value
274 * for now.
275 */
276 usleep_range(10000, 15000);
277 ret = reset_control_deassert(priv->sw_reset);
278 if (ret)
279 goto error;
280 /* There is no information on how long should we wait after reset.
281 * AR8136 has an EEPROM and there is an Interrupt for EEPROM load
282 * status. AR9331 has no EEPROM support.
283 * For now, do not wait. In case AR8136 will be needed, the after
284 * reset delay can be added as well.
285 */
286
287 return 0;
288error:
289 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
290 return ret;
291}
292
293static int ar9331_sw_mbus_write(struct mii_bus *mbus, int port, int regnum,
294 u16 data)
295{
296 struct ar9331_sw_priv *priv = mbus->priv;
297 struct regmap *regmap = priv->regmap;
298 u32 val;
299 int ret;
300
301 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL,
302 AR9331_SW_MDIO_CTRL_BUSY |
303 AR9331_SW_MDIO_CTRL_MASTER_EN |
304 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
305 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum) |
306 FIELD_PREP(AR9331_SW_MDIO_CTRL_DATA_M, data));
307 if (ret)
308 goto error;
309
310 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val,
311 !(val & AR9331_SW_MDIO_CTRL_BUSY),
312 AR9331_SW_MDIO_POLL_SLEEP_US,
313 AR9331_SW_MDIO_POLL_TIMEOUT_US);
314 if (ret)
315 goto error;
316
317 return 0;
318error:
319 dev_err_ratelimited(priv->dev, "PHY write error: %i\n", ret);
320 return ret;
321}
322
323static int ar9331_sw_mbus_read(struct mii_bus *mbus, int port, int regnum)
324{
325 struct ar9331_sw_priv *priv = mbus->priv;
326 struct regmap *regmap = priv->regmap;
327 u32 val;
328 int ret;
329
330 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL,
331 AR9331_SW_MDIO_CTRL_BUSY |
332 AR9331_SW_MDIO_CTRL_MASTER_EN |
333 AR9331_SW_MDIO_CTRL_CMD_READ |
334 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
335 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum));
336 if (ret)
337 goto error;
338
339 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val,
340 !(val & AR9331_SW_MDIO_CTRL_BUSY),
341 AR9331_SW_MDIO_POLL_SLEEP_US,
342 AR9331_SW_MDIO_POLL_TIMEOUT_US);
343 if (ret)
344 goto error;
345
346 ret = regmap_read(regmap, AR9331_SW_REG_MDIO_CTRL, &val);
347 if (ret)
348 goto error;
349
350 return FIELD_GET(AR9331_SW_MDIO_CTRL_DATA_M, val);
351
352error:
353 dev_err_ratelimited(priv->dev, "PHY read error: %i\n", ret);
354 return ret;
355}
356
357static int ar9331_sw_mbus_init(struct ar9331_sw_priv *priv)
358{
359 struct device *dev = priv->dev;
360 struct mii_bus *mbus;
361 struct device_node *np, *mnp;
362 int ret;
363
364 np = dev->of_node;
365
366 mbus = devm_mdiobus_alloc(dev);
367 if (!mbus)
368 return -ENOMEM;
369
370 mbus->name = np->full_name;
371 snprintf(mbus->id, MII_BUS_ID_SIZE, "%pOF", np);
372
373 mbus->read = ar9331_sw_mbus_read;
374 mbus->write = ar9331_sw_mbus_write;
375 mbus->priv = priv;
376 mbus->parent = dev;
377
378 mnp = of_get_child_by_name(np, "mdio");
379 if (!mnp)
380 return -ENODEV;
381
382 ret = devm_of_mdiobus_register(dev, mbus, mnp);
383 of_node_put(mnp);
384 if (ret)
385 return ret;
386
387 priv->mbus = mbus;
388
389 return 0;
390}
391
392static int ar9331_sw_setup_port(struct dsa_switch *ds, int port)
393{
394 struct ar9331_sw_priv *priv = ds->priv;
395 struct regmap *regmap = priv->regmap;
396 u32 port_mask, port_ctrl, val;
397 int ret;
398
399 /* Generate default port settings */
400 port_ctrl = FIELD_PREP(AR9331_SW_PORT_CTRL_PORT_STATE,
401 AR9331_SW_PORT_CTRL_PORT_STATE_FORWARD);
402
403 if (dsa_is_cpu_port(ds, port)) {
404 /* CPU port should be allowed to communicate with all user
405 * ports.
406 */
407 port_mask = dsa_user_ports(ds);
408 /* Enable Atheros header on CPU port. This will allow us
409 * communicate with each port separately
410 */
411 port_ctrl |= AR9331_SW_PORT_CTRL_HEAD_EN;
412 } else if (dsa_is_user_port(ds, port)) {
413 /* User ports should communicate only with the CPU port.
414 */
415 port_mask = BIT(dsa_upstream_port(ds, port));
416 } else {
417 /* Other ports do not need to communicate at all */
418 port_mask = 0;
419 }
420
421 val = FIELD_PREP(AR9331_SW_PORT_VLAN_8021Q_MODE,
422 AR9331_SW_8021Q_MODE_NONE) |
423 FIELD_PREP(AR9331_SW_PORT_VLAN_PORT_VID_MEMBER, port_mask);
424
425 ret = regmap_write(regmap, AR9331_SW_REG_PORT_VLAN(port), val);
426 if (ret)
427 goto error;
428
429 ret = regmap_write(regmap, AR9331_SW_REG_PORT_CTRL(port), port_ctrl);
430 if (ret)
431 goto error;
432
433 return 0;
434error:
435 dev_err(priv->dev, "%s: error: %i\n", __func__, ret);
436
437 return ret;
438}
439
440static int ar9331_sw_setup(struct dsa_switch *ds)
441{
442 struct ar9331_sw_priv *priv = ds->priv;
443 struct regmap *regmap = priv->regmap;
444 int ret, i;
445
446 ret = ar9331_sw_reset(priv);
447 if (ret)
448 return ret;
449
450 /* Reset will set proper defaults. CPU - Port0 will be enabled and
451 * configured. All other ports (ports 1 - 5) are disabled
452 */
453 ret = ar9331_sw_mbus_init(priv);
454 if (ret)
455 return ret;
456
457 /* Do not drop broadcast frames */
458 ret = regmap_write_bits(regmap, AR9331_SW_REG_FLOOD_MASK,
459 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU,
460 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU);
461 if (ret)
462 goto error;
463
464 /* Set max frame size to the maximum supported value */
465 ret = regmap_write_bits(regmap, AR9331_SW_REG_GLOBAL_CTRL,
466 AR9331_SW_GLOBAL_CTRL_MFS_M,
467 AR9331_SW_GLOBAL_CTRL_MFS_M);
468 if (ret)
469 goto error;
470
471 for (i = 0; i < ds->num_ports; i++) {
472 ret = ar9331_sw_setup_port(ds, i);
473 if (ret)
474 goto error;
475 }
476
477 ds->configure_vlan_while_not_filtering = false;
478
479 return 0;
480error:
481 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
482 return ret;
483}
484
485static void ar9331_sw_port_disable(struct dsa_switch *ds, int port)
486{
487 struct ar9331_sw_priv *priv = ds->priv;
488 struct regmap *regmap = priv->regmap;
489 int ret;
490
491 ret = regmap_write(regmap, AR9331_SW_REG_PORT_STATUS(port), 0);
492 if (ret)
493 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
494}
495
496static enum dsa_tag_protocol ar9331_sw_get_tag_protocol(struct dsa_switch *ds,
497 int port,
498 enum dsa_tag_protocol m)
499{
500 return DSA_TAG_PROTO_AR9331;
501}
502
503static void ar9331_sw_phylink_get_caps(struct dsa_switch *ds, int port,
504 struct phylink_config *config)
505{
506 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
507 MAC_10 | MAC_100;
508
509 switch (port) {
510 case 0:
511 __set_bit(PHY_INTERFACE_MODE_GMII,
512 config->supported_interfaces);
513 config->mac_capabilities |= MAC_1000;
514 break;
515 case 1:
516 case 2:
517 case 3:
518 case 4:
519 case 5:
520 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
521 config->supported_interfaces);
522 break;
523 }
524}
525
526static void ar9331_sw_phylink_mac_config(struct dsa_switch *ds, int port,
527 unsigned int mode,
528 const struct phylink_link_state *state)
529{
530 struct ar9331_sw_priv *priv = ds->priv;
531 struct regmap *regmap = priv->regmap;
532 int ret;
533
534 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
535 AR9331_SW_PORT_STATUS_LINK_EN |
536 AR9331_SW_PORT_STATUS_FLOW_LINK_EN, 0);
537 if (ret)
538 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
539}
540
541static void ar9331_sw_phylink_mac_link_down(struct dsa_switch *ds, int port,
542 unsigned int mode,
543 phy_interface_t interface)
544{
545 struct ar9331_sw_priv *priv = ds->priv;
546 struct ar9331_sw_port *p = &priv->port[port];
547 struct regmap *regmap = priv->regmap;
548 int ret;
549
550 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
551 AR9331_SW_PORT_STATUS_MAC_MASK, 0);
552 if (ret)
553 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
554
555 cancel_delayed_work_sync(&p->mib_read);
556}
557
558static void ar9331_sw_phylink_mac_link_up(struct dsa_switch *ds, int port,
559 unsigned int mode,
560 phy_interface_t interface,
561 struct phy_device *phydev,
562 int speed, int duplex,
563 bool tx_pause, bool rx_pause)
564{
565 struct ar9331_sw_priv *priv = ds->priv;
566 struct ar9331_sw_port *p = &priv->port[port];
567 struct regmap *regmap = priv->regmap;
568 u32 val;
569 int ret;
570
571 schedule_delayed_work(&p->mib_read, 0);
572
573 val = AR9331_SW_PORT_STATUS_MAC_MASK;
574 switch (speed) {
575 case SPEED_1000:
576 val |= AR9331_SW_PORT_STATUS_SPEED_1000;
577 break;
578 case SPEED_100:
579 val |= AR9331_SW_PORT_STATUS_SPEED_100;
580 break;
581 case SPEED_10:
582 val |= AR9331_SW_PORT_STATUS_SPEED_10;
583 break;
584 default:
585 return;
586 }
587
588 if (duplex)
589 val |= AR9331_SW_PORT_STATUS_DUPLEX_MODE;
590
591 if (tx_pause)
592 val |= AR9331_SW_PORT_STATUS_TX_FLOW_EN;
593
594 if (rx_pause)
595 val |= AR9331_SW_PORT_STATUS_RX_FLOW_EN;
596
597 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
598 AR9331_SW_PORT_STATUS_MAC_MASK |
599 AR9331_SW_PORT_STATUS_LINK_MASK,
600 val);
601 if (ret)
602 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
603}
604
605static void ar9331_read_stats(struct ar9331_sw_port *port)
606{
607 struct ar9331_sw_priv *priv = ar9331_sw_port_to_priv(port);
608 struct ethtool_pause_stats *pstats = &port->pause_stats;
609 struct rtnl_link_stats64 *stats = &port->stats;
610 struct ar9331_sw_stats_raw raw;
611 int ret;
612
613 /* Do the slowest part first, to avoid needless locking for long time */
614 ret = regmap_bulk_read(priv->regmap, AR9331_MIB_COUNTER(port->idx),
615 &raw, sizeof(raw) / sizeof(u32));
616 if (ret) {
617 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
618 return;
619 }
620 /* All MIB counters are cleared automatically on read */
621
622 spin_lock(&port->stats_lock);
623
624 stats->rx_bytes += raw.rxgoodbyte;
625 stats->tx_bytes += raw.txbyte;
626
627 stats->rx_packets += raw.rx64byte + raw.rx128byte + raw.rx256byte +
628 raw.rx512byte + raw.rx1024byte + raw.rx1518byte + raw.rxmaxbyte;
629 stats->tx_packets += raw.tx64byte + raw.tx128byte + raw.tx256byte +
630 raw.tx512byte + raw.tx1024byte + raw.tx1518byte + raw.txmaxbyte;
631
632 stats->rx_length_errors += raw.rxrunt + raw.rxfragment + raw.rxtoolong;
633 stats->rx_crc_errors += raw.rxfcserr;
634 stats->rx_frame_errors += raw.rxalignerr;
635 stats->rx_missed_errors += raw.rxoverflow;
636 stats->rx_dropped += raw.filtered;
637 stats->rx_errors += raw.rxfcserr + raw.rxalignerr + raw.rxrunt +
638 raw.rxfragment + raw.rxoverflow + raw.rxtoolong;
639
640 stats->tx_window_errors += raw.txlatecol;
641 stats->tx_fifo_errors += raw.txunderrun;
642 stats->tx_aborted_errors += raw.txabortcol;
643 stats->tx_errors += raw.txoversize + raw.txabortcol + raw.txunderrun +
644 raw.txlatecol;
645
646 stats->multicast += raw.rxmulti;
647 stats->collisions += raw.txcollision;
648
649 pstats->tx_pause_frames += raw.txpause;
650 pstats->rx_pause_frames += raw.rxpause;
651
652 spin_unlock(&port->stats_lock);
653}
654
655static void ar9331_do_stats_poll(struct work_struct *work)
656{
657 struct ar9331_sw_port *port = container_of(work, struct ar9331_sw_port,
658 mib_read.work);
659
660 ar9331_read_stats(port);
661
662 schedule_delayed_work(&port->mib_read, STATS_INTERVAL_JIFFIES);
663}
664
665static void ar9331_get_stats64(struct dsa_switch *ds, int port,
666 struct rtnl_link_stats64 *s)
667{
668 struct ar9331_sw_priv *priv = ds->priv;
669 struct ar9331_sw_port *p = &priv->port[port];
670
671 spin_lock(&p->stats_lock);
672 memcpy(s, &p->stats, sizeof(*s));
673 spin_unlock(&p->stats_lock);
674}
675
676static void ar9331_get_pause_stats(struct dsa_switch *ds, int port,
677 struct ethtool_pause_stats *pause_stats)
678{
679 struct ar9331_sw_priv *priv = ds->priv;
680 struct ar9331_sw_port *p = &priv->port[port];
681
682 spin_lock(&p->stats_lock);
683 memcpy(pause_stats, &p->pause_stats, sizeof(*pause_stats));
684 spin_unlock(&p->stats_lock);
685}
686
687static const struct dsa_switch_ops ar9331_sw_ops = {
688 .get_tag_protocol = ar9331_sw_get_tag_protocol,
689 .setup = ar9331_sw_setup,
690 .port_disable = ar9331_sw_port_disable,
691 .phylink_get_caps = ar9331_sw_phylink_get_caps,
692 .phylink_mac_config = ar9331_sw_phylink_mac_config,
693 .phylink_mac_link_down = ar9331_sw_phylink_mac_link_down,
694 .phylink_mac_link_up = ar9331_sw_phylink_mac_link_up,
695 .get_stats64 = ar9331_get_stats64,
696 .get_pause_stats = ar9331_get_pause_stats,
697};
698
699static irqreturn_t ar9331_sw_irq(int irq, void *data)
700{
701 struct ar9331_sw_priv *priv = data;
702 struct regmap *regmap = priv->regmap;
703 u32 stat;
704 int ret;
705
706 ret = regmap_read(regmap, AR9331_SW_REG_GINT, &stat);
707 if (ret) {
708 dev_err(priv->dev, "can't read interrupt status\n");
709 return IRQ_NONE;
710 }
711
712 if (!stat)
713 return IRQ_NONE;
714
715 if (stat & AR9331_SW_GINT_PHY_INT) {
716 int child_irq;
717
718 child_irq = irq_find_mapping(priv->irqdomain, 0);
719 handle_nested_irq(child_irq);
720 }
721
722 ret = regmap_write(regmap, AR9331_SW_REG_GINT, stat);
723 if (ret) {
724 dev_err(priv->dev, "can't write interrupt status\n");
725 return IRQ_NONE;
726 }
727
728 return IRQ_HANDLED;
729}
730
731static void ar9331_sw_mask_irq(struct irq_data *d)
732{
733 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
734
735 priv->irq_mask = 0;
736}
737
738static void ar9331_sw_unmask_irq(struct irq_data *d)
739{
740 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
741
742 priv->irq_mask = AR9331_SW_GINT_PHY_INT;
743}
744
745static void ar9331_sw_irq_bus_lock(struct irq_data *d)
746{
747 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
748
749 mutex_lock(&priv->lock_irq);
750}
751
752static void ar9331_sw_irq_bus_sync_unlock(struct irq_data *d)
753{
754 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
755 struct regmap *regmap = priv->regmap;
756 int ret;
757
758 ret = regmap_update_bits(regmap, AR9331_SW_REG_GINT_MASK,
759 AR9331_SW_GINT_PHY_INT, priv->irq_mask);
760 if (ret)
761 dev_err(priv->dev, "failed to change IRQ mask\n");
762
763 mutex_unlock(&priv->lock_irq);
764}
765
766static struct irq_chip ar9331_sw_irq_chip = {
767 .name = AR9331_SW_NAME,
768 .irq_mask = ar9331_sw_mask_irq,
769 .irq_unmask = ar9331_sw_unmask_irq,
770 .irq_bus_lock = ar9331_sw_irq_bus_lock,
771 .irq_bus_sync_unlock = ar9331_sw_irq_bus_sync_unlock,
772};
773
774static int ar9331_sw_irq_map(struct irq_domain *domain, unsigned int irq,
775 irq_hw_number_t hwirq)
776{
777 irq_set_chip_data(irq, domain->host_data);
778 irq_set_chip_and_handler(irq, &ar9331_sw_irq_chip, handle_simple_irq);
779 irq_set_nested_thread(irq, 1);
780 irq_set_noprobe(irq);
781
782 return 0;
783}
784
785static void ar9331_sw_irq_unmap(struct irq_domain *d, unsigned int irq)
786{
787 irq_set_nested_thread(irq, 0);
788 irq_set_chip_and_handler(irq, NULL, NULL);
789 irq_set_chip_data(irq, NULL);
790}
791
792static const struct irq_domain_ops ar9331_sw_irqdomain_ops = {
793 .map = ar9331_sw_irq_map,
794 .unmap = ar9331_sw_irq_unmap,
795 .xlate = irq_domain_xlate_onecell,
796};
797
798static int ar9331_sw_irq_init(struct ar9331_sw_priv *priv)
799{
800 struct device_node *np = priv->dev->of_node;
801 struct device *dev = priv->dev;
802 int ret, irq;
803
804 irq = of_irq_get(np, 0);
805 if (irq <= 0) {
806 dev_err(dev, "failed to get parent IRQ\n");
807 return irq ? irq : -EINVAL;
808 }
809
810 mutex_init(&priv->lock_irq);
811 ret = devm_request_threaded_irq(dev, irq, NULL, ar9331_sw_irq,
812 IRQF_ONESHOT, AR9331_SW_NAME, priv);
813 if (ret) {
814 dev_err(dev, "unable to request irq: %d\n", ret);
815 return ret;
816 }
817
818 priv->irqdomain = irq_domain_add_linear(np, 1, &ar9331_sw_irqdomain_ops,
819 priv);
820 if (!priv->irqdomain) {
821 dev_err(dev, "failed to create IRQ domain\n");
822 return -EINVAL;
823 }
824
825 irq_set_parent(irq_create_mapping(priv->irqdomain, 0), irq);
826
827 return 0;
828}
829
830static int __ar9331_mdio_write(struct mii_bus *sbus, u8 mode, u16 reg, u16 val)
831{
832 u8 r, p;
833
834 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, mode) |
835 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg);
836 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg);
837
838 return __mdiobus_write(sbus, p, r, val);
839}
840
841static int __ar9331_mdio_read(struct mii_bus *sbus, u16 reg)
842{
843 u8 r, p;
844
845 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, AR9331_SW_MDIO_PHY_MODE_REG) |
846 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg);
847 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg);
848
849 return __mdiobus_read(sbus, p, r);
850}
851
852static int ar9331_mdio_read(void *ctx, const void *reg_buf, size_t reg_len,
853 void *val_buf, size_t val_len)
854{
855 struct ar9331_sw_priv *priv = ctx;
856 struct mii_bus *sbus = priv->sbus;
857 u32 reg = *(u32 *)reg_buf;
858 int ret;
859
860 if (reg == AR9331_SW_REG_PAGE) {
861 /* We cannot read the page selector register from hardware and
862 * we cache its value in regmap. Return all bits set here,
863 * that regmap will always write the page on first use.
864 */
865 *(u32 *)val_buf = GENMASK(9, 0);
866 return 0;
867 }
868
869 mutex_lock_nested(&sbus->mdio_lock, MDIO_MUTEX_NESTED);
870
871 ret = __ar9331_mdio_read(sbus, reg);
872 if (ret < 0)
873 goto error;
874
875 *(u32 *)val_buf = ret;
876 ret = __ar9331_mdio_read(sbus, reg + 2);
877 if (ret < 0)
878 goto error;
879
880 *(u32 *)val_buf |= ret << 16;
881
882 mutex_unlock(&sbus->mdio_lock);
883
884 return 0;
885error:
886 mutex_unlock(&sbus->mdio_lock);
887 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to read register.\n");
888
889 return ret;
890}
891
892static int ar9331_mdio_write(void *ctx, u32 reg, u32 val)
893{
894 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ctx;
895 struct mii_bus *sbus = priv->sbus;
896 int ret;
897
898 mutex_lock_nested(&sbus->mdio_lock, MDIO_MUTEX_NESTED);
899 if (reg == AR9331_SW_REG_PAGE) {
900 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_PAGE,
901 0, val);
902 if (ret < 0)
903 goto error;
904
905 mutex_unlock(&sbus->mdio_lock);
906
907 return 0;
908 }
909
910 /* In case of this switch we work with 32bit registers on top of 16bit
911 * bus. Some registers (for example access to forwarding database) have
912 * trigger bit on the first 16bit half of request, the result and
913 * configuration of request in the second half.
914 * To make it work properly, we should do the second part of transfer
915 * before the first one is done.
916 */
917 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg + 2,
918 val >> 16);
919 if (ret < 0)
920 goto error;
921
922 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg, val);
923 if (ret < 0)
924 goto error;
925
926 mutex_unlock(&sbus->mdio_lock);
927
928 return 0;
929
930error:
931 mutex_unlock(&sbus->mdio_lock);
932 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to write register.\n");
933
934 return ret;
935}
936
937static int ar9331_sw_bus_write(void *context, const void *data, size_t count)
938{
939 u32 reg = *(u32 *)data;
940 u32 val = *((u32 *)data + 1);
941
942 return ar9331_mdio_write(context, reg, val);
943}
944
945static const struct regmap_range ar9331_valid_regs[] = {
946 regmap_reg_range(0x0, 0x0),
947 regmap_reg_range(0x10, 0x14),
948 regmap_reg_range(0x20, 0x24),
949 regmap_reg_range(0x2c, 0x30),
950 regmap_reg_range(0x40, 0x44),
951 regmap_reg_range(0x50, 0x78),
952 regmap_reg_range(0x80, 0x98),
953
954 regmap_reg_range(0x100, 0x120),
955 regmap_reg_range(0x200, 0x220),
956 regmap_reg_range(0x300, 0x320),
957 regmap_reg_range(0x400, 0x420),
958 regmap_reg_range(0x500, 0x520),
959 regmap_reg_range(0x600, 0x620),
960
961 regmap_reg_range(0x20000, 0x200a4),
962 regmap_reg_range(0x20100, 0x201a4),
963 regmap_reg_range(0x20200, 0x202a4),
964 regmap_reg_range(0x20300, 0x203a4),
965 regmap_reg_range(0x20400, 0x204a4),
966 regmap_reg_range(0x20500, 0x205a4),
967
968 /* dummy page selector reg */
969 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE),
970};
971
972static const struct regmap_range ar9331_nonvolatile_regs[] = {
973 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE),
974};
975
976static const struct regmap_range_cfg ar9331_regmap_range[] = {
977 {
978 .selector_reg = AR9331_SW_REG_PAGE,
979 .selector_mask = GENMASK(9, 0),
980 .selector_shift = 0,
981
982 .window_start = 0,
983 .window_len = 512,
984
985 .range_min = 0,
986 .range_max = AR9331_SW_REG_PAGE - 4,
987 },
988};
989
990static const struct regmap_access_table ar9331_register_set = {
991 .yes_ranges = ar9331_valid_regs,
992 .n_yes_ranges = ARRAY_SIZE(ar9331_valid_regs),
993};
994
995static const struct regmap_access_table ar9331_volatile_set = {
996 .no_ranges = ar9331_nonvolatile_regs,
997 .n_no_ranges = ARRAY_SIZE(ar9331_nonvolatile_regs),
998};
999
1000static const struct regmap_config ar9331_mdio_regmap_config = {
1001 .reg_bits = 32,
1002 .val_bits = 32,
1003 .reg_stride = 4,
1004 .max_register = AR9331_SW_REG_PAGE,
1005 .use_single_read = true,
1006 .use_single_write = true,
1007
1008 .ranges = ar9331_regmap_range,
1009 .num_ranges = ARRAY_SIZE(ar9331_regmap_range),
1010
1011 .volatile_table = &ar9331_volatile_set,
1012 .wr_table = &ar9331_register_set,
1013 .rd_table = &ar9331_register_set,
1014
1015 .cache_type = REGCACHE_MAPLE,
1016};
1017
1018static struct regmap_bus ar9331_sw_bus = {
1019 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
1020 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
1021 .read = ar9331_mdio_read,
1022 .write = ar9331_sw_bus_write,
1023};
1024
1025static int ar9331_sw_probe(struct mdio_device *mdiodev)
1026{
1027 struct ar9331_sw_priv *priv;
1028 struct dsa_switch *ds;
1029 int ret, i;
1030
1031 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1032 if (!priv)
1033 return -ENOMEM;
1034
1035 priv->regmap = devm_regmap_init(&mdiodev->dev, &ar9331_sw_bus, priv,
1036 &ar9331_mdio_regmap_config);
1037 if (IS_ERR(priv->regmap)) {
1038 ret = PTR_ERR(priv->regmap);
1039 dev_err(&mdiodev->dev, "regmap init failed: %d\n", ret);
1040 return ret;
1041 }
1042
1043 priv->sw_reset = devm_reset_control_get(&mdiodev->dev, "switch");
1044 if (IS_ERR(priv->sw_reset)) {
1045 dev_err(&mdiodev->dev, "missing switch reset\n");
1046 return PTR_ERR(priv->sw_reset);
1047 }
1048
1049 priv->sbus = mdiodev->bus;
1050 priv->dev = &mdiodev->dev;
1051
1052 ret = ar9331_sw_irq_init(priv);
1053 if (ret)
1054 return ret;
1055
1056 ds = &priv->ds;
1057 ds->dev = &mdiodev->dev;
1058 ds->num_ports = AR9331_SW_PORTS;
1059 ds->priv = priv;
1060 priv->ops = ar9331_sw_ops;
1061 ds->ops = &priv->ops;
1062 dev_set_drvdata(&mdiodev->dev, priv);
1063
1064 for (i = 0; i < ARRAY_SIZE(priv->port); i++) {
1065 struct ar9331_sw_port *port = &priv->port[i];
1066
1067 port->idx = i;
1068 spin_lock_init(&port->stats_lock);
1069 INIT_DELAYED_WORK(&port->mib_read, ar9331_do_stats_poll);
1070 }
1071
1072 ret = dsa_register_switch(ds);
1073 if (ret)
1074 goto err_remove_irq;
1075
1076 return 0;
1077
1078err_remove_irq:
1079 irq_domain_remove(priv->irqdomain);
1080
1081 return ret;
1082}
1083
1084static void ar9331_sw_remove(struct mdio_device *mdiodev)
1085{
1086 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev);
1087 unsigned int i;
1088
1089 if (!priv)
1090 return;
1091
1092 for (i = 0; i < ARRAY_SIZE(priv->port); i++) {
1093 struct ar9331_sw_port *port = &priv->port[i];
1094
1095 cancel_delayed_work_sync(&port->mib_read);
1096 }
1097
1098 irq_domain_remove(priv->irqdomain);
1099 dsa_unregister_switch(&priv->ds);
1100
1101 reset_control_assert(priv->sw_reset);
1102}
1103
1104static void ar9331_sw_shutdown(struct mdio_device *mdiodev)
1105{
1106 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev);
1107
1108 if (!priv)
1109 return;
1110
1111 dsa_switch_shutdown(&priv->ds);
1112
1113 dev_set_drvdata(&mdiodev->dev, NULL);
1114}
1115
1116static const struct of_device_id ar9331_sw_of_match[] = {
1117 { .compatible = "qca,ar9331-switch" },
1118 { },
1119};
1120
1121static struct mdio_driver ar9331_sw_mdio_driver = {
1122 .probe = ar9331_sw_probe,
1123 .remove = ar9331_sw_remove,
1124 .shutdown = ar9331_sw_shutdown,
1125 .mdiodrv.driver = {
1126 .name = AR9331_SW_NAME,
1127 .of_match_table = ar9331_sw_of_match,
1128 },
1129};
1130
1131mdio_module_driver(ar9331_sw_mdio_driver);
1132
1133MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
1134MODULE_DESCRIPTION("Driver for Atheros AR9331 switch");
1135MODULE_LICENSE("GPL v2");