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1/*
2 * SH7091/SH7750/SH7750S/SH7750R/SH7751/SH7751R Setup
3 *
4 * Copyright (C) 2006 Paul Mundt
5 * Copyright (C) 2006 Jamie Lenehan
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/serial.h>
14#include <linux/io.h>
15#include <linux/sh_timer.h>
16#include <linux/sh_intc.h>
17#include <linux/serial_sci.h>
18#include <generated/machtypes.h>
19
20static struct resource rtc_resources[] = {
21 [0] = {
22 .start = 0xffc80000,
23 .end = 0xffc80000 + 0x58 - 1,
24 .flags = IORESOURCE_IO,
25 },
26 [1] = {
27 /* Shared Period/Carry/Alarm IRQ */
28 .start = evt2irq(0x480),
29 .flags = IORESOURCE_IRQ,
30 },
31};
32
33static struct platform_device rtc_device = {
34 .name = "sh-rtc",
35 .id = -1,
36 .num_resources = ARRAY_SIZE(rtc_resources),
37 .resource = rtc_resources,
38};
39
40static struct plat_sci_port sci_platform_data = {
41 .port_reg = 0xffe0001C,
42 .flags = UPF_BOOT_AUTOCONF,
43 .scscr = SCSCR_TE | SCSCR_RE,
44 .type = PORT_SCI,
45 .regshift = 2,
46};
47
48static struct resource sci_resources[] = {
49 DEFINE_RES_MEM(0xffe00000, 0x100),
50 DEFINE_RES_IRQ(evt2irq(0x4e0)),
51};
52
53static struct platform_device sci_device = {
54 .name = "sh-sci",
55 .id = 0,
56 .resource = sci_resources,
57 .num_resources = ARRAY_SIZE(sci_resources),
58 .dev = {
59 .platform_data = &sci_platform_data,
60 },
61};
62
63static struct plat_sci_port scif_platform_data = {
64 .flags = UPF_BOOT_AUTOCONF,
65 .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE,
66 .type = PORT_SCIF,
67};
68
69static struct resource scif_resources[] = {
70 DEFINE_RES_MEM(0xffe80000, 0x100),
71 DEFINE_RES_IRQ(evt2irq(0x700)),
72};
73
74static struct platform_device scif_device = {
75 .name = "sh-sci",
76 .id = 1,
77 .resource = scif_resources,
78 .num_resources = ARRAY_SIZE(scif_resources),
79 .dev = {
80 .platform_data = &scif_platform_data,
81 },
82};
83
84static struct sh_timer_config tmu0_platform_data = {
85 .channel_offset = 0x04,
86 .timer_bit = 0,
87 .clockevent_rating = 200,
88};
89
90static struct resource tmu0_resources[] = {
91 [0] = {
92 .start = 0xffd80008,
93 .end = 0xffd80013,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = evt2irq(0x400),
98 .flags = IORESOURCE_IRQ,
99 },
100};
101
102static struct platform_device tmu0_device = {
103 .name = "sh_tmu",
104 .id = 0,
105 .dev = {
106 .platform_data = &tmu0_platform_data,
107 },
108 .resource = tmu0_resources,
109 .num_resources = ARRAY_SIZE(tmu0_resources),
110};
111
112static struct sh_timer_config tmu1_platform_data = {
113 .channel_offset = 0x10,
114 .timer_bit = 1,
115 .clocksource_rating = 200,
116};
117
118static struct resource tmu1_resources[] = {
119 [0] = {
120 .start = 0xffd80014,
121 .end = 0xffd8001f,
122 .flags = IORESOURCE_MEM,
123 },
124 [1] = {
125 .start = evt2irq(0x420),
126 .flags = IORESOURCE_IRQ,
127 },
128};
129
130static struct platform_device tmu1_device = {
131 .name = "sh_tmu",
132 .id = 1,
133 .dev = {
134 .platform_data = &tmu1_platform_data,
135 },
136 .resource = tmu1_resources,
137 .num_resources = ARRAY_SIZE(tmu1_resources),
138};
139
140static struct sh_timer_config tmu2_platform_data = {
141 .channel_offset = 0x1c,
142 .timer_bit = 2,
143};
144
145static struct resource tmu2_resources[] = {
146 [0] = {
147 .start = 0xffd80020,
148 .end = 0xffd8002f,
149 .flags = IORESOURCE_MEM,
150 },
151 [1] = {
152 .start = evt2irq(0x440),
153 .flags = IORESOURCE_IRQ,
154 },
155};
156
157static struct platform_device tmu2_device = {
158 .name = "sh_tmu",
159 .id = 2,
160 .dev = {
161 .platform_data = &tmu2_platform_data,
162 },
163 .resource = tmu2_resources,
164 .num_resources = ARRAY_SIZE(tmu2_resources),
165};
166
167/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
168#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
169 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
170 defined(CONFIG_CPU_SUBTYPE_SH7751R)
171
172static struct sh_timer_config tmu3_platform_data = {
173 .channel_offset = 0x04,
174 .timer_bit = 0,
175};
176
177static struct resource tmu3_resources[] = {
178 [0] = {
179 .start = 0xfe100008,
180 .end = 0xfe100013,
181 .flags = IORESOURCE_MEM,
182 },
183 [1] = {
184 .start = evt2irq(0xb00),
185 .flags = IORESOURCE_IRQ,
186 },
187};
188
189static struct platform_device tmu3_device = {
190 .name = "sh_tmu",
191 .id = 3,
192 .dev = {
193 .platform_data = &tmu3_platform_data,
194 },
195 .resource = tmu3_resources,
196 .num_resources = ARRAY_SIZE(tmu3_resources),
197};
198
199static struct sh_timer_config tmu4_platform_data = {
200 .channel_offset = 0x10,
201 .timer_bit = 1,
202};
203
204static struct resource tmu4_resources[] = {
205 [0] = {
206 .start = 0xfe100014,
207 .end = 0xfe10001f,
208 .flags = IORESOURCE_MEM,
209 },
210 [1] = {
211 .start = evt2irq(0xb80),
212 .flags = IORESOURCE_IRQ,
213 },
214};
215
216static struct platform_device tmu4_device = {
217 .name = "sh_tmu",
218 .id = 4,
219 .dev = {
220 .platform_data = &tmu4_platform_data,
221 },
222 .resource = tmu4_resources,
223 .num_resources = ARRAY_SIZE(tmu4_resources),
224};
225
226#endif
227
228static struct platform_device *sh7750_devices[] __initdata = {
229 &rtc_device,
230 &tmu0_device,
231 &tmu1_device,
232 &tmu2_device,
233#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
234 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
235 defined(CONFIG_CPU_SUBTYPE_SH7751R)
236 &tmu3_device,
237 &tmu4_device,
238#endif
239};
240
241static int __init sh7750_devices_setup(void)
242{
243 if (mach_is_rts7751r2d()) {
244 platform_device_register(&scif_device);
245 } else {
246 platform_device_register(&sci_device);
247 platform_device_register(&scif_device);
248 }
249
250 return platform_add_devices(sh7750_devices,
251 ARRAY_SIZE(sh7750_devices));
252}
253arch_initcall(sh7750_devices_setup);
254
255static struct platform_device *sh7750_early_devices[] __initdata = {
256 &tmu0_device,
257 &tmu1_device,
258 &tmu2_device,
259#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
260 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
261 defined(CONFIG_CPU_SUBTYPE_SH7751R)
262 &tmu3_device,
263 &tmu4_device,
264#endif
265};
266
267void __init plat_early_device_setup(void)
268{
269 struct platform_device *dev[1];
270
271 if (mach_is_rts7751r2d()) {
272 scif_platform_data.scscr |= SCSCR_CKE1;
273 dev[0] = &scif_device;
274 early_platform_add_devices(dev, 1);
275 } else {
276 dev[0] = &sci_device;
277 early_platform_add_devices(dev, 1);
278 dev[0] = &scif_device;
279 early_platform_add_devices(dev, 1);
280 }
281
282 early_platform_add_devices(sh7750_early_devices,
283 ARRAY_SIZE(sh7750_early_devices));
284}
285
286enum {
287 UNUSED = 0,
288
289 /* interrupt sources */
290 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
291 HUDI, GPIOI, DMAC,
292 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
293 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
294 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
295
296 /* interrupt groups */
297 PCIC1,
298};
299
300static struct intc_vect vectors[] __initdata = {
301 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
302 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
303 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
304 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
305 INTC_VECT(RTC, 0x4c0),
306 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
307 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
308 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
309 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
310 INTC_VECT(WDT, 0x560),
311 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
312};
313
314static struct intc_prio_reg prio_registers[] __initdata = {
315 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
316 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
317 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
318 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
319 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
320 TMU4, TMU3,
321 PCIC1, PCIC0_PCISERR } },
322};
323
324static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
325 NULL, prio_registers, NULL);
326
327/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
328#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
329 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
330 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
331 defined(CONFIG_CPU_SUBTYPE_SH7091)
332static struct intc_vect vectors_dma4[] __initdata = {
333 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
334 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
335 INTC_VECT(DMAC, 0x6c0),
336};
337
338static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
339 vectors_dma4, NULL,
340 NULL, prio_registers, NULL);
341#endif
342
343/* SH7750R and SH7751R both have 8-channel DMA controllers */
344#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
345static struct intc_vect vectors_dma8[] __initdata = {
346 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
347 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
348 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
349 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
350 INTC_VECT(DMAC, 0x6c0),
351};
352
353static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
354 vectors_dma8, NULL,
355 NULL, prio_registers, NULL);
356#endif
357
358/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
359#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
360 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
361 defined(CONFIG_CPU_SUBTYPE_SH7751R)
362static struct intc_vect vectors_tmu34[] __initdata = {
363 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
364};
365
366static struct intc_mask_reg mask_registers[] __initdata = {
367 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
368 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
369 0, 0, 0, 0, 0, 0, TMU4, TMU3,
370 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
371 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
372 PCIC1_PCIDMA3, PCIC0_PCISERR } },
373};
374
375static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
376 vectors_tmu34, NULL,
377 mask_registers, prio_registers, NULL);
378#endif
379
380/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
381static struct intc_vect vectors_irlm[] __initdata = {
382 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
383 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
384};
385
386static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
387 NULL, prio_registers, NULL);
388
389/* SH7751 and SH7751R both have PCI */
390#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
391static struct intc_vect vectors_pci[] __initdata = {
392 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
393 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
394 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
395 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
396};
397
398static struct intc_group groups_pci[] __initdata = {
399 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
400 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
401};
402
403static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
404 mask_registers, prio_registers, NULL);
405#endif
406
407#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
408 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
409 defined(CONFIG_CPU_SUBTYPE_SH7091)
410void __init plat_irq_setup(void)
411{
412 /*
413 * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
414 * see below..
415 */
416 register_intc_controller(&intc_desc);
417 register_intc_controller(&intc_desc_dma4);
418}
419#endif
420
421#if defined(CONFIG_CPU_SUBTYPE_SH7750R)
422void __init plat_irq_setup(void)
423{
424 register_intc_controller(&intc_desc);
425 register_intc_controller(&intc_desc_dma8);
426 register_intc_controller(&intc_desc_tmu34);
427}
428#endif
429
430#if defined(CONFIG_CPU_SUBTYPE_SH7751)
431void __init plat_irq_setup(void)
432{
433 register_intc_controller(&intc_desc);
434 register_intc_controller(&intc_desc_dma4);
435 register_intc_controller(&intc_desc_tmu34);
436 register_intc_controller(&intc_desc_pci);
437}
438#endif
439
440#if defined(CONFIG_CPU_SUBTYPE_SH7751R)
441void __init plat_irq_setup(void)
442{
443 register_intc_controller(&intc_desc);
444 register_intc_controller(&intc_desc_dma8);
445 register_intc_controller(&intc_desc_tmu34);
446 register_intc_controller(&intc_desc_pci);
447}
448#endif
449
450#define INTC_ICR 0xffd00000UL
451#define INTC_ICR_IRLM (1<<7)
452
453void __init plat_irq_setup_pins(int mode)
454{
455#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
456 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
457 return;
458#endif
459
460 switch (mode) {
461 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
462 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
463 register_intc_controller(&intc_desc_irlm);
464 break;
465 default:
466 BUG();
467 }
468}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SH7091/SH7750/SH7750S/SH7750R/SH7751/SH7751R Setup
4 *
5 * Copyright (C) 2006 Paul Mundt
6 * Copyright (C) 2006 Jamie Lenehan
7 */
8#include <linux/platform_device.h>
9#include <linux/init.h>
10#include <linux/serial.h>
11#include <linux/io.h>
12#include <linux/sh_timer.h>
13#include <linux/sh_intc.h>
14#include <linux/serial_sci.h>
15#include <generated/machtypes.h>
16#include <asm/platform_early.h>
17
18static struct resource rtc_resources[] = {
19 [0] = {
20 .start = 0xffc80000,
21 .end = 0xffc80000 + 0x58 - 1,
22 .flags = IORESOURCE_IO,
23 },
24 [1] = {
25 /* Shared Period/Carry/Alarm IRQ */
26 .start = evt2irq(0x480),
27 .flags = IORESOURCE_IRQ,
28 },
29};
30
31static struct platform_device rtc_device = {
32 .name = "sh-rtc",
33 .id = -1,
34 .num_resources = ARRAY_SIZE(rtc_resources),
35 .resource = rtc_resources,
36};
37
38static struct plat_sci_port sci_platform_data = {
39 .type = PORT_SCI,
40};
41
42static struct resource sci_resources[] = {
43 DEFINE_RES_MEM(0xffe00000, 0x20),
44 DEFINE_RES_IRQ(evt2irq(0x4e0)),
45};
46
47static struct platform_device sci_device = {
48 .name = "sh-sci",
49 .id = 0,
50 .resource = sci_resources,
51 .num_resources = ARRAY_SIZE(sci_resources),
52 .dev = {
53 .platform_data = &sci_platform_data,
54 },
55};
56
57static struct plat_sci_port scif_platform_data = {
58 .scscr = SCSCR_REIE,
59 .type = PORT_SCIF,
60};
61
62static struct resource scif_resources[] = {
63 DEFINE_RES_MEM(0xffe80000, 0x100),
64 DEFINE_RES_IRQ(evt2irq(0x700)),
65};
66
67static struct platform_device scif_device = {
68 .name = "sh-sci",
69 .id = 1,
70 .resource = scif_resources,
71 .num_resources = ARRAY_SIZE(scif_resources),
72 .dev = {
73 .platform_data = &scif_platform_data,
74 },
75};
76
77static struct sh_timer_config tmu0_platform_data = {
78 .channels_mask = 7,
79};
80
81static struct resource tmu0_resources[] = {
82 DEFINE_RES_MEM(0xffd80000, 0x30),
83 DEFINE_RES_IRQ(evt2irq(0x400)),
84 DEFINE_RES_IRQ(evt2irq(0x420)),
85 DEFINE_RES_IRQ(evt2irq(0x440)),
86};
87
88static struct platform_device tmu0_device = {
89 .name = "sh-tmu",
90 .id = 0,
91 .dev = {
92 .platform_data = &tmu0_platform_data,
93 },
94 .resource = tmu0_resources,
95 .num_resources = ARRAY_SIZE(tmu0_resources),
96};
97
98/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
99#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
100 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
101 defined(CONFIG_CPU_SUBTYPE_SH7751R)
102
103static struct sh_timer_config tmu1_platform_data = {
104 .channels_mask = 3,
105};
106
107static struct resource tmu1_resources[] = {
108 DEFINE_RES_MEM(0xfe100000, 0x20),
109 DEFINE_RES_IRQ(evt2irq(0xb00)),
110 DEFINE_RES_IRQ(evt2irq(0xb80)),
111};
112
113static struct platform_device tmu1_device = {
114 .name = "sh-tmu",
115 .id = 1,
116 .dev = {
117 .platform_data = &tmu1_platform_data,
118 },
119 .resource = tmu1_resources,
120 .num_resources = ARRAY_SIZE(tmu1_resources),
121};
122
123#endif
124
125static struct platform_device *sh7750_devices[] __initdata = {
126 &rtc_device,
127 &tmu0_device,
128#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
129 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
130 defined(CONFIG_CPU_SUBTYPE_SH7751R)
131 &tmu1_device,
132#endif
133};
134
135static int __init sh7750_devices_setup(void)
136{
137 if (mach_is_rts7751r2d()) {
138 platform_device_register(&scif_device);
139 } else {
140 platform_device_register(&sci_device);
141 platform_device_register(&scif_device);
142 }
143
144 return platform_add_devices(sh7750_devices,
145 ARRAY_SIZE(sh7750_devices));
146}
147arch_initcall(sh7750_devices_setup);
148
149static struct platform_device *sh7750_early_devices[] __initdata = {
150 &tmu0_device,
151#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
152 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
153 defined(CONFIG_CPU_SUBTYPE_SH7751R)
154 &tmu1_device,
155#endif
156};
157
158void __init plat_early_device_setup(void)
159{
160 struct platform_device *dev[1];
161
162 if (mach_is_rts7751r2d()) {
163 scif_platform_data.scscr |= SCSCR_CKE1;
164 dev[0] = &scif_device;
165 sh_early_platform_add_devices(dev, 1);
166 } else {
167 dev[0] = &sci_device;
168 sh_early_platform_add_devices(dev, 1);
169 dev[0] = &scif_device;
170 sh_early_platform_add_devices(dev, 1);
171 }
172
173 sh_early_platform_add_devices(sh7750_early_devices,
174 ARRAY_SIZE(sh7750_early_devices));
175}
176
177enum {
178 UNUSED = 0,
179
180 /* interrupt sources */
181 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
182 HUDI, GPIOI, DMAC,
183 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
184 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
185 TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
186
187 /* interrupt groups */
188 PCIC1,
189};
190
191static struct intc_vect vectors[] __initdata = {
192 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
193 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
194 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
195 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
196 INTC_VECT(RTC, 0x4c0),
197 INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
198 INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
199 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
200 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
201 INTC_VECT(WDT, 0x560),
202 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
203};
204
205static struct intc_prio_reg prio_registers[] __initdata = {
206 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
207 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
208 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
209 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
210 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
211 TMU4, TMU3,
212 PCIC1, PCIC0_PCISERR } },
213};
214
215static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
216 NULL, prio_registers, NULL);
217
218/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
219#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
220 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
221 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
222 defined(CONFIG_CPU_SUBTYPE_SH7091)
223static struct intc_vect vectors_dma4[] __initdata = {
224 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
225 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
226 INTC_VECT(DMAC, 0x6c0),
227};
228
229static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
230 vectors_dma4, NULL,
231 NULL, prio_registers, NULL);
232#endif
233
234/* SH7750R and SH7751R both have 8-channel DMA controllers */
235#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
236static struct intc_vect vectors_dma8[] __initdata = {
237 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
238 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
239 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
240 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
241 INTC_VECT(DMAC, 0x6c0),
242};
243
244static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
245 vectors_dma8, NULL,
246 NULL, prio_registers, NULL);
247#endif
248
249/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
250#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
251 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
252 defined(CONFIG_CPU_SUBTYPE_SH7751R)
253static struct intc_vect vectors_tmu34[] __initdata = {
254 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
255};
256
257static struct intc_mask_reg mask_registers[] __initdata = {
258 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
259 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
260 0, 0, 0, 0, 0, 0, TMU4, TMU3,
261 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
262 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
263 PCIC1_PCIDMA3, PCIC0_PCISERR } },
264};
265
266static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
267 vectors_tmu34, NULL,
268 mask_registers, prio_registers, NULL);
269#endif
270
271/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
272static struct intc_vect vectors_irlm[] __initdata = {
273 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
274 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
275};
276
277static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
278 NULL, prio_registers, NULL);
279
280/* SH7751 and SH7751R both have PCI */
281#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
282static struct intc_vect vectors_pci[] __initdata = {
283 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
284 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
285 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
286 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
287};
288
289static struct intc_group groups_pci[] __initdata = {
290 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
291 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
292};
293
294static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
295 mask_registers, prio_registers, NULL);
296#endif
297
298#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
299 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
300 defined(CONFIG_CPU_SUBTYPE_SH7091)
301void __init plat_irq_setup(void)
302{
303 /*
304 * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
305 * see below..
306 */
307 register_intc_controller(&intc_desc);
308 register_intc_controller(&intc_desc_dma4);
309}
310#endif
311
312#if defined(CONFIG_CPU_SUBTYPE_SH7750R)
313void __init plat_irq_setup(void)
314{
315 register_intc_controller(&intc_desc);
316 register_intc_controller(&intc_desc_dma8);
317 register_intc_controller(&intc_desc_tmu34);
318}
319#endif
320
321#if defined(CONFIG_CPU_SUBTYPE_SH7751)
322void __init plat_irq_setup(void)
323{
324 register_intc_controller(&intc_desc);
325 register_intc_controller(&intc_desc_dma4);
326 register_intc_controller(&intc_desc_tmu34);
327 register_intc_controller(&intc_desc_pci);
328}
329#endif
330
331#if defined(CONFIG_CPU_SUBTYPE_SH7751R)
332void __init plat_irq_setup(void)
333{
334 register_intc_controller(&intc_desc);
335 register_intc_controller(&intc_desc_dma8);
336 register_intc_controller(&intc_desc_tmu34);
337 register_intc_controller(&intc_desc_pci);
338}
339#endif
340
341#define INTC_ICR 0xffd00000UL
342#define INTC_ICR_IRLM (1<<7)
343
344void __init plat_irq_setup_pins(int mode)
345{
346#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
347 BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
348 return;
349#endif
350
351 switch (mode) {
352 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
353 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
354 register_intc_controller(&intc_desc_irlm);
355 break;
356 default:
357 BUG();
358 }
359}