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1/*
2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * XXX handle crossbar/shared link difference for L3?
13 * XXX these should be marked initdata for multi-OMAP kernels
14 */
15
16#include <linux/i2c-omap.h>
17#include <linux/platform_data/spi-omap2-mcspi.h>
18#include <linux/omap-dma.h>
19#include <linux/platform_data/mailbox-omap.h>
20#include <plat/dmtimer.h>
21
22#include "omap_hwmod.h"
23#include "l3_2xxx.h"
24#include "l4_2xxx.h"
25
26#include "omap_hwmod_common_data.h"
27
28#include "cm-regbits-24xx.h"
29#include "prm-regbits-24xx.h"
30#include "i2c.h"
31#include "mmc.h"
32#include "serial.h"
33#include "wd_timer.h"
34
35/*
36 * OMAP2420 hardware module integration data
37 *
38 * All of the data in this section should be autogeneratable from the
39 * TI hardware database or other technical documentation. Data that
40 * is driver-specific or driver-kernel integration-specific belongs
41 * elsewhere.
42 */
43
44/*
45 * IP blocks
46 */
47
48/* IVA1 (IVA1) */
49static struct omap_hwmod_class iva1_hwmod_class = {
50 .name = "iva1",
51};
52
53static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
54 { .name = "iva", .rst_shift = 8 },
55};
56
57static struct omap_hwmod omap2420_iva_hwmod = {
58 .name = "iva",
59 .class = &iva1_hwmod_class,
60 .clkdm_name = "iva1_clkdm",
61 .rst_lines = omap2420_iva_resets,
62 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
63 .main_clk = "iva1_ifck",
64};
65
66/* DSP */
67static struct omap_hwmod_class dsp_hwmod_class = {
68 .name = "dsp",
69};
70
71static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
72 { .name = "logic", .rst_shift = 0 },
73 { .name = "mmu", .rst_shift = 1 },
74};
75
76static struct omap_hwmod omap2420_dsp_hwmod = {
77 .name = "dsp",
78 .class = &dsp_hwmod_class,
79 .clkdm_name = "dsp_clkdm",
80 .rst_lines = omap2420_dsp_resets,
81 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
82 .main_clk = "dsp_fck",
83};
84
85/* I2C common */
86static struct omap_hwmod_class_sysconfig i2c_sysc = {
87 .rev_offs = 0x00,
88 .sysc_offs = 0x20,
89 .syss_offs = 0x10,
90 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
91 .sysc_fields = &omap_hwmod_sysc_type1,
92};
93
94static struct omap_hwmod_class i2c_class = {
95 .name = "i2c",
96 .sysc = &i2c_sysc,
97 .rev = OMAP_I2C_IP_VERSION_1,
98 .reset = &omap_i2c_reset,
99};
100
101static struct omap_i2c_dev_attr i2c_dev_attr = {
102 .flags = OMAP_I2C_FLAG_NO_FIFO |
103 OMAP_I2C_FLAG_SIMPLE_CLOCK |
104 OMAP_I2C_FLAG_16BIT_DATA_REG |
105 OMAP_I2C_FLAG_BUS_SHIFT_2,
106};
107
108/* I2C1 */
109static struct omap_hwmod omap2420_i2c1_hwmod = {
110 .name = "i2c1",
111 .main_clk = "i2c1_fck",
112 .prcm = {
113 .omap2 = {
114 .module_offs = CORE_MOD,
115 .prcm_reg_id = 1,
116 .module_bit = OMAP2420_EN_I2C1_SHIFT,
117 .idlest_reg_id = 1,
118 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
119 },
120 },
121 .class = &i2c_class,
122 .dev_attr = &i2c_dev_attr,
123 /*
124 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
125 * while a transfer is active seems to cause the I2C block to
126 * timeout. Why? Good question."
127 */
128 .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
129};
130
131/* I2C2 */
132static struct omap_hwmod omap2420_i2c2_hwmod = {
133 .name = "i2c2",
134 .main_clk = "i2c2_fck",
135 .prcm = {
136 .omap2 = {
137 .module_offs = CORE_MOD,
138 .prcm_reg_id = 1,
139 .module_bit = OMAP2420_EN_I2C2_SHIFT,
140 .idlest_reg_id = 1,
141 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
142 },
143 },
144 .class = &i2c_class,
145 .dev_attr = &i2c_dev_attr,
146 .flags = HWMOD_16BIT_REG,
147};
148
149/* dma attributes */
150static struct omap_dma_dev_attr dma_dev_attr = {
151 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
152 IS_CSSA_32 | IS_CDSA_32,
153 .lch_count = 32,
154};
155
156static struct omap_hwmod omap2420_dma_system_hwmod = {
157 .name = "dma",
158 .class = &omap2xxx_dma_hwmod_class,
159 .mpu_irqs = omap2_dma_system_irqs,
160 .main_clk = "core_l3_ck",
161 .dev_attr = &dma_dev_attr,
162 .flags = HWMOD_NO_IDLEST,
163};
164
165/* mailbox */
166static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
167 { .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
168 { .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
169};
170
171static struct omap_mbox_pdata omap2420_mailbox_attrs = {
172 .num_users = 4,
173 .num_fifos = 6,
174 .info_cnt = ARRAY_SIZE(omap2420_mailbox_info),
175 .info = omap2420_mailbox_info,
176};
177
178static struct omap_hwmod omap2420_mailbox_hwmod = {
179 .name = "mailbox",
180 .class = &omap2xxx_mailbox_hwmod_class,
181 .main_clk = "mailboxes_ick",
182 .prcm = {
183 .omap2 = {
184 .prcm_reg_id = 1,
185 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
186 .module_offs = CORE_MOD,
187 .idlest_reg_id = 1,
188 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
189 },
190 },
191 .dev_attr = &omap2420_mailbox_attrs,
192};
193
194/*
195 * 'mcbsp' class
196 * multi channel buffered serial port controller
197 */
198
199static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
200 .name = "mcbsp",
201};
202
203static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
204 { .role = "pad_fck", .clk = "mcbsp_clks" },
205 { .role = "prcm_fck", .clk = "func_96m_ck" },
206};
207
208/* mcbsp1 */
209static struct omap_hwmod omap2420_mcbsp1_hwmod = {
210 .name = "mcbsp1",
211 .class = &omap2420_mcbsp_hwmod_class,
212 .main_clk = "mcbsp1_fck",
213 .prcm = {
214 .omap2 = {
215 .prcm_reg_id = 1,
216 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
217 .module_offs = CORE_MOD,
218 .idlest_reg_id = 1,
219 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
220 },
221 },
222 .opt_clks = mcbsp_opt_clks,
223 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
224};
225
226/* mcbsp2 */
227static struct omap_hwmod omap2420_mcbsp2_hwmod = {
228 .name = "mcbsp2",
229 .class = &omap2420_mcbsp_hwmod_class,
230 .main_clk = "mcbsp2_fck",
231 .prcm = {
232 .omap2 = {
233 .prcm_reg_id = 1,
234 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
235 .module_offs = CORE_MOD,
236 .idlest_reg_id = 1,
237 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
238 },
239 },
240 .opt_clks = mcbsp_opt_clks,
241 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
242};
243
244static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
245 .rev_offs = 0x3c,
246 .sysc_offs = 0x64,
247 .syss_offs = 0x68,
248 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
249 .sysc_fields = &omap_hwmod_sysc_type1,
250};
251
252static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
253 .name = "msdi",
254 .sysc = &omap2420_msdi_sysc,
255 .reset = &omap_msdi_reset,
256};
257
258/* msdi1 */
259static struct omap_hwmod omap2420_msdi1_hwmod = {
260 .name = "msdi1",
261 .class = &omap2420_msdi_hwmod_class,
262 .main_clk = "mmc_fck",
263 .prcm = {
264 .omap2 = {
265 .prcm_reg_id = 1,
266 .module_bit = OMAP2420_EN_MMC_SHIFT,
267 .module_offs = CORE_MOD,
268 .idlest_reg_id = 1,
269 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
270 },
271 },
272 .flags = HWMOD_16BIT_REG,
273};
274
275/* HDQ1W/1-wire */
276static struct omap_hwmod omap2420_hdq1w_hwmod = {
277 .name = "hdq1w",
278 .main_clk = "hdq_fck",
279 .prcm = {
280 .omap2 = {
281 .module_offs = CORE_MOD,
282 .prcm_reg_id = 1,
283 .module_bit = OMAP24XX_EN_HDQ_SHIFT,
284 .idlest_reg_id = 1,
285 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
286 },
287 },
288 .class = &omap2_hdq1w_class,
289};
290
291/*
292 * interfaces
293 */
294
295/* L4 CORE -> I2C1 interface */
296static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
297 .master = &omap2xxx_l4_core_hwmod,
298 .slave = &omap2420_i2c1_hwmod,
299 .clk = "i2c1_ick",
300 .user = OCP_USER_MPU | OCP_USER_SDMA,
301};
302
303/* L4 CORE -> I2C2 interface */
304static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
305 .master = &omap2xxx_l4_core_hwmod,
306 .slave = &omap2420_i2c2_hwmod,
307 .clk = "i2c2_ick",
308 .user = OCP_USER_MPU | OCP_USER_SDMA,
309};
310
311/* IVA <- L3 interface */
312static struct omap_hwmod_ocp_if omap2420_l3__iva = {
313 .master = &omap2xxx_l3_main_hwmod,
314 .slave = &omap2420_iva_hwmod,
315 .clk = "core_l3_ck",
316 .user = OCP_USER_MPU | OCP_USER_SDMA,
317};
318
319/* DSP <- L3 interface */
320static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
321 .master = &omap2xxx_l3_main_hwmod,
322 .slave = &omap2420_dsp_hwmod,
323 .clk = "dsp_ick",
324 .user = OCP_USER_MPU | OCP_USER_SDMA,
325};
326
327/* l4_wkup -> timer1 */
328static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
329 .master = &omap2xxx_l4_wkup_hwmod,
330 .slave = &omap2xxx_timer1_hwmod,
331 .clk = "gpt1_ick",
332 .user = OCP_USER_MPU | OCP_USER_SDMA,
333};
334
335/* l4_wkup -> wd_timer2 */
336static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
337 .master = &omap2xxx_l4_wkup_hwmod,
338 .slave = &omap2xxx_wd_timer2_hwmod,
339 .clk = "mpu_wdt_ick",
340 .user = OCP_USER_MPU | OCP_USER_SDMA,
341};
342
343/* l4_wkup -> gpio1 */
344static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
345 .master = &omap2xxx_l4_wkup_hwmod,
346 .slave = &omap2xxx_gpio1_hwmod,
347 .clk = "gpios_ick",
348 .user = OCP_USER_MPU | OCP_USER_SDMA,
349};
350
351/* l4_wkup -> gpio2 */
352static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
353 .master = &omap2xxx_l4_wkup_hwmod,
354 .slave = &omap2xxx_gpio2_hwmod,
355 .clk = "gpios_ick",
356 .user = OCP_USER_MPU | OCP_USER_SDMA,
357};
358
359/* l4_wkup -> gpio3 */
360static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
361 .master = &omap2xxx_l4_wkup_hwmod,
362 .slave = &omap2xxx_gpio3_hwmod,
363 .clk = "gpios_ick",
364 .user = OCP_USER_MPU | OCP_USER_SDMA,
365};
366
367/* l4_wkup -> gpio4 */
368static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
369 .master = &omap2xxx_l4_wkup_hwmod,
370 .slave = &omap2xxx_gpio4_hwmod,
371 .clk = "gpios_ick",
372 .user = OCP_USER_MPU | OCP_USER_SDMA,
373};
374
375/* dma_system -> L3 */
376static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
377 .master = &omap2420_dma_system_hwmod,
378 .slave = &omap2xxx_l3_main_hwmod,
379 .clk = "core_l3_ck",
380 .user = OCP_USER_MPU | OCP_USER_SDMA,
381};
382
383/* l4_core -> dma_system */
384static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
385 .master = &omap2xxx_l4_core_hwmod,
386 .slave = &omap2420_dma_system_hwmod,
387 .clk = "sdma_ick",
388 .addr = omap2_dma_system_addrs,
389 .user = OCP_USER_MPU | OCP_USER_SDMA,
390};
391
392/* l4_core -> mailbox */
393static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
394 .master = &omap2xxx_l4_core_hwmod,
395 .slave = &omap2420_mailbox_hwmod,
396 .user = OCP_USER_MPU | OCP_USER_SDMA,
397};
398
399/* l4_core -> mcbsp1 */
400static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
401 .master = &omap2xxx_l4_core_hwmod,
402 .slave = &omap2420_mcbsp1_hwmod,
403 .clk = "mcbsp1_ick",
404 .user = OCP_USER_MPU | OCP_USER_SDMA,
405};
406
407/* l4_core -> mcbsp2 */
408static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
409 .master = &omap2xxx_l4_core_hwmod,
410 .slave = &omap2420_mcbsp2_hwmod,
411 .clk = "mcbsp2_ick",
412 .user = OCP_USER_MPU | OCP_USER_SDMA,
413};
414
415/* l4_core -> msdi1 */
416static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
417 .master = &omap2xxx_l4_core_hwmod,
418 .slave = &omap2420_msdi1_hwmod,
419 .clk = "mmc_ick",
420 .user = OCP_USER_MPU | OCP_USER_SDMA,
421};
422
423/* l4_core -> hdq1w interface */
424static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
425 .master = &omap2xxx_l4_core_hwmod,
426 .slave = &omap2420_hdq1w_hwmod,
427 .clk = "hdq_ick",
428 .user = OCP_USER_MPU | OCP_USER_SDMA,
429 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
430};
431
432
433/* l4_wkup -> 32ksync_counter */
434static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
435 .master = &omap2xxx_l4_wkup_hwmod,
436 .slave = &omap2xxx_counter_32k_hwmod,
437 .clk = "sync_32k_ick",
438 .user = OCP_USER_MPU | OCP_USER_SDMA,
439};
440
441static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
442 .master = &omap2xxx_l3_main_hwmod,
443 .slave = &omap2xxx_gpmc_hwmod,
444 .clk = "core_l3_ck",
445 .user = OCP_USER_MPU | OCP_USER_SDMA,
446};
447
448static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
449 &omap2xxx_l3_main__l4_core,
450 &omap2xxx_mpu__l3_main,
451 &omap2xxx_dss__l3,
452 &omap2xxx_l4_core__mcspi1,
453 &omap2xxx_l4_core__mcspi2,
454 &omap2xxx_l4_core__l4_wkup,
455 &omap2_l4_core__uart1,
456 &omap2_l4_core__uart2,
457 &omap2_l4_core__uart3,
458 &omap2420_l4_core__i2c1,
459 &omap2420_l4_core__i2c2,
460 &omap2420_l3__iva,
461 &omap2420_l3__dsp,
462 &omap2420_l4_wkup__timer1,
463 &omap2xxx_l4_core__timer2,
464 &omap2xxx_l4_core__timer3,
465 &omap2xxx_l4_core__timer4,
466 &omap2xxx_l4_core__timer5,
467 &omap2xxx_l4_core__timer6,
468 &omap2xxx_l4_core__timer7,
469 &omap2xxx_l4_core__timer8,
470 &omap2xxx_l4_core__timer9,
471 &omap2xxx_l4_core__timer10,
472 &omap2xxx_l4_core__timer11,
473 &omap2xxx_l4_core__timer12,
474 &omap2420_l4_wkup__wd_timer2,
475 &omap2xxx_l4_core__dss,
476 &omap2xxx_l4_core__dss_dispc,
477 &omap2xxx_l4_core__dss_rfbi,
478 &omap2xxx_l4_core__dss_venc,
479 &omap2420_l4_wkup__gpio1,
480 &omap2420_l4_wkup__gpio2,
481 &omap2420_l4_wkup__gpio3,
482 &omap2420_l4_wkup__gpio4,
483 &omap2420_dma_system__l3,
484 &omap2420_l4_core__dma_system,
485 &omap2420_l4_core__mailbox,
486 &omap2420_l4_core__mcbsp1,
487 &omap2420_l4_core__mcbsp2,
488 &omap2420_l4_core__msdi1,
489 &omap2xxx_l4_core__rng,
490 &omap2xxx_l4_core__sham,
491 &omap2xxx_l4_core__aes,
492 &omap2420_l4_core__hdq1w,
493 &omap2420_l4_wkup__counter_32k,
494 &omap2420_l3__gpmc,
495 NULL,
496};
497
498int __init omap2420_hwmod_init(void)
499{
500 omap_hwmod_init();
501 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
502}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
4 *
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2012 Texas Instruments, Inc.
7 * Paul Walmsley
8 *
9 * XXX handle crossbar/shared link difference for L3?
10 * XXX these should be marked initdata for multi-OMAP kernels
11 */
12
13#include <linux/platform_data/i2c-omap.h>
14
15#include "omap_hwmod.h"
16#include "l3_2xxx.h"
17#include "l4_2xxx.h"
18
19#include "omap_hwmod_common_data.h"
20
21#include "cm-regbits-24xx.h"
22#include "prm-regbits-24xx.h"
23#include "i2c.h"
24#include "mmc.h"
25#include "wd_timer.h"
26
27/*
28 * OMAP2420 hardware module integration data
29 *
30 * All of the data in this section should be autogeneratable from the
31 * TI hardware database or other technical documentation. Data that
32 * is driver-specific or driver-kernel integration-specific belongs
33 * elsewhere.
34 */
35
36/*
37 * IP blocks
38 */
39
40/* IVA1 (IVA1) */
41static struct omap_hwmod_class iva1_hwmod_class = {
42 .name = "iva1",
43};
44
45static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
46 { .name = "iva", .rst_shift = 8 },
47};
48
49static struct omap_hwmod omap2420_iva_hwmod = {
50 .name = "iva",
51 .class = &iva1_hwmod_class,
52 .clkdm_name = "iva1_clkdm",
53 .rst_lines = omap2420_iva_resets,
54 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
55 .main_clk = "iva1_ifck",
56};
57
58/* DSP */
59static struct omap_hwmod_class dsp_hwmod_class = {
60 .name = "dsp",
61};
62
63static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
64 { .name = "logic", .rst_shift = 0 },
65 { .name = "mmu", .rst_shift = 1 },
66};
67
68static struct omap_hwmod omap2420_dsp_hwmod = {
69 .name = "dsp",
70 .class = &dsp_hwmod_class,
71 .clkdm_name = "dsp_clkdm",
72 .rst_lines = omap2420_dsp_resets,
73 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
74 .main_clk = "dsp_fck",
75};
76
77/* I2C common */
78static struct omap_hwmod_class_sysconfig i2c_sysc = {
79 .rev_offs = 0x00,
80 .sysc_offs = 0x20,
81 .syss_offs = 0x10,
82 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
83 .sysc_fields = &omap_hwmod_sysc_type1,
84};
85
86static struct omap_hwmod_class i2c_class = {
87 .name = "i2c",
88 .sysc = &i2c_sysc,
89 .reset = &omap_i2c_reset,
90};
91
92/* I2C1 */
93static struct omap_hwmod omap2420_i2c1_hwmod = {
94 .name = "i2c1",
95 .main_clk = "i2c1_fck",
96 .prcm = {
97 .omap2 = {
98 .module_offs = CORE_MOD,
99 .idlest_reg_id = 1,
100 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
101 },
102 },
103 .class = &i2c_class,
104 /*
105 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
106 * while a transfer is active seems to cause the I2C block to
107 * timeout. Why? Good question."
108 */
109 .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
110};
111
112/* I2C2 */
113static struct omap_hwmod omap2420_i2c2_hwmod = {
114 .name = "i2c2",
115 .main_clk = "i2c2_fck",
116 .prcm = {
117 .omap2 = {
118 .module_offs = CORE_MOD,
119 .idlest_reg_id = 1,
120 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
121 },
122 },
123 .class = &i2c_class,
124 .flags = HWMOD_16BIT_REG,
125};
126
127/* mailbox */
128static struct omap_hwmod omap2420_mailbox_hwmod = {
129 .name = "mailbox",
130 .class = &omap2xxx_mailbox_hwmod_class,
131 .main_clk = "mailboxes_ick",
132 .prcm = {
133 .omap2 = {
134 .module_offs = CORE_MOD,
135 .idlest_reg_id = 1,
136 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
137 },
138 },
139};
140
141/*
142 * 'mcbsp' class
143 * multi channel buffered serial port controller
144 */
145
146static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
147 .name = "mcbsp",
148};
149
150static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
151 { .role = "pad_fck", .clk = "mcbsp_clks" },
152 { .role = "prcm_fck", .clk = "func_96m_ck" },
153};
154
155/* mcbsp1 */
156static struct omap_hwmod omap2420_mcbsp1_hwmod = {
157 .name = "mcbsp1",
158 .class = &omap2420_mcbsp_hwmod_class,
159 .main_clk = "mcbsp1_fck",
160 .prcm = {
161 .omap2 = {
162 .module_offs = CORE_MOD,
163 .idlest_reg_id = 1,
164 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
165 },
166 },
167 .opt_clks = mcbsp_opt_clks,
168 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
169};
170
171/* mcbsp2 */
172static struct omap_hwmod omap2420_mcbsp2_hwmod = {
173 .name = "mcbsp2",
174 .class = &omap2420_mcbsp_hwmod_class,
175 .main_clk = "mcbsp2_fck",
176 .prcm = {
177 .omap2 = {
178 .module_offs = CORE_MOD,
179 .idlest_reg_id = 1,
180 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
181 },
182 },
183 .opt_clks = mcbsp_opt_clks,
184 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
185};
186
187static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
188 .rev_offs = 0x3c,
189 .sysc_offs = 0x64,
190 .syss_offs = 0x68,
191 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
192 .sysc_fields = &omap_hwmod_sysc_type1,
193};
194
195static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
196 .name = "msdi",
197 .sysc = &omap2420_msdi_sysc,
198 .reset = &omap_msdi_reset,
199};
200
201/* msdi1 */
202static struct omap_hwmod omap2420_msdi1_hwmod = {
203 .name = "msdi1",
204 .class = &omap2420_msdi_hwmod_class,
205 .main_clk = "mmc_fck",
206 .prcm = {
207 .omap2 = {
208 .module_offs = CORE_MOD,
209 .idlest_reg_id = 1,
210 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
211 },
212 },
213 .flags = HWMOD_16BIT_REG,
214};
215
216/* HDQ1W/1-wire */
217static struct omap_hwmod omap2420_hdq1w_hwmod = {
218 .name = "hdq1w",
219 .main_clk = "hdq_fck",
220 .prcm = {
221 .omap2 = {
222 .module_offs = CORE_MOD,
223 .idlest_reg_id = 1,
224 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
225 },
226 },
227 .class = &omap2_hdq1w_class,
228};
229
230/*
231 * interfaces
232 */
233
234/* L4 CORE -> I2C1 interface */
235static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
236 .master = &omap2xxx_l4_core_hwmod,
237 .slave = &omap2420_i2c1_hwmod,
238 .clk = "i2c1_ick",
239 .user = OCP_USER_MPU | OCP_USER_SDMA,
240};
241
242/* L4 CORE -> I2C2 interface */
243static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
244 .master = &omap2xxx_l4_core_hwmod,
245 .slave = &omap2420_i2c2_hwmod,
246 .clk = "i2c2_ick",
247 .user = OCP_USER_MPU | OCP_USER_SDMA,
248};
249
250/* IVA <- L3 interface */
251static struct omap_hwmod_ocp_if omap2420_l3__iva = {
252 .master = &omap2xxx_l3_main_hwmod,
253 .slave = &omap2420_iva_hwmod,
254 .clk = "core_l3_ck",
255 .user = OCP_USER_MPU | OCP_USER_SDMA,
256};
257
258/* DSP <- L3 interface */
259static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
260 .master = &omap2xxx_l3_main_hwmod,
261 .slave = &omap2420_dsp_hwmod,
262 .clk = "dsp_ick",
263 .user = OCP_USER_MPU | OCP_USER_SDMA,
264};
265
266/* l4_wkup -> wd_timer2 */
267static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
268 .master = &omap2xxx_l4_wkup_hwmod,
269 .slave = &omap2xxx_wd_timer2_hwmod,
270 .clk = "mpu_wdt_ick",
271 .user = OCP_USER_MPU | OCP_USER_SDMA,
272};
273
274/* l4_wkup -> gpio1 */
275static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
276 .master = &omap2xxx_l4_wkup_hwmod,
277 .slave = &omap2xxx_gpio1_hwmod,
278 .clk = "gpios_ick",
279 .user = OCP_USER_MPU | OCP_USER_SDMA,
280};
281
282/* l4_wkup -> gpio2 */
283static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
284 .master = &omap2xxx_l4_wkup_hwmod,
285 .slave = &omap2xxx_gpio2_hwmod,
286 .clk = "gpios_ick",
287 .user = OCP_USER_MPU | OCP_USER_SDMA,
288};
289
290/* l4_wkup -> gpio3 */
291static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
292 .master = &omap2xxx_l4_wkup_hwmod,
293 .slave = &omap2xxx_gpio3_hwmod,
294 .clk = "gpios_ick",
295 .user = OCP_USER_MPU | OCP_USER_SDMA,
296};
297
298/* l4_wkup -> gpio4 */
299static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
300 .master = &omap2xxx_l4_wkup_hwmod,
301 .slave = &omap2xxx_gpio4_hwmod,
302 .clk = "gpios_ick",
303 .user = OCP_USER_MPU | OCP_USER_SDMA,
304};
305
306/* l4_core -> mailbox */
307static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
308 .master = &omap2xxx_l4_core_hwmod,
309 .slave = &omap2420_mailbox_hwmod,
310 .user = OCP_USER_MPU | OCP_USER_SDMA,
311};
312
313/* l4_core -> mcbsp1 */
314static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
315 .master = &omap2xxx_l4_core_hwmod,
316 .slave = &omap2420_mcbsp1_hwmod,
317 .clk = "mcbsp1_ick",
318 .user = OCP_USER_MPU | OCP_USER_SDMA,
319};
320
321/* l4_core -> mcbsp2 */
322static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
323 .master = &omap2xxx_l4_core_hwmod,
324 .slave = &omap2420_mcbsp2_hwmod,
325 .clk = "mcbsp2_ick",
326 .user = OCP_USER_MPU | OCP_USER_SDMA,
327};
328
329/* l4_core -> msdi1 */
330static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
331 .master = &omap2xxx_l4_core_hwmod,
332 .slave = &omap2420_msdi1_hwmod,
333 .clk = "mmc_ick",
334 .user = OCP_USER_MPU | OCP_USER_SDMA,
335};
336
337/* l4_core -> hdq1w interface */
338static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
339 .master = &omap2xxx_l4_core_hwmod,
340 .slave = &omap2420_hdq1w_hwmod,
341 .clk = "hdq_ick",
342 .user = OCP_USER_MPU | OCP_USER_SDMA,
343 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
344};
345
346static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
347 .master = &omap2xxx_l3_main_hwmod,
348 .slave = &omap2xxx_gpmc_hwmod,
349 .clk = "core_l3_ck",
350 .user = OCP_USER_MPU | OCP_USER_SDMA,
351};
352
353static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
354 &omap2xxx_l3_main__l4_core,
355 &omap2xxx_mpu__l3_main,
356 &omap2xxx_dss__l3,
357 &omap2xxx_l4_core__mcspi1,
358 &omap2xxx_l4_core__mcspi2,
359 &omap2xxx_l4_core__l4_wkup,
360 &omap2_l4_core__uart1,
361 &omap2_l4_core__uart2,
362 &omap2_l4_core__uart3,
363 &omap2420_l4_core__i2c1,
364 &omap2420_l4_core__i2c2,
365 &omap2420_l3__iva,
366 &omap2420_l3__dsp,
367 &omap2xxx_l4_core__timer3,
368 &omap2xxx_l4_core__timer4,
369 &omap2xxx_l4_core__timer5,
370 &omap2xxx_l4_core__timer6,
371 &omap2xxx_l4_core__timer7,
372 &omap2xxx_l4_core__timer8,
373 &omap2xxx_l4_core__timer9,
374 &omap2xxx_l4_core__timer10,
375 &omap2xxx_l4_core__timer11,
376 &omap2xxx_l4_core__timer12,
377 &omap2420_l4_wkup__wd_timer2,
378 &omap2xxx_l4_core__dss,
379 &omap2xxx_l4_core__dss_dispc,
380 &omap2xxx_l4_core__dss_rfbi,
381 &omap2xxx_l4_core__dss_venc,
382 &omap2420_l4_wkup__gpio1,
383 &omap2420_l4_wkup__gpio2,
384 &omap2420_l4_wkup__gpio3,
385 &omap2420_l4_wkup__gpio4,
386 &omap2420_l4_core__mailbox,
387 &omap2420_l4_core__mcbsp1,
388 &omap2420_l4_core__mcbsp2,
389 &omap2420_l4_core__msdi1,
390 &omap2xxx_l4_core__rng,
391 &omap2xxx_l4_core__sham,
392 &omap2xxx_l4_core__aes,
393 &omap2420_l4_core__hdq1w,
394 &omap2420_l3__gpmc,
395 NULL,
396};
397
398int __init omap2420_hwmod_init(void)
399{
400 omap_hwmod_init();
401 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
402}