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1#ifndef dprintk
2# define dprintk(x)
3#endif
4/* eg: if (nblank(dprintk(x))) */
5#define _nblank(x) #x
6#define nblank(x) _nblank(x)[0]
7
8#include <linux/interrupt.h>
9
10/*------------------------------------------------------------------------------
11 * D E F I N E S
12 *----------------------------------------------------------------------------*/
13
14#ifndef AAC_DRIVER_BUILD
15# define AAC_DRIVER_BUILD 30300
16# define AAC_DRIVER_BRANCH "-ms"
17#endif
18#define MAXIMUM_NUM_CONTAINERS 32
19
20#define AAC_NUM_MGT_FIB 8
21#define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB)
22#define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB)
23
24#define AAC_MAX_LUN (8)
25
26#define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff)
27#define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256)
28
29#define AAC_DEBUG_INSTRUMENT_AIF_DELETE
30
31/*
32 * These macros convert from physical channels to virtual channels
33 */
34#define CONTAINER_CHANNEL (0)
35#define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL)
36#define CONTAINER_TO_ID(cont) (cont)
37#define CONTAINER_TO_LUN(cont) (0)
38
39#define PMC_DEVICE_S7 0x28c
40#define PMC_DEVICE_S8 0x28d
41#define PMC_DEVICE_S9 0x28f
42
43#define aac_phys_to_logical(x) ((x)+1)
44#define aac_logical_to_phys(x) ((x)?(x)-1:0)
45
46/* #define AAC_DETAILED_STATUS_INFO */
47
48struct diskparm
49{
50 int heads;
51 int sectors;
52 int cylinders;
53};
54
55
56/*
57 * Firmware constants
58 */
59
60#define CT_NONE 0
61#define CT_OK 218
62#define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */
63#define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/id/lun */
64
65/*
66 * Host side memory scatter gather list
67 * Used by the adapter for read, write, and readdirplus operations
68 * We have separate 32 and 64 bit version because even
69 * on 64 bit systems not all cards support the 64 bit version
70 */
71struct sgentry {
72 __le32 addr; /* 32-bit address. */
73 __le32 count; /* Length. */
74};
75
76struct user_sgentry {
77 u32 addr; /* 32-bit address. */
78 u32 count; /* Length. */
79};
80
81struct sgentry64 {
82 __le32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
83 __le32 count; /* Length. */
84};
85
86struct user_sgentry64 {
87 u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
88 u32 count; /* Length. */
89};
90
91struct sgentryraw {
92 __le32 next; /* reserved for F/W use */
93 __le32 prev; /* reserved for F/W use */
94 __le32 addr[2];
95 __le32 count;
96 __le32 flags; /* reserved for F/W use */
97};
98
99struct user_sgentryraw {
100 u32 next; /* reserved for F/W use */
101 u32 prev; /* reserved for F/W use */
102 u32 addr[2];
103 u32 count;
104 u32 flags; /* reserved for F/W use */
105};
106
107struct sge_ieee1212 {
108 u32 addrLow;
109 u32 addrHigh;
110 u32 length;
111 u32 flags;
112};
113
114/*
115 * SGMAP
116 *
117 * This is the SGMAP structure for all commands that use
118 * 32-bit addressing.
119 */
120
121struct sgmap {
122 __le32 count;
123 struct sgentry sg[1];
124};
125
126struct user_sgmap {
127 u32 count;
128 struct user_sgentry sg[1];
129};
130
131struct sgmap64 {
132 __le32 count;
133 struct sgentry64 sg[1];
134};
135
136struct user_sgmap64 {
137 u32 count;
138 struct user_sgentry64 sg[1];
139};
140
141struct sgmapraw {
142 __le32 count;
143 struct sgentryraw sg[1];
144};
145
146struct user_sgmapraw {
147 u32 count;
148 struct user_sgentryraw sg[1];
149};
150
151struct creation_info
152{
153 u8 buildnum; /* e.g., 588 */
154 u8 usec; /* e.g., 588 */
155 u8 via; /* e.g., 1 = FSU,
156 * 2 = API
157 */
158 u8 year; /* e.g., 1997 = 97 */
159 __le32 date; /*
160 * unsigned Month :4; // 1 - 12
161 * unsigned Day :6; // 1 - 32
162 * unsigned Hour :6; // 0 - 23
163 * unsigned Minute :6; // 0 - 60
164 * unsigned Second :6; // 0 - 60
165 */
166 __le32 serial[2]; /* e.g., 0x1DEADB0BFAFAF001 */
167};
168
169
170/*
171 * Define all the constants needed for the communication interface
172 */
173
174/*
175 * Define how many queue entries each queue will have and the total
176 * number of entries for the entire communication interface. Also define
177 * how many queues we support.
178 *
179 * This has to match the controller
180 */
181
182#define NUMBER_OF_COMM_QUEUES 8 // 4 command; 4 response
183#define HOST_HIGH_CMD_ENTRIES 4
184#define HOST_NORM_CMD_ENTRIES 8
185#define ADAP_HIGH_CMD_ENTRIES 4
186#define ADAP_NORM_CMD_ENTRIES 512
187#define HOST_HIGH_RESP_ENTRIES 4
188#define HOST_NORM_RESP_ENTRIES 512
189#define ADAP_HIGH_RESP_ENTRIES 4
190#define ADAP_NORM_RESP_ENTRIES 8
191
192#define TOTAL_QUEUE_ENTRIES \
193 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \
194 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES)
195
196
197/*
198 * Set the queues on a 16 byte alignment
199 */
200
201#define QUEUE_ALIGNMENT 16
202
203/*
204 * The queue headers define the Communication Region queues. These
205 * are physically contiguous and accessible by both the adapter and the
206 * host. Even though all queue headers are in the same contiguous block
207 * they will be represented as individual units in the data structures.
208 */
209
210struct aac_entry {
211 __le32 size; /* Size in bytes of Fib which this QE points to */
212 __le32 addr; /* Receiver address of the FIB */
213};
214
215/*
216 * The adapter assumes the ProducerIndex and ConsumerIndex are grouped
217 * adjacently and in that order.
218 */
219
220struct aac_qhdr {
221 __le64 header_addr;/* Address to hand the adapter to access
222 to this queue head */
223 __le32 *producer; /* The producer index for this queue (host address) */
224 __le32 *consumer; /* The consumer index for this queue (host address) */
225};
226
227/*
228 * Define all the events which the adapter would like to notify
229 * the host of.
230 */
231
232#define HostNormCmdQue 1 /* Change in host normal priority command queue */
233#define HostHighCmdQue 2 /* Change in host high priority command queue */
234#define HostNormRespQue 3 /* Change in host normal priority response queue */
235#define HostHighRespQue 4 /* Change in host high priority response queue */
236#define AdapNormRespNotFull 5
237#define AdapHighRespNotFull 6
238#define AdapNormCmdNotFull 7
239#define AdapHighCmdNotFull 8
240#define SynchCommandComplete 9
241#define AdapInternalError 0xfe /* The adapter detected an internal error shutting down */
242
243/*
244 * Define all the events the host wishes to notify the
245 * adapter of. The first four values much match the Qid the
246 * corresponding queue.
247 */
248
249#define AdapNormCmdQue 2
250#define AdapHighCmdQue 3
251#define AdapNormRespQue 6
252#define AdapHighRespQue 7
253#define HostShutdown 8
254#define HostPowerFail 9
255#define FatalCommError 10
256#define HostNormRespNotFull 11
257#define HostHighRespNotFull 12
258#define HostNormCmdNotFull 13
259#define HostHighCmdNotFull 14
260#define FastIo 15
261#define AdapPrintfDone 16
262
263/*
264 * Define all the queues that the adapter and host use to communicate
265 * Number them to match the physical queue layout.
266 */
267
268enum aac_queue_types {
269 HostNormCmdQueue = 0, /* Adapter to host normal priority command traffic */
270 HostHighCmdQueue, /* Adapter to host high priority command traffic */
271 AdapNormCmdQueue, /* Host to adapter normal priority command traffic */
272 AdapHighCmdQueue, /* Host to adapter high priority command traffic */
273 HostNormRespQueue, /* Adapter to host normal priority response traffic */
274 HostHighRespQueue, /* Adapter to host high priority response traffic */
275 AdapNormRespQueue, /* Host to adapter normal priority response traffic */
276 AdapHighRespQueue /* Host to adapter high priority response traffic */
277};
278
279/*
280 * Assign type values to the FSA communication data structures
281 */
282
283#define FIB_MAGIC 0x0001
284#define FIB_MAGIC2 0x0004
285#define FIB_MAGIC2_64 0x0005
286
287/*
288 * Define the priority levels the FSA communication routines support.
289 */
290
291#define FsaNormal 1
292
293/* transport FIB header (PMC) */
294struct aac_fib_xporthdr {
295 u64 HostAddress; /* FIB host address w/o xport header */
296 u32 Size; /* FIB size excluding xport header */
297 u32 Handle; /* driver handle to reference the FIB */
298 u64 Reserved[2];
299};
300
301#define ALIGN32 32
302
303/*
304 * Define the FIB. The FIB is the where all the requested data and
305 * command information are put to the application on the FSA adapter.
306 */
307
308struct aac_fibhdr {
309 __le32 XferState; /* Current transfer state for this CCB */
310 __le16 Command; /* Routing information for the destination */
311 u8 StructType; /* Type FIB */
312 u8 Unused; /* Unused */
313 __le16 Size; /* Size of this FIB in bytes */
314 __le16 SenderSize; /* Size of the FIB in the sender
315 (for response sizing) */
316 __le32 SenderFibAddress; /* Host defined data in the FIB */
317 union {
318 __le32 ReceiverFibAddress;/* Logical address of this FIB for
319 the adapter (old) */
320 __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */
321 __le32 TimeStamp; /* otherwise timestamp for FW internal use */
322 } u;
323 u32 Handle; /* FIB handle used for MSGU commnunication */
324 u32 Previous; /* FW internal use */
325 u32 Next; /* FW internal use */
326};
327
328struct hw_fib {
329 struct aac_fibhdr header;
330 u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data
331};
332
333/*
334 * FIB commands
335 */
336
337#define TestCommandResponse 1
338#define TestAdapterCommand 2
339/*
340 * Lowlevel and comm commands
341 */
342#define LastTestCommand 100
343#define ReinitHostNormCommandQueue 101
344#define ReinitHostHighCommandQueue 102
345#define ReinitHostHighRespQueue 103
346#define ReinitHostNormRespQueue 104
347#define ReinitAdapNormCommandQueue 105
348#define ReinitAdapHighCommandQueue 107
349#define ReinitAdapHighRespQueue 108
350#define ReinitAdapNormRespQueue 109
351#define InterfaceShutdown 110
352#define DmaCommandFib 120
353#define StartProfile 121
354#define TermProfile 122
355#define SpeedTest 123
356#define TakeABreakPt 124
357#define RequestPerfData 125
358#define SetInterruptDefTimer 126
359#define SetInterruptDefCount 127
360#define GetInterruptDefStatus 128
361#define LastCommCommand 129
362/*
363 * Filesystem commands
364 */
365#define NuFileSystem 300
366#define UFS 301
367#define HostFileSystem 302
368#define LastFileSystemCommand 303
369/*
370 * Container Commands
371 */
372#define ContainerCommand 500
373#define ContainerCommand64 501
374#define ContainerRawIo 502
375#define ContainerRawIo2 503
376/*
377 * Scsi Port commands (scsi passthrough)
378 */
379#define ScsiPortCommand 600
380#define ScsiPortCommand64 601
381/*
382 * Misc house keeping and generic adapter initiated commands
383 */
384#define AifRequest 700
385#define CheckRevision 701
386#define FsaHostShutdown 702
387#define RequestAdapterInfo 703
388#define IsAdapterPaused 704
389#define SendHostTime 705
390#define RequestSupplementAdapterInfo 706
391#define LastMiscCommand 707
392
393/*
394 * Commands that will target the failover level on the FSA adapter
395 */
396
397enum fib_xfer_state {
398 HostOwned = (1<<0),
399 AdapterOwned = (1<<1),
400 FibInitialized = (1<<2),
401 FibEmpty = (1<<3),
402 AllocatedFromPool = (1<<4),
403 SentFromHost = (1<<5),
404 SentFromAdapter = (1<<6),
405 ResponseExpected = (1<<7),
406 NoResponseExpected = (1<<8),
407 AdapterProcessed = (1<<9),
408 HostProcessed = (1<<10),
409 HighPriority = (1<<11),
410 NormalPriority = (1<<12),
411 Async = (1<<13),
412 AsyncIo = (1<<13), // rpbfix: remove with new regime
413 PageFileIo = (1<<14), // rpbfix: remove with new regime
414 ShutdownRequest = (1<<15),
415 LazyWrite = (1<<16), // rpbfix: remove with new regime
416 AdapterMicroFib = (1<<17),
417 BIOSFibPath = (1<<18),
418 FastResponseCapable = (1<<19),
419 ApiFib = (1<<20), /* Its an API Fib */
420 /* PMC NEW COMM: There is no more AIF data pending */
421 NoMoreAifDataAvailable = (1<<21)
422};
423
424/*
425 * The following defines needs to be updated any time there is an
426 * incompatible change made to the aac_init structure.
427 */
428
429#define ADAPTER_INIT_STRUCT_REVISION 3
430#define ADAPTER_INIT_STRUCT_REVISION_4 4 // rocket science
431#define ADAPTER_INIT_STRUCT_REVISION_6 6 /* PMC src */
432#define ADAPTER_INIT_STRUCT_REVISION_7 7 /* Denali */
433
434struct aac_init
435{
436 __le32 InitStructRevision;
437 __le32 MiniPortRevision;
438 __le32 fsrev;
439 __le32 CommHeaderAddress;
440 __le32 FastIoCommAreaAddress;
441 __le32 AdapterFibsPhysicalAddress;
442 __le32 AdapterFibsVirtualAddress;
443 __le32 AdapterFibsSize;
444 __le32 AdapterFibAlign;
445 __le32 printfbuf;
446 __le32 printfbufsiz;
447 __le32 HostPhysMemPages; /* number of 4k pages of host
448 physical memory */
449 __le32 HostElapsedSeconds; /* number of seconds since 1970. */
450 /*
451 * ADAPTER_INIT_STRUCT_REVISION_4 begins here
452 */
453 __le32 InitFlags; /* flags for supported features */
454#define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001
455#define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010
456#define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020
457#define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040
458#define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080
459#define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100
460 __le32 MaxIoCommands; /* max outstanding commands */
461 __le32 MaxIoSize; /* largest I/O command */
462 __le32 MaxFibSize; /* largest FIB to adapter */
463 /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */
464 __le32 MaxNumAif; /* max number of aif */
465 /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */
466 __le32 HostRRQ_AddrLow;
467 __le32 HostRRQ_AddrHigh; /* Host RRQ (response queue) for SRC */
468};
469
470enum aac_log_level {
471 LOG_AAC_INIT = 10,
472 LOG_AAC_INFORMATIONAL = 20,
473 LOG_AAC_WARNING = 30,
474 LOG_AAC_LOW_ERROR = 40,
475 LOG_AAC_MEDIUM_ERROR = 50,
476 LOG_AAC_HIGH_ERROR = 60,
477 LOG_AAC_PANIC = 70,
478 LOG_AAC_DEBUG = 80,
479 LOG_AAC_WINDBG_PRINT = 90
480};
481
482#define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b
483#define FSAFS_NTC_FIB_CONTEXT 0x030c
484
485struct aac_dev;
486struct fib;
487struct scsi_cmnd;
488
489struct adapter_ops
490{
491 /* Low level operations */
492 void (*adapter_interrupt)(struct aac_dev *dev);
493 void (*adapter_notify)(struct aac_dev *dev, u32 event);
494 void (*adapter_disable_int)(struct aac_dev *dev);
495 void (*adapter_enable_int)(struct aac_dev *dev);
496 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4);
497 int (*adapter_check_health)(struct aac_dev *dev);
498 int (*adapter_restart)(struct aac_dev *dev, int bled);
499 /* Transport operations */
500 int (*adapter_ioremap)(struct aac_dev * dev, u32 size);
501 irq_handler_t adapter_intr;
502 /* Packet operations */
503 int (*adapter_deliver)(struct fib * fib);
504 int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba);
505 int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count);
506 int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua);
507 int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd);
508 /* Administrative operations */
509 int (*adapter_comm)(struct aac_dev * dev, int comm);
510};
511
512/*
513 * Define which interrupt handler needs to be installed
514 */
515
516struct aac_driver_ident
517{
518 int (*init)(struct aac_dev *dev);
519 char * name;
520 char * vname;
521 char * model;
522 u16 channels;
523 int quirks;
524};
525/*
526 * Some adapter firmware needs communication memory
527 * below 2gig. This tells the init function to set the
528 * dma mask such that fib memory will be allocated where the
529 * adapter firmware can get to it.
530 */
531#define AAC_QUIRK_31BIT 0x0001
532
533/*
534 * Some adapter firmware, when the raid card's cache is turned off, can not
535 * split up scatter gathers in order to deal with the limits of the
536 * underlying CHIM. This limit is 34 scatter gather elements.
537 */
538#define AAC_QUIRK_34SG 0x0002
539
540/*
541 * This adapter is a slave (no Firmware)
542 */
543#define AAC_QUIRK_SLAVE 0x0004
544
545/*
546 * This adapter is a master.
547 */
548#define AAC_QUIRK_MASTER 0x0008
549
550/*
551 * Some adapter firmware perform poorly when it must split up scatter gathers
552 * in order to deal with the limits of the underlying CHIM. This limit in this
553 * class of adapters is 17 scatter gather elements.
554 */
555#define AAC_QUIRK_17SG 0x0010
556
557/*
558 * Some adapter firmware does not support 64 bit scsi passthrough
559 * commands.
560 */
561#define AAC_QUIRK_SCSI_32 0x0020
562
563/*
564 * The adapter interface specs all queues to be located in the same
565 * physically contiguous block. The host structure that defines the
566 * commuication queues will assume they are each a separate physically
567 * contiguous memory region that will support them all being one big
568 * contiguous block.
569 * There is a command and response queue for each level and direction of
570 * commuication. These regions are accessed by both the host and adapter.
571 */
572
573struct aac_queue {
574 u64 logical; /*address we give the adapter */
575 struct aac_entry *base; /*system virtual address */
576 struct aac_qhdr headers; /*producer,consumer q headers*/
577 u32 entries; /*Number of queue entries */
578 wait_queue_head_t qfull; /*Event to wait on if q full */
579 wait_queue_head_t cmdready; /*Cmd ready from the adapter */
580 /* This is only valid for adapter to host command queues. */
581 spinlock_t *lock; /* Spinlock for this queue must take this lock before accessing the lock */
582 spinlock_t lockdata; /* Actual lock (used only on one side of the lock) */
583 struct list_head cmdq; /* A queue of FIBs which need to be prcessed by the FS thread. This is */
584 /* only valid for command queues which receive entries from the adapter. */
585 u32 numpending; /* Number of entries on outstanding queue. */
586 struct aac_dev * dev; /* Back pointer to adapter structure */
587};
588
589/*
590 * Message queues. The order here is important, see also the
591 * queue type ordering
592 */
593
594struct aac_queue_block
595{
596 struct aac_queue queue[8];
597};
598
599/*
600 * SaP1 Message Unit Registers
601 */
602
603struct sa_drawbridge_CSR {
604 /* Offset | Name */
605 __le32 reserved[10]; /* 00h-27h | Reserved */
606 u8 LUT_Offset; /* 28h | Lookup Table Offset */
607 u8 reserved1[3]; /* 29h-2bh | Reserved */
608 __le32 LUT_Data; /* 2ch | Looup Table Data */
609 __le32 reserved2[26]; /* 30h-97h | Reserved */
610 __le16 PRICLEARIRQ; /* 98h | Primary Clear Irq */
611 __le16 SECCLEARIRQ; /* 9ah | Secondary Clear Irq */
612 __le16 PRISETIRQ; /* 9ch | Primary Set Irq */
613 __le16 SECSETIRQ; /* 9eh | Secondary Set Irq */
614 __le16 PRICLEARIRQMASK;/* a0h | Primary Clear Irq Mask */
615 __le16 SECCLEARIRQMASK;/* a2h | Secondary Clear Irq Mask */
616 __le16 PRISETIRQMASK; /* a4h | Primary Set Irq Mask */
617 __le16 SECSETIRQMASK; /* a6h | Secondary Set Irq Mask */
618 __le32 MAILBOX0; /* a8h | Scratchpad 0 */
619 __le32 MAILBOX1; /* ach | Scratchpad 1 */
620 __le32 MAILBOX2; /* b0h | Scratchpad 2 */
621 __le32 MAILBOX3; /* b4h | Scratchpad 3 */
622 __le32 MAILBOX4; /* b8h | Scratchpad 4 */
623 __le32 MAILBOX5; /* bch | Scratchpad 5 */
624 __le32 MAILBOX6; /* c0h | Scratchpad 6 */
625 __le32 MAILBOX7; /* c4h | Scratchpad 7 */
626 __le32 ROM_Setup_Data; /* c8h | Rom Setup and Data */
627 __le32 ROM_Control_Addr;/* cch | Rom Control and Address */
628 __le32 reserved3[12]; /* d0h-ffh | reserved */
629 __le32 LUT[64]; /* 100h-1ffh | Lookup Table Entries */
630};
631
632#define Mailbox0 SaDbCSR.MAILBOX0
633#define Mailbox1 SaDbCSR.MAILBOX1
634#define Mailbox2 SaDbCSR.MAILBOX2
635#define Mailbox3 SaDbCSR.MAILBOX3
636#define Mailbox4 SaDbCSR.MAILBOX4
637#define Mailbox5 SaDbCSR.MAILBOX5
638#define Mailbox6 SaDbCSR.MAILBOX6
639#define Mailbox7 SaDbCSR.MAILBOX7
640
641#define DoorbellReg_p SaDbCSR.PRISETIRQ
642#define DoorbellReg_s SaDbCSR.SECSETIRQ
643#define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ
644
645
646#define DOORBELL_0 0x0001
647#define DOORBELL_1 0x0002
648#define DOORBELL_2 0x0004
649#define DOORBELL_3 0x0008
650#define DOORBELL_4 0x0010
651#define DOORBELL_5 0x0020
652#define DOORBELL_6 0x0040
653
654
655#define PrintfReady DOORBELL_5
656#define PrintfDone DOORBELL_5
657
658struct sa_registers {
659 struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */
660};
661
662
663#define Sa_MINIPORT_REVISION 1
664
665#define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
666#define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
667#define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR))
668#define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
669
670/*
671 * Rx Message Unit Registers
672 */
673
674struct rx_mu_registers {
675 /* Local | PCI*| Name */
676 __le32 ARSR; /* 1300h | 00h | APIC Register Select Register */
677 __le32 reserved0; /* 1304h | 04h | Reserved */
678 __le32 AWR; /* 1308h | 08h | APIC Window Register */
679 __le32 reserved1; /* 130Ch | 0Ch | Reserved */
680 __le32 IMRx[2]; /* 1310h | 10h | Inbound Message Registers */
681 __le32 OMRx[2]; /* 1318h | 18h | Outbound Message Registers */
682 __le32 IDR; /* 1320h | 20h | Inbound Doorbell Register */
683 __le32 IISR; /* 1324h | 24h | Inbound Interrupt
684 Status Register */
685 __le32 IIMR; /* 1328h | 28h | Inbound Interrupt
686 Mask Register */
687 __le32 ODR; /* 132Ch | 2Ch | Outbound Doorbell Register */
688 __le32 OISR; /* 1330h | 30h | Outbound Interrupt
689 Status Register */
690 __le32 OIMR; /* 1334h | 34h | Outbound Interrupt
691 Mask Register */
692 __le32 reserved2; /* 1338h | 38h | Reserved */
693 __le32 reserved3; /* 133Ch | 3Ch | Reserved */
694 __le32 InboundQueue;/* 1340h | 40h | Inbound Queue Port relative to firmware */
695 __le32 OutboundQueue;/*1344h | 44h | Outbound Queue Port relative to firmware */
696 /* * Must access through ATU Inbound
697 Translation Window */
698};
699
700struct rx_inbound {
701 __le32 Mailbox[8];
702};
703
704#define INBOUNDDOORBELL_0 0x00000001
705#define INBOUNDDOORBELL_1 0x00000002
706#define INBOUNDDOORBELL_2 0x00000004
707#define INBOUNDDOORBELL_3 0x00000008
708#define INBOUNDDOORBELL_4 0x00000010
709#define INBOUNDDOORBELL_5 0x00000020
710#define INBOUNDDOORBELL_6 0x00000040
711
712#define OUTBOUNDDOORBELL_0 0x00000001
713#define OUTBOUNDDOORBELL_1 0x00000002
714#define OUTBOUNDDOORBELL_2 0x00000004
715#define OUTBOUNDDOORBELL_3 0x00000008
716#define OUTBOUNDDOORBELL_4 0x00000010
717
718#define InboundDoorbellReg MUnit.IDR
719#define OutboundDoorbellReg MUnit.ODR
720
721struct rx_registers {
722 struct rx_mu_registers MUnit; /* 1300h - 1347h */
723 __le32 reserved1[2]; /* 1348h - 134ch */
724 struct rx_inbound IndexRegs;
725};
726
727#define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR))
728#define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR))
729#define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR))
730#define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
731
732/*
733 * Rkt Message Unit Registers (same as Rx, except a larger reserve region)
734 */
735
736#define rkt_mu_registers rx_mu_registers
737#define rkt_inbound rx_inbound
738
739struct rkt_registers {
740 struct rkt_mu_registers MUnit; /* 1300h - 1347h */
741 __le32 reserved1[1006]; /* 1348h - 22fch */
742 struct rkt_inbound IndexRegs; /* 2300h - */
743};
744
745#define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR))
746#define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR))
747#define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR))
748#define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR))
749
750/*
751 * PMC SRC message unit registers
752 */
753
754#define src_inbound rx_inbound
755
756struct src_mu_registers {
757 /* PCI*| Name */
758 __le32 reserved0[8]; /* 00h | Reserved */
759 __le32 IDR; /* 20h | Inbound Doorbell Register */
760 __le32 IISR; /* 24h | Inbound Int. Status Register */
761 __le32 reserved1[3]; /* 28h | Reserved */
762 __le32 OIMR; /* 34h | Outbound Int. Mask Register */
763 __le32 reserved2[25]; /* 38h | Reserved */
764 __le32 ODR_R; /* 9ch | Outbound Doorbell Read */
765 __le32 ODR_C; /* a0h | Outbound Doorbell Clear */
766 __le32 reserved3[6]; /* a4h | Reserved */
767 __le32 OMR; /* bch | Outbound Message Register */
768 __le32 IQ_L; /* c0h | Inbound Queue (Low address) */
769 __le32 IQ_H; /* c4h | Inbound Queue (High address) */
770};
771
772struct src_registers {
773 struct src_mu_registers MUnit; /* 00h - c7h */
774 union {
775 struct {
776 __le32 reserved1[130790]; /* c8h - 7fc5fh */
777 struct src_inbound IndexRegs; /* 7fc60h */
778 } tupelo;
779 struct {
780 __le32 reserved1[974]; /* c8h - fffh */
781 struct src_inbound IndexRegs; /* 1000h */
782 } denali;
783 } u;
784};
785
786#define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR))
787#define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR))
788#define src_writeb(AEP, CSR, value) writeb(value, \
789 &((AEP)->regs.src.bar0->CSR))
790#define src_writel(AEP, CSR, value) writel(value, \
791 &((AEP)->regs.src.bar0->CSR))
792
793#define SRC_ODR_SHIFT 12
794#define SRC_IDR_SHIFT 9
795
796typedef void (*fib_callback)(void *ctxt, struct fib *fibctx);
797
798struct aac_fib_context {
799 s16 type; // used for verification of structure
800 s16 size;
801 u32 unique; // unique value representing this context
802 ulong jiffies; // used for cleanup - dmb changed to ulong
803 struct list_head next; // used to link context's into a linked list
804 struct semaphore wait_sem; // this is used to wait for the next fib to arrive.
805 int wait; // Set to true when thread is in WaitForSingleObject
806 unsigned long count; // total number of FIBs on FibList
807 struct list_head fib_list; // this holds fibs and their attachd hw_fibs
808};
809
810struct sense_data {
811 u8 error_code; /* 70h (current errors), 71h(deferred errors) */
812 u8 valid:1; /* A valid bit of one indicates that the information */
813 /* field contains valid information as defined in the
814 * SCSI-2 Standard.
815 */
816 u8 segment_number; /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */
817 u8 sense_key:4; /* Sense Key */
818 u8 reserved:1;
819 u8 ILI:1; /* Incorrect Length Indicator */
820 u8 EOM:1; /* End Of Medium - reserved for random access devices */
821 u8 filemark:1; /* Filemark - reserved for random access devices */
822
823 u8 information[4]; /* for direct-access devices, contains the unsigned
824 * logical block address or residue associated with
825 * the sense key
826 */
827 u8 add_sense_len; /* number of additional sense bytes to follow this field */
828 u8 cmnd_info[4]; /* not used */
829 u8 ASC; /* Additional Sense Code */
830 u8 ASCQ; /* Additional Sense Code Qualifier */
831 u8 FRUC; /* Field Replaceable Unit Code - not used */
832 u8 bit_ptr:3; /* indicates which byte of the CDB or parameter data
833 * was in error
834 */
835 u8 BPV:1; /* bit pointer valid (BPV): 1- indicates that
836 * the bit_ptr field has valid value
837 */
838 u8 reserved2:2;
839 u8 CD:1; /* command data bit: 1- illegal parameter in CDB.
840 * 0- illegal parameter in data.
841 */
842 u8 SKSV:1;
843 u8 field_ptr[2]; /* byte of the CDB or parameter data in error */
844};
845
846struct fsa_dev_info {
847 u64 last;
848 u64 size;
849 u32 type;
850 u32 config_waiting_on;
851 unsigned long config_waiting_stamp;
852 u16 queue_depth;
853 u8 config_needed;
854 u8 valid;
855 u8 ro;
856 u8 locked;
857 u8 deleted;
858 char devname[8];
859 struct sense_data sense_data;
860};
861
862struct fib {
863 void *next; /* this is used by the allocator */
864 s16 type;
865 s16 size;
866 /*
867 * The Adapter that this I/O is destined for.
868 */
869 struct aac_dev *dev;
870 /*
871 * This is the event the sendfib routine will wait on if the
872 * caller did not pass one and this is synch io.
873 */
874 struct semaphore event_wait;
875 spinlock_t event_lock;
876
877 u32 done; /* gets set to 1 when fib is complete */
878 fib_callback callback;
879 void *callback_data;
880 u32 flags; // u32 dmb was ulong
881 /*
882 * And for the internal issue/reply queues (we may be able
883 * to merge these two)
884 */
885 struct list_head fiblink;
886 void *data;
887 struct hw_fib *hw_fib_va; /* Actual shared object */
888 dma_addr_t hw_fib_pa; /* physical address of hw_fib*/
889};
890
891/*
892 * Adapter Information Block
893 *
894 * This is returned by the RequestAdapterInfo block
895 */
896
897struct aac_adapter_info
898{
899 __le32 platform;
900 __le32 cpu;
901 __le32 subcpu;
902 __le32 clock;
903 __le32 execmem;
904 __le32 buffermem;
905 __le32 totalmem;
906 __le32 kernelrev;
907 __le32 kernelbuild;
908 __le32 monitorrev;
909 __le32 monitorbuild;
910 __le32 hwrev;
911 __le32 hwbuild;
912 __le32 biosrev;
913 __le32 biosbuild;
914 __le32 cluster;
915 __le32 clusterchannelmask;
916 __le32 serial[2];
917 __le32 battery;
918 __le32 options;
919 __le32 OEM;
920};
921
922struct aac_supplement_adapter_info
923{
924 u8 AdapterTypeText[17+1];
925 u8 Pad[2];
926 __le32 FlashMemoryByteSize;
927 __le32 FlashImageId;
928 __le32 MaxNumberPorts;
929 __le32 Version;
930 __le32 FeatureBits;
931 u8 SlotNumber;
932 u8 ReservedPad0[3];
933 u8 BuildDate[12];
934 __le32 CurrentNumberPorts;
935 struct {
936 u8 AssemblyPn[8];
937 u8 FruPn[8];
938 u8 BatteryFruPn[8];
939 u8 EcVersionString[8];
940 u8 Tsid[12];
941 } VpdInfo;
942 __le32 FlashFirmwareRevision;
943 __le32 FlashFirmwareBuild;
944 __le32 RaidTypeMorphOptions;
945 __le32 FlashFirmwareBootRevision;
946 __le32 FlashFirmwareBootBuild;
947 u8 MfgPcbaSerialNo[12];
948 u8 MfgWWNName[8];
949 __le32 SupportedOptions2;
950 __le32 StructExpansion;
951 /* StructExpansion == 1 */
952 __le32 FeatureBits3;
953 __le32 SupportedPerformanceModes;
954 __le32 ReservedForFutureGrowth[80];
955};
956#define AAC_FEATURE_FALCON cpu_to_le32(0x00000010)
957#define AAC_FEATURE_JBOD cpu_to_le32(0x08000000)
958/* SupportedOptions2 */
959#define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001)
960#define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002)
961#define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004)
962#define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000)
963#define AAC_SIS_VERSION_V3 3
964#define AAC_SIS_SLOT_UNKNOWN 0xFF
965
966#define GetBusInfo 0x00000009
967struct aac_bus_info {
968 __le32 Command; /* VM_Ioctl */
969 __le32 ObjType; /* FT_DRIVE */
970 __le32 MethodId; /* 1 = SCSI Layer */
971 __le32 ObjectId; /* Handle */
972 __le32 CtlCmd; /* GetBusInfo */
973};
974
975struct aac_bus_info_response {
976 __le32 Status; /* ST_OK */
977 __le32 ObjType;
978 __le32 MethodId; /* unused */
979 __le32 ObjectId; /* unused */
980 __le32 CtlCmd; /* unused */
981 __le32 ProbeComplete;
982 __le32 BusCount;
983 __le32 TargetsPerBus;
984 u8 InitiatorBusId[10];
985 u8 BusValid[10];
986};
987
988/*
989 * Battery platforms
990 */
991#define AAC_BAT_REQ_PRESENT (1)
992#define AAC_BAT_REQ_NOTPRESENT (2)
993#define AAC_BAT_OPT_PRESENT (3)
994#define AAC_BAT_OPT_NOTPRESENT (4)
995#define AAC_BAT_NOT_SUPPORTED (5)
996/*
997 * cpu types
998 */
999#define AAC_CPU_SIMULATOR (1)
1000#define AAC_CPU_I960 (2)
1001#define AAC_CPU_STRONGARM (3)
1002
1003/*
1004 * Supported Options
1005 */
1006#define AAC_OPT_SNAPSHOT cpu_to_le32(1)
1007#define AAC_OPT_CLUSTERS cpu_to_le32(1<<1)
1008#define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2)
1009#define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3)
1010#define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4)
1011#define AAC_OPT_RAID50 cpu_to_le32(1<<5)
1012#define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6)
1013#define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7)
1014#define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8)
1015#define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9)
1016#define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10)
1017#define AAC_OPT_ALARM cpu_to_le32(1<<11)
1018#define AAC_OPT_NONDASD cpu_to_le32(1<<12)
1019#define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13)
1020#define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14)
1021#define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16)
1022#define AAC_OPT_NEW_COMM cpu_to_le32(1<<17)
1023#define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18)
1024#define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28)
1025#define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29)
1026#define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30)
1027#define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31)
1028
1029
1030struct aac_dev
1031{
1032 struct list_head entry;
1033 const char *name;
1034 int id;
1035
1036 /*
1037 * negotiated FIB settings
1038 */
1039 unsigned max_fib_size;
1040 unsigned sg_tablesize;
1041 unsigned max_num_aif;
1042
1043 /*
1044 * Map for 128 fib objects (64k)
1045 */
1046 dma_addr_t hw_fib_pa;
1047 struct hw_fib *hw_fib_va;
1048 struct hw_fib *aif_base_va;
1049 /*
1050 * Fib Headers
1051 */
1052 struct fib *fibs;
1053
1054 struct fib *free_fib;
1055 spinlock_t fib_lock;
1056
1057 struct aac_queue_block *queues;
1058 /*
1059 * The user API will use an IOCTL to register itself to receive
1060 * FIBs from the adapter. The following list is used to keep
1061 * track of all the threads that have requested these FIBs. The
1062 * mutex is used to synchronize access to all data associated
1063 * with the adapter fibs.
1064 */
1065 struct list_head fib_list;
1066
1067 struct adapter_ops a_ops;
1068 unsigned long fsrev; /* Main driver's revision number */
1069
1070 resource_size_t base_start; /* main IO base */
1071 resource_size_t dbg_base; /* address of UART
1072 * debug buffer */
1073
1074 resource_size_t base_size, dbg_size; /* Size of
1075 * mapped in region */
1076
1077 struct aac_init *init; /* Holds initialization info to communicate with adapter */
1078 dma_addr_t init_pa; /* Holds physical address of the init struct */
1079
1080 u32 *host_rrq; /* response queue
1081 * if AAC_COMM_MESSAGE_TYPE1 */
1082
1083 dma_addr_t host_rrq_pa; /* phys. address */
1084 u32 host_rrq_idx; /* index into rrq buffer */
1085
1086 struct pci_dev *pdev; /* Our PCI interface */
1087 void * printfbuf; /* pointer to buffer used for printf's from the adapter */
1088 void * comm_addr; /* Base address of Comm area */
1089 dma_addr_t comm_phys; /* Physical Address of Comm area */
1090 size_t comm_size;
1091
1092 struct Scsi_Host *scsi_host_ptr;
1093 int maximum_num_containers;
1094 int maximum_num_physicals;
1095 int maximum_num_channels;
1096 struct fsa_dev_info *fsa_dev;
1097 struct task_struct *thread;
1098 int cardtype;
1099
1100 /*
1101 * The following is the device specific extension.
1102 */
1103#ifndef AAC_MIN_FOOTPRINT_SIZE
1104# define AAC_MIN_FOOTPRINT_SIZE 8192
1105# define AAC_MIN_SRC_BAR0_SIZE 0x400000
1106# define AAC_MIN_SRC_BAR1_SIZE 0x800
1107# define AAC_MIN_SRCV_BAR0_SIZE 0x100000
1108# define AAC_MIN_SRCV_BAR1_SIZE 0x400
1109#endif
1110 union
1111 {
1112 struct sa_registers __iomem *sa;
1113 struct rx_registers __iomem *rx;
1114 struct rkt_registers __iomem *rkt;
1115 struct {
1116 struct src_registers __iomem *bar0;
1117 char __iomem *bar1;
1118 } src;
1119 } regs;
1120 volatile void __iomem *base, *dbg_base_mapped;
1121 volatile struct rx_inbound __iomem *IndexRegs;
1122 u32 OIMR; /* Mask Register Cache */
1123 /*
1124 * AIF thread states
1125 */
1126 u32 aif_thread;
1127 struct aac_adapter_info adapter_info;
1128 struct aac_supplement_adapter_info supplement_adapter_info;
1129 /* These are in adapter info but they are in the io flow so
1130 * lets break them out so we don't have to do an AND to check them
1131 */
1132 u8 nondasd_support;
1133 u8 jbod;
1134 u8 cache_protected;
1135 u8 dac_support;
1136 u8 needs_dac;
1137 u8 raid_scsi_mode;
1138 u8 comm_interface;
1139# define AAC_COMM_PRODUCER 0
1140# define AAC_COMM_MESSAGE 1
1141# define AAC_COMM_MESSAGE_TYPE1 3
1142# define AAC_COMM_MESSAGE_TYPE2 4
1143 u8 raw_io_interface;
1144 u8 raw_io_64;
1145 u8 printf_enabled;
1146 u8 in_reset;
1147 u8 msi;
1148 int management_fib_count;
1149 spinlock_t manage_lock;
1150 spinlock_t sync_lock;
1151 int sync_mode;
1152 struct fib *sync_fib;
1153 struct list_head sync_fib_list;
1154};
1155
1156#define aac_adapter_interrupt(dev) \
1157 (dev)->a_ops.adapter_interrupt(dev)
1158
1159#define aac_adapter_notify(dev, event) \
1160 (dev)->a_ops.adapter_notify(dev, event)
1161
1162#define aac_adapter_disable_int(dev) \
1163 (dev)->a_ops.adapter_disable_int(dev)
1164
1165#define aac_adapter_enable_int(dev) \
1166 (dev)->a_ops.adapter_enable_int(dev)
1167
1168#define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \
1169 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4)
1170
1171#define aac_adapter_check_health(dev) \
1172 (dev)->a_ops.adapter_check_health(dev)
1173
1174#define aac_adapter_restart(dev,bled) \
1175 (dev)->a_ops.adapter_restart(dev,bled)
1176
1177#define aac_adapter_ioremap(dev, size) \
1178 (dev)->a_ops.adapter_ioremap(dev, size)
1179
1180#define aac_adapter_deliver(fib) \
1181 ((fib)->dev)->a_ops.adapter_deliver(fib)
1182
1183#define aac_adapter_bounds(dev,cmd,lba) \
1184 dev->a_ops.adapter_bounds(dev,cmd,lba)
1185
1186#define aac_adapter_read(fib,cmd,lba,count) \
1187 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count)
1188
1189#define aac_adapter_write(fib,cmd,lba,count,fua) \
1190 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua)
1191
1192#define aac_adapter_scsi(fib,cmd) \
1193 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd)
1194
1195#define aac_adapter_comm(dev,comm) \
1196 (dev)->a_ops.adapter_comm(dev, comm)
1197
1198#define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001)
1199#define FIB_CONTEXT_FLAG (0x00000002)
1200#define FIB_CONTEXT_FLAG_WAIT (0x00000004)
1201#define FIB_CONTEXT_FLAG_FASTRESP (0x00000008)
1202
1203/*
1204 * Define the command values
1205 */
1206
1207#define Null 0
1208#define GetAttributes 1
1209#define SetAttributes 2
1210#define Lookup 3
1211#define ReadLink 4
1212#define Read 5
1213#define Write 6
1214#define Create 7
1215#define MakeDirectory 8
1216#define SymbolicLink 9
1217#define MakeNode 10
1218#define Removex 11
1219#define RemoveDirectoryx 12
1220#define Rename 13
1221#define Link 14
1222#define ReadDirectory 15
1223#define ReadDirectoryPlus 16
1224#define FileSystemStatus 17
1225#define FileSystemInfo 18
1226#define PathConfigure 19
1227#define Commit 20
1228#define Mount 21
1229#define UnMount 22
1230#define Newfs 23
1231#define FsCheck 24
1232#define FsSync 25
1233#define SimReadWrite 26
1234#define SetFileSystemStatus 27
1235#define BlockRead 28
1236#define BlockWrite 29
1237#define NvramIoctl 30
1238#define FsSyncWait 31
1239#define ClearArchiveBit 32
1240#define SetAcl 33
1241#define GetAcl 34
1242#define AssignAcl 35
1243#define FaultInsertion 36 /* Fault Insertion Command */
1244#define CrazyCache 37 /* Crazycache */
1245
1246#define MAX_FSACOMMAND_NUM 38
1247
1248
1249/*
1250 * Define the status returns. These are very unixlike although
1251 * most are not in fact used
1252 */
1253
1254#define ST_OK 0
1255#define ST_PERM 1
1256#define ST_NOENT 2
1257#define ST_IO 5
1258#define ST_NXIO 6
1259#define ST_E2BIG 7
1260#define ST_ACCES 13
1261#define ST_EXIST 17
1262#define ST_XDEV 18
1263#define ST_NODEV 19
1264#define ST_NOTDIR 20
1265#define ST_ISDIR 21
1266#define ST_INVAL 22
1267#define ST_FBIG 27
1268#define ST_NOSPC 28
1269#define ST_ROFS 30
1270#define ST_MLINK 31
1271#define ST_WOULDBLOCK 35
1272#define ST_NAMETOOLONG 63
1273#define ST_NOTEMPTY 66
1274#define ST_DQUOT 69
1275#define ST_STALE 70
1276#define ST_REMOTE 71
1277#define ST_NOT_READY 72
1278#define ST_BADHANDLE 10001
1279#define ST_NOT_SYNC 10002
1280#define ST_BAD_COOKIE 10003
1281#define ST_NOTSUPP 10004
1282#define ST_TOOSMALL 10005
1283#define ST_SERVERFAULT 10006
1284#define ST_BADTYPE 10007
1285#define ST_JUKEBOX 10008
1286#define ST_NOTMOUNTED 10009
1287#define ST_MAINTMODE 10010
1288#define ST_STALEACL 10011
1289
1290/*
1291 * On writes how does the client want the data written.
1292 */
1293
1294#define CACHE_CSTABLE 1
1295#define CACHE_UNSTABLE 2
1296
1297/*
1298 * Lets the client know at which level the data was committed on
1299 * a write request
1300 */
1301
1302#define CMFILE_SYNCH_NVRAM 1
1303#define CMDATA_SYNCH_NVRAM 2
1304#define CMFILE_SYNCH 3
1305#define CMDATA_SYNCH 4
1306#define CMUNSTABLE 5
1307
1308#define RIO_TYPE_WRITE 0x0000
1309#define RIO_TYPE_READ 0x0001
1310#define RIO_SUREWRITE 0x0008
1311
1312#define RIO2_IO_TYPE 0x0003
1313#define RIO2_IO_TYPE_WRITE 0x0000
1314#define RIO2_IO_TYPE_READ 0x0001
1315#define RIO2_IO_TYPE_VERIFY 0x0002
1316#define RIO2_IO_ERROR 0x0004
1317#define RIO2_IO_SUREWRITE 0x0008
1318#define RIO2_SGL_CONFORMANT 0x0010
1319#define RIO2_SG_FORMAT 0xF000
1320#define RIO2_SG_FORMAT_ARC 0x0000
1321#define RIO2_SG_FORMAT_SRL 0x1000
1322#define RIO2_SG_FORMAT_IEEE1212 0x2000
1323
1324struct aac_read
1325{
1326 __le32 command;
1327 __le32 cid;
1328 __le32 block;
1329 __le32 count;
1330 struct sgmap sg; // Must be last in struct because it is variable
1331};
1332
1333struct aac_read64
1334{
1335 __le32 command;
1336 __le16 cid;
1337 __le16 sector_count;
1338 __le32 block;
1339 __le16 pad;
1340 __le16 flags;
1341 struct sgmap64 sg; // Must be last in struct because it is variable
1342};
1343
1344struct aac_read_reply
1345{
1346 __le32 status;
1347 __le32 count;
1348};
1349
1350struct aac_write
1351{
1352 __le32 command;
1353 __le32 cid;
1354 __le32 block;
1355 __le32 count;
1356 __le32 stable; // Not used
1357 struct sgmap sg; // Must be last in struct because it is variable
1358};
1359
1360struct aac_write64
1361{
1362 __le32 command;
1363 __le16 cid;
1364 __le16 sector_count;
1365 __le32 block;
1366 __le16 pad;
1367 __le16 flags;
1368 struct sgmap64 sg; // Must be last in struct because it is variable
1369};
1370struct aac_write_reply
1371{
1372 __le32 status;
1373 __le32 count;
1374 __le32 committed;
1375};
1376
1377struct aac_raw_io
1378{
1379 __le32 block[2];
1380 __le32 count;
1381 __le16 cid;
1382 __le16 flags; /* 00 W, 01 R */
1383 __le16 bpTotal; /* reserved for F/W use */
1384 __le16 bpComplete; /* reserved for F/W use */
1385 struct sgmapraw sg;
1386};
1387
1388struct aac_raw_io2 {
1389 __le32 blockLow;
1390 __le32 blockHigh;
1391 __le32 byteCount;
1392 __le16 cid;
1393 __le16 flags; /* RIO2 flags */
1394 __le32 sgeFirstSize; /* size of first sge el. */
1395 __le32 sgeNominalSize; /* size of 2nd sge el. (if conformant) */
1396 u8 sgeCnt; /* only 8 bits required */
1397 u8 bpTotal; /* reserved for F/W use */
1398 u8 bpComplete; /* reserved for F/W use */
1399 u8 sgeFirstIndex; /* reserved for F/W use */
1400 u8 unused[4];
1401 struct sge_ieee1212 sge[1];
1402};
1403
1404#define CT_FLUSH_CACHE 129
1405struct aac_synchronize {
1406 __le32 command; /* VM_ContainerConfig */
1407 __le32 type; /* CT_FLUSH_CACHE */
1408 __le32 cid;
1409 __le32 parm1;
1410 __le32 parm2;
1411 __le32 parm3;
1412 __le32 parm4;
1413 __le32 count; /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */
1414};
1415
1416struct aac_synchronize_reply {
1417 __le32 dummy0;
1418 __le32 dummy1;
1419 __le32 status; /* CT_OK */
1420 __le32 parm1;
1421 __le32 parm2;
1422 __le32 parm3;
1423 __le32 parm4;
1424 __le32 parm5;
1425 u8 data[16];
1426};
1427
1428#define CT_POWER_MANAGEMENT 245
1429#define CT_PM_START_UNIT 2
1430#define CT_PM_STOP_UNIT 3
1431#define CT_PM_UNIT_IMMEDIATE 1
1432struct aac_power_management {
1433 __le32 command; /* VM_ContainerConfig */
1434 __le32 type; /* CT_POWER_MANAGEMENT */
1435 __le32 sub; /* CT_PM_* */
1436 __le32 cid;
1437 __le32 parm; /* CT_PM_sub_* */
1438};
1439
1440#define CT_PAUSE_IO 65
1441#define CT_RELEASE_IO 66
1442struct aac_pause {
1443 __le32 command; /* VM_ContainerConfig */
1444 __le32 type; /* CT_PAUSE_IO */
1445 __le32 timeout; /* 10ms ticks */
1446 __le32 min;
1447 __le32 noRescan;
1448 __le32 parm3;
1449 __le32 parm4;
1450 __le32 count; /* sizeof(((struct aac_pause_reply *)NULL)->data) */
1451};
1452
1453struct aac_srb
1454{
1455 __le32 function;
1456 __le32 channel;
1457 __le32 id;
1458 __le32 lun;
1459 __le32 timeout;
1460 __le32 flags;
1461 __le32 count; // Data xfer size
1462 __le32 retry_limit;
1463 __le32 cdb_size;
1464 u8 cdb[16];
1465 struct sgmap sg;
1466};
1467
1468/*
1469 * This and associated data structs are used by the
1470 * ioctl caller and are in cpu order.
1471 */
1472struct user_aac_srb
1473{
1474 u32 function;
1475 u32 channel;
1476 u32 id;
1477 u32 lun;
1478 u32 timeout;
1479 u32 flags;
1480 u32 count; // Data xfer size
1481 u32 retry_limit;
1482 u32 cdb_size;
1483 u8 cdb[16];
1484 struct user_sgmap sg;
1485};
1486
1487#define AAC_SENSE_BUFFERSIZE 30
1488
1489struct aac_srb_reply
1490{
1491 __le32 status;
1492 __le32 srb_status;
1493 __le32 scsi_status;
1494 __le32 data_xfer_length;
1495 __le32 sense_data_size;
1496 u8 sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE
1497};
1498/*
1499 * SRB Flags
1500 */
1501#define SRB_NoDataXfer 0x0000
1502#define SRB_DisableDisconnect 0x0004
1503#define SRB_DisableSynchTransfer 0x0008
1504#define SRB_BypassFrozenQueue 0x0010
1505#define SRB_DisableAutosense 0x0020
1506#define SRB_DataIn 0x0040
1507#define SRB_DataOut 0x0080
1508
1509/*
1510 * SRB Functions - set in aac_srb->function
1511 */
1512#define SRBF_ExecuteScsi 0x0000
1513#define SRBF_ClaimDevice 0x0001
1514#define SRBF_IO_Control 0x0002
1515#define SRBF_ReceiveEvent 0x0003
1516#define SRBF_ReleaseQueue 0x0004
1517#define SRBF_AttachDevice 0x0005
1518#define SRBF_ReleaseDevice 0x0006
1519#define SRBF_Shutdown 0x0007
1520#define SRBF_Flush 0x0008
1521#define SRBF_AbortCommand 0x0010
1522#define SRBF_ReleaseRecovery 0x0011
1523#define SRBF_ResetBus 0x0012
1524#define SRBF_ResetDevice 0x0013
1525#define SRBF_TerminateIO 0x0014
1526#define SRBF_FlushQueue 0x0015
1527#define SRBF_RemoveDevice 0x0016
1528#define SRBF_DomainValidation 0x0017
1529
1530/*
1531 * SRB SCSI Status - set in aac_srb->scsi_status
1532 */
1533#define SRB_STATUS_PENDING 0x00
1534#define SRB_STATUS_SUCCESS 0x01
1535#define SRB_STATUS_ABORTED 0x02
1536#define SRB_STATUS_ABORT_FAILED 0x03
1537#define SRB_STATUS_ERROR 0x04
1538#define SRB_STATUS_BUSY 0x05
1539#define SRB_STATUS_INVALID_REQUEST 0x06
1540#define SRB_STATUS_INVALID_PATH_ID 0x07
1541#define SRB_STATUS_NO_DEVICE 0x08
1542#define SRB_STATUS_TIMEOUT 0x09
1543#define SRB_STATUS_SELECTION_TIMEOUT 0x0A
1544#define SRB_STATUS_COMMAND_TIMEOUT 0x0B
1545#define SRB_STATUS_MESSAGE_REJECTED 0x0D
1546#define SRB_STATUS_BUS_RESET 0x0E
1547#define SRB_STATUS_PARITY_ERROR 0x0F
1548#define SRB_STATUS_REQUEST_SENSE_FAILED 0x10
1549#define SRB_STATUS_NO_HBA 0x11
1550#define SRB_STATUS_DATA_OVERRUN 0x12
1551#define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13
1552#define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14
1553#define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15
1554#define SRB_STATUS_REQUEST_FLUSHED 0x16
1555#define SRB_STATUS_DELAYED_RETRY 0x17
1556#define SRB_STATUS_INVALID_LUN 0x20
1557#define SRB_STATUS_INVALID_TARGET_ID 0x21
1558#define SRB_STATUS_BAD_FUNCTION 0x22
1559#define SRB_STATUS_ERROR_RECOVERY 0x23
1560#define SRB_STATUS_NOT_STARTED 0x24
1561#define SRB_STATUS_NOT_IN_USE 0x30
1562#define SRB_STATUS_FORCE_ABORT 0x31
1563#define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32
1564
1565/*
1566 * Object-Server / Volume-Manager Dispatch Classes
1567 */
1568
1569#define VM_Null 0
1570#define VM_NameServe 1
1571#define VM_ContainerConfig 2
1572#define VM_Ioctl 3
1573#define VM_FilesystemIoctl 4
1574#define VM_CloseAll 5
1575#define VM_CtBlockRead 6
1576#define VM_CtBlockWrite 7
1577#define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */
1578#define VM_SliceBlockWrite 9
1579#define VM_DriveBlockRead 10 /* raw access to physical devices */
1580#define VM_DriveBlockWrite 11
1581#define VM_EnclosureMgt 12 /* enclosure management */
1582#define VM_Unused 13 /* used to be diskset management */
1583#define VM_CtBlockVerify 14
1584#define VM_CtPerf 15 /* performance test */
1585#define VM_CtBlockRead64 16
1586#define VM_CtBlockWrite64 17
1587#define VM_CtBlockVerify64 18
1588#define VM_CtHostRead64 19
1589#define VM_CtHostWrite64 20
1590#define VM_DrvErrTblLog 21
1591#define VM_NameServe64 22
1592
1593#define MAX_VMCOMMAND_NUM 23 /* used for sizing stats array - leave last */
1594
1595/*
1596 * Descriptive information (eg, vital stats)
1597 * that a content manager might report. The
1598 * FileArray filesystem component is one example
1599 * of a content manager. Raw mode might be
1600 * another.
1601 */
1602
1603struct aac_fsinfo {
1604 __le32 fsTotalSize; /* Consumed by fs, incl. metadata */
1605 __le32 fsBlockSize;
1606 __le32 fsFragSize;
1607 __le32 fsMaxExtendSize;
1608 __le32 fsSpaceUnits;
1609 __le32 fsMaxNumFiles;
1610 __le32 fsNumFreeFiles;
1611 __le32 fsInodeDensity;
1612}; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */
1613
1614union aac_contentinfo {
1615 struct aac_fsinfo filesys; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */
1616};
1617
1618/*
1619 * Query for Container Configuration Status
1620 */
1621
1622#define CT_GET_CONFIG_STATUS 147
1623struct aac_get_config_status {
1624 __le32 command; /* VM_ContainerConfig */
1625 __le32 type; /* CT_GET_CONFIG_STATUS */
1626 __le32 parm1;
1627 __le32 parm2;
1628 __le32 parm3;
1629 __le32 parm4;
1630 __le32 parm5;
1631 __le32 count; /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */
1632};
1633
1634#define CFACT_CONTINUE 0
1635#define CFACT_PAUSE 1
1636#define CFACT_ABORT 2
1637struct aac_get_config_status_resp {
1638 __le32 response; /* ST_OK */
1639 __le32 dummy0;
1640 __le32 status; /* CT_OK */
1641 __le32 parm1;
1642 __le32 parm2;
1643 __le32 parm3;
1644 __le32 parm4;
1645 __le32 parm5;
1646 struct {
1647 __le32 action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */
1648 __le16 flags;
1649 __le16 count;
1650 } data;
1651};
1652
1653/*
1654 * Accept the configuration as-is
1655 */
1656
1657#define CT_COMMIT_CONFIG 152
1658
1659struct aac_commit_config {
1660 __le32 command; /* VM_ContainerConfig */
1661 __le32 type; /* CT_COMMIT_CONFIG */
1662};
1663
1664/*
1665 * Query for Container Configuration Status
1666 */
1667
1668#define CT_GET_CONTAINER_COUNT 4
1669struct aac_get_container_count {
1670 __le32 command; /* VM_ContainerConfig */
1671 __le32 type; /* CT_GET_CONTAINER_COUNT */
1672};
1673
1674struct aac_get_container_count_resp {
1675 __le32 response; /* ST_OK */
1676 __le32 dummy0;
1677 __le32 MaxContainers;
1678 __le32 ContainerSwitchEntries;
1679 __le32 MaxPartitions;
1680};
1681
1682
1683/*
1684 * Query for "mountable" objects, ie, objects that are typically
1685 * associated with a drive letter on the client (host) side.
1686 */
1687
1688struct aac_mntent {
1689 __le32 oid;
1690 u8 name[16]; /* if applicable */
1691 struct creation_info create_info; /* if applicable */
1692 __le32 capacity;
1693 __le32 vol; /* substrate structure */
1694 __le32 obj; /* FT_FILESYS, etc. */
1695 __le32 state; /* unready for mounting,
1696 readonly, etc. */
1697 union aac_contentinfo fileinfo; /* Info specific to content
1698 manager (eg, filesystem) */
1699 __le32 altoid; /* != oid <==> snapshot or
1700 broken mirror exists */
1701 __le32 capacityhigh;
1702};
1703
1704#define FSCS_NOTCLEAN 0x0001 /* fsck is necessary before mounting */
1705#define FSCS_READONLY 0x0002 /* possible result of broken mirror */
1706#define FSCS_HIDDEN 0x0004 /* should be ignored - set during a clear */
1707#define FSCS_NOT_READY 0x0008 /* Array spinning up to fulfil request */
1708
1709struct aac_query_mount {
1710 __le32 command;
1711 __le32 type;
1712 __le32 count;
1713};
1714
1715struct aac_mount {
1716 __le32 status;
1717 __le32 type; /* should be same as that requested */
1718 __le32 count;
1719 struct aac_mntent mnt[1];
1720};
1721
1722#define CT_READ_NAME 130
1723struct aac_get_name {
1724 __le32 command; /* VM_ContainerConfig */
1725 __le32 type; /* CT_READ_NAME */
1726 __le32 cid;
1727 __le32 parm1;
1728 __le32 parm2;
1729 __le32 parm3;
1730 __le32 parm4;
1731 __le32 count; /* sizeof(((struct aac_get_name_resp *)NULL)->data) */
1732};
1733
1734struct aac_get_name_resp {
1735 __le32 dummy0;
1736 __le32 dummy1;
1737 __le32 status; /* CT_OK */
1738 __le32 parm1;
1739 __le32 parm2;
1740 __le32 parm3;
1741 __le32 parm4;
1742 __le32 parm5;
1743 u8 data[16];
1744};
1745
1746#define CT_CID_TO_32BITS_UID 165
1747struct aac_get_serial {
1748 __le32 command; /* VM_ContainerConfig */
1749 __le32 type; /* CT_CID_TO_32BITS_UID */
1750 __le32 cid;
1751};
1752
1753struct aac_get_serial_resp {
1754 __le32 dummy0;
1755 __le32 dummy1;
1756 __le32 status; /* CT_OK */
1757 __le32 uid;
1758};
1759
1760/*
1761 * The following command is sent to shut down each container.
1762 */
1763
1764struct aac_close {
1765 __le32 command;
1766 __le32 cid;
1767};
1768
1769struct aac_query_disk
1770{
1771 s32 cnum;
1772 s32 bus;
1773 s32 id;
1774 s32 lun;
1775 u32 valid;
1776 u32 locked;
1777 u32 deleted;
1778 s32 instance;
1779 s8 name[10];
1780 u32 unmapped;
1781};
1782
1783struct aac_delete_disk {
1784 u32 disknum;
1785 u32 cnum;
1786};
1787
1788struct fib_ioctl
1789{
1790 u32 fibctx;
1791 s32 wait;
1792 char __user *fib;
1793};
1794
1795struct revision
1796{
1797 u32 compat;
1798 __le32 version;
1799 __le32 build;
1800};
1801
1802
1803/*
1804 * Ugly - non Linux like ioctl coding for back compat.
1805 */
1806
1807#define CTL_CODE(function, method) ( \
1808 (4<< 16) | ((function) << 2) | (method) \
1809)
1810
1811/*
1812 * Define the method codes for how buffers are passed for I/O and FS
1813 * controls
1814 */
1815
1816#define METHOD_BUFFERED 0
1817#define METHOD_NEITHER 3
1818
1819/*
1820 * Filesystem ioctls
1821 */
1822
1823#define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED)
1824#define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED)
1825#define FSACTL_DELETE_DISK 0x163
1826#define FSACTL_QUERY_DISK 0x173
1827#define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED)
1828#define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED)
1829#define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED)
1830#define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED)
1831#define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED)
1832#define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER)
1833#define FSACTL_GET_CONTAINERS 2131
1834#define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED)
1835
1836
1837struct aac_common
1838{
1839 /*
1840 * If this value is set to 1 then interrupt moderation will occur
1841 * in the base commuication support.
1842 */
1843 u32 irq_mod;
1844 u32 peak_fibs;
1845 u32 zero_fibs;
1846 u32 fib_timeouts;
1847 /*
1848 * Statistical counters in debug mode
1849 */
1850#ifdef DBG
1851 u32 FibsSent;
1852 u32 FibRecved;
1853 u32 NoResponseSent;
1854 u32 NoResponseRecved;
1855 u32 AsyncSent;
1856 u32 AsyncRecved;
1857 u32 NormalSent;
1858 u32 NormalRecved;
1859#endif
1860};
1861
1862extern struct aac_common aac_config;
1863
1864
1865/*
1866 * The following macro is used when sending and receiving FIBs. It is
1867 * only used for debugging.
1868 */
1869
1870#ifdef DBG
1871#define FIB_COUNTER_INCREMENT(counter) (counter)++
1872#else
1873#define FIB_COUNTER_INCREMENT(counter)
1874#endif
1875
1876/*
1877 * Adapter direct commands
1878 * Monitor/Kernel API
1879 */
1880
1881#define BREAKPOINT_REQUEST 0x00000004
1882#define INIT_STRUCT_BASE_ADDRESS 0x00000005
1883#define READ_PERMANENT_PARAMETERS 0x0000000a
1884#define WRITE_PERMANENT_PARAMETERS 0x0000000b
1885#define HOST_CRASHING 0x0000000d
1886#define SEND_SYNCHRONOUS_FIB 0x0000000c
1887#define COMMAND_POST_RESULTS 0x00000014
1888#define GET_ADAPTER_PROPERTIES 0x00000019
1889#define GET_DRIVER_BUFFER_PROPERTIES 0x00000023
1890#define RCV_TEMP_READINGS 0x00000025
1891#define GET_COMM_PREFERRED_SETTINGS 0x00000026
1892#define IOP_RESET 0x00001000
1893#define IOP_RESET_ALWAYS 0x00001001
1894#define RE_INIT_ADAPTER 0x000000ee
1895
1896/*
1897 * Adapter Status Register
1898 *
1899 * Phase Staus mailbox is 32bits:
1900 * <31:16> = Phase Status
1901 * <15:0> = Phase
1902 *
1903 * The adapter reports is present state through the phase. Only
1904 * a single phase should be ever be set. Each phase can have multiple
1905 * phase status bits to provide more detailed information about the
1906 * state of the board. Care should be taken to ensure that any phase
1907 * status bits that are set when changing the phase are also valid
1908 * for the new phase or be cleared out. Adapter software (monitor,
1909 * iflash, kernel) is responsible for properly maintining the phase
1910 * status mailbox when it is running.
1911 *
1912 * MONKER_API Phases
1913 *
1914 * Phases are bit oriented. It is NOT valid to have multiple bits set
1915 */
1916
1917#define SELF_TEST_FAILED 0x00000004
1918#define MONITOR_PANIC 0x00000020
1919#define KERNEL_UP_AND_RUNNING 0x00000080
1920#define KERNEL_PANIC 0x00000100
1921#define FLASH_UPD_PENDING 0x00002000
1922#define FLASH_UPD_SUCCESS 0x00004000
1923#define FLASH_UPD_FAILED 0x00008000
1924#define FWUPD_TIMEOUT (5 * 60)
1925
1926/*
1927 * Doorbell bit defines
1928 */
1929
1930#define DoorBellSyncCmdAvailable (1<<0) /* Host -> Adapter */
1931#define DoorBellPrintfDone (1<<5) /* Host -> Adapter */
1932#define DoorBellAdapterNormCmdReady (1<<1) /* Adapter -> Host */
1933#define DoorBellAdapterNormRespReady (1<<2) /* Adapter -> Host */
1934#define DoorBellAdapterNormCmdNotFull (1<<3) /* Adapter -> Host */
1935#define DoorBellAdapterNormRespNotFull (1<<4) /* Adapter -> Host */
1936#define DoorBellPrintfReady (1<<5) /* Adapter -> Host */
1937#define DoorBellAifPending (1<<6) /* Adapter -> Host */
1938
1939/* PMC specific outbound doorbell bits */
1940#define PmDoorBellResponseSent (1<<1) /* Adapter -> Host */
1941
1942/*
1943 * For FIB communication, we need all of the following things
1944 * to send back to the user.
1945 */
1946
1947#define AifCmdEventNotify 1 /* Notify of event */
1948#define AifEnConfigChange 3 /* Adapter configuration change */
1949#define AifEnContainerChange 4 /* Container configuration change */
1950#define AifEnDeviceFailure 5 /* SCSI device failed */
1951#define AifEnEnclosureManagement 13 /* EM_DRIVE_* */
1952#define EM_DRIVE_INSERTION 31
1953#define EM_DRIVE_REMOVAL 32
1954#define AifEnBatteryEvent 14 /* Change in Battery State */
1955#define AifEnAddContainer 15 /* A new array was created */
1956#define AifEnDeleteContainer 16 /* A container was deleted */
1957#define AifEnExpEvent 23 /* Firmware Event Log */
1958#define AifExeFirmwarePanic 3 /* Firmware Event Panic */
1959#define AifHighPriority 3 /* Highest Priority Event */
1960#define AifEnAddJBOD 30 /* JBOD created */
1961#define AifEnDeleteJBOD 31 /* JBOD deleted */
1962
1963#define AifCmdJobProgress 2 /* Progress report */
1964#define AifJobCtrZero 101 /* Array Zero progress */
1965#define AifJobStsSuccess 1 /* Job completes */
1966#define AifJobStsRunning 102 /* Job running */
1967#define AifCmdAPIReport 3 /* Report from other user of API */
1968#define AifCmdDriverNotify 4 /* Notify host driver of event */
1969#define AifDenMorphComplete 200 /* A morph operation completed */
1970#define AifDenVolumeExtendComplete 201 /* A volume extend completed */
1971#define AifReqJobList 100 /* Gets back complete job list */
1972#define AifReqJobsForCtr 101 /* Gets back jobs for specific container */
1973#define AifReqJobsForScsi 102 /* Gets back jobs for specific SCSI device */
1974#define AifReqJobReport 103 /* Gets back a specific job report or list of them */
1975#define AifReqTerminateJob 104 /* Terminates job */
1976#define AifReqSuspendJob 105 /* Suspends a job */
1977#define AifReqResumeJob 106 /* Resumes a job */
1978#define AifReqSendAPIReport 107 /* API generic report requests */
1979#define AifReqAPIJobStart 108 /* Start a job from the API */
1980#define AifReqAPIJobUpdate 109 /* Update a job report from the API */
1981#define AifReqAPIJobFinish 110 /* Finish a job from the API */
1982
1983/* PMC NEW COMM: Request the event data */
1984#define AifReqEvent 200
1985
1986/*
1987 * Adapter Initiated FIB command structures. Start with the adapter
1988 * initiated FIBs that really come from the adapter, and get responded
1989 * to by the host.
1990 */
1991
1992struct aac_aifcmd {
1993 __le32 command; /* Tell host what type of notify this is */
1994 __le32 seqnum; /* To allow ordering of reports (if necessary) */
1995 u8 data[1]; /* Undefined length (from kernel viewpoint) */
1996};
1997
1998/**
1999 * Convert capacity to cylinders
2000 * accounting for the fact capacity could be a 64 bit value
2001 *
2002 */
2003static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor)
2004{
2005 sector_div(capacity, divisor);
2006 return capacity;
2007}
2008
2009/* SCp.phase values */
2010#define AAC_OWNER_MIDLEVEL 0x101
2011#define AAC_OWNER_LOWLEVEL 0x102
2012#define AAC_OWNER_ERROR_HANDLER 0x103
2013#define AAC_OWNER_FIRMWARE 0x106
2014
2015const char *aac_driverinfo(struct Scsi_Host *);
2016struct fib *aac_fib_alloc(struct aac_dev *dev);
2017int aac_fib_setup(struct aac_dev *dev);
2018void aac_fib_map_free(struct aac_dev *dev);
2019void aac_fib_free(struct fib * context);
2020void aac_fib_init(struct fib * context);
2021void aac_printf(struct aac_dev *dev, u32 val);
2022int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt);
2023int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry);
2024void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum);
2025int aac_fib_complete(struct fib * context);
2026#define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data)
2027struct aac_dev *aac_init_adapter(struct aac_dev *dev);
2028int aac_get_config_status(struct aac_dev *dev, int commit_flag);
2029int aac_get_containers(struct aac_dev *dev);
2030int aac_scsi_cmd(struct scsi_cmnd *cmd);
2031int aac_dev_ioctl(struct aac_dev *dev, int cmd, void __user *arg);
2032#ifndef shost_to_class
2033#define shost_to_class(shost) &shost->shost_dev
2034#endif
2035ssize_t aac_get_serial_number(struct device *dev, char *buf);
2036int aac_do_ioctl(struct aac_dev * dev, int cmd, void __user *arg);
2037int aac_rx_init(struct aac_dev *dev);
2038int aac_rkt_init(struct aac_dev *dev);
2039int aac_nark_init(struct aac_dev *dev);
2040int aac_sa_init(struct aac_dev *dev);
2041int aac_src_init(struct aac_dev *dev);
2042int aac_srcv_init(struct aac_dev *dev);
2043int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify);
2044unsigned int aac_response_normal(struct aac_queue * q);
2045unsigned int aac_command_normal(struct aac_queue * q);
2046unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index,
2047 int isAif, int isFastResponse,
2048 struct hw_fib *aif_fib);
2049int aac_reset_adapter(struct aac_dev * dev, int forced);
2050int aac_check_health(struct aac_dev * dev);
2051int aac_command_thread(void *data);
2052int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx);
2053int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size);
2054struct aac_driver_ident* aac_get_driver_ident(int devtype);
2055int aac_get_adapter_info(struct aac_dev* dev);
2056int aac_send_shutdown(struct aac_dev *dev);
2057int aac_probe_container(struct aac_dev *dev, int cid);
2058int _aac_rx_init(struct aac_dev *dev);
2059int aac_rx_select_comm(struct aac_dev *dev, int comm);
2060int aac_rx_deliver_producer(struct fib * fib);
2061char * get_container_type(unsigned type);
2062extern int numacb;
2063extern int acbsize;
2064extern char aac_driver_version[];
2065extern int startup_timeout;
2066extern int aif_timeout;
2067extern int expose_physicals;
2068extern int aac_reset_devices;
2069extern int aac_msi;
2070extern int aac_commit;
2071extern int update_interval;
2072extern int check_interval;
2073extern int aac_check_reset;
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Adaptec AAC series RAID controller driver
4 * (c) Copyright 2001 Red Hat Inc. <alan@redhat.com>
5 *
6 * based on the old aacraid driver that is..
7 * Adaptec aacraid device driver for Linux.
8 *
9 * Copyright (c) 2000-2010 Adaptec, Inc.
10 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
11 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
12 *
13 * Module Name:
14 * aacraid.h
15 *
16 * Abstract: Contains all routines for control of the aacraid driver
17 */
18
19#ifndef _AACRAID_H_
20#define _AACRAID_H_
21#ifndef dprintk
22# define dprintk(x)
23#endif
24/* eg: if (nblank(dprintk(x))) */
25#define _nblank(x) #x
26#define nblank(x) _nblank(x)[0]
27
28#include <linux/interrupt.h>
29#include <linux/completion.h>
30#include <linux/pci.h>
31#include <scsi/scsi_host.h>
32#include <scsi/scsi_cmnd.h>
33
34/*------------------------------------------------------------------------------
35 * D E F I N E S
36 *----------------------------------------------------------------------------*/
37
38#define AAC_MAX_MSIX 32 /* vectors */
39#define AAC_PCI_MSI_ENABLE 0x8000
40
41enum {
42 AAC_ENABLE_INTERRUPT = 0x0,
43 AAC_DISABLE_INTERRUPT,
44 AAC_ENABLE_MSIX,
45 AAC_DISABLE_MSIX,
46 AAC_CLEAR_AIF_BIT,
47 AAC_CLEAR_SYNC_BIT,
48 AAC_ENABLE_INTX
49};
50
51#define AAC_INT_MODE_INTX (1<<0)
52#define AAC_INT_MODE_MSI (1<<1)
53#define AAC_INT_MODE_AIF (1<<2)
54#define AAC_INT_MODE_SYNC (1<<3)
55#define AAC_INT_MODE_MSIX (1<<16)
56
57#define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb
58#define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa
59#define AAC_INT_DISABLE_ALL 0xffffffff
60
61/* Bit definitions in IOA->Host Interrupt Register */
62#define PMC_TRANSITION_TO_OPERATIONAL (1<<31)
63#define PMC_IOARCB_TRANSFER_FAILED (1<<28)
64#define PMC_IOA_UNIT_CHECK (1<<27)
65#define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26)
66#define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25)
67#define PMC_IOARRIN_LOST (1<<4)
68#define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3)
69#define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2)
70#define PMC_HOST_RRQ_VALID (1<<1)
71#define PMC_OPERATIONAL_STATUS (1<<31)
72#define PMC_ALLOW_MSIX_VECTOR0 (1<<0)
73
74#define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \
75 PMC_IOA_UNIT_CHECK | \
76 PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \
77 PMC_IOARRIN_LOST | \
78 PMC_SYSTEM_BUS_MMIO_ERROR | \
79 PMC_IOA_PROCESSOR_IN_ERROR_STATE)
80
81#define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \
82 PMC_HOST_RRQ_VALID | \
83 PMC_TRANSITION_TO_OPERATIONAL | \
84 PMC_ALLOW_MSIX_VECTOR0)
85#define PMC_GLOBAL_INT_BIT2 0x00000004
86#define PMC_GLOBAL_INT_BIT0 0x00000001
87
88#ifndef AAC_DRIVER_BUILD
89# define AAC_DRIVER_BUILD 50983
90# define AAC_DRIVER_BRANCH "-custom"
91#endif
92#define MAXIMUM_NUM_CONTAINERS 32
93
94#define AAC_NUM_MGT_FIB 8
95#define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB)
96#define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB)
97
98#define AAC_MAX_LUN 256
99
100#define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff)
101#define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256)
102
103#define AAC_DEBUG_INSTRUMENT_AIF_DELETE
104
105#define AAC_MAX_NATIVE_TARGETS 1024
106/* Thor: 5 phys. buses: #0: empty, 1-4: 256 targets each */
107#define AAC_MAX_BUSES 5
108#define AAC_MAX_TARGETS 256
109#define AAC_BUS_TARGET_LOOP (AAC_MAX_BUSES * AAC_MAX_TARGETS)
110#define AAC_MAX_NATIVE_SIZE 2048
111#define FW_ERROR_BUFFER_SIZE 512
112#define AAC_SA_TIMEOUT 180
113#define AAC_ARC_TIMEOUT 60
114
115#define get_bus_number(x) (x/AAC_MAX_TARGETS)
116#define get_target_number(x) (x%AAC_MAX_TARGETS)
117
118/* Thor AIF events */
119#define SA_AIF_HOTPLUG (1<<1)
120#define SA_AIF_HARDWARE (1<<2)
121#define SA_AIF_PDEV_CHANGE (1<<4)
122#define SA_AIF_LDEV_CHANGE (1<<5)
123#define SA_AIF_BPSTAT_CHANGE (1<<30)
124#define SA_AIF_BPCFG_CHANGE (1U<<31)
125
126#define HBA_MAX_SG_EMBEDDED 28
127#define HBA_MAX_SG_SEPARATE 90
128#define HBA_SENSE_DATA_LEN_MAX 32
129#define HBA_REQUEST_TAG_ERROR_FLAG 0x00000002
130#define HBA_SGL_FLAGS_EXT 0x80000000UL
131
132struct aac_hba_sgl {
133 u32 addr_lo; /* Lower 32-bits of SGL element address */
134 u32 addr_hi; /* Upper 32-bits of SGL element address */
135 u32 len; /* Length of SGL element in bytes */
136 u32 flags; /* SGL element flags */
137};
138
139enum {
140 HBA_IU_TYPE_SCSI_CMD_REQ = 0x40,
141 HBA_IU_TYPE_SCSI_TM_REQ = 0x41,
142 HBA_IU_TYPE_SATA_REQ = 0x42,
143 HBA_IU_TYPE_RESP = 0x60,
144 HBA_IU_TYPE_COALESCED_RESP = 0x61,
145 HBA_IU_TYPE_INT_COALESCING_CFG_REQ = 0x70
146};
147
148enum {
149 HBA_CMD_BYTE1_DATA_DIR_IN = 0x1,
150 HBA_CMD_BYTE1_DATA_DIR_OUT = 0x2,
151 HBA_CMD_BYTE1_DATA_TYPE_DDR = 0x4,
152 HBA_CMD_BYTE1_CRYPTO_ENABLE = 0x8
153};
154
155enum {
156 HBA_CMD_BYTE1_BITOFF_DATA_DIR_IN = 0x0,
157 HBA_CMD_BYTE1_BITOFF_DATA_DIR_OUT,
158 HBA_CMD_BYTE1_BITOFF_DATA_TYPE_DDR,
159 HBA_CMD_BYTE1_BITOFF_CRYPTO_ENABLE
160};
161
162enum {
163 HBA_RESP_DATAPRES_NO_DATA = 0x0,
164 HBA_RESP_DATAPRES_RESPONSE_DATA,
165 HBA_RESP_DATAPRES_SENSE_DATA
166};
167
168enum {
169 HBA_RESP_SVCRES_TASK_COMPLETE = 0x0,
170 HBA_RESP_SVCRES_FAILURE,
171 HBA_RESP_SVCRES_TMF_COMPLETE,
172 HBA_RESP_SVCRES_TMF_SUCCEEDED,
173 HBA_RESP_SVCRES_TMF_REJECTED,
174 HBA_RESP_SVCRES_TMF_LUN_INVALID
175};
176
177enum {
178 HBA_RESP_STAT_IO_ERROR = 0x1,
179 HBA_RESP_STAT_IO_ABORTED,
180 HBA_RESP_STAT_NO_PATH_TO_DEVICE,
181 HBA_RESP_STAT_INVALID_DEVICE,
182 HBA_RESP_STAT_HBAMODE_DISABLED = 0xE,
183 HBA_RESP_STAT_UNDERRUN = 0x51,
184 HBA_RESP_STAT_OVERRUN = 0x75
185};
186
187struct aac_hba_cmd_req {
188 u8 iu_type; /* HBA information unit type */
189 /*
190 * byte1:
191 * [1:0] DIR - 0=No data, 0x1 = IN, 0x2 = OUT
192 * [2] TYPE - 0=PCI, 1=DDR
193 * [3] CRYPTO_ENABLE - 0=Crypto disabled, 1=Crypto enabled
194 */
195 u8 byte1;
196 u8 reply_qid; /* Host reply queue to post response to */
197 u8 reserved1;
198 __le32 it_nexus; /* Device handle for the request */
199 __le32 request_id; /* Sender context */
200 /* Lower 32-bits of tweak value for crypto enabled IOs */
201 __le32 tweak_value_lo;
202 u8 cdb[16]; /* SCSI CDB of the command */
203 u8 lun[8]; /* SCSI LUN of the command */
204
205 /* Total data length in bytes to be read/written (if any) */
206 __le32 data_length;
207
208 /* [2:0] Task Attribute, [6:3] Command Priority */
209 u8 attr_prio;
210
211 /* Number of SGL elements embedded in the HBA req */
212 u8 emb_data_desc_count;
213
214 __le16 dek_index; /* DEK index for crypto enabled IOs */
215
216 /* Lower 32-bits of reserved error data target location on the host */
217 __le32 error_ptr_lo;
218
219 /* Upper 32-bits of reserved error data target location on the host */
220 __le32 error_ptr_hi;
221
222 /* Length of reserved error data area on the host in bytes */
223 __le32 error_length;
224
225 /* Upper 32-bits of tweak value for crypto enabled IOs */
226 __le32 tweak_value_hi;
227
228 struct aac_hba_sgl sge[HBA_MAX_SG_SEPARATE+2]; /* SG list space */
229
230 /*
231 * structure must not exceed
232 * AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE
233 */
234};
235
236/* Task Management Functions (TMF) */
237#define HBA_TMF_ABORT_TASK 0x01
238#define HBA_TMF_LUN_RESET 0x08
239
240struct aac_hba_tm_req {
241 u8 iu_type; /* HBA information unit type */
242 u8 reply_qid; /* Host reply queue to post response to */
243 u8 tmf; /* Task management function */
244 u8 reserved1;
245
246 __le32 it_nexus; /* Device handle for the command */
247
248 u8 lun[8]; /* SCSI LUN */
249
250 /* Used to hold sender context. */
251 __le32 request_id; /* Sender context */
252 __le32 reserved2;
253
254 /* Request identifier of managed task */
255 __le32 managed_request_id; /* Sender context being managed */
256 __le32 reserved3;
257
258 /* Lower 32-bits of reserved error data target location on the host */
259 __le32 error_ptr_lo;
260 /* Upper 32-bits of reserved error data target location on the host */
261 __le32 error_ptr_hi;
262 /* Length of reserved error data area on the host in bytes */
263 __le32 error_length;
264};
265
266struct aac_hba_reset_req {
267 u8 iu_type; /* HBA information unit type */
268 /* 0 - reset specified device, 1 - reset all devices */
269 u8 reset_type;
270 u8 reply_qid; /* Host reply queue to post response to */
271 u8 reserved1;
272
273 __le32 it_nexus; /* Device handle for the command */
274 __le32 request_id; /* Sender context */
275 /* Lower 32-bits of reserved error data target location on the host */
276 __le32 error_ptr_lo;
277 /* Upper 32-bits of reserved error data target location on the host */
278 __le32 error_ptr_hi;
279 /* Length of reserved error data area on the host in bytes */
280 __le32 error_length;
281};
282
283struct aac_hba_resp {
284 u8 iu_type; /* HBA information unit type */
285 u8 reserved1[3];
286 __le32 request_identifier; /* sender context */
287 __le32 reserved2;
288 u8 service_response; /* SCSI service response */
289 u8 status; /* SCSI status */
290 u8 datapres; /* [1:0] - data present, [7:2] - reserved */
291 u8 sense_response_data_len; /* Sense/response data length */
292 __le32 residual_count; /* Residual data length in bytes */
293 /* Sense/response data */
294 u8 sense_response_buf[HBA_SENSE_DATA_LEN_MAX];
295};
296
297struct aac_native_hba {
298 union {
299 struct aac_hba_cmd_req cmd;
300 struct aac_hba_tm_req tmr;
301 u8 cmd_bytes[AAC_MAX_NATIVE_SIZE-FW_ERROR_BUFFER_SIZE];
302 } cmd;
303 union {
304 struct aac_hba_resp err;
305 u8 resp_bytes[FW_ERROR_BUFFER_SIZE];
306 } resp;
307};
308
309#define CISS_REPORT_PHYSICAL_LUNS 0xc3
310#define WRITE_HOST_WELLNESS 0xa5
311#define CISS_IDENTIFY_PHYSICAL_DEVICE 0x15
312#define BMIC_IN 0x26
313#define BMIC_OUT 0x27
314
315struct aac_ciss_phys_luns_resp {
316 u8 list_length[4]; /* LUN list length (N-7, big endian) */
317 u8 resp_flag; /* extended response_flag */
318 u8 reserved[3];
319 struct _ciss_lun {
320 u8 tid[3]; /* Target ID */
321 u8 bus; /* Bus, flag (bits 6,7) */
322 u8 level3[2];
323 u8 level2[2];
324 u8 node_ident[16]; /* phys. node identifier */
325 } lun[1]; /* List of phys. devices */
326};
327
328/*
329 * Interrupts
330 */
331#define AAC_MAX_HRRQ 64
332
333struct aac_ciss_identify_pd {
334 u8 scsi_bus; /* SCSI Bus number on controller */
335 u8 scsi_id; /* SCSI ID on this bus */
336 u16 block_size; /* sector size in bytes */
337 u32 total_blocks; /* number for sectors on drive */
338 u32 reserved_blocks; /* controller reserved (RIS) */
339 u8 model[40]; /* Physical Drive Model */
340 u8 serial_number[40]; /* Drive Serial Number */
341 u8 firmware_revision[8]; /* drive firmware revision */
342 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */
343 u8 compaq_drive_stamp; /* 0 means drive not stamped */
344 u8 last_failure_reason;
345
346 u8 flags;
347 u8 more_flags;
348 u8 scsi_lun; /* SCSI LUN for phys drive */
349 u8 yet_more_flags;
350 u8 even_more_flags;
351 u32 spi_speed_rules; /* SPI Speed :Ultra disable diagnose */
352 u8 phys_connector[2]; /* connector number on controller */
353 u8 phys_box_on_bus; /* phys enclosure this drive resides */
354 u8 phys_bay_in_box; /* phys drv bay this drive resides */
355 u32 rpm; /* Drive rotational speed in rpm */
356 u8 device_type; /* type of drive */
357 u8 sata_version; /* only valid when drive_type is SATA */
358 u64 big_total_block_count;
359 u64 ris_starting_lba;
360 u32 ris_size;
361 u8 wwid[20];
362 u8 controller_phy_map[32];
363 u16 phy_count;
364 u8 phy_connected_dev_type[256];
365 u8 phy_to_drive_bay_num[256];
366 u16 phy_to_attached_dev_index[256];
367 u8 box_index;
368 u8 spitfire_support;
369 u16 extra_physical_drive_flags;
370 u8 negotiated_link_rate[256];
371 u8 phy_to_phy_map[256];
372 u8 redundant_path_present_map;
373 u8 redundant_path_failure_map;
374 u8 active_path_number;
375 u16 alternate_paths_phys_connector[8];
376 u8 alternate_paths_phys_box_on_port[8];
377 u8 multi_lun_device_lun_count;
378 u8 minimum_good_fw_revision[8];
379 u8 unique_inquiry_bytes[20];
380 u8 current_temperature_degreesC;
381 u8 temperature_threshold_degreesC;
382 u8 max_temperature_degreesC;
383 u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512 * 2^exp */
384 u16 current_queue_depth_limit;
385 u8 switch_name[10];
386 u16 switch_port;
387 u8 alternate_paths_switch_name[40];
388 u8 alternate_paths_switch_port[8];
389 u16 power_on_hours; /* valid only if gas gauge supported */
390 u16 percent_endurance_used; /* valid only if gas gauge supported. */
391 u8 drive_authentication;
392 u8 smart_carrier_authentication;
393 u8 smart_carrier_app_fw_version;
394 u8 smart_carrier_bootloader_fw_version;
395 u8 SanitizeSecureEraseSupport;
396 u8 DriveKeyFlags;
397 u8 encryption_key_name[64];
398 u32 misc_drive_flags;
399 u16 dek_index;
400 u16 drive_encryption_flags;
401 u8 sanitize_maximum_time[6];
402 u8 connector_info_mode;
403 u8 connector_info_number[4];
404 u8 long_connector_name[64];
405 u8 device_unique_identifier[16];
406 u8 padto_2K[17];
407} __packed;
408
409/*
410 * These macros convert from physical channels to virtual channels
411 */
412#define CONTAINER_CHANNEL (0)
413#define NATIVE_CHANNEL (1)
414#define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL)
415#define CONTAINER_TO_ID(cont) (cont)
416#define CONTAINER_TO_LUN(cont) (0)
417#define ENCLOSURE_CHANNEL (3)
418
419#define PMC_DEVICE_S6 0x28b
420#define PMC_DEVICE_S7 0x28c
421#define PMC_DEVICE_S8 0x28d
422
423#define aac_phys_to_logical(x) ((x)+1)
424#define aac_logical_to_phys(x) ((x)?(x)-1:0)
425
426/*
427 * These macros are for keeping track of
428 * character device state.
429 */
430#define AAC_CHARDEV_UNREGISTERED (-1)
431#define AAC_CHARDEV_NEEDS_REINIT (-2)
432
433/* #define AAC_DETAILED_STATUS_INFO */
434
435struct diskparm
436{
437 int heads;
438 int sectors;
439 int cylinders;
440};
441
442
443/*
444 * Firmware constants
445 */
446
447#define CT_NONE 0
448#define CT_OK 218
449#define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */
450#define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/id/lun */
451
452/*
453 * Host side memory scatter gather list
454 * Used by the adapter for read, write, and readdirplus operations
455 * We have separate 32 and 64 bit version because even
456 * on 64 bit systems not all cards support the 64 bit version
457 */
458struct sgentry {
459 __le32 addr; /* 32-bit address. */
460 __le32 count; /* Length. */
461};
462
463struct user_sgentry {
464 u32 addr; /* 32-bit address. */
465 u32 count; /* Length. */
466};
467
468struct sgentry64 {
469 __le32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
470 __le32 count; /* Length. */
471};
472
473struct user_sgentry64 {
474 u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */
475 u32 count; /* Length. */
476};
477
478struct sgentryraw {
479 __le32 next; /* reserved for F/W use */
480 __le32 prev; /* reserved for F/W use */
481 __le32 addr[2];
482 __le32 count;
483 __le32 flags; /* reserved for F/W use */
484};
485
486struct user_sgentryraw {
487 u32 next; /* reserved for F/W use */
488 u32 prev; /* reserved for F/W use */
489 u32 addr[2];
490 u32 count;
491 u32 flags; /* reserved for F/W use */
492};
493
494struct sge_ieee1212 {
495 u32 addrLow;
496 u32 addrHigh;
497 u32 length;
498 u32 flags;
499};
500
501/*
502 * SGMAP
503 *
504 * This is the SGMAP structure for all commands that use
505 * 32-bit addressing.
506 */
507
508struct sgmap {
509 __le32 count;
510 struct sgentry sg[1];
511};
512
513struct user_sgmap {
514 u32 count;
515 struct user_sgentry sg[1];
516};
517
518struct sgmap64 {
519 __le32 count;
520 struct sgentry64 sg[1];
521};
522
523struct user_sgmap64 {
524 u32 count;
525 struct user_sgentry64 sg[1];
526};
527
528struct sgmapraw {
529 __le32 count;
530 struct sgentryraw sg[1];
531};
532
533struct user_sgmapraw {
534 u32 count;
535 struct user_sgentryraw sg[1];
536};
537
538struct creation_info
539{
540 u8 buildnum; /* e.g., 588 */
541 u8 usec; /* e.g., 588 */
542 u8 via; /* e.g., 1 = FSU,
543 * 2 = API
544 */
545 u8 year; /* e.g., 1997 = 97 */
546 __le32 date; /*
547 * unsigned Month :4; // 1 - 12
548 * unsigned Day :6; // 1 - 32
549 * unsigned Hour :6; // 0 - 23
550 * unsigned Minute :6; // 0 - 60
551 * unsigned Second :6; // 0 - 60
552 */
553 __le32 serial[2]; /* e.g., 0x1DEADB0BFAFAF001 */
554};
555
556
557/*
558 * Define all the constants needed for the communication interface
559 */
560
561/*
562 * Define how many queue entries each queue will have and the total
563 * number of entries for the entire communication interface. Also define
564 * how many queues we support.
565 *
566 * This has to match the controller
567 */
568
569#define NUMBER_OF_COMM_QUEUES 8 // 4 command; 4 response
570#define HOST_HIGH_CMD_ENTRIES 4
571#define HOST_NORM_CMD_ENTRIES 8
572#define ADAP_HIGH_CMD_ENTRIES 4
573#define ADAP_NORM_CMD_ENTRIES 512
574#define HOST_HIGH_RESP_ENTRIES 4
575#define HOST_NORM_RESP_ENTRIES 512
576#define ADAP_HIGH_RESP_ENTRIES 4
577#define ADAP_NORM_RESP_ENTRIES 8
578
579#define TOTAL_QUEUE_ENTRIES \
580 (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \
581 HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES)
582
583
584/*
585 * Set the queues on a 16 byte alignment
586 */
587
588#define QUEUE_ALIGNMENT 16
589
590/*
591 * The queue headers define the Communication Region queues. These
592 * are physically contiguous and accessible by both the adapter and the
593 * host. Even though all queue headers are in the same contiguous block
594 * they will be represented as individual units in the data structures.
595 */
596
597struct aac_entry {
598 __le32 size; /* Size in bytes of Fib which this QE points to */
599 __le32 addr; /* Receiver address of the FIB */
600};
601
602/*
603 * The adapter assumes the ProducerIndex and ConsumerIndex are grouped
604 * adjacently and in that order.
605 */
606
607struct aac_qhdr {
608 __le64 header_addr;/* Address to hand the adapter to access
609 to this queue head */
610 __le32 *producer; /* The producer index for this queue (host address) */
611 __le32 *consumer; /* The consumer index for this queue (host address) */
612};
613
614/*
615 * Define all the events which the adapter would like to notify
616 * the host of.
617 */
618
619#define HostNormCmdQue 1 /* Change in host normal priority command queue */
620#define HostHighCmdQue 2 /* Change in host high priority command queue */
621#define HostNormRespQue 3 /* Change in host normal priority response queue */
622#define HostHighRespQue 4 /* Change in host high priority response queue */
623#define AdapNormRespNotFull 5
624#define AdapHighRespNotFull 6
625#define AdapNormCmdNotFull 7
626#define AdapHighCmdNotFull 8
627#define SynchCommandComplete 9
628#define AdapInternalError 0xfe /* The adapter detected an internal error shutting down */
629
630/*
631 * Define all the events the host wishes to notify the
632 * adapter of. The first four values much match the Qid the
633 * corresponding queue.
634 */
635
636#define AdapNormCmdQue 2
637#define AdapHighCmdQue 3
638#define AdapNormRespQue 6
639#define AdapHighRespQue 7
640#define HostShutdown 8
641#define HostPowerFail 9
642#define FatalCommError 10
643#define HostNormRespNotFull 11
644#define HostHighRespNotFull 12
645#define HostNormCmdNotFull 13
646#define HostHighCmdNotFull 14
647#define FastIo 15
648#define AdapPrintfDone 16
649
650/*
651 * Define all the queues that the adapter and host use to communicate
652 * Number them to match the physical queue layout.
653 */
654
655enum aac_queue_types {
656 HostNormCmdQueue = 0, /* Adapter to host normal priority command traffic */
657 HostHighCmdQueue, /* Adapter to host high priority command traffic */
658 AdapNormCmdQueue, /* Host to adapter normal priority command traffic */
659 AdapHighCmdQueue, /* Host to adapter high priority command traffic */
660 HostNormRespQueue, /* Adapter to host normal priority response traffic */
661 HostHighRespQueue, /* Adapter to host high priority response traffic */
662 AdapNormRespQueue, /* Host to adapter normal priority response traffic */
663 AdapHighRespQueue /* Host to adapter high priority response traffic */
664};
665
666/*
667 * Assign type values to the FSA communication data structures
668 */
669
670#define FIB_MAGIC 0x0001
671#define FIB_MAGIC2 0x0004
672#define FIB_MAGIC2_64 0x0005
673
674/*
675 * Define the priority levels the FSA communication routines support.
676 */
677
678#define FsaNormal 1
679
680/* transport FIB header (PMC) */
681struct aac_fib_xporthdr {
682 __le64 HostAddress; /* FIB host address w/o xport header */
683 __le32 Size; /* FIB size excluding xport header */
684 __le32 Handle; /* driver handle to reference the FIB */
685 __le64 Reserved[2];
686};
687
688#define ALIGN32 32
689
690/*
691 * Define the FIB. The FIB is the where all the requested data and
692 * command information are put to the application on the FSA adapter.
693 */
694
695struct aac_fibhdr {
696 __le32 XferState; /* Current transfer state for this CCB */
697 __le16 Command; /* Routing information for the destination */
698 u8 StructType; /* Type FIB */
699 u8 Unused; /* Unused */
700 __le16 Size; /* Size of this FIB in bytes */
701 __le16 SenderSize; /* Size of the FIB in the sender
702 (for response sizing) */
703 __le32 SenderFibAddress; /* Host defined data in the FIB */
704 union {
705 __le32 ReceiverFibAddress;/* Logical address of this FIB for
706 the adapter (old) */
707 __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */
708 __le32 TimeStamp; /* otherwise timestamp for FW internal use */
709 } u;
710 __le32 Handle; /* FIB handle used for MSGU commnunication */
711 u32 Previous; /* FW internal use */
712 u32 Next; /* FW internal use */
713};
714
715struct hw_fib {
716 struct aac_fibhdr header;
717 u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data
718};
719
720/*
721 * FIB commands
722 */
723
724#define TestCommandResponse 1
725#define TestAdapterCommand 2
726/*
727 * Lowlevel and comm commands
728 */
729#define LastTestCommand 100
730#define ReinitHostNormCommandQueue 101
731#define ReinitHostHighCommandQueue 102
732#define ReinitHostHighRespQueue 103
733#define ReinitHostNormRespQueue 104
734#define ReinitAdapNormCommandQueue 105
735#define ReinitAdapHighCommandQueue 107
736#define ReinitAdapHighRespQueue 108
737#define ReinitAdapNormRespQueue 109
738#define InterfaceShutdown 110
739#define DmaCommandFib 120
740#define StartProfile 121
741#define TermProfile 122
742#define SpeedTest 123
743#define TakeABreakPt 124
744#define RequestPerfData 125
745#define SetInterruptDefTimer 126
746#define SetInterruptDefCount 127
747#define GetInterruptDefStatus 128
748#define LastCommCommand 129
749/*
750 * Filesystem commands
751 */
752#define NuFileSystem 300
753#define UFS 301
754#define HostFileSystem 302
755#define LastFileSystemCommand 303
756/*
757 * Container Commands
758 */
759#define ContainerCommand 500
760#define ContainerCommand64 501
761#define ContainerRawIo 502
762#define ContainerRawIo2 503
763/*
764 * Scsi Port commands (scsi passthrough)
765 */
766#define ScsiPortCommand 600
767#define ScsiPortCommand64 601
768/*
769 * Misc house keeping and generic adapter initiated commands
770 */
771#define AifRequest 700
772#define CheckRevision 701
773#define FsaHostShutdown 702
774#define RequestAdapterInfo 703
775#define IsAdapterPaused 704
776#define SendHostTime 705
777#define RequestSupplementAdapterInfo 706
778#define LastMiscCommand 707
779
780/*
781 * Commands that will target the failover level on the FSA adapter
782 */
783
784enum fib_xfer_state {
785 HostOwned = (1<<0),
786 AdapterOwned = (1<<1),
787 FibInitialized = (1<<2),
788 FibEmpty = (1<<3),
789 AllocatedFromPool = (1<<4),
790 SentFromHost = (1<<5),
791 SentFromAdapter = (1<<6),
792 ResponseExpected = (1<<7),
793 NoResponseExpected = (1<<8),
794 AdapterProcessed = (1<<9),
795 HostProcessed = (1<<10),
796 HighPriority = (1<<11),
797 NormalPriority = (1<<12),
798 Async = (1<<13),
799 AsyncIo = (1<<13), // rpbfix: remove with new regime
800 PageFileIo = (1<<14), // rpbfix: remove with new regime
801 ShutdownRequest = (1<<15),
802 LazyWrite = (1<<16), // rpbfix: remove with new regime
803 AdapterMicroFib = (1<<17),
804 BIOSFibPath = (1<<18),
805 FastResponseCapable = (1<<19),
806 ApiFib = (1<<20), /* Its an API Fib */
807 /* PMC NEW COMM: There is no more AIF data pending */
808 NoMoreAifDataAvailable = (1<<21)
809};
810
811/*
812 * The following defines needs to be updated any time there is an
813 * incompatible change made to the aac_init structure.
814 */
815
816#define ADAPTER_INIT_STRUCT_REVISION 3
817#define ADAPTER_INIT_STRUCT_REVISION_4 4 // rocket science
818#define ADAPTER_INIT_STRUCT_REVISION_6 6 /* PMC src */
819#define ADAPTER_INIT_STRUCT_REVISION_7 7 /* Denali */
820#define ADAPTER_INIT_STRUCT_REVISION_8 8 // Thor
821
822union aac_init
823{
824 struct _r7 {
825 __le32 init_struct_revision;
826 __le32 no_of_msix_vectors;
827 __le32 fsrev;
828 __le32 comm_header_address;
829 __le32 fast_io_comm_area_address;
830 __le32 adapter_fibs_physical_address;
831 __le32 adapter_fibs_virtual_address;
832 __le32 adapter_fibs_size;
833 __le32 adapter_fib_align;
834 __le32 printfbuf;
835 __le32 printfbufsiz;
836 /* number of 4k pages of host phys. mem. */
837 __le32 host_phys_mem_pages;
838 /* number of seconds since 1970. */
839 __le32 host_elapsed_seconds;
840 /* ADAPTER_INIT_STRUCT_REVISION_4 begins here */
841 __le32 init_flags; /* flags for supported features */
842#define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001
843#define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010
844#define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020
845#define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040
846#define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080
847#define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100
848#define INITFLAGS_DRIVER_SUPPORTS_HBA_MODE 0x00000400
849 __le32 max_io_commands; /* max outstanding commands */
850 __le32 max_io_size; /* largest I/O command */
851 __le32 max_fib_size; /* largest FIB to adapter */
852 /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */
853 __le32 max_num_aif; /* max number of aif */
854 /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */
855 /* Host RRQ (response queue) for SRC */
856 __le32 host_rrq_addr_low;
857 __le32 host_rrq_addr_high;
858 } r7;
859 struct _r8 {
860 /* ADAPTER_INIT_STRUCT_REVISION_8 */
861 __le32 init_struct_revision;
862 __le32 rr_queue_count;
863 __le32 host_elapsed_seconds; /* number of secs since 1970. */
864 __le32 init_flags;
865 __le32 max_io_size; /* largest I/O command */
866 __le32 max_num_aif; /* max number of aif */
867 __le32 reserved1;
868 __le32 reserved2;
869 struct _rrq {
870 __le32 host_addr_low;
871 __le32 host_addr_high;
872 __le16 msix_id;
873 __le16 element_count;
874 __le16 comp_thresh;
875 __le16 unused;
876 } rrq[1]; /* up to 64 RRQ addresses */
877 } r8;
878};
879
880enum aac_log_level {
881 LOG_AAC_INIT = 10,
882 LOG_AAC_INFORMATIONAL = 20,
883 LOG_AAC_WARNING = 30,
884 LOG_AAC_LOW_ERROR = 40,
885 LOG_AAC_MEDIUM_ERROR = 50,
886 LOG_AAC_HIGH_ERROR = 60,
887 LOG_AAC_PANIC = 70,
888 LOG_AAC_DEBUG = 80,
889 LOG_AAC_WINDBG_PRINT = 90
890};
891
892#define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b
893#define FSAFS_NTC_FIB_CONTEXT 0x030c
894
895struct aac_dev;
896struct fib;
897struct scsi_cmnd;
898
899struct adapter_ops
900{
901 /* Low level operations */
902 void (*adapter_interrupt)(struct aac_dev *dev);
903 void (*adapter_notify)(struct aac_dev *dev, u32 event);
904 void (*adapter_disable_int)(struct aac_dev *dev);
905 void (*adapter_enable_int)(struct aac_dev *dev);
906 int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4);
907 int (*adapter_check_health)(struct aac_dev *dev);
908 int (*adapter_restart)(struct aac_dev *dev, int bled, u8 reset_type);
909 void (*adapter_start)(struct aac_dev *dev);
910 /* Transport operations */
911 int (*adapter_ioremap)(struct aac_dev * dev, u32 size);
912 irq_handler_t adapter_intr;
913 /* Packet operations */
914 int (*adapter_deliver)(struct fib * fib);
915 int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba);
916 int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count);
917 int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua);
918 int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd);
919 /* Administrative operations */
920 int (*adapter_comm)(struct aac_dev * dev, int comm);
921};
922
923/*
924 * Define which interrupt handler needs to be installed
925 */
926
927struct aac_driver_ident
928{
929 int (*init)(struct aac_dev *dev);
930 char * name;
931 char * vname;
932 char * model;
933 u16 channels;
934 int quirks;
935};
936/*
937 * Some adapter firmware needs communication memory
938 * below 2gig. This tells the init function to set the
939 * dma mask such that fib memory will be allocated where the
940 * adapter firmware can get to it.
941 */
942#define AAC_QUIRK_31BIT 0x0001
943
944/*
945 * Some adapter firmware, when the raid card's cache is turned off, can not
946 * split up scatter gathers in order to deal with the limits of the
947 * underlying CHIM. This limit is 34 scatter gather elements.
948 */
949#define AAC_QUIRK_34SG 0x0002
950
951/*
952 * This adapter is a slave (no Firmware)
953 */
954#define AAC_QUIRK_SLAVE 0x0004
955
956/*
957 * This adapter is a master.
958 */
959#define AAC_QUIRK_MASTER 0x0008
960
961/*
962 * Some adapter firmware perform poorly when it must split up scatter gathers
963 * in order to deal with the limits of the underlying CHIM. This limit in this
964 * class of adapters is 17 scatter gather elements.
965 */
966#define AAC_QUIRK_17SG 0x0010
967
968/*
969 * Some adapter firmware does not support 64 bit scsi passthrough
970 * commands.
971 */
972#define AAC_QUIRK_SCSI_32 0x0020
973
974/*
975 * SRC based adapters support the AifReqEvent functions
976 */
977#define AAC_QUIRK_SRC 0x0040
978
979/*
980 * The adapter interface specs all queues to be located in the same
981 * physically contiguous block. The host structure that defines the
982 * commuication queues will assume they are each a separate physically
983 * contiguous memory region that will support them all being one big
984 * contiguous block.
985 * There is a command and response queue for each level and direction of
986 * commuication. These regions are accessed by both the host and adapter.
987 */
988
989struct aac_queue {
990 u64 logical; /*address we give the adapter */
991 struct aac_entry *base; /*system virtual address */
992 struct aac_qhdr headers; /*producer,consumer q headers*/
993 u32 entries; /*Number of queue entries */
994 wait_queue_head_t qfull; /*Event to wait on if q full */
995 wait_queue_head_t cmdready; /*Cmd ready from the adapter */
996 /* This is only valid for adapter to host command queues. */
997 spinlock_t *lock; /* Spinlock for this queue must take this lock before accessing the lock */
998 spinlock_t lockdata; /* Actual lock (used only on one side of the lock) */
999 struct list_head cmdq; /* A queue of FIBs which need to be prcessed by the FS thread. This is */
1000 /* only valid for command queues which receive entries from the adapter. */
1001 /* Number of entries on outstanding queue. */
1002 atomic_t numpending;
1003 struct aac_dev * dev; /* Back pointer to adapter structure */
1004};
1005
1006/*
1007 * Message queues. The order here is important, see also the
1008 * queue type ordering
1009 */
1010
1011struct aac_queue_block
1012{
1013 struct aac_queue queue[8];
1014};
1015
1016/*
1017 * SaP1 Message Unit Registers
1018 */
1019
1020struct sa_drawbridge_CSR {
1021 /* Offset | Name */
1022 __le32 reserved[10]; /* 00h-27h | Reserved */
1023 u8 LUT_Offset; /* 28h | Lookup Table Offset */
1024 u8 reserved1[3]; /* 29h-2bh | Reserved */
1025 __le32 LUT_Data; /* 2ch | Looup Table Data */
1026 __le32 reserved2[26]; /* 30h-97h | Reserved */
1027 __le16 PRICLEARIRQ; /* 98h | Primary Clear Irq */
1028 __le16 SECCLEARIRQ; /* 9ah | Secondary Clear Irq */
1029 __le16 PRISETIRQ; /* 9ch | Primary Set Irq */
1030 __le16 SECSETIRQ; /* 9eh | Secondary Set Irq */
1031 __le16 PRICLEARIRQMASK;/* a0h | Primary Clear Irq Mask */
1032 __le16 SECCLEARIRQMASK;/* a2h | Secondary Clear Irq Mask */
1033 __le16 PRISETIRQMASK; /* a4h | Primary Set Irq Mask */
1034 __le16 SECSETIRQMASK; /* a6h | Secondary Set Irq Mask */
1035 __le32 MAILBOX0; /* a8h | Scratchpad 0 */
1036 __le32 MAILBOX1; /* ach | Scratchpad 1 */
1037 __le32 MAILBOX2; /* b0h | Scratchpad 2 */
1038 __le32 MAILBOX3; /* b4h | Scratchpad 3 */
1039 __le32 MAILBOX4; /* b8h | Scratchpad 4 */
1040 __le32 MAILBOX5; /* bch | Scratchpad 5 */
1041 __le32 MAILBOX6; /* c0h | Scratchpad 6 */
1042 __le32 MAILBOX7; /* c4h | Scratchpad 7 */
1043 __le32 ROM_Setup_Data; /* c8h | Rom Setup and Data */
1044 __le32 ROM_Control_Addr;/* cch | Rom Control and Address */
1045 __le32 reserved3[12]; /* d0h-ffh | reserved */
1046 __le32 LUT[64]; /* 100h-1ffh | Lookup Table Entries */
1047};
1048
1049#define Mailbox0 SaDbCSR.MAILBOX0
1050#define Mailbox1 SaDbCSR.MAILBOX1
1051#define Mailbox2 SaDbCSR.MAILBOX2
1052#define Mailbox3 SaDbCSR.MAILBOX3
1053#define Mailbox4 SaDbCSR.MAILBOX4
1054#define Mailbox5 SaDbCSR.MAILBOX5
1055#define Mailbox6 SaDbCSR.MAILBOX6
1056#define Mailbox7 SaDbCSR.MAILBOX7
1057
1058#define DoorbellReg_p SaDbCSR.PRISETIRQ
1059#define DoorbellReg_s SaDbCSR.SECSETIRQ
1060#define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ
1061
1062
1063#define DOORBELL_0 0x0001
1064#define DOORBELL_1 0x0002
1065#define DOORBELL_2 0x0004
1066#define DOORBELL_3 0x0008
1067#define DOORBELL_4 0x0010
1068#define DOORBELL_5 0x0020
1069#define DOORBELL_6 0x0040
1070
1071
1072#define PrintfReady DOORBELL_5
1073#define PrintfDone DOORBELL_5
1074
1075struct sa_registers {
1076 struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */
1077};
1078
1079
1080#define SA_INIT_NUM_MSIXVECTORS 1
1081#define SA_MINIPORT_REVISION SA_INIT_NUM_MSIXVECTORS
1082
1083#define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
1084#define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
1085#define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR))
1086#define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
1087
1088/*
1089 * Rx Message Unit Registers
1090 */
1091
1092struct rx_mu_registers {
1093 /* Local | PCI*| Name */
1094 __le32 ARSR; /* 1300h | 00h | APIC Register Select Register */
1095 __le32 reserved0; /* 1304h | 04h | Reserved */
1096 __le32 AWR; /* 1308h | 08h | APIC Window Register */
1097 __le32 reserved1; /* 130Ch | 0Ch | Reserved */
1098 __le32 IMRx[2]; /* 1310h | 10h | Inbound Message Registers */
1099 __le32 OMRx[2]; /* 1318h | 18h | Outbound Message Registers */
1100 __le32 IDR; /* 1320h | 20h | Inbound Doorbell Register */
1101 __le32 IISR; /* 1324h | 24h | Inbound Interrupt
1102 Status Register */
1103 __le32 IIMR; /* 1328h | 28h | Inbound Interrupt
1104 Mask Register */
1105 __le32 ODR; /* 132Ch | 2Ch | Outbound Doorbell Register */
1106 __le32 OISR; /* 1330h | 30h | Outbound Interrupt
1107 Status Register */
1108 __le32 OIMR; /* 1334h | 34h | Outbound Interrupt
1109 Mask Register */
1110 __le32 reserved2; /* 1338h | 38h | Reserved */
1111 __le32 reserved3; /* 133Ch | 3Ch | Reserved */
1112 __le32 InboundQueue;/* 1340h | 40h | Inbound Queue Port relative to firmware */
1113 __le32 OutboundQueue;/*1344h | 44h | Outbound Queue Port relative to firmware */
1114 /* * Must access through ATU Inbound
1115 Translation Window */
1116};
1117
1118struct rx_inbound {
1119 __le32 Mailbox[8];
1120};
1121
1122#define INBOUNDDOORBELL_0 0x00000001
1123#define INBOUNDDOORBELL_1 0x00000002
1124#define INBOUNDDOORBELL_2 0x00000004
1125#define INBOUNDDOORBELL_3 0x00000008
1126#define INBOUNDDOORBELL_4 0x00000010
1127#define INBOUNDDOORBELL_5 0x00000020
1128#define INBOUNDDOORBELL_6 0x00000040
1129
1130#define OUTBOUNDDOORBELL_0 0x00000001
1131#define OUTBOUNDDOORBELL_1 0x00000002
1132#define OUTBOUNDDOORBELL_2 0x00000004
1133#define OUTBOUNDDOORBELL_3 0x00000008
1134#define OUTBOUNDDOORBELL_4 0x00000010
1135
1136#define InboundDoorbellReg MUnit.IDR
1137#define OutboundDoorbellReg MUnit.ODR
1138
1139struct rx_registers {
1140 struct rx_mu_registers MUnit; /* 1300h - 1347h */
1141 __le32 reserved1[2]; /* 1348h - 134ch */
1142 struct rx_inbound IndexRegs;
1143};
1144
1145#define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR))
1146#define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR))
1147#define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR))
1148#define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
1149
1150/*
1151 * Rkt Message Unit Registers (same as Rx, except a larger reserve region)
1152 */
1153
1154#define rkt_mu_registers rx_mu_registers
1155#define rkt_inbound rx_inbound
1156
1157struct rkt_registers {
1158 struct rkt_mu_registers MUnit; /* 1300h - 1347h */
1159 __le32 reserved1[1006]; /* 1348h - 22fch */
1160 struct rkt_inbound IndexRegs; /* 2300h - */
1161};
1162
1163#define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR))
1164#define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR))
1165#define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR))
1166#define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR))
1167
1168/*
1169 * PMC SRC message unit registers
1170 */
1171
1172#define src_inbound rx_inbound
1173
1174struct src_mu_registers {
1175 /* PCI*| Name */
1176 __le32 reserved0[6]; /* 00h | Reserved */
1177 __le32 IOAR[2]; /* 18h | IOA->host interrupt register */
1178 __le32 IDR; /* 20h | Inbound Doorbell Register */
1179 __le32 IISR; /* 24h | Inbound Int. Status Register */
1180 __le32 reserved1[3]; /* 28h | Reserved */
1181 __le32 OIMR; /* 34h | Outbound Int. Mask Register */
1182 __le32 reserved2[25]; /* 38h | Reserved */
1183 __le32 ODR_R; /* 9ch | Outbound Doorbell Read */
1184 __le32 ODR_C; /* a0h | Outbound Doorbell Clear */
1185 __le32 reserved3[3]; /* a4h | Reserved */
1186 __le32 SCR0; /* b0h | Scratchpad 0 */
1187 __le32 reserved4[2]; /* b4h | Reserved */
1188 __le32 OMR; /* bch | Outbound Message Register */
1189 __le32 IQ_L; /* c0h | Inbound Queue (Low address) */
1190 __le32 IQ_H; /* c4h | Inbound Queue (High address) */
1191 __le32 ODR_MSI; /* c8h | MSI register for sync./AIF */
1192 __le32 reserved5; /* cch | Reserved */
1193 __le32 IQN_L; /* d0h | Inbound (native cmd) low */
1194 __le32 IQN_H; /* d4h | Inbound (native cmd) high */
1195};
1196
1197struct src_registers {
1198 struct src_mu_registers MUnit; /* 00h - cbh */
1199 union {
1200 struct {
1201 __le32 reserved1[130786]; /* d8h - 7fc5fh */
1202 struct src_inbound IndexRegs; /* 7fc60h */
1203 } tupelo;
1204 struct {
1205 __le32 reserved1[970]; /* d8h - fffh */
1206 struct src_inbound IndexRegs; /* 1000h */
1207 } denali;
1208 } u;
1209};
1210
1211#define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR))
1212#define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR))
1213#define src_writeb(AEP, CSR, value) writeb(value, \
1214 &((AEP)->regs.src.bar0->CSR))
1215#define src_writel(AEP, CSR, value) writel(value, \
1216 &((AEP)->regs.src.bar0->CSR))
1217#if defined(writeq)
1218#define src_writeq(AEP, CSR, value) writeq(value, \
1219 &((AEP)->regs.src.bar0->CSR))
1220#endif
1221
1222#define SRC_ODR_SHIFT 12
1223#define SRC_IDR_SHIFT 9
1224#define SRC_MSI_READ_MASK 0x1000
1225
1226typedef void (*fib_callback)(void *ctxt, struct fib *fibctx);
1227
1228struct aac_fib_context {
1229 s16 type; // used for verification of structure
1230 s16 size;
1231 u32 unique; // unique value representing this context
1232 ulong jiffies; // used for cleanup - dmb changed to ulong
1233 struct list_head next; // used to link context's into a linked list
1234 struct completion completion; // this is used to wait for the next fib to arrive.
1235 int wait; // Set to true when thread is in WaitForSingleObject
1236 unsigned long count; // total number of FIBs on FibList
1237 struct list_head fib_list; // this holds fibs and their attachd hw_fibs
1238};
1239
1240struct sense_data {
1241 u8 error_code; /* 70h (current errors), 71h(deferred errors) */
1242 u8 valid:1; /* A valid bit of one indicates that the information */
1243 /* field contains valid information as defined in the
1244 * SCSI-2 Standard.
1245 */
1246 u8 segment_number; /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */
1247 u8 sense_key:4; /* Sense Key */
1248 u8 reserved:1;
1249 u8 ILI:1; /* Incorrect Length Indicator */
1250 u8 EOM:1; /* End Of Medium - reserved for random access devices */
1251 u8 filemark:1; /* Filemark - reserved for random access devices */
1252
1253 u8 information[4]; /* for direct-access devices, contains the unsigned
1254 * logical block address or residue associated with
1255 * the sense key
1256 */
1257 u8 add_sense_len; /* number of additional sense bytes to follow this field */
1258 u8 cmnd_info[4]; /* not used */
1259 u8 ASC; /* Additional Sense Code */
1260 u8 ASCQ; /* Additional Sense Code Qualifier */
1261 u8 FRUC; /* Field Replaceable Unit Code - not used */
1262 u8 bit_ptr:3; /* indicates which byte of the CDB or parameter data
1263 * was in error
1264 */
1265 u8 BPV:1; /* bit pointer valid (BPV): 1- indicates that
1266 * the bit_ptr field has valid value
1267 */
1268 u8 reserved2:2;
1269 u8 CD:1; /* command data bit: 1- illegal parameter in CDB.
1270 * 0- illegal parameter in data.
1271 */
1272 u8 SKSV:1;
1273 u8 field_ptr[2]; /* byte of the CDB or parameter data in error */
1274};
1275
1276struct fsa_dev_info {
1277 u64 last;
1278 u64 size;
1279 u32 type;
1280 u32 config_waiting_on;
1281 unsigned long config_waiting_stamp;
1282 u16 queue_depth;
1283 u8 config_needed;
1284 u8 valid;
1285 u8 ro;
1286 u8 locked;
1287 u8 deleted;
1288 char devname[8];
1289 struct sense_data sense_data;
1290 u32 block_size;
1291 u8 identifier[16];
1292};
1293
1294struct fib {
1295 void *next; /* this is used by the allocator */
1296 s16 type;
1297 s16 size;
1298 /*
1299 * The Adapter that this I/O is destined for.
1300 */
1301 struct aac_dev *dev;
1302 /*
1303 * This is the event the sendfib routine will wait on if the
1304 * caller did not pass one and this is synch io.
1305 */
1306 struct completion event_wait;
1307 spinlock_t event_lock;
1308
1309 u32 done; /* gets set to 1 when fib is complete */
1310 fib_callback callback;
1311 void *callback_data;
1312 u32 flags; // u32 dmb was ulong
1313 /*
1314 * And for the internal issue/reply queues (we may be able
1315 * to merge these two)
1316 */
1317 struct list_head fiblink;
1318 void *data;
1319 u32 vector_no;
1320 struct hw_fib *hw_fib_va; /* also used for native */
1321 dma_addr_t hw_fib_pa; /* physical address of hw_fib*/
1322 dma_addr_t hw_sgl_pa; /* extra sgl for native */
1323 dma_addr_t hw_error_pa; /* error buffer for native */
1324 u32 hbacmd_size; /* cmd size for native */
1325};
1326
1327#define AAC_INIT 0
1328#define AAC_RESCAN 1
1329
1330#define AAC_DEVTYPE_RAID_MEMBER 1
1331#define AAC_DEVTYPE_ARC_RAW 2
1332#define AAC_DEVTYPE_NATIVE_RAW 3
1333
1334#define AAC_RESCAN_DELAY (10 * HZ)
1335
1336struct aac_hba_map_info {
1337 __le32 rmw_nexus; /* nexus for native HBA devices */
1338 u8 devtype; /* device type */
1339 s8 reset_state; /* 0 - no reset, 1..x - */
1340 /* after xth TM LUN reset */
1341 u16 qd_limit;
1342 u32 scan_counter;
1343 struct aac_ciss_identify_pd *safw_identify_resp;
1344};
1345
1346/*
1347 * Adapter Information Block
1348 *
1349 * This is returned by the RequestAdapterInfo block
1350 */
1351
1352struct aac_adapter_info
1353{
1354 __le32 platform;
1355 __le32 cpu;
1356 __le32 subcpu;
1357 __le32 clock;
1358 __le32 execmem;
1359 __le32 buffermem;
1360 __le32 totalmem;
1361 __le32 kernelrev;
1362 __le32 kernelbuild;
1363 __le32 monitorrev;
1364 __le32 monitorbuild;
1365 __le32 hwrev;
1366 __le32 hwbuild;
1367 __le32 biosrev;
1368 __le32 biosbuild;
1369 __le32 cluster;
1370 __le32 clusterchannelmask;
1371 __le32 serial[2];
1372 __le32 battery;
1373 __le32 options;
1374 __le32 OEM;
1375};
1376
1377struct aac_supplement_adapter_info
1378{
1379 u8 adapter_type_text[17+1];
1380 u8 pad[2];
1381 __le32 flash_memory_byte_size;
1382 __le32 flash_image_id;
1383 __le32 max_number_ports;
1384 __le32 version;
1385 __le32 feature_bits;
1386 u8 slot_number;
1387 u8 reserved_pad0[3];
1388 u8 build_date[12];
1389 __le32 current_number_ports;
1390 struct {
1391 u8 assembly_pn[8];
1392 u8 fru_pn[8];
1393 u8 battery_fru_pn[8];
1394 u8 ec_version_string[8];
1395 u8 tsid[12];
1396 } vpd_info;
1397 __le32 flash_firmware_revision;
1398 __le32 flash_firmware_build;
1399 __le32 raid_type_morph_options;
1400 __le32 flash_firmware_boot_revision;
1401 __le32 flash_firmware_boot_build;
1402 u8 mfg_pcba_serial_no[12];
1403 u8 mfg_wwn_name[8];
1404 __le32 supported_options2;
1405 __le32 struct_expansion;
1406 /* StructExpansion == 1 */
1407 __le32 feature_bits3;
1408 __le32 supported_performance_modes;
1409 u8 host_bus_type; /* uses HOST_BUS_TYPE_xxx defines */
1410 u8 host_bus_width; /* actual width in bits or links */
1411 u16 host_bus_speed; /* actual bus speed/link rate in MHz */
1412 u8 max_rrc_drives; /* max. number of ITP-RRC drives/pool */
1413 u8 max_disk_xtasks; /* max. possible num of DiskX Tasks */
1414
1415 u8 cpld_ver_loaded;
1416 u8 cpld_ver_in_flash;
1417
1418 __le64 max_rrc_capacity;
1419 __le32 compiled_max_hist_log_level;
1420 u8 custom_board_name[12];
1421 u16 supported_cntlr_mode; /* identify supported controller mode */
1422 u16 reserved_for_future16;
1423 __le32 supported_options3; /* reserved for future options */
1424
1425 __le16 virt_device_bus; /* virt. SCSI device for Thor */
1426 __le16 virt_device_target;
1427 __le16 virt_device_lun;
1428 __le16 unused;
1429 __le32 reserved_for_future_growth[68];
1430
1431};
1432#define AAC_FEATURE_FALCON cpu_to_le32(0x00000010)
1433#define AAC_FEATURE_JBOD cpu_to_le32(0x08000000)
1434/* SupportedOptions2 */
1435#define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001)
1436#define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002)
1437#define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004)
1438#define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000)
1439/* 4KB sector size */
1440#define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000)
1441/* 240 simple volume support */
1442#define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000)
1443/*
1444 * Supports FIB dump sync command send prior to IOP_RESET
1445 */
1446#define AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP cpu_to_le32(0x00004000)
1447#define AAC_SIS_VERSION_V3 3
1448#define AAC_SIS_SLOT_UNKNOWN 0xFF
1449
1450#define GetBusInfo 0x00000009
1451struct aac_bus_info {
1452 __le32 Command; /* VM_Ioctl */
1453 __le32 ObjType; /* FT_DRIVE */
1454 __le32 MethodId; /* 1 = SCSI Layer */
1455 __le32 ObjectId; /* Handle */
1456 __le32 CtlCmd; /* GetBusInfo */
1457};
1458
1459struct aac_bus_info_response {
1460 __le32 Status; /* ST_OK */
1461 __le32 ObjType;
1462 __le32 MethodId; /* unused */
1463 __le32 ObjectId; /* unused */
1464 __le32 CtlCmd; /* unused */
1465 __le32 ProbeComplete;
1466 __le32 BusCount;
1467 __le32 TargetsPerBus;
1468 u8 InitiatorBusId[10];
1469 u8 BusValid[10];
1470};
1471
1472/*
1473 * Battery platforms
1474 */
1475#define AAC_BAT_REQ_PRESENT (1)
1476#define AAC_BAT_REQ_NOTPRESENT (2)
1477#define AAC_BAT_OPT_PRESENT (3)
1478#define AAC_BAT_OPT_NOTPRESENT (4)
1479#define AAC_BAT_NOT_SUPPORTED (5)
1480/*
1481 * cpu types
1482 */
1483#define AAC_CPU_SIMULATOR (1)
1484#define AAC_CPU_I960 (2)
1485#define AAC_CPU_STRONGARM (3)
1486
1487/*
1488 * Supported Options
1489 */
1490#define AAC_OPT_SNAPSHOT cpu_to_le32(1)
1491#define AAC_OPT_CLUSTERS cpu_to_le32(1<<1)
1492#define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2)
1493#define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3)
1494#define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4)
1495#define AAC_OPT_RAID50 cpu_to_le32(1<<5)
1496#define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6)
1497#define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7)
1498#define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8)
1499#define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9)
1500#define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10)
1501#define AAC_OPT_ALARM cpu_to_le32(1<<11)
1502#define AAC_OPT_NONDASD cpu_to_le32(1<<12)
1503#define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13)
1504#define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14)
1505#define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16)
1506#define AAC_OPT_NEW_COMM cpu_to_le32(1<<17)
1507#define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18)
1508#define AAC_OPT_EXTENDED cpu_to_le32(1<<23)
1509#define AAC_OPT_NATIVE_HBA cpu_to_le32(1<<25)
1510#define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28)
1511#define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29)
1512#define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30)
1513#define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31)
1514
1515#define AAC_COMM_PRODUCER 0
1516#define AAC_COMM_MESSAGE 1
1517#define AAC_COMM_MESSAGE_TYPE1 3
1518#define AAC_COMM_MESSAGE_TYPE2 4
1519#define AAC_COMM_MESSAGE_TYPE3 5
1520
1521#define AAC_EXTOPT_SA_FIRMWARE cpu_to_le32(1<<1)
1522#define AAC_EXTOPT_SOFT_RESET cpu_to_le32(1<<16)
1523
1524/* MSIX context */
1525struct aac_msix_ctx {
1526 int vector_no;
1527 struct aac_dev *dev;
1528};
1529
1530struct aac_dev
1531{
1532 struct list_head entry;
1533 const char *name;
1534 int id;
1535
1536 /*
1537 * negotiated FIB settings
1538 */
1539 unsigned int max_fib_size;
1540 unsigned int sg_tablesize;
1541 unsigned int max_num_aif;
1542
1543 unsigned int max_cmd_size; /* max_fib_size or MAX_NATIVE */
1544
1545 /*
1546 * Map for 128 fib objects (64k)
1547 */
1548 dma_addr_t hw_fib_pa; /* also used for native cmd */
1549 struct hw_fib *hw_fib_va; /* also used for native cmd */
1550 struct hw_fib *aif_base_va;
1551 /*
1552 * Fib Headers
1553 */
1554 struct fib *fibs;
1555
1556 struct fib *free_fib;
1557 spinlock_t fib_lock;
1558
1559 struct mutex ioctl_mutex;
1560 struct mutex scan_mutex;
1561 struct aac_queue_block *queues;
1562 /*
1563 * The user API will use an IOCTL to register itself to receive
1564 * FIBs from the adapter. The following list is used to keep
1565 * track of all the threads that have requested these FIBs. The
1566 * mutex is used to synchronize access to all data associated
1567 * with the adapter fibs.
1568 */
1569 struct list_head fib_list;
1570
1571 struct adapter_ops a_ops;
1572 unsigned long fsrev; /* Main driver's revision number */
1573
1574 resource_size_t base_start; /* main IO base */
1575 resource_size_t dbg_base; /* address of UART
1576 * debug buffer */
1577
1578 resource_size_t base_size, dbg_size; /* Size of
1579 * mapped in region */
1580 /*
1581 * Holds initialization info
1582 * to communicate with adapter
1583 */
1584 union aac_init *init;
1585 dma_addr_t init_pa; /* Holds physical address of the init struct */
1586 /* response queue (if AAC_COMM_MESSAGE_TYPE1) */
1587 __le32 *host_rrq;
1588 dma_addr_t host_rrq_pa; /* phys. address */
1589 /* index into rrq buffer */
1590 u32 host_rrq_idx[AAC_MAX_MSIX];
1591 atomic_t rrq_outstanding[AAC_MAX_MSIX];
1592 u32 fibs_pushed_no;
1593 struct pci_dev *pdev; /* Our PCI interface */
1594 /* pointer to buffer used for printf's from the adapter */
1595 void *printfbuf;
1596 void *comm_addr; /* Base address of Comm area */
1597 dma_addr_t comm_phys; /* Physical Address of Comm area */
1598 size_t comm_size;
1599
1600 struct Scsi_Host *scsi_host_ptr;
1601 int maximum_num_containers;
1602 int maximum_num_physicals;
1603 int maximum_num_channels;
1604 struct fsa_dev_info *fsa_dev;
1605 struct task_struct *thread;
1606 struct delayed_work safw_rescan_work;
1607 struct delayed_work src_reinit_aif_worker;
1608 int cardtype;
1609 /*
1610 *This lock will protect the two 32-bit
1611 *writes to the Inbound Queue
1612 */
1613 spinlock_t iq_lock;
1614
1615 /*
1616 * The following is the device specific extension.
1617 */
1618#ifndef AAC_MIN_FOOTPRINT_SIZE
1619# define AAC_MIN_FOOTPRINT_SIZE 8192
1620# define AAC_MIN_SRC_BAR0_SIZE 0x400000
1621# define AAC_MIN_SRC_BAR1_SIZE 0x800
1622# define AAC_MIN_SRCV_BAR0_SIZE 0x100000
1623# define AAC_MIN_SRCV_BAR1_SIZE 0x400
1624#endif
1625 union
1626 {
1627 struct sa_registers __iomem *sa;
1628 struct rx_registers __iomem *rx;
1629 struct rkt_registers __iomem *rkt;
1630 struct {
1631 struct src_registers __iomem *bar0;
1632 char __iomem *bar1;
1633 } src;
1634 } regs;
1635 volatile void __iomem *base, *dbg_base_mapped;
1636 volatile struct rx_inbound __iomem *IndexRegs;
1637 u32 OIMR; /* Mask Register Cache */
1638 /*
1639 * AIF thread states
1640 */
1641 u32 aif_thread;
1642 struct aac_adapter_info adapter_info;
1643 struct aac_supplement_adapter_info supplement_adapter_info;
1644 /* These are in adapter info but they are in the io flow so
1645 * lets break them out so we don't have to do an AND to check them
1646 */
1647 u8 nondasd_support;
1648 u8 jbod;
1649 u8 cache_protected;
1650 u8 dac_support;
1651 u8 needs_dac;
1652 u8 raid_scsi_mode;
1653 u8 comm_interface;
1654 u8 raw_io_interface;
1655 u8 raw_io_64;
1656 u8 printf_enabled;
1657 u8 in_reset;
1658 u8 in_soft_reset;
1659 u8 msi;
1660 u8 sa_firmware;
1661 int management_fib_count;
1662 spinlock_t manage_lock;
1663 spinlock_t sync_lock;
1664 int sync_mode;
1665 struct fib *sync_fib;
1666 struct list_head sync_fib_list;
1667 u32 doorbell_mask;
1668 u32 max_msix; /* max. MSI-X vectors */
1669 u32 vector_cap; /* MSI-X vector capab.*/
1670 int msi_enabled; /* MSI/MSI-X enabled */
1671 atomic_t msix_counter;
1672 u32 scan_counter;
1673 struct msix_entry msixentry[AAC_MAX_MSIX];
1674 struct aac_msix_ctx aac_msix[AAC_MAX_MSIX]; /* context */
1675 struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS];
1676 struct aac_ciss_phys_luns_resp *safw_phys_luns;
1677 u8 adapter_shutdown;
1678 u32 handle_pci_error;
1679 bool init_reset;
1680 u8 soft_reset_support;
1681};
1682
1683#define aac_adapter_interrupt(dev) \
1684 (dev)->a_ops.adapter_interrupt(dev)
1685
1686#define aac_adapter_notify(dev, event) \
1687 (dev)->a_ops.adapter_notify(dev, event)
1688
1689#define aac_adapter_disable_int(dev) \
1690 (dev)->a_ops.adapter_disable_int(dev)
1691
1692#define aac_adapter_enable_int(dev) \
1693 (dev)->a_ops.adapter_enable_int(dev)
1694
1695#define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \
1696 (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4)
1697
1698#define aac_adapter_restart(dev, bled, reset_type) \
1699 ((dev)->a_ops.adapter_restart(dev, bled, reset_type))
1700
1701#define aac_adapter_start(dev) \
1702 ((dev)->a_ops.adapter_start(dev))
1703
1704#define aac_adapter_ioremap(dev, size) \
1705 (dev)->a_ops.adapter_ioremap(dev, size)
1706
1707#define aac_adapter_deliver(fib) \
1708 ((fib)->dev)->a_ops.adapter_deliver(fib)
1709
1710#define aac_adapter_bounds(dev,cmd,lba) \
1711 dev->a_ops.adapter_bounds(dev,cmd,lba)
1712
1713#define aac_adapter_read(fib,cmd,lba,count) \
1714 ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count)
1715
1716#define aac_adapter_write(fib,cmd,lba,count,fua) \
1717 ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua)
1718
1719#define aac_adapter_scsi(fib,cmd) \
1720 ((fib)->dev)->a_ops.adapter_scsi(fib,cmd)
1721
1722#define aac_adapter_comm(dev,comm) \
1723 (dev)->a_ops.adapter_comm(dev, comm)
1724
1725#define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001)
1726#define FIB_CONTEXT_FLAG (0x00000002)
1727#define FIB_CONTEXT_FLAG_WAIT (0x00000004)
1728#define FIB_CONTEXT_FLAG_FASTRESP (0x00000008)
1729#define FIB_CONTEXT_FLAG_NATIVE_HBA (0x00000010)
1730#define FIB_CONTEXT_FLAG_NATIVE_HBA_TMF (0x00000020)
1731#define FIB_CONTEXT_FLAG_SCSI_CMD (0x00000040)
1732#define FIB_CONTEXT_FLAG_EH_RESET (0x00000080)
1733
1734/*
1735 * Define the command values
1736 */
1737
1738#define Null 0
1739#define GetAttributes 1
1740#define SetAttributes 2
1741#define Lookup 3
1742#define ReadLink 4
1743#define Read 5
1744#define Write 6
1745#define Create 7
1746#define MakeDirectory 8
1747#define SymbolicLink 9
1748#define MakeNode 10
1749#define Removex 11
1750#define RemoveDirectoryx 12
1751#define Rename 13
1752#define Link 14
1753#define ReadDirectory 15
1754#define ReadDirectoryPlus 16
1755#define FileSystemStatus 17
1756#define FileSystemInfo 18
1757#define PathConfigure 19
1758#define Commit 20
1759#define Mount 21
1760#define UnMount 22
1761#define Newfs 23
1762#define FsCheck 24
1763#define FsSync 25
1764#define SimReadWrite 26
1765#define SetFileSystemStatus 27
1766#define BlockRead 28
1767#define BlockWrite 29
1768#define NvramIoctl 30
1769#define FsSyncWait 31
1770#define ClearArchiveBit 32
1771#define SetAcl 33
1772#define GetAcl 34
1773#define AssignAcl 35
1774#define FaultInsertion 36 /* Fault Insertion Command */
1775#define CrazyCache 37 /* Crazycache */
1776
1777#define MAX_FSACOMMAND_NUM 38
1778
1779
1780/*
1781 * Define the status returns. These are very unixlike although
1782 * most are not in fact used
1783 */
1784
1785#define ST_OK 0
1786#define ST_PERM 1
1787#define ST_NOENT 2
1788#define ST_IO 5
1789#define ST_NXIO 6
1790#define ST_E2BIG 7
1791#define ST_MEDERR 8
1792#define ST_ACCES 13
1793#define ST_EXIST 17
1794#define ST_XDEV 18
1795#define ST_NODEV 19
1796#define ST_NOTDIR 20
1797#define ST_ISDIR 21
1798#define ST_INVAL 22
1799#define ST_FBIG 27
1800#define ST_NOSPC 28
1801#define ST_ROFS 30
1802#define ST_MLINK 31
1803#define ST_WOULDBLOCK 35
1804#define ST_NAMETOOLONG 63
1805#define ST_NOTEMPTY 66
1806#define ST_DQUOT 69
1807#define ST_STALE 70
1808#define ST_REMOTE 71
1809#define ST_NOT_READY 72
1810#define ST_BADHANDLE 10001
1811#define ST_NOT_SYNC 10002
1812#define ST_BAD_COOKIE 10003
1813#define ST_NOTSUPP 10004
1814#define ST_TOOSMALL 10005
1815#define ST_SERVERFAULT 10006
1816#define ST_BADTYPE 10007
1817#define ST_JUKEBOX 10008
1818#define ST_NOTMOUNTED 10009
1819#define ST_MAINTMODE 10010
1820#define ST_STALEACL 10011
1821
1822/*
1823 * On writes how does the client want the data written.
1824 */
1825
1826#define CACHE_CSTABLE 1
1827#define CACHE_UNSTABLE 2
1828
1829/*
1830 * Lets the client know at which level the data was committed on
1831 * a write request
1832 */
1833
1834#define CMFILE_SYNCH_NVRAM 1
1835#define CMDATA_SYNCH_NVRAM 2
1836#define CMFILE_SYNCH 3
1837#define CMDATA_SYNCH 4
1838#define CMUNSTABLE 5
1839
1840#define RIO_TYPE_WRITE 0x0000
1841#define RIO_TYPE_READ 0x0001
1842#define RIO_SUREWRITE 0x0008
1843
1844#define RIO2_IO_TYPE 0x0003
1845#define RIO2_IO_TYPE_WRITE 0x0000
1846#define RIO2_IO_TYPE_READ 0x0001
1847#define RIO2_IO_TYPE_VERIFY 0x0002
1848#define RIO2_IO_ERROR 0x0004
1849#define RIO2_IO_SUREWRITE 0x0008
1850#define RIO2_SGL_CONFORMANT 0x0010
1851#define RIO2_SG_FORMAT 0xF000
1852#define RIO2_SG_FORMAT_ARC 0x0000
1853#define RIO2_SG_FORMAT_SRL 0x1000
1854#define RIO2_SG_FORMAT_IEEE1212 0x2000
1855
1856struct aac_read
1857{
1858 __le32 command;
1859 __le32 cid;
1860 __le32 block;
1861 __le32 count;
1862 struct sgmap sg; // Must be last in struct because it is variable
1863};
1864
1865struct aac_read64
1866{
1867 __le32 command;
1868 __le16 cid;
1869 __le16 sector_count;
1870 __le32 block;
1871 __le16 pad;
1872 __le16 flags;
1873 struct sgmap64 sg; // Must be last in struct because it is variable
1874};
1875
1876struct aac_read_reply
1877{
1878 __le32 status;
1879 __le32 count;
1880};
1881
1882struct aac_write
1883{
1884 __le32 command;
1885 __le32 cid;
1886 __le32 block;
1887 __le32 count;
1888 __le32 stable; // Not used
1889 struct sgmap sg; // Must be last in struct because it is variable
1890};
1891
1892struct aac_write64
1893{
1894 __le32 command;
1895 __le16 cid;
1896 __le16 sector_count;
1897 __le32 block;
1898 __le16 pad;
1899 __le16 flags;
1900 struct sgmap64 sg; // Must be last in struct because it is variable
1901};
1902struct aac_write_reply
1903{
1904 __le32 status;
1905 __le32 count;
1906 __le32 committed;
1907};
1908
1909struct aac_raw_io
1910{
1911 __le32 block[2];
1912 __le32 count;
1913 __le16 cid;
1914 __le16 flags; /* 00 W, 01 R */
1915 __le16 bpTotal; /* reserved for F/W use */
1916 __le16 bpComplete; /* reserved for F/W use */
1917 struct sgmapraw sg;
1918};
1919
1920struct aac_raw_io2 {
1921 __le32 blockLow;
1922 __le32 blockHigh;
1923 __le32 byteCount;
1924 __le16 cid;
1925 __le16 flags; /* RIO2 flags */
1926 __le32 sgeFirstSize; /* size of first sge el. */
1927 __le32 sgeNominalSize; /* size of 2nd sge el. (if conformant) */
1928 u8 sgeCnt; /* only 8 bits required */
1929 u8 bpTotal; /* reserved for F/W use */
1930 u8 bpComplete; /* reserved for F/W use */
1931 u8 sgeFirstIndex; /* reserved for F/W use */
1932 u8 unused[4];
1933 struct sge_ieee1212 sge[];
1934};
1935
1936#define CT_FLUSH_CACHE 129
1937struct aac_synchronize {
1938 __le32 command; /* VM_ContainerConfig */
1939 __le32 type; /* CT_FLUSH_CACHE */
1940 __le32 cid;
1941 __le32 parm1;
1942 __le32 parm2;
1943 __le32 parm3;
1944 __le32 parm4;
1945 __le32 count; /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */
1946};
1947
1948struct aac_synchronize_reply {
1949 __le32 dummy0;
1950 __le32 dummy1;
1951 __le32 status; /* CT_OK */
1952 __le32 parm1;
1953 __le32 parm2;
1954 __le32 parm3;
1955 __le32 parm4;
1956 __le32 parm5;
1957 u8 data[16];
1958};
1959
1960#define CT_POWER_MANAGEMENT 245
1961#define CT_PM_START_UNIT 2
1962#define CT_PM_STOP_UNIT 3
1963#define CT_PM_UNIT_IMMEDIATE 1
1964struct aac_power_management {
1965 __le32 command; /* VM_ContainerConfig */
1966 __le32 type; /* CT_POWER_MANAGEMENT */
1967 __le32 sub; /* CT_PM_* */
1968 __le32 cid;
1969 __le32 parm; /* CT_PM_sub_* */
1970};
1971
1972#define CT_PAUSE_IO 65
1973#define CT_RELEASE_IO 66
1974struct aac_pause {
1975 __le32 command; /* VM_ContainerConfig */
1976 __le32 type; /* CT_PAUSE_IO */
1977 __le32 timeout; /* 10ms ticks */
1978 __le32 min;
1979 __le32 noRescan;
1980 __le32 parm3;
1981 __le32 parm4;
1982 __le32 count; /* sizeof(((struct aac_pause_reply *)NULL)->data) */
1983};
1984
1985struct aac_srb
1986{
1987 __le32 function;
1988 __le32 channel;
1989 __le32 id;
1990 __le32 lun;
1991 __le32 timeout;
1992 __le32 flags;
1993 __le32 count; // Data xfer size
1994 __le32 retry_limit;
1995 __le32 cdb_size;
1996 u8 cdb[16];
1997 struct sgmap sg;
1998};
1999
2000/*
2001 * This and associated data structs are used by the
2002 * ioctl caller and are in cpu order.
2003 */
2004struct user_aac_srb
2005{
2006 u32 function;
2007 u32 channel;
2008 u32 id;
2009 u32 lun;
2010 u32 timeout;
2011 u32 flags;
2012 u32 count; // Data xfer size
2013 u32 retry_limit;
2014 u32 cdb_size;
2015 u8 cdb[16];
2016 struct user_sgmap sg;
2017};
2018
2019#define AAC_SENSE_BUFFERSIZE 30
2020
2021struct aac_srb_reply
2022{
2023 __le32 status;
2024 __le32 srb_status;
2025 __le32 scsi_status;
2026 __le32 data_xfer_length;
2027 __le32 sense_data_size;
2028 u8 sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE
2029};
2030
2031struct aac_srb_unit {
2032 struct aac_srb srb;
2033 struct aac_srb_reply srb_reply;
2034};
2035
2036/*
2037 * SRB Flags
2038 */
2039#define SRB_NoDataXfer 0x0000
2040#define SRB_DisableDisconnect 0x0004
2041#define SRB_DisableSynchTransfer 0x0008
2042#define SRB_BypassFrozenQueue 0x0010
2043#define SRB_DisableAutosense 0x0020
2044#define SRB_DataIn 0x0040
2045#define SRB_DataOut 0x0080
2046
2047/*
2048 * SRB Functions - set in aac_srb->function
2049 */
2050#define SRBF_ExecuteScsi 0x0000
2051#define SRBF_ClaimDevice 0x0001
2052#define SRBF_IO_Control 0x0002
2053#define SRBF_ReceiveEvent 0x0003
2054#define SRBF_ReleaseQueue 0x0004
2055#define SRBF_AttachDevice 0x0005
2056#define SRBF_ReleaseDevice 0x0006
2057#define SRBF_Shutdown 0x0007
2058#define SRBF_Flush 0x0008
2059#define SRBF_AbortCommand 0x0010
2060#define SRBF_ReleaseRecovery 0x0011
2061#define SRBF_ResetBus 0x0012
2062#define SRBF_ResetDevice 0x0013
2063#define SRBF_TerminateIO 0x0014
2064#define SRBF_FlushQueue 0x0015
2065#define SRBF_RemoveDevice 0x0016
2066#define SRBF_DomainValidation 0x0017
2067
2068/*
2069 * SRB SCSI Status - set in aac_srb->scsi_status
2070 */
2071#define SRB_STATUS_PENDING 0x00
2072#define SRB_STATUS_SUCCESS 0x01
2073#define SRB_STATUS_ABORTED 0x02
2074#define SRB_STATUS_ABORT_FAILED 0x03
2075#define SRB_STATUS_ERROR 0x04
2076#define SRB_STATUS_BUSY 0x05
2077#define SRB_STATUS_INVALID_REQUEST 0x06
2078#define SRB_STATUS_INVALID_PATH_ID 0x07
2079#define SRB_STATUS_NO_DEVICE 0x08
2080#define SRB_STATUS_TIMEOUT 0x09
2081#define SRB_STATUS_SELECTION_TIMEOUT 0x0A
2082#define SRB_STATUS_COMMAND_TIMEOUT 0x0B
2083#define SRB_STATUS_MESSAGE_REJECTED 0x0D
2084#define SRB_STATUS_BUS_RESET 0x0E
2085#define SRB_STATUS_PARITY_ERROR 0x0F
2086#define SRB_STATUS_REQUEST_SENSE_FAILED 0x10
2087#define SRB_STATUS_NO_HBA 0x11
2088#define SRB_STATUS_DATA_OVERRUN 0x12
2089#define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13
2090#define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14
2091#define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15
2092#define SRB_STATUS_REQUEST_FLUSHED 0x16
2093#define SRB_STATUS_DELAYED_RETRY 0x17
2094#define SRB_STATUS_INVALID_LUN 0x20
2095#define SRB_STATUS_INVALID_TARGET_ID 0x21
2096#define SRB_STATUS_BAD_FUNCTION 0x22
2097#define SRB_STATUS_ERROR_RECOVERY 0x23
2098#define SRB_STATUS_NOT_STARTED 0x24
2099#define SRB_STATUS_NOT_IN_USE 0x30
2100#define SRB_STATUS_FORCE_ABORT 0x31
2101#define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32
2102
2103/*
2104 * Object-Server / Volume-Manager Dispatch Classes
2105 */
2106
2107#define VM_Null 0
2108#define VM_NameServe 1
2109#define VM_ContainerConfig 2
2110#define VM_Ioctl 3
2111#define VM_FilesystemIoctl 4
2112#define VM_CloseAll 5
2113#define VM_CtBlockRead 6
2114#define VM_CtBlockWrite 7
2115#define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */
2116#define VM_SliceBlockWrite 9
2117#define VM_DriveBlockRead 10 /* raw access to physical devices */
2118#define VM_DriveBlockWrite 11
2119#define VM_EnclosureMgt 12 /* enclosure management */
2120#define VM_Unused 13 /* used to be diskset management */
2121#define VM_CtBlockVerify 14
2122#define VM_CtPerf 15 /* performance test */
2123#define VM_CtBlockRead64 16
2124#define VM_CtBlockWrite64 17
2125#define VM_CtBlockVerify64 18
2126#define VM_CtHostRead64 19
2127#define VM_CtHostWrite64 20
2128#define VM_DrvErrTblLog 21
2129#define VM_NameServe64 22
2130#define VM_NameServeAllBlk 30
2131
2132#define MAX_VMCOMMAND_NUM 23 /* used for sizing stats array - leave last */
2133
2134/*
2135 * Descriptive information (eg, vital stats)
2136 * that a content manager might report. The
2137 * FileArray filesystem component is one example
2138 * of a content manager. Raw mode might be
2139 * another.
2140 */
2141
2142struct aac_fsinfo {
2143 __le32 fsTotalSize; /* Consumed by fs, incl. metadata */
2144 __le32 fsBlockSize;
2145 __le32 fsFragSize;
2146 __le32 fsMaxExtendSize;
2147 __le32 fsSpaceUnits;
2148 __le32 fsMaxNumFiles;
2149 __le32 fsNumFreeFiles;
2150 __le32 fsInodeDensity;
2151}; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */
2152
2153struct aac_blockdevinfo {
2154 __le32 block_size;
2155 __le32 logical_phys_map;
2156 u8 identifier[16];
2157};
2158
2159union aac_contentinfo {
2160 struct aac_fsinfo filesys;
2161 struct aac_blockdevinfo bdevinfo;
2162};
2163
2164/*
2165 * Query for Container Configuration Status
2166 */
2167
2168#define CT_GET_CONFIG_STATUS 147
2169struct aac_get_config_status {
2170 __le32 command; /* VM_ContainerConfig */
2171 __le32 type; /* CT_GET_CONFIG_STATUS */
2172 __le32 parm1;
2173 __le32 parm2;
2174 __le32 parm3;
2175 __le32 parm4;
2176 __le32 parm5;
2177 __le32 count; /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */
2178};
2179
2180#define CFACT_CONTINUE 0
2181#define CFACT_PAUSE 1
2182#define CFACT_ABORT 2
2183struct aac_get_config_status_resp {
2184 __le32 response; /* ST_OK */
2185 __le32 dummy0;
2186 __le32 status; /* CT_OK */
2187 __le32 parm1;
2188 __le32 parm2;
2189 __le32 parm3;
2190 __le32 parm4;
2191 __le32 parm5;
2192 struct {
2193 __le32 action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */
2194 __le16 flags;
2195 __le16 count;
2196 } data;
2197};
2198
2199/*
2200 * Accept the configuration as-is
2201 */
2202
2203#define CT_COMMIT_CONFIG 152
2204
2205struct aac_commit_config {
2206 __le32 command; /* VM_ContainerConfig */
2207 __le32 type; /* CT_COMMIT_CONFIG */
2208};
2209
2210/*
2211 * Query for Container Configuration Status
2212 */
2213
2214#define CT_GET_CONTAINER_COUNT 4
2215struct aac_get_container_count {
2216 __le32 command; /* VM_ContainerConfig */
2217 __le32 type; /* CT_GET_CONTAINER_COUNT */
2218};
2219
2220struct aac_get_container_count_resp {
2221 __le32 response; /* ST_OK */
2222 __le32 dummy0;
2223 __le32 MaxContainers;
2224 __le32 ContainerSwitchEntries;
2225 __le32 MaxPartitions;
2226 __le32 MaxSimpleVolumes;
2227};
2228
2229
2230/*
2231 * Query for "mountable" objects, ie, objects that are typically
2232 * associated with a drive letter on the client (host) side.
2233 */
2234
2235struct aac_mntent {
2236 __le32 oid;
2237 u8 name[16]; /* if applicable */
2238 struct creation_info create_info; /* if applicable */
2239 __le32 capacity;
2240 __le32 vol; /* substrate structure */
2241 __le32 obj; /* FT_FILESYS, etc. */
2242 __le32 state; /* unready for mounting,
2243 readonly, etc. */
2244 union aac_contentinfo fileinfo; /* Info specific to content
2245 manager (eg, filesystem) */
2246 __le32 altoid; /* != oid <==> snapshot or
2247 broken mirror exists */
2248 __le32 capacityhigh;
2249};
2250
2251#define FSCS_NOTCLEAN 0x0001 /* fsck is necessary before mounting */
2252#define FSCS_READONLY 0x0002 /* possible result of broken mirror */
2253#define FSCS_HIDDEN 0x0004 /* should be ignored - set during a clear */
2254#define FSCS_NOT_READY 0x0008 /* Array spinning up to fulfil request */
2255
2256struct aac_query_mount {
2257 __le32 command;
2258 __le32 type;
2259 __le32 count;
2260};
2261
2262struct aac_mount {
2263 __le32 status;
2264 __le32 type; /* should be same as that requested */
2265 __le32 count;
2266 struct aac_mntent mnt[1];
2267};
2268
2269#define CT_READ_NAME 130
2270struct aac_get_name {
2271 __le32 command; /* VM_ContainerConfig */
2272 __le32 type; /* CT_READ_NAME */
2273 __le32 cid;
2274 __le32 parm1;
2275 __le32 parm2;
2276 __le32 parm3;
2277 __le32 parm4;
2278 __le32 count; /* sizeof(((struct aac_get_name_resp *)NULL)->data) */
2279};
2280
2281struct aac_get_name_resp {
2282 __le32 dummy0;
2283 __le32 dummy1;
2284 __le32 status; /* CT_OK */
2285 __le32 parm1;
2286 __le32 parm2;
2287 __le32 parm3;
2288 __le32 parm4;
2289 __le32 parm5;
2290 u8 data[17];
2291};
2292
2293#define CT_CID_TO_32BITS_UID 165
2294struct aac_get_serial {
2295 __le32 command; /* VM_ContainerConfig */
2296 __le32 type; /* CT_CID_TO_32BITS_UID */
2297 __le32 cid;
2298};
2299
2300struct aac_get_serial_resp {
2301 __le32 dummy0;
2302 __le32 dummy1;
2303 __le32 status; /* CT_OK */
2304 __le32 uid;
2305};
2306
2307/*
2308 * The following command is sent to shut down each container.
2309 */
2310
2311struct aac_close {
2312 __le32 command;
2313 __le32 cid;
2314};
2315
2316struct aac_query_disk
2317{
2318 s32 cnum;
2319 s32 bus;
2320 s32 id;
2321 s32 lun;
2322 u32 valid;
2323 u32 locked;
2324 u32 deleted;
2325 s32 instance;
2326 s8 name[10];
2327 u32 unmapped;
2328};
2329
2330struct aac_delete_disk {
2331 u32 disknum;
2332 u32 cnum;
2333};
2334
2335struct fib_ioctl
2336{
2337 u32 fibctx;
2338 s32 wait;
2339 char __user *fib;
2340};
2341
2342struct revision
2343{
2344 u32 compat;
2345 __le32 version;
2346 __le32 build;
2347};
2348
2349
2350/*
2351 * Ugly - non Linux like ioctl coding for back compat.
2352 */
2353
2354#define CTL_CODE(function, method) ( \
2355 (4<< 16) | ((function) << 2) | (method) \
2356)
2357
2358/*
2359 * Define the method codes for how buffers are passed for I/O and FS
2360 * controls
2361 */
2362
2363#define METHOD_BUFFERED 0
2364#define METHOD_NEITHER 3
2365
2366/*
2367 * Filesystem ioctls
2368 */
2369
2370#define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED)
2371#define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED)
2372#define FSACTL_DELETE_DISK 0x163
2373#define FSACTL_QUERY_DISK 0x173
2374#define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED)
2375#define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED)
2376#define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED)
2377#define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED)
2378#define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED)
2379#define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER)
2380#define FSACTL_GET_CONTAINERS 2131
2381#define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED)
2382#define FSACTL_RESET_IOP CTL_CODE(2140, METHOD_BUFFERED)
2383#define FSACTL_GET_HBA_INFO CTL_CODE(2150, METHOD_BUFFERED)
2384/* flags defined for IOP & HW SOFT RESET */
2385#define HW_IOP_RESET 0x01
2386#define HW_SOFT_RESET 0x02
2387#define IOP_HWSOFT_RESET (HW_IOP_RESET | HW_SOFT_RESET)
2388/* HW Soft Reset register offset */
2389#define IBW_SWR_OFFSET 0x4000
2390#define SOFT_RESET_TIME 60
2391
2392
2393
2394struct aac_common
2395{
2396 /*
2397 * If this value is set to 1 then interrupt moderation will occur
2398 * in the base commuication support.
2399 */
2400 u32 irq_mod;
2401 u32 peak_fibs;
2402 u32 zero_fibs;
2403 u32 fib_timeouts;
2404 /*
2405 * Statistical counters in debug mode
2406 */
2407#ifdef DBG
2408 u32 FibsSent;
2409 u32 FibRecved;
2410 u32 NativeSent;
2411 u32 NativeRecved;
2412 u32 NoResponseSent;
2413 u32 NoResponseRecved;
2414 u32 AsyncSent;
2415 u32 AsyncRecved;
2416 u32 NormalSent;
2417 u32 NormalRecved;
2418#endif
2419};
2420
2421extern struct aac_common aac_config;
2422
2423/*
2424 * This is for management ioctl purpose only.
2425 */
2426struct aac_hba_info {
2427
2428 u8 driver_name[50];
2429 u8 adapter_number;
2430 u8 system_io_bus_number;
2431 u8 device_number;
2432 u32 function_number;
2433 u32 vendor_id;
2434 u32 device_id;
2435 u32 sub_vendor_id;
2436 u32 sub_system_id;
2437 u32 mapped_base_address_size;
2438 u32 base_physical_address_high_part;
2439 u32 base_physical_address_low_part;
2440
2441 u32 max_command_size;
2442 u32 max_fib_size;
2443 u32 max_scatter_gather_from_os;
2444 u32 max_scatter_gather_to_fw;
2445 u32 max_outstanding_fibs;
2446
2447 u32 queue_start_threshold;
2448 u32 queue_dump_threshold;
2449 u32 max_io_size_queued;
2450 u32 outstanding_io;
2451
2452 u32 firmware_build_number;
2453 u32 bios_build_number;
2454 u32 driver_build_number;
2455 u32 serial_number_high_part;
2456 u32 serial_number_low_part;
2457 u32 supported_options;
2458 u32 feature_bits;
2459 u32 currentnumber_ports;
2460
2461 u8 new_comm_interface:1;
2462 u8 new_commands_supported:1;
2463 u8 disable_passthrough:1;
2464 u8 expose_non_dasd:1;
2465 u8 queue_allowed:1;
2466 u8 bled_check_enabled:1;
2467 u8 reserved1:1;
2468 u8 reserted2:1;
2469
2470 u32 reserved3[10];
2471
2472};
2473
2474/*
2475 * The following macro is used when sending and receiving FIBs. It is
2476 * only used for debugging.
2477 */
2478
2479#ifdef DBG
2480#define FIB_COUNTER_INCREMENT(counter) (counter)++
2481#else
2482#define FIB_COUNTER_INCREMENT(counter)
2483#endif
2484
2485/*
2486 * Adapter direct commands
2487 * Monitor/Kernel API
2488 */
2489
2490#define BREAKPOINT_REQUEST 0x00000004
2491#define INIT_STRUCT_BASE_ADDRESS 0x00000005
2492#define READ_PERMANENT_PARAMETERS 0x0000000a
2493#define WRITE_PERMANENT_PARAMETERS 0x0000000b
2494#define HOST_CRASHING 0x0000000d
2495#define SEND_SYNCHRONOUS_FIB 0x0000000c
2496#define COMMAND_POST_RESULTS 0x00000014
2497#define GET_ADAPTER_PROPERTIES 0x00000019
2498#define GET_DRIVER_BUFFER_PROPERTIES 0x00000023
2499#define RCV_TEMP_READINGS 0x00000025
2500#define GET_COMM_PREFERRED_SETTINGS 0x00000026
2501#define IOP_RESET_FW_FIB_DUMP 0x00000034
2502#define DROP_IO 0x00000035
2503#define IOP_RESET 0x00001000
2504#define IOP_RESET_ALWAYS 0x00001001
2505#define RE_INIT_ADAPTER 0x000000ee
2506
2507#define IOP_SRC_RESET_MASK 0x00000100
2508
2509/*
2510 * Adapter Status Register
2511 *
2512 * Phase Staus mailbox is 32bits:
2513 * <31:16> = Phase Status
2514 * <15:0> = Phase
2515 *
2516 * The adapter reports is present state through the phase. Only
2517 * a single phase should be ever be set. Each phase can have multiple
2518 * phase status bits to provide more detailed information about the
2519 * state of the board. Care should be taken to ensure that any phase
2520 * status bits that are set when changing the phase are also valid
2521 * for the new phase or be cleared out. Adapter software (monitor,
2522 * iflash, kernel) is responsible for properly maintining the phase
2523 * status mailbox when it is running.
2524 *
2525 * MONKER_API Phases
2526 *
2527 * Phases are bit oriented. It is NOT valid to have multiple bits set
2528 */
2529
2530#define SELF_TEST_FAILED 0x00000004
2531#define MONITOR_PANIC 0x00000020
2532#define KERNEL_BOOTING 0x00000040
2533#define KERNEL_UP_AND_RUNNING 0x00000080
2534#define KERNEL_PANIC 0x00000100
2535#define FLASH_UPD_PENDING 0x00002000
2536#define FLASH_UPD_SUCCESS 0x00004000
2537#define FLASH_UPD_FAILED 0x00008000
2538#define INVALID_OMR 0xffffffff
2539#define FWUPD_TIMEOUT (5 * 60)
2540
2541/*
2542 * Doorbell bit defines
2543 */
2544
2545#define DoorBellSyncCmdAvailable (1<<0) /* Host -> Adapter */
2546#define DoorBellPrintfDone (1<<5) /* Host -> Adapter */
2547#define DoorBellAdapterNormCmdReady (1<<1) /* Adapter -> Host */
2548#define DoorBellAdapterNormRespReady (1<<2) /* Adapter -> Host */
2549#define DoorBellAdapterNormCmdNotFull (1<<3) /* Adapter -> Host */
2550#define DoorBellAdapterNormRespNotFull (1<<4) /* Adapter -> Host */
2551#define DoorBellPrintfReady (1<<5) /* Adapter -> Host */
2552#define DoorBellAifPending (1<<6) /* Adapter -> Host */
2553
2554/* PMC specific outbound doorbell bits */
2555#define PmDoorBellResponseSent (1<<1) /* Adapter -> Host */
2556
2557/*
2558 * For FIB communication, we need all of the following things
2559 * to send back to the user.
2560 */
2561
2562#define AifCmdEventNotify 1 /* Notify of event */
2563#define AifEnConfigChange 3 /* Adapter configuration change */
2564#define AifEnContainerChange 4 /* Container configuration change */
2565#define AifEnDeviceFailure 5 /* SCSI device failed */
2566#define AifEnEnclosureManagement 13 /* EM_DRIVE_* */
2567#define EM_DRIVE_INSERTION 31
2568#define EM_DRIVE_REMOVAL 32
2569#define EM_SES_DRIVE_INSERTION 33
2570#define EM_SES_DRIVE_REMOVAL 26
2571#define AifEnBatteryEvent 14 /* Change in Battery State */
2572#define AifEnAddContainer 15 /* A new array was created */
2573#define AifEnDeleteContainer 16 /* A container was deleted */
2574#define AifEnExpEvent 23 /* Firmware Event Log */
2575#define AifExeFirmwarePanic 3 /* Firmware Event Panic */
2576#define AifHighPriority 3 /* Highest Priority Event */
2577#define AifEnAddJBOD 30 /* JBOD created */
2578#define AifEnDeleteJBOD 31 /* JBOD deleted */
2579
2580#define AifBuManagerEvent 42 /* Bu management*/
2581#define AifBuCacheDataLoss 10
2582#define AifBuCacheDataRecover 11
2583
2584#define AifCmdJobProgress 2 /* Progress report */
2585#define AifJobCtrZero 101 /* Array Zero progress */
2586#define AifJobStsSuccess 1 /* Job completes */
2587#define AifJobStsRunning 102 /* Job running */
2588#define AifCmdAPIReport 3 /* Report from other user of API */
2589#define AifCmdDriverNotify 4 /* Notify host driver of event */
2590#define AifDenMorphComplete 200 /* A morph operation completed */
2591#define AifDenVolumeExtendComplete 201 /* A volume extend completed */
2592#define AifReqJobList 100 /* Gets back complete job list */
2593#define AifReqJobsForCtr 101 /* Gets back jobs for specific container */
2594#define AifReqJobsForScsi 102 /* Gets back jobs for specific SCSI device */
2595#define AifReqJobReport 103 /* Gets back a specific job report or list of them */
2596#define AifReqTerminateJob 104 /* Terminates job */
2597#define AifReqSuspendJob 105 /* Suspends a job */
2598#define AifReqResumeJob 106 /* Resumes a job */
2599#define AifReqSendAPIReport 107 /* API generic report requests */
2600#define AifReqAPIJobStart 108 /* Start a job from the API */
2601#define AifReqAPIJobUpdate 109 /* Update a job report from the API */
2602#define AifReqAPIJobFinish 110 /* Finish a job from the API */
2603
2604/* PMC NEW COMM: Request the event data */
2605#define AifReqEvent 200
2606#define AifRawDeviceRemove 203 /* RAW device deleted */
2607#define AifNativeDeviceAdd 204 /* native HBA device added */
2608#define AifNativeDeviceRemove 205 /* native HBA device removed */
2609
2610
2611/*
2612 * Adapter Initiated FIB command structures. Start with the adapter
2613 * initiated FIBs that really come from the adapter, and get responded
2614 * to by the host.
2615 */
2616
2617struct aac_aifcmd {
2618 __le32 command; /* Tell host what type of notify this is */
2619 __le32 seqnum; /* To allow ordering of reports (if necessary) */
2620 u8 data[]; /* Undefined length (from kernel viewpoint) */
2621};
2622
2623/**
2624 * Convert capacity to cylinders
2625 * accounting for the fact capacity could be a 64 bit value
2626 *
2627 */
2628static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor)
2629{
2630 sector_div(capacity, divisor);
2631 return capacity;
2632}
2633
2634static inline int aac_pci_offline(struct aac_dev *dev)
2635{
2636 return pci_channel_offline(dev->pdev) || dev->handle_pci_error;
2637}
2638
2639static inline int aac_adapter_check_health(struct aac_dev *dev)
2640{
2641 if (unlikely(aac_pci_offline(dev)))
2642 return -1;
2643
2644 return (dev)->a_ops.adapter_check_health(dev);
2645}
2646
2647
2648int aac_scan_host(struct aac_dev *dev);
2649
2650static inline void aac_schedule_safw_scan_worker(struct aac_dev *dev)
2651{
2652 schedule_delayed_work(&dev->safw_rescan_work, AAC_RESCAN_DELAY);
2653}
2654
2655static inline void aac_schedule_src_reinit_aif_worker(struct aac_dev *dev)
2656{
2657 schedule_delayed_work(&dev->src_reinit_aif_worker, AAC_RESCAN_DELAY);
2658}
2659
2660static inline void aac_safw_rescan_worker(struct work_struct *work)
2661{
2662 struct aac_dev *dev = container_of(to_delayed_work(work),
2663 struct aac_dev, safw_rescan_work);
2664
2665 wait_event(dev->scsi_host_ptr->host_wait,
2666 !scsi_host_in_recovery(dev->scsi_host_ptr));
2667
2668 aac_scan_host(dev);
2669}
2670
2671static inline void aac_cancel_rescan_worker(struct aac_dev *dev)
2672{
2673 cancel_delayed_work_sync(&dev->safw_rescan_work);
2674 cancel_delayed_work_sync(&dev->src_reinit_aif_worker);
2675}
2676
2677enum aac_cmd_owner {
2678 AAC_OWNER_MIDLEVEL = 0x101,
2679 AAC_OWNER_LOWLEVEL = 0x102,
2680 AAC_OWNER_ERROR_HANDLER = 0x103,
2681 AAC_OWNER_FIRMWARE = 0x106,
2682};
2683
2684struct aac_cmd_priv {
2685 int (*callback)(struct scsi_cmnd *);
2686 int status;
2687 enum aac_cmd_owner owner;
2688 bool sent_command;
2689};
2690
2691static inline struct aac_cmd_priv *aac_priv(struct scsi_cmnd *cmd)
2692{
2693 return scsi_cmd_priv(cmd);
2694}
2695
2696void aac_safw_rescan_worker(struct work_struct *work);
2697void aac_src_reinit_aif_worker(struct work_struct *work);
2698int aac_acquire_irq(struct aac_dev *dev);
2699void aac_free_irq(struct aac_dev *dev);
2700int aac_setup_safw_adapter(struct aac_dev *dev);
2701const char *aac_driverinfo(struct Scsi_Host *);
2702void aac_fib_vector_assign(struct aac_dev *dev);
2703struct fib *aac_fib_alloc(struct aac_dev *dev);
2704struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd);
2705int aac_fib_setup(struct aac_dev *dev);
2706void aac_fib_map_free(struct aac_dev *dev);
2707void aac_fib_free(struct fib * context);
2708void aac_fib_init(struct fib * context);
2709void aac_printf(struct aac_dev *dev, u32 val);
2710int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt);
2711int aac_hba_send(u8 command, struct fib *context,
2712 fib_callback callback, void *ctxt);
2713int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry);
2714void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum);
2715int aac_fib_complete(struct fib * context);
2716void aac_hba_callback(void *context, struct fib *fibptr);
2717#define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data)
2718struct aac_dev *aac_init_adapter(struct aac_dev *dev);
2719void aac_src_access_devreg(struct aac_dev *dev, int mode);
2720void aac_set_intx_mode(struct aac_dev *dev);
2721int aac_get_config_status(struct aac_dev *dev, int commit_flag);
2722int aac_get_containers(struct aac_dev *dev);
2723int aac_scsi_cmd(struct scsi_cmnd *cmd);
2724int aac_dev_ioctl(struct aac_dev *dev, unsigned int cmd, void __user *arg);
2725#ifndef shost_to_class
2726#define shost_to_class(shost) &shost->shost_dev
2727#endif
2728ssize_t aac_get_serial_number(struct device *dev, char *buf);
2729int aac_do_ioctl(struct aac_dev *dev, unsigned int cmd, void __user *arg);
2730int aac_rx_init(struct aac_dev *dev);
2731int aac_rkt_init(struct aac_dev *dev);
2732int aac_nark_init(struct aac_dev *dev);
2733int aac_sa_init(struct aac_dev *dev);
2734int aac_src_init(struct aac_dev *dev);
2735int aac_srcv_init(struct aac_dev *dev);
2736int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify);
2737void aac_define_int_mode(struct aac_dev *dev);
2738unsigned int aac_response_normal(struct aac_queue * q);
2739unsigned int aac_command_normal(struct aac_queue * q);
2740unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index,
2741 int isAif, int isFastResponse,
2742 struct hw_fib *aif_fib);
2743int aac_reset_adapter(struct aac_dev *dev, int forced, u8 reset_type);
2744int aac_check_health(struct aac_dev * dev);
2745int aac_command_thread(void *data);
2746int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx);
2747int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size);
2748struct aac_driver_ident* aac_get_driver_ident(int devtype);
2749int aac_get_adapter_info(struct aac_dev* dev);
2750int aac_send_shutdown(struct aac_dev *dev);
2751int aac_probe_container(struct aac_dev *dev, int cid);
2752int _aac_rx_init(struct aac_dev *dev);
2753int aac_rx_select_comm(struct aac_dev *dev, int comm);
2754int aac_rx_deliver_producer(struct fib * fib);
2755void aac_reinit_aif(struct aac_dev *aac, unsigned int index);
2756
2757static inline int aac_is_src(struct aac_dev *dev)
2758{
2759 u16 device = dev->pdev->device;
2760
2761 if (device == PMC_DEVICE_S6 ||
2762 device == PMC_DEVICE_S7 ||
2763 device == PMC_DEVICE_S8)
2764 return 1;
2765 return 0;
2766}
2767
2768static inline int aac_supports_2T(struct aac_dev *dev)
2769{
2770 return (dev->adapter_info.options & AAC_OPT_NEW_COMM_64);
2771}
2772
2773char * get_container_type(unsigned type);
2774extern int numacb;
2775extern char aac_driver_version[];
2776extern int startup_timeout;
2777extern int aif_timeout;
2778extern int expose_physicals;
2779extern int aac_reset_devices;
2780extern int aac_msi;
2781extern int aac_commit;
2782extern int update_interval;
2783extern int check_interval;
2784extern int aac_check_reset;
2785extern int aac_fib_dump;
2786#endif