Loading...
1/*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/signal.h>
34#include <linux/jiffies.h>
35#include <linux/timer.h>
36#include <linux/pci.h>
37#include <linux/interrupt.h>
38#include <linux/time.h>
39#include <linux/slab.h>
40
41#include "../pci.h"
42#include "pciehp.h"
43
44static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
45{
46 return ctrl->pcie->port;
47}
48
49static irqreturn_t pcie_isr(int irq, void *dev_id);
50static void start_int_poll_timer(struct controller *ctrl, int sec);
51
52/* This is the interrupt polling timeout function. */
53static void int_poll_timeout(unsigned long data)
54{
55 struct controller *ctrl = (struct controller *)data;
56
57 /* Poll for interrupt events. regs == NULL => polling */
58 pcie_isr(0, ctrl);
59
60 init_timer(&ctrl->poll_timer);
61 if (!pciehp_poll_time)
62 pciehp_poll_time = 2; /* default polling interval is 2 sec */
63
64 start_int_poll_timer(ctrl, pciehp_poll_time);
65}
66
67/* This function starts the interrupt polling timer. */
68static void start_int_poll_timer(struct controller *ctrl, int sec)
69{
70 /* Clamp to sane value */
71 if ((sec <= 0) || (sec > 60))
72 sec = 2;
73
74 ctrl->poll_timer.function = &int_poll_timeout;
75 ctrl->poll_timer.data = (unsigned long)ctrl;
76 ctrl->poll_timer.expires = jiffies + sec * HZ;
77 add_timer(&ctrl->poll_timer);
78}
79
80static inline int pciehp_request_irq(struct controller *ctrl)
81{
82 int retval, irq = ctrl->pcie->irq;
83
84 /* Install interrupt polling timer. Start with 10 sec delay */
85 if (pciehp_poll_mode) {
86 init_timer(&ctrl->poll_timer);
87 start_int_poll_timer(ctrl, 10);
88 return 0;
89 }
90
91 /* Installs the interrupt handler */
92 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
93 if (retval)
94 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
95 irq);
96 return retval;
97}
98
99static inline void pciehp_free_irq(struct controller *ctrl)
100{
101 if (pciehp_poll_mode)
102 del_timer_sync(&ctrl->poll_timer);
103 else
104 free_irq(ctrl->pcie->irq, ctrl);
105}
106
107static int pcie_poll_cmd(struct controller *ctrl)
108{
109 struct pci_dev *pdev = ctrl_dev(ctrl);
110 u16 slot_status;
111 int timeout = 1000;
112
113 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
114 if (slot_status & PCI_EXP_SLTSTA_CC) {
115 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
116 PCI_EXP_SLTSTA_CC);
117 return 1;
118 }
119 while (timeout > 0) {
120 msleep(10);
121 timeout -= 10;
122 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
123 if (slot_status & PCI_EXP_SLTSTA_CC) {
124 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
125 PCI_EXP_SLTSTA_CC);
126 return 1;
127 }
128 }
129 return 0; /* timeout */
130}
131
132static void pcie_wait_cmd(struct controller *ctrl, int poll)
133{
134 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
135 unsigned long timeout = msecs_to_jiffies(msecs);
136 int rc;
137
138 if (poll)
139 rc = pcie_poll_cmd(ctrl);
140 else
141 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
142 if (!rc)
143 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
144}
145
146/**
147 * pcie_write_cmd - Issue controller command
148 * @ctrl: controller to which the command is issued
149 * @cmd: command value written to slot control register
150 * @mask: bitmask of slot control register to be modified
151 */
152static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
153{
154 struct pci_dev *pdev = ctrl_dev(ctrl);
155 u16 slot_status;
156 u16 slot_ctrl;
157
158 mutex_lock(&ctrl->ctrl_lock);
159
160 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
161 if (slot_status & PCI_EXP_SLTSTA_CC) {
162 if (!ctrl->no_cmd_complete) {
163 /*
164 * After 1 sec and CMD_COMPLETED still not set, just
165 * proceed forward to issue the next command according
166 * to spec. Just print out the error message.
167 */
168 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
169 } else if (!NO_CMD_CMPL(ctrl)) {
170 /*
171 * This controller seems to notify of command completed
172 * event even though it supports none of power
173 * controller, attention led, power led and EMI.
174 */
175 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
176 "wait for command completed event.\n");
177 ctrl->no_cmd_complete = 0;
178 } else {
179 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
180 "the controller is broken.\n");
181 }
182 }
183
184 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
185 slot_ctrl &= ~mask;
186 slot_ctrl |= (cmd & mask);
187 ctrl->cmd_busy = 1;
188 smp_mb();
189 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
190
191 /*
192 * Wait for command completion.
193 */
194 if (!ctrl->no_cmd_complete) {
195 int poll = 0;
196 /*
197 * if hotplug interrupt is not enabled or command
198 * completed interrupt is not enabled, we need to poll
199 * command completed event.
200 */
201 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
202 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
203 poll = 1;
204 pcie_wait_cmd(ctrl, poll);
205 }
206 mutex_unlock(&ctrl->ctrl_lock);
207}
208
209bool pciehp_check_link_active(struct controller *ctrl)
210{
211 struct pci_dev *pdev = ctrl_dev(ctrl);
212 u16 lnk_status;
213 bool ret;
214
215 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
216 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
217
218 if (ret)
219 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
220
221 return ret;
222}
223
224static void __pcie_wait_link_active(struct controller *ctrl, bool active)
225{
226 int timeout = 1000;
227
228 if (pciehp_check_link_active(ctrl) == active)
229 return;
230 while (timeout > 0) {
231 msleep(10);
232 timeout -= 10;
233 if (pciehp_check_link_active(ctrl) == active)
234 return;
235 }
236 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
237 active ? "set" : "cleared");
238}
239
240static void pcie_wait_link_active(struct controller *ctrl)
241{
242 __pcie_wait_link_active(ctrl, true);
243}
244
245static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
246{
247 u32 l;
248 int count = 0;
249 int delay = 1000, step = 20;
250 bool found = false;
251
252 do {
253 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
254 count++;
255
256 if (found)
257 break;
258
259 msleep(step);
260 delay -= step;
261 } while (delay > 0);
262
263 if (count > 1 && pciehp_debug)
264 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
265 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
266 PCI_FUNC(devfn), count, step, l);
267
268 return found;
269}
270
271int pciehp_check_link_status(struct controller *ctrl)
272{
273 struct pci_dev *pdev = ctrl_dev(ctrl);
274 bool found;
275 u16 lnk_status;
276
277 /*
278 * Data Link Layer Link Active Reporting must be capable for
279 * hot-plug capable downstream port. But old controller might
280 * not implement it. In this case, we wait for 1000 ms.
281 */
282 if (ctrl->link_active_reporting)
283 pcie_wait_link_active(ctrl);
284 else
285 msleep(1000);
286
287 /* wait 100ms before read pci conf, and try in 1s */
288 msleep(100);
289 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
290 PCI_DEVFN(0, 0));
291
292 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
293 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
294 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
295 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
296 ctrl_err(ctrl, "Link Training Error occurs \n");
297 return -1;
298 }
299
300 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
301
302 if (!found)
303 return -1;
304
305 return 0;
306}
307
308static int __pciehp_link_set(struct controller *ctrl, bool enable)
309{
310 struct pci_dev *pdev = ctrl_dev(ctrl);
311 u16 lnk_ctrl;
312
313 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
314
315 if (enable)
316 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
317 else
318 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
319
320 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
321 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
322 return 0;
323}
324
325static int pciehp_link_enable(struct controller *ctrl)
326{
327 return __pciehp_link_set(ctrl, true);
328}
329
330void pciehp_get_attention_status(struct slot *slot, u8 *status)
331{
332 struct controller *ctrl = slot->ctrl;
333 struct pci_dev *pdev = ctrl_dev(ctrl);
334 u16 slot_ctrl;
335
336 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
337 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
338 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
339
340 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
341 case PCI_EXP_SLTCTL_ATTN_IND_ON:
342 *status = 1; /* On */
343 break;
344 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
345 *status = 2; /* Blink */
346 break;
347 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
348 *status = 0; /* Off */
349 break;
350 default:
351 *status = 0xFF;
352 break;
353 }
354}
355
356void pciehp_get_power_status(struct slot *slot, u8 *status)
357{
358 struct controller *ctrl = slot->ctrl;
359 struct pci_dev *pdev = ctrl_dev(ctrl);
360 u16 slot_ctrl;
361
362 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
363 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
364 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
365
366 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
367 case PCI_EXP_SLTCTL_PWR_ON:
368 *status = 1; /* On */
369 break;
370 case PCI_EXP_SLTCTL_PWR_OFF:
371 *status = 0; /* Off */
372 break;
373 default:
374 *status = 0xFF;
375 break;
376 }
377}
378
379void pciehp_get_latch_status(struct slot *slot, u8 *status)
380{
381 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
382 u16 slot_status;
383
384 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
385 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
386}
387
388void pciehp_get_adapter_status(struct slot *slot, u8 *status)
389{
390 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
391 u16 slot_status;
392
393 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
394 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
395}
396
397int pciehp_query_power_fault(struct slot *slot)
398{
399 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
400 u16 slot_status;
401
402 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
403 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
404}
405
406void pciehp_set_attention_status(struct slot *slot, u8 value)
407{
408 struct controller *ctrl = slot->ctrl;
409 u16 slot_cmd;
410
411 if (!ATTN_LED(ctrl))
412 return;
413
414 switch (value) {
415 case 0 : /* turn off */
416 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
417 break;
418 case 1: /* turn on */
419 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
420 break;
421 case 2: /* turn blink */
422 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
423 break;
424 default:
425 return;
426 }
427 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
428 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
429 pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
430}
431
432void pciehp_green_led_on(struct slot *slot)
433{
434 struct controller *ctrl = slot->ctrl;
435
436 if (!PWR_LED(ctrl))
437 return;
438
439 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, PCI_EXP_SLTCTL_PIC);
440 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
441 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
442 PCI_EXP_SLTCTL_PWR_IND_ON);
443}
444
445void pciehp_green_led_off(struct slot *slot)
446{
447 struct controller *ctrl = slot->ctrl;
448
449 if (!PWR_LED(ctrl))
450 return;
451
452 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, PCI_EXP_SLTCTL_PIC);
453 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
454 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
455 PCI_EXP_SLTCTL_PWR_IND_OFF);
456}
457
458void pciehp_green_led_blink(struct slot *slot)
459{
460 struct controller *ctrl = slot->ctrl;
461
462 if (!PWR_LED(ctrl))
463 return;
464
465 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, PCI_EXP_SLTCTL_PIC);
466 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
467 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
468 PCI_EXP_SLTCTL_PWR_IND_BLINK);
469}
470
471int pciehp_power_on_slot(struct slot * slot)
472{
473 struct controller *ctrl = slot->ctrl;
474 struct pci_dev *pdev = ctrl_dev(ctrl);
475 u16 slot_status;
476 int retval;
477
478 /* Clear sticky power-fault bit from previous power failures */
479 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
480 if (slot_status & PCI_EXP_SLTSTA_PFD)
481 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
482 PCI_EXP_SLTSTA_PFD);
483 ctrl->power_fault_detected = 0;
484
485 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
486 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
487 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
488 PCI_EXP_SLTCTL_PWR_ON);
489
490 retval = pciehp_link_enable(ctrl);
491 if (retval)
492 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
493
494 return retval;
495}
496
497void pciehp_power_off_slot(struct slot * slot)
498{
499 struct controller *ctrl = slot->ctrl;
500
501 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
502 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
503 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
504 PCI_EXP_SLTCTL_PWR_OFF);
505}
506
507static irqreturn_t pcie_isr(int irq, void *dev_id)
508{
509 struct controller *ctrl = (struct controller *)dev_id;
510 struct pci_dev *pdev = ctrl_dev(ctrl);
511 struct slot *slot = ctrl->slot;
512 u16 detected, intr_loc;
513
514 /*
515 * In order to guarantee that all interrupt events are
516 * serviced, we need to re-inspect Slot Status register after
517 * clearing what is presumed to be the last pending interrupt.
518 */
519 intr_loc = 0;
520 do {
521 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
522
523 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
524 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
525 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
526 detected &= ~intr_loc;
527 intr_loc |= detected;
528 if (!intr_loc)
529 return IRQ_NONE;
530 if (detected)
531 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
532 intr_loc);
533 } while (detected);
534
535 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
536
537 /* Check Command Complete Interrupt Pending */
538 if (intr_loc & PCI_EXP_SLTSTA_CC) {
539 ctrl->cmd_busy = 0;
540 smp_mb();
541 wake_up(&ctrl->queue);
542 }
543
544 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
545 return IRQ_HANDLED;
546
547 /* Check MRL Sensor Changed */
548 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
549 pciehp_handle_switch_change(slot);
550
551 /* Check Attention Button Pressed */
552 if (intr_loc & PCI_EXP_SLTSTA_ABP)
553 pciehp_handle_attention_button(slot);
554
555 /* Check Presence Detect Changed */
556 if (intr_loc & PCI_EXP_SLTSTA_PDC)
557 pciehp_handle_presence_change(slot);
558
559 /* Check Power Fault Detected */
560 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
561 ctrl->power_fault_detected = 1;
562 pciehp_handle_power_fault(slot);
563 }
564
565 if (intr_loc & PCI_EXP_SLTSTA_DLLSC)
566 pciehp_handle_linkstate_change(slot);
567
568 return IRQ_HANDLED;
569}
570
571void pcie_enable_notification(struct controller *ctrl)
572{
573 u16 cmd, mask;
574
575 /*
576 * TBD: Power fault detected software notification support.
577 *
578 * Power fault detected software notification is not enabled
579 * now, because it caused power fault detected interrupt storm
580 * on some machines. On those machines, power fault detected
581 * bit in the slot status register was set again immediately
582 * when it is cleared in the interrupt service routine, and
583 * next power fault detected interrupt was notified again.
584 */
585
586 /*
587 * Always enable link events: thus link-up and link-down shall
588 * always be treated as hotplug and unplug respectively. Enable
589 * presence detect only if Attention Button is not present.
590 */
591 cmd = PCI_EXP_SLTCTL_DLLSCE;
592 if (ATTN_BUTTN(ctrl))
593 cmd |= PCI_EXP_SLTCTL_ABPE;
594 else
595 cmd |= PCI_EXP_SLTCTL_PDCE;
596 if (MRL_SENS(ctrl))
597 cmd |= PCI_EXP_SLTCTL_MRLSCE;
598 if (!pciehp_poll_mode)
599 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
600
601 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
602 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
603 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
604 PCI_EXP_SLTCTL_DLLSCE);
605
606 pcie_write_cmd(ctrl, cmd, mask);
607}
608
609static void pcie_disable_notification(struct controller *ctrl)
610{
611 u16 mask;
612
613 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
614 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
615 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
616 PCI_EXP_SLTCTL_DLLSCE);
617 pcie_write_cmd(ctrl, 0, mask);
618}
619
620/*
621 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
622 * bus reset of the bridge, but at the same time we want to ensure that it is
623 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
624 * disable link state notification and presence detection change notification
625 * momentarily, if we see that they could interfere. Also, clear any spurious
626 * events after.
627 */
628int pciehp_reset_slot(struct slot *slot, int probe)
629{
630 struct controller *ctrl = slot->ctrl;
631 struct pci_dev *pdev = ctrl_dev(ctrl);
632 u16 stat_mask = 0, ctrl_mask = 0;
633
634 if (probe)
635 return 0;
636
637 if (!ATTN_BUTTN(ctrl)) {
638 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
639 stat_mask |= PCI_EXP_SLTSTA_PDC;
640 }
641 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
642 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
643
644 pcie_write_cmd(ctrl, 0, ctrl_mask);
645 if (pciehp_poll_mode)
646 del_timer_sync(&ctrl->poll_timer);
647
648 pci_reset_bridge_secondary_bus(ctrl->pcie->port);
649
650 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
651 pcie_write_cmd(ctrl, ctrl_mask, ctrl_mask);
652 if (pciehp_poll_mode)
653 int_poll_timeout(ctrl->poll_timer.data);
654
655 return 0;
656}
657
658int pcie_init_notification(struct controller *ctrl)
659{
660 if (pciehp_request_irq(ctrl))
661 return -1;
662 pcie_enable_notification(ctrl);
663 ctrl->notification_enabled = 1;
664 return 0;
665}
666
667static void pcie_shutdown_notification(struct controller *ctrl)
668{
669 if (ctrl->notification_enabled) {
670 pcie_disable_notification(ctrl);
671 pciehp_free_irq(ctrl);
672 ctrl->notification_enabled = 0;
673 }
674}
675
676static int pcie_init_slot(struct controller *ctrl)
677{
678 struct slot *slot;
679
680 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
681 if (!slot)
682 return -ENOMEM;
683
684 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
685 if (!slot->wq)
686 goto abort;
687
688 slot->ctrl = ctrl;
689 mutex_init(&slot->lock);
690 mutex_init(&slot->hotplug_lock);
691 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
692 ctrl->slot = slot;
693 return 0;
694abort:
695 kfree(slot);
696 return -ENOMEM;
697}
698
699static void pcie_cleanup_slot(struct controller *ctrl)
700{
701 struct slot *slot = ctrl->slot;
702 cancel_delayed_work(&slot->work);
703 destroy_workqueue(slot->wq);
704 kfree(slot);
705}
706
707static inline void dbg_ctrl(struct controller *ctrl)
708{
709 int i;
710 u16 reg16;
711 struct pci_dev *pdev = ctrl->pcie->port;
712
713 if (!pciehp_debug)
714 return;
715
716 ctrl_info(ctrl, "Hotplug Controller:\n");
717 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
718 pci_name(pdev), pdev->irq);
719 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
720 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
721 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
722 pdev->subsystem_device);
723 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
724 pdev->subsystem_vendor);
725 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
726 pci_pcie_cap(pdev));
727 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
728 if (!pci_resource_len(pdev, i))
729 continue;
730 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
731 i, &pdev->resource[i]);
732 }
733 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
734 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
735 ctrl_info(ctrl, " Attention Button : %3s\n",
736 ATTN_BUTTN(ctrl) ? "yes" : "no");
737 ctrl_info(ctrl, " Power Controller : %3s\n",
738 POWER_CTRL(ctrl) ? "yes" : "no");
739 ctrl_info(ctrl, " MRL Sensor : %3s\n",
740 MRL_SENS(ctrl) ? "yes" : "no");
741 ctrl_info(ctrl, " Attention Indicator : %3s\n",
742 ATTN_LED(ctrl) ? "yes" : "no");
743 ctrl_info(ctrl, " Power Indicator : %3s\n",
744 PWR_LED(ctrl) ? "yes" : "no");
745 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
746 HP_SUPR_RM(ctrl) ? "yes" : "no");
747 ctrl_info(ctrl, " EMI Present : %3s\n",
748 EMI(ctrl) ? "yes" : "no");
749 ctrl_info(ctrl, " Command Completed : %3s\n",
750 NO_CMD_CMPL(ctrl) ? "no" : "yes");
751 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
752 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
753 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
754 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
755}
756
757#define FLAG(x,y) (((x) & (y)) ? '+' : '-')
758
759struct controller *pcie_init(struct pcie_device *dev)
760{
761 struct controller *ctrl;
762 u32 slot_cap, link_cap;
763 struct pci_dev *pdev = dev->port;
764
765 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
766 if (!ctrl) {
767 dev_err(&dev->device, "%s: Out of memory\n", __func__);
768 goto abort;
769 }
770 ctrl->pcie = dev;
771 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
772 ctrl->slot_cap = slot_cap;
773 mutex_init(&ctrl->ctrl_lock);
774 init_waitqueue_head(&ctrl->queue);
775 dbg_ctrl(ctrl);
776 /*
777 * Controller doesn't notify of command completion if the "No
778 * Command Completed Support" bit is set in Slot Capability
779 * register or the controller supports none of power
780 * controller, attention led, power led and EMI.
781 */
782 if (NO_CMD_CMPL(ctrl) ||
783 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
784 ctrl->no_cmd_complete = 1;
785
786 /* Check if Data Link Layer Link Active Reporting is implemented */
787 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
788 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
789 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
790 ctrl->link_active_reporting = 1;
791 }
792
793 /* Clear all remaining event bits in Slot Status register */
794 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
795 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
796 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
797 PCI_EXP_SLTSTA_CC);
798
799 /* Disable software notification */
800 pcie_disable_notification(ctrl);
801
802 ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n",
803 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
804 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
805 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
806 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
807 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
808 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
809 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
810 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
811 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
812
813 if (pcie_init_slot(ctrl))
814 goto abort_ctrl;
815
816 return ctrl;
817
818abort_ctrl:
819 kfree(ctrl);
820abort:
821 return NULL;
822}
823
824void pciehp_release_ctrl(struct controller *ctrl)
825{
826 pcie_shutdown_notification(ctrl);
827 pcie_cleanup_slot(ctrl);
828 kfree(ctrl);
829}
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * PCI Express PCI Hot Plug Driver
4 *
5 * Copyright (C) 1995,2001 Compaq Computer Corporation
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7 * Copyright (C) 2001 IBM Corp.
8 * Copyright (C) 2003-2004 Intel Corporation
9 *
10 * All rights reserved.
11 *
12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
13 */
14
15#define dev_fmt(fmt) "pciehp: " fmt
16
17#include <linux/bitfield.h>
18#include <linux/dmi.h>
19#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/jiffies.h>
22#include <linux/kthread.h>
23#include <linux/pci.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/slab.h>
27
28#include "../pci.h"
29#include "pciehp.h"
30
31static const struct dmi_system_id inband_presence_disabled_dmi_table[] = {
32 /*
33 * Match all Dell systems, as some Dell systems have inband
34 * presence disabled on NVMe slots (but don't support the bit to
35 * report it). Setting inband presence disabled should have no
36 * negative effect, except on broken hotplug slots that never
37 * assert presence detect--and those will still work, they will
38 * just have a bit of extra delay before being probed.
39 */
40 {
41 .ident = "Dell System",
42 .matches = {
43 DMI_MATCH(DMI_OEM_STRING, "Dell System"),
44 },
45 },
46 {}
47};
48
49static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
50{
51 return ctrl->pcie->port;
52}
53
54static irqreturn_t pciehp_isr(int irq, void *dev_id);
55static irqreturn_t pciehp_ist(int irq, void *dev_id);
56static int pciehp_poll(void *data);
57
58static inline int pciehp_request_irq(struct controller *ctrl)
59{
60 int retval, irq = ctrl->pcie->irq;
61
62 if (pciehp_poll_mode) {
63 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl,
64 "pciehp_poll-%s",
65 slot_name(ctrl));
66 return PTR_ERR_OR_ZERO(ctrl->poll_thread);
67 }
68
69 /* Installs the interrupt handler */
70 retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist,
71 IRQF_SHARED, "pciehp", ctrl);
72 if (retval)
73 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
74 irq);
75 return retval;
76}
77
78static inline void pciehp_free_irq(struct controller *ctrl)
79{
80 if (pciehp_poll_mode)
81 kthread_stop(ctrl->poll_thread);
82 else
83 free_irq(ctrl->pcie->irq, ctrl);
84}
85
86static int pcie_poll_cmd(struct controller *ctrl, int timeout)
87{
88 struct pci_dev *pdev = ctrl_dev(ctrl);
89 u16 slot_status;
90
91 do {
92 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
93 if (PCI_POSSIBLE_ERROR(slot_status)) {
94 ctrl_info(ctrl, "%s: no response from device\n",
95 __func__);
96 return 0;
97 }
98
99 if (slot_status & PCI_EXP_SLTSTA_CC) {
100 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
101 PCI_EXP_SLTSTA_CC);
102 ctrl->cmd_busy = 0;
103 smp_mb();
104 return 1;
105 }
106 msleep(10);
107 timeout -= 10;
108 } while (timeout >= 0);
109 return 0; /* timeout */
110}
111
112static void pcie_wait_cmd(struct controller *ctrl)
113{
114 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
115 unsigned long duration = msecs_to_jiffies(msecs);
116 unsigned long cmd_timeout = ctrl->cmd_started + duration;
117 unsigned long now, timeout;
118 int rc;
119
120 /*
121 * If the controller does not generate notifications for command
122 * completions, we never need to wait between writes.
123 */
124 if (NO_CMD_CMPL(ctrl))
125 return;
126
127 if (!ctrl->cmd_busy)
128 return;
129
130 /*
131 * Even if the command has already timed out, we want to call
132 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
133 */
134 now = jiffies;
135 if (time_before_eq(cmd_timeout, now))
136 timeout = 1;
137 else
138 timeout = cmd_timeout - now;
139
140 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
141 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
142 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
143 else
144 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
145
146 if (!rc)
147 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
148 ctrl->slot_ctrl,
149 jiffies_to_msecs(jiffies - ctrl->cmd_started));
150}
151
152#define CC_ERRATUM_MASK (PCI_EXP_SLTCTL_PCC | \
153 PCI_EXP_SLTCTL_PIC | \
154 PCI_EXP_SLTCTL_AIC | \
155 PCI_EXP_SLTCTL_EIC)
156
157static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
158 u16 mask, bool wait)
159{
160 struct pci_dev *pdev = ctrl_dev(ctrl);
161 u16 slot_ctrl_orig, slot_ctrl;
162
163 mutex_lock(&ctrl->ctrl_lock);
164
165 /*
166 * Always wait for any previous command that might still be in progress
167 */
168 pcie_wait_cmd(ctrl);
169
170 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
171 if (PCI_POSSIBLE_ERROR(slot_ctrl)) {
172 ctrl_info(ctrl, "%s: no response from device\n", __func__);
173 goto out;
174 }
175
176 slot_ctrl_orig = slot_ctrl;
177 slot_ctrl &= ~mask;
178 slot_ctrl |= (cmd & mask);
179 ctrl->cmd_busy = 1;
180 smp_mb();
181 ctrl->slot_ctrl = slot_ctrl;
182 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
183 ctrl->cmd_started = jiffies;
184
185 /*
186 * Controllers with the Intel CF118 and similar errata advertise
187 * Command Completed support, but they only set Command Completed
188 * if we change the "Control" bits for power, power indicator,
189 * attention indicator, or interlock. If we only change the
190 * "Enable" bits, they never set the Command Completed bit.
191 */
192 if (pdev->broken_cmd_compl &&
193 (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
194 ctrl->cmd_busy = 0;
195
196 /*
197 * Optionally wait for the hardware to be ready for a new command,
198 * indicating completion of the above issued command.
199 */
200 if (wait)
201 pcie_wait_cmd(ctrl);
202
203out:
204 mutex_unlock(&ctrl->ctrl_lock);
205}
206
207/**
208 * pcie_write_cmd - Issue controller command
209 * @ctrl: controller to which the command is issued
210 * @cmd: command value written to slot control register
211 * @mask: bitmask of slot control register to be modified
212 */
213static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
214{
215 pcie_do_write_cmd(ctrl, cmd, mask, true);
216}
217
218/* Same as above without waiting for the hardware to latch */
219static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
220{
221 pcie_do_write_cmd(ctrl, cmd, mask, false);
222}
223
224/**
225 * pciehp_check_link_active() - Is the link active
226 * @ctrl: PCIe hotplug controller
227 *
228 * Check whether the downstream link is currently active. Note it is
229 * possible that the card is removed immediately after this so the
230 * caller may need to take it into account.
231 *
232 * If the hotplug controller itself is not available anymore returns
233 * %-ENODEV.
234 */
235int pciehp_check_link_active(struct controller *ctrl)
236{
237 struct pci_dev *pdev = ctrl_dev(ctrl);
238 u16 lnk_status;
239 int ret;
240
241 ret = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
242 if (ret == PCIBIOS_DEVICE_NOT_FOUND || PCI_POSSIBLE_ERROR(lnk_status))
243 return -ENODEV;
244
245 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
246 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
247
248 return ret;
249}
250
251static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
252{
253 u32 l;
254 int count = 0;
255 int delay = 1000, step = 20;
256 bool found = false;
257
258 do {
259 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
260 count++;
261
262 if (found)
263 break;
264
265 msleep(step);
266 delay -= step;
267 } while (delay > 0);
268
269 if (count > 1)
270 pr_debug("pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
271 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
272 PCI_FUNC(devfn), count, step, l);
273
274 return found;
275}
276
277static void pcie_wait_for_presence(struct pci_dev *pdev)
278{
279 int timeout = 1250;
280 u16 slot_status;
281
282 do {
283 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
284 if (slot_status & PCI_EXP_SLTSTA_PDS)
285 return;
286 msleep(10);
287 timeout -= 10;
288 } while (timeout > 0);
289}
290
291int pciehp_check_link_status(struct controller *ctrl)
292{
293 struct pci_dev *pdev = ctrl_dev(ctrl);
294 bool found;
295 u16 lnk_status;
296
297 if (!pcie_wait_for_link(pdev, true)) {
298 ctrl_info(ctrl, "Slot(%s): No link\n", slot_name(ctrl));
299 return -1;
300 }
301
302 if (ctrl->inband_presence_disabled)
303 pcie_wait_for_presence(pdev);
304
305 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
306 PCI_DEVFN(0, 0));
307
308 /* ignore link or presence changes up to this point */
309 if (found)
310 atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC),
311 &ctrl->pending_events);
312
313 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
314 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
315 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
316 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
317 ctrl_info(ctrl, "Slot(%s): Cannot train link: status %#06x\n",
318 slot_name(ctrl), lnk_status);
319 return -1;
320 }
321
322 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
323
324 if (!found) {
325 ctrl_info(ctrl, "Slot(%s): No device found\n",
326 slot_name(ctrl));
327 return -1;
328 }
329
330 return 0;
331}
332
333static int __pciehp_link_set(struct controller *ctrl, bool enable)
334{
335 struct pci_dev *pdev = ctrl_dev(ctrl);
336
337 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
338 PCI_EXP_LNKCTL_LD,
339 enable ? 0 : PCI_EXP_LNKCTL_LD);
340
341 return 0;
342}
343
344static int pciehp_link_enable(struct controller *ctrl)
345{
346 return __pciehp_link_set(ctrl, true);
347}
348
349int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
350 u8 *status)
351{
352 struct controller *ctrl = to_ctrl(hotplug_slot);
353 struct pci_dev *pdev = ctrl_dev(ctrl);
354 u16 slot_ctrl;
355
356 pci_config_pm_runtime_get(pdev);
357 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
358 pci_config_pm_runtime_put(pdev);
359 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
360 return 0;
361}
362
363int pciehp_get_attention_status(struct hotplug_slot *hotplug_slot, u8 *status)
364{
365 struct controller *ctrl = to_ctrl(hotplug_slot);
366 struct pci_dev *pdev = ctrl_dev(ctrl);
367 u16 slot_ctrl;
368
369 pci_config_pm_runtime_get(pdev);
370 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
371 pci_config_pm_runtime_put(pdev);
372 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
373 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
374
375 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
376 case PCI_EXP_SLTCTL_ATTN_IND_ON:
377 *status = 1; /* On */
378 break;
379 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
380 *status = 2; /* Blink */
381 break;
382 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
383 *status = 0; /* Off */
384 break;
385 default:
386 *status = 0xFF;
387 break;
388 }
389
390 return 0;
391}
392
393void pciehp_get_power_status(struct controller *ctrl, u8 *status)
394{
395 struct pci_dev *pdev = ctrl_dev(ctrl);
396 u16 slot_ctrl;
397
398 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
399 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
400 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
401
402 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
403 case PCI_EXP_SLTCTL_PWR_ON:
404 *status = 1; /* On */
405 break;
406 case PCI_EXP_SLTCTL_PWR_OFF:
407 *status = 0; /* Off */
408 break;
409 default:
410 *status = 0xFF;
411 break;
412 }
413}
414
415void pciehp_get_latch_status(struct controller *ctrl, u8 *status)
416{
417 struct pci_dev *pdev = ctrl_dev(ctrl);
418 u16 slot_status;
419
420 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
421 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
422}
423
424/**
425 * pciehp_card_present() - Is the card present
426 * @ctrl: PCIe hotplug controller
427 *
428 * Function checks whether the card is currently present in the slot and
429 * in that case returns true. Note it is possible that the card is
430 * removed immediately after the check so the caller may need to take
431 * this into account.
432 *
433 * It the hotplug controller itself is not available anymore returns
434 * %-ENODEV.
435 */
436int pciehp_card_present(struct controller *ctrl)
437{
438 struct pci_dev *pdev = ctrl_dev(ctrl);
439 u16 slot_status;
440 int ret;
441
442 ret = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
443 if (ret == PCIBIOS_DEVICE_NOT_FOUND || PCI_POSSIBLE_ERROR(slot_status))
444 return -ENODEV;
445
446 return !!(slot_status & PCI_EXP_SLTSTA_PDS);
447}
448
449/**
450 * pciehp_card_present_or_link_active() - whether given slot is occupied
451 * @ctrl: PCIe hotplug controller
452 *
453 * Unlike pciehp_card_present(), which determines presence solely from the
454 * Presence Detect State bit, this helper also returns true if the Link Active
455 * bit is set. This is a concession to broken hotplug ports which hardwire
456 * Presence Detect State to zero, such as Wilocity's [1ae9:0200].
457 *
458 * Returns: %1 if the slot is occupied and %0 if it is not. If the hotplug
459 * port is not present anymore returns %-ENODEV.
460 */
461int pciehp_card_present_or_link_active(struct controller *ctrl)
462{
463 int ret;
464
465 ret = pciehp_card_present(ctrl);
466 if (ret)
467 return ret;
468
469 return pciehp_check_link_active(ctrl);
470}
471
472int pciehp_query_power_fault(struct controller *ctrl)
473{
474 struct pci_dev *pdev = ctrl_dev(ctrl);
475 u16 slot_status;
476
477 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
478 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
479}
480
481int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
482 u8 status)
483{
484 struct controller *ctrl = to_ctrl(hotplug_slot);
485 struct pci_dev *pdev = ctrl_dev(ctrl);
486
487 pci_config_pm_runtime_get(pdev);
488 pcie_write_cmd_nowait(ctrl, FIELD_PREP(PCI_EXP_SLTCTL_AIC, status),
489 PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
490 pci_config_pm_runtime_put(pdev);
491 return 0;
492}
493
494/**
495 * pciehp_set_indicators() - set attention indicator, power indicator, or both
496 * @ctrl: PCIe hotplug controller
497 * @pwr: one of:
498 * PCI_EXP_SLTCTL_PWR_IND_ON
499 * PCI_EXP_SLTCTL_PWR_IND_BLINK
500 * PCI_EXP_SLTCTL_PWR_IND_OFF
501 * @attn: one of:
502 * PCI_EXP_SLTCTL_ATTN_IND_ON
503 * PCI_EXP_SLTCTL_ATTN_IND_BLINK
504 * PCI_EXP_SLTCTL_ATTN_IND_OFF
505 *
506 * Either @pwr or @attn can also be INDICATOR_NOOP to leave that indicator
507 * unchanged.
508 */
509void pciehp_set_indicators(struct controller *ctrl, int pwr, int attn)
510{
511 u16 cmd = 0, mask = 0;
512
513 if (PWR_LED(ctrl) && pwr != INDICATOR_NOOP) {
514 cmd |= (pwr & PCI_EXP_SLTCTL_PIC);
515 mask |= PCI_EXP_SLTCTL_PIC;
516 }
517
518 if (ATTN_LED(ctrl) && attn != INDICATOR_NOOP) {
519 cmd |= (attn & PCI_EXP_SLTCTL_AIC);
520 mask |= PCI_EXP_SLTCTL_AIC;
521 }
522
523 if (cmd) {
524 pcie_write_cmd_nowait(ctrl, cmd, mask);
525 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
526 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
527 }
528}
529
530int pciehp_power_on_slot(struct controller *ctrl)
531{
532 struct pci_dev *pdev = ctrl_dev(ctrl);
533 u16 slot_status;
534 int retval;
535
536 /* Clear power-fault bit from previous power failures */
537 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
538 if (slot_status & PCI_EXP_SLTSTA_PFD)
539 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
540 PCI_EXP_SLTSTA_PFD);
541 ctrl->power_fault_detected = 0;
542
543 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
544 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
545 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
546 PCI_EXP_SLTCTL_PWR_ON);
547
548 retval = pciehp_link_enable(ctrl);
549 if (retval)
550 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
551
552 return retval;
553}
554
555void pciehp_power_off_slot(struct controller *ctrl)
556{
557 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
558 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
559 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
560 PCI_EXP_SLTCTL_PWR_OFF);
561}
562
563static void pciehp_ignore_dpc_link_change(struct controller *ctrl,
564 struct pci_dev *pdev, int irq)
565{
566 /*
567 * Ignore link changes which occurred while waiting for DPC recovery.
568 * Could be several if DPC triggered multiple times consecutively.
569 */
570 synchronize_hardirq(irq);
571 atomic_and(~PCI_EXP_SLTSTA_DLLSC, &ctrl->pending_events);
572 if (pciehp_poll_mode)
573 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
574 PCI_EXP_SLTSTA_DLLSC);
575 ctrl_info(ctrl, "Slot(%s): Link Down/Up ignored (recovered by DPC)\n",
576 slot_name(ctrl));
577
578 /*
579 * If the link is unexpectedly down after successful recovery,
580 * the corresponding link change may have been ignored above.
581 * Synthesize it to ensure that it is acted on.
582 */
583 down_read_nested(&ctrl->reset_lock, ctrl->depth);
584 if (!pciehp_check_link_active(ctrl))
585 pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC);
586 up_read(&ctrl->reset_lock);
587}
588
589static irqreturn_t pciehp_isr(int irq, void *dev_id)
590{
591 struct controller *ctrl = (struct controller *)dev_id;
592 struct pci_dev *pdev = ctrl_dev(ctrl);
593 struct device *parent = pdev->dev.parent;
594 u16 status, events = 0;
595
596 /*
597 * Interrupts only occur in D3hot or shallower and only if enabled
598 * in the Slot Control register (PCIe r4.0, sec 6.7.3.4).
599 */
600 if (pdev->current_state == PCI_D3cold ||
601 (!(ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE) && !pciehp_poll_mode))
602 return IRQ_NONE;
603
604 /*
605 * Keep the port accessible by holding a runtime PM ref on its parent.
606 * Defer resume of the parent to the IRQ thread if it's suspended.
607 * Mask the interrupt until then.
608 */
609 if (parent) {
610 pm_runtime_get_noresume(parent);
611 if (!pm_runtime_active(parent)) {
612 pm_runtime_put(parent);
613 disable_irq_nosync(irq);
614 atomic_or(RERUN_ISR, &ctrl->pending_events);
615 return IRQ_WAKE_THREAD;
616 }
617 }
618
619read_status:
620 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
621 if (PCI_POSSIBLE_ERROR(status)) {
622 ctrl_info(ctrl, "%s: no response from device\n", __func__);
623 if (parent)
624 pm_runtime_put(parent);
625 return IRQ_NONE;
626 }
627
628 /*
629 * Slot Status contains plain status bits as well as event
630 * notification bits; right now we only want the event bits.
631 */
632 status &= PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
633 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
634 PCI_EXP_SLTSTA_DLLSC;
635
636 /*
637 * If we've already reported a power fault, don't report it again
638 * until we've done something to handle it.
639 */
640 if (ctrl->power_fault_detected)
641 status &= ~PCI_EXP_SLTSTA_PFD;
642 else if (status & PCI_EXP_SLTSTA_PFD)
643 ctrl->power_fault_detected = true;
644
645 events |= status;
646 if (!events) {
647 if (parent)
648 pm_runtime_put(parent);
649 return IRQ_NONE;
650 }
651
652 if (status) {
653 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, status);
654
655 /*
656 * In MSI mode, all event bits must be zero before the port
657 * will send a new interrupt (PCIe Base Spec r5.0 sec 6.7.3.4).
658 * So re-read the Slot Status register in case a bit was set
659 * between read and write.
660 */
661 if (pci_dev_msi_enabled(pdev) && !pciehp_poll_mode)
662 goto read_status;
663 }
664
665 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
666 if (parent)
667 pm_runtime_put(parent);
668
669 /*
670 * Command Completed notifications are not deferred to the
671 * IRQ thread because it may be waiting for their arrival.
672 */
673 if (events & PCI_EXP_SLTSTA_CC) {
674 ctrl->cmd_busy = 0;
675 smp_mb();
676 wake_up(&ctrl->queue);
677
678 if (events == PCI_EXP_SLTSTA_CC)
679 return IRQ_HANDLED;
680
681 events &= ~PCI_EXP_SLTSTA_CC;
682 }
683
684 if (pdev->ignore_hotplug) {
685 ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
686 return IRQ_HANDLED;
687 }
688
689 /* Save pending events for consumption by IRQ thread. */
690 atomic_or(events, &ctrl->pending_events);
691 return IRQ_WAKE_THREAD;
692}
693
694static irqreturn_t pciehp_ist(int irq, void *dev_id)
695{
696 struct controller *ctrl = (struct controller *)dev_id;
697 struct pci_dev *pdev = ctrl_dev(ctrl);
698 irqreturn_t ret;
699 u32 events;
700
701 ctrl->ist_running = true;
702 pci_config_pm_runtime_get(pdev);
703
704 /* rerun pciehp_isr() if the port was inaccessible on interrupt */
705 if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) {
706 ret = pciehp_isr(irq, dev_id);
707 enable_irq(irq);
708 if (ret != IRQ_WAKE_THREAD)
709 goto out;
710 }
711
712 synchronize_hardirq(irq);
713 events = atomic_xchg(&ctrl->pending_events, 0);
714 if (!events) {
715 ret = IRQ_NONE;
716 goto out;
717 }
718
719 /* Check Attention Button Pressed */
720 if (events & PCI_EXP_SLTSTA_ABP)
721 pciehp_handle_button_press(ctrl);
722
723 /* Check Power Fault Detected */
724 if (events & PCI_EXP_SLTSTA_PFD) {
725 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(ctrl));
726 pciehp_set_indicators(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
727 PCI_EXP_SLTCTL_ATTN_IND_ON);
728 }
729
730 /*
731 * Ignore Link Down/Up events caused by Downstream Port Containment
732 * if recovery from the error succeeded.
733 */
734 if ((events & PCI_EXP_SLTSTA_DLLSC) && pci_dpc_recovered(pdev) &&
735 ctrl->state == ON_STATE) {
736 events &= ~PCI_EXP_SLTSTA_DLLSC;
737 pciehp_ignore_dpc_link_change(ctrl, pdev, irq);
738 }
739
740 /*
741 * Disable requests have higher priority than Presence Detect Changed
742 * or Data Link Layer State Changed events.
743 */
744 down_read_nested(&ctrl->reset_lock, ctrl->depth);
745 if (events & DISABLE_SLOT)
746 pciehp_handle_disable_request(ctrl);
747 else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
748 pciehp_handle_presence_or_link_change(ctrl, events);
749 up_read(&ctrl->reset_lock);
750
751 ret = IRQ_HANDLED;
752out:
753 pci_config_pm_runtime_put(pdev);
754 ctrl->ist_running = false;
755 wake_up(&ctrl->requester);
756 return ret;
757}
758
759static int pciehp_poll(void *data)
760{
761 struct controller *ctrl = data;
762
763 schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */
764
765 while (!kthread_should_stop()) {
766 /* poll for interrupt events or user requests */
767 while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD ||
768 atomic_read(&ctrl->pending_events))
769 pciehp_ist(IRQ_NOTCONNECTED, ctrl);
770
771 if (pciehp_poll_time <= 0 || pciehp_poll_time > 60)
772 pciehp_poll_time = 2; /* clamp to sane value */
773
774 schedule_timeout_idle(pciehp_poll_time * HZ);
775 }
776
777 return 0;
778}
779
780static void pcie_enable_notification(struct controller *ctrl)
781{
782 u16 cmd, mask;
783
784 /*
785 * TBD: Power fault detected software notification support.
786 *
787 * Power fault detected software notification is not enabled
788 * now, because it caused power fault detected interrupt storm
789 * on some machines. On those machines, power fault detected
790 * bit in the slot status register was set again immediately
791 * when it is cleared in the interrupt service routine, and
792 * next power fault detected interrupt was notified again.
793 */
794
795 /*
796 * Always enable link events: thus link-up and link-down shall
797 * always be treated as hotplug and unplug respectively. Enable
798 * presence detect only if Attention Button is not present.
799 */
800 cmd = PCI_EXP_SLTCTL_DLLSCE;
801 if (ATTN_BUTTN(ctrl))
802 cmd |= PCI_EXP_SLTCTL_ABPE;
803 else
804 cmd |= PCI_EXP_SLTCTL_PDCE;
805 if (!pciehp_poll_mode)
806 cmd |= PCI_EXP_SLTCTL_HPIE;
807 if (!pciehp_poll_mode && !NO_CMD_CMPL(ctrl))
808 cmd |= PCI_EXP_SLTCTL_CCIE;
809
810 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
811 PCI_EXP_SLTCTL_PFDE |
812 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
813 PCI_EXP_SLTCTL_DLLSCE);
814
815 pcie_write_cmd_nowait(ctrl, cmd, mask);
816 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
817 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
818}
819
820static void pcie_disable_notification(struct controller *ctrl)
821{
822 u16 mask;
823
824 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
825 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
826 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
827 PCI_EXP_SLTCTL_DLLSCE);
828 pcie_write_cmd(ctrl, 0, mask);
829 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
830 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
831}
832
833void pcie_clear_hotplug_events(struct controller *ctrl)
834{
835 pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA,
836 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
837}
838
839void pcie_enable_interrupt(struct controller *ctrl)
840{
841 u16 mask;
842
843 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
844 pcie_write_cmd(ctrl, mask, mask);
845}
846
847void pcie_disable_interrupt(struct controller *ctrl)
848{
849 u16 mask;
850
851 /*
852 * Mask hot-plug interrupt to prevent it triggering immediately
853 * when the link goes inactive (we still get PME when any of the
854 * enabled events is detected). Same goes with Link Layer State
855 * changed event which generates PME immediately when the link goes
856 * inactive so mask it as well.
857 */
858 mask = PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_DLLSCE;
859 pcie_write_cmd(ctrl, 0, mask);
860}
861
862/**
863 * pciehp_slot_reset() - ignore link event caused by error-induced hot reset
864 * @dev: PCI Express port service device
865 *
866 * Called from pcie_portdrv_slot_reset() after AER or DPC initiated a reset
867 * further up in the hierarchy to recover from an error. The reset was
868 * propagated down to this hotplug port. Ignore the resulting link flap.
869 * If the link failed to retrain successfully, synthesize the ignored event.
870 * Surprise removal during reset is detected through Presence Detect Changed.
871 */
872int pciehp_slot_reset(struct pcie_device *dev)
873{
874 struct controller *ctrl = get_service_data(dev);
875
876 if (ctrl->state != ON_STATE)
877 return 0;
878
879 pcie_capability_write_word(dev->port, PCI_EXP_SLTSTA,
880 PCI_EXP_SLTSTA_DLLSC);
881
882 if (!pciehp_check_link_active(ctrl))
883 pciehp_request(ctrl, PCI_EXP_SLTSTA_DLLSC);
884
885 return 0;
886}
887
888/*
889 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
890 * bus reset of the bridge, but at the same time we want to ensure that it is
891 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
892 * disable link state notification and presence detection change notification
893 * momentarily, if we see that they could interfere. Also, clear any spurious
894 * events after.
895 */
896int pciehp_reset_slot(struct hotplug_slot *hotplug_slot, bool probe)
897{
898 struct controller *ctrl = to_ctrl(hotplug_slot);
899 struct pci_dev *pdev = ctrl_dev(ctrl);
900 u16 stat_mask = 0, ctrl_mask = 0;
901 int rc;
902
903 if (probe)
904 return 0;
905
906 down_write_nested(&ctrl->reset_lock, ctrl->depth);
907
908 if (!ATTN_BUTTN(ctrl)) {
909 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
910 stat_mask |= PCI_EXP_SLTSTA_PDC;
911 }
912 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
913 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
914
915 pcie_write_cmd(ctrl, 0, ctrl_mask);
916 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
917 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
918
919 rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port);
920
921 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
922 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
923 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
924 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
925
926 up_write(&ctrl->reset_lock);
927 return rc;
928}
929
930int pcie_init_notification(struct controller *ctrl)
931{
932 if (pciehp_request_irq(ctrl))
933 return -1;
934 pcie_enable_notification(ctrl);
935 ctrl->notification_enabled = 1;
936 return 0;
937}
938
939void pcie_shutdown_notification(struct controller *ctrl)
940{
941 if (ctrl->notification_enabled) {
942 pcie_disable_notification(ctrl);
943 pciehp_free_irq(ctrl);
944 ctrl->notification_enabled = 0;
945 }
946}
947
948static inline void dbg_ctrl(struct controller *ctrl)
949{
950 struct pci_dev *pdev = ctrl->pcie->port;
951 u16 reg16;
952
953 ctrl_dbg(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
954 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
955 ctrl_dbg(ctrl, "Slot Status : 0x%04x\n", reg16);
956 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
957 ctrl_dbg(ctrl, "Slot Control : 0x%04x\n", reg16);
958}
959
960#define FLAG(x, y) (((x) & (y)) ? '+' : '-')
961
962static inline int pcie_hotplug_depth(struct pci_dev *dev)
963{
964 struct pci_bus *bus = dev->bus;
965 int depth = 0;
966
967 while (bus->parent) {
968 bus = bus->parent;
969 if (bus->self && bus->self->is_hotplug_bridge)
970 depth++;
971 }
972
973 return depth;
974}
975
976struct controller *pcie_init(struct pcie_device *dev)
977{
978 struct controller *ctrl;
979 u32 slot_cap, slot_cap2;
980 u8 poweron;
981 struct pci_dev *pdev = dev->port;
982 struct pci_bus *subordinate = pdev->subordinate;
983
984 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
985 if (!ctrl)
986 return NULL;
987
988 ctrl->pcie = dev;
989 ctrl->depth = pcie_hotplug_depth(dev->port);
990 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
991
992 if (pdev->hotplug_user_indicators)
993 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
994
995 /*
996 * We assume no Thunderbolt controllers support Command Complete events,
997 * but some controllers falsely claim they do.
998 */
999 if (pdev->is_thunderbolt)
1000 slot_cap |= PCI_EXP_SLTCAP_NCCS;
1001
1002 ctrl->slot_cap = slot_cap;
1003 mutex_init(&ctrl->ctrl_lock);
1004 mutex_init(&ctrl->state_lock);
1005 init_rwsem(&ctrl->reset_lock);
1006 init_waitqueue_head(&ctrl->requester);
1007 init_waitqueue_head(&ctrl->queue);
1008 INIT_DELAYED_WORK(&ctrl->button_work, pciehp_queue_pushbutton_work);
1009 dbg_ctrl(ctrl);
1010
1011 down_read(&pci_bus_sem);
1012 ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
1013 up_read(&pci_bus_sem);
1014
1015 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP2, &slot_cap2);
1016 if (slot_cap2 & PCI_EXP_SLTCAP2_IBPD) {
1017 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_IBPD_DISABLE,
1018 PCI_EXP_SLTCTL_IBPD_DISABLE);
1019 ctrl->inband_presence_disabled = 1;
1020 }
1021
1022 if (dmi_first_match(inband_presence_disabled_dmi_table))
1023 ctrl->inband_presence_disabled = 1;
1024
1025 /* Clear all remaining event bits in Slot Status register. */
1026 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
1027 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
1028 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
1029 PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
1030
1031 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c IbPresDis%c LLActRep%c%s\n",
1032 FIELD_GET(PCI_EXP_SLTCAP_PSN, slot_cap),
1033 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
1034 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
1035 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
1036 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
1037 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
1038 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
1039 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
1040 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
1041 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
1042 FLAG(slot_cap2, PCI_EXP_SLTCAP2_IBPD),
1043 FLAG(pdev->link_active_reporting, true),
1044 pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
1045
1046 /*
1047 * If empty slot's power status is on, turn power off. The IRQ isn't
1048 * requested yet, so avoid triggering a notification with this command.
1049 */
1050 if (POWER_CTRL(ctrl)) {
1051 pciehp_get_power_status(ctrl, &poweron);
1052 if (!pciehp_card_present_or_link_active(ctrl) && poweron) {
1053 pcie_disable_notification(ctrl);
1054 pciehp_power_off_slot(ctrl);
1055 }
1056 }
1057
1058 return ctrl;
1059}
1060
1061void pciehp_release_ctrl(struct controller *ctrl)
1062{
1063 cancel_delayed_work_sync(&ctrl->button_work);
1064 kfree(ctrl);
1065}
1066
1067static void quirk_cmd_compl(struct pci_dev *pdev)
1068{
1069 u32 slot_cap;
1070
1071 if (pci_is_pcie(pdev)) {
1072 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
1073 if (slot_cap & PCI_EXP_SLTCAP_HPC &&
1074 !(slot_cap & PCI_EXP_SLTCAP_NCCS))
1075 pdev->broken_cmd_compl = 1;
1076 }
1077}
1078DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1079 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1080DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x010e,
1081 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1082DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0110,
1083 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1084DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
1085 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1086DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
1087 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
1088DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_HXT, 0x0401,
1089 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);