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1/*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/blkdev.h>
11#include <linux/clk.h>
12#include <linux/debugfs.h>
13#include <linux/device.h>
14#include <linux/dmaengine.h>
15#include <linux/dma-mapping.h>
16#include <linux/err.h>
17#include <linux/gpio.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/of_gpio.h>
25#include <linux/platform_device.h>
26#include <linux/scatterlist.h>
27#include <linux/seq_file.h>
28#include <linux/slab.h>
29#include <linux/stat.h>
30#include <linux/types.h>
31#include <linux/platform_data/atmel.h>
32
33#include <linux/mmc/host.h>
34#include <linux/mmc/sdio.h>
35
36#include <mach/atmel-mci.h>
37#include <linux/atmel-mci.h>
38#include <linux/atmel_pdc.h>
39
40#include <asm/io.h>
41#include <asm/unaligned.h>
42
43#include "atmel-mci-regs.h"
44
45#define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
46#define ATMCI_DMA_THRESHOLD 16
47
48enum {
49 EVENT_CMD_RDY = 0,
50 EVENT_XFER_COMPLETE,
51 EVENT_NOTBUSY,
52 EVENT_DATA_ERROR,
53};
54
55enum atmel_mci_state {
56 STATE_IDLE = 0,
57 STATE_SENDING_CMD,
58 STATE_DATA_XFER,
59 STATE_WAITING_NOTBUSY,
60 STATE_SENDING_STOP,
61 STATE_END_REQUEST,
62};
63
64enum atmci_xfer_dir {
65 XFER_RECEIVE = 0,
66 XFER_TRANSMIT,
67};
68
69enum atmci_pdc_buf {
70 PDC_FIRST_BUF = 0,
71 PDC_SECOND_BUF,
72};
73
74struct atmel_mci_caps {
75 bool has_dma_conf_reg;
76 bool has_pdc;
77 bool has_cfg_reg;
78 bool has_cstor_reg;
79 bool has_highspeed;
80 bool has_rwproof;
81 bool has_odd_clk_div;
82 bool has_bad_data_ordering;
83 bool need_reset_after_xfer;
84 bool need_blksz_mul_4;
85 bool need_notbusy_for_read_ops;
86};
87
88struct atmel_mci_dma {
89 struct dma_chan *chan;
90 struct dma_async_tx_descriptor *data_desc;
91};
92
93/**
94 * struct atmel_mci - MMC controller state shared between all slots
95 * @lock: Spinlock protecting the queue and associated data.
96 * @regs: Pointer to MMIO registers.
97 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
98 * @pio_offset: Offset into the current scatterlist entry.
99 * @buffer: Buffer used if we don't have the r/w proof capability. We
100 * don't have the time to switch pdc buffers so we have to use only
101 * one buffer for the full transaction.
102 * @buf_size: size of the buffer.
103 * @phys_buf_addr: buffer address needed for pdc.
104 * @cur_slot: The slot which is currently using the controller.
105 * @mrq: The request currently being processed on @cur_slot,
106 * or NULL if the controller is idle.
107 * @cmd: The command currently being sent to the card, or NULL.
108 * @data: The data currently being transferred, or NULL if no data
109 * transfer is in progress.
110 * @data_size: just data->blocks * data->blksz.
111 * @dma: DMA client state.
112 * @data_chan: DMA channel being used for the current data transfer.
113 * @cmd_status: Snapshot of SR taken upon completion of the current
114 * command. Only valid when EVENT_CMD_COMPLETE is pending.
115 * @data_status: Snapshot of SR taken upon completion of the current
116 * data transfer. Only valid when EVENT_DATA_COMPLETE or
117 * EVENT_DATA_ERROR is pending.
118 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
119 * to be sent.
120 * @tasklet: Tasklet running the request state machine.
121 * @pending_events: Bitmask of events flagged by the interrupt handler
122 * to be processed by the tasklet.
123 * @completed_events: Bitmask of events which the state machine has
124 * processed.
125 * @state: Tasklet state.
126 * @queue: List of slots waiting for access to the controller.
127 * @need_clock_update: Update the clock rate before the next request.
128 * @need_reset: Reset controller before next request.
129 * @timer: Timer to balance the data timeout error flag which cannot rise.
130 * @mode_reg: Value of the MR register.
131 * @cfg_reg: Value of the CFG register.
132 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
133 * rate and timeout calculations.
134 * @mapbase: Physical address of the MMIO registers.
135 * @mck: The peripheral bus clock hooked up to the MMC controller.
136 * @pdev: Platform device associated with the MMC controller.
137 * @slot: Slots sharing this MMC controller.
138 * @caps: MCI capabilities depending on MCI version.
139 * @prepare_data: function to setup MCI before data transfer which
140 * depends on MCI capabilities.
141 * @submit_data: function to start data transfer which depends on MCI
142 * capabilities.
143 * @stop_transfer: function to stop data transfer which depends on MCI
144 * capabilities.
145 *
146 * Locking
147 * =======
148 *
149 * @lock is a softirq-safe spinlock protecting @queue as well as
150 * @cur_slot, @mrq and @state. These must always be updated
151 * at the same time while holding @lock.
152 *
153 * @lock also protects mode_reg and need_clock_update since these are
154 * used to synchronize mode register updates with the queue
155 * processing.
156 *
157 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
158 * and must always be written at the same time as the slot is added to
159 * @queue.
160 *
161 * @pending_events and @completed_events are accessed using atomic bit
162 * operations, so they don't need any locking.
163 *
164 * None of the fields touched by the interrupt handler need any
165 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
166 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
167 * interrupts must be disabled and @data_status updated with a
168 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
169 * CMDRDY interrupt must be disabled and @cmd_status updated with a
170 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
171 * bytes_xfered field of @data must be written. This is ensured by
172 * using barriers.
173 */
174struct atmel_mci {
175 spinlock_t lock;
176 void __iomem *regs;
177
178 struct scatterlist *sg;
179 unsigned int sg_len;
180 unsigned int pio_offset;
181 unsigned int *buffer;
182 unsigned int buf_size;
183 dma_addr_t buf_phys_addr;
184
185 struct atmel_mci_slot *cur_slot;
186 struct mmc_request *mrq;
187 struct mmc_command *cmd;
188 struct mmc_data *data;
189 unsigned int data_size;
190
191 struct atmel_mci_dma dma;
192 struct dma_chan *data_chan;
193 struct dma_slave_config dma_conf;
194
195 u32 cmd_status;
196 u32 data_status;
197 u32 stop_cmdr;
198
199 struct tasklet_struct tasklet;
200 unsigned long pending_events;
201 unsigned long completed_events;
202 enum atmel_mci_state state;
203 struct list_head queue;
204
205 bool need_clock_update;
206 bool need_reset;
207 struct timer_list timer;
208 u32 mode_reg;
209 u32 cfg_reg;
210 unsigned long bus_hz;
211 unsigned long mapbase;
212 struct clk *mck;
213 struct platform_device *pdev;
214
215 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
216
217 struct atmel_mci_caps caps;
218
219 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
220 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
221 void (*stop_transfer)(struct atmel_mci *host);
222};
223
224/**
225 * struct atmel_mci_slot - MMC slot state
226 * @mmc: The mmc_host representing this slot.
227 * @host: The MMC controller this slot is using.
228 * @sdc_reg: Value of SDCR to be written before using this slot.
229 * @sdio_irq: SDIO irq mask for this slot.
230 * @mrq: mmc_request currently being processed or waiting to be
231 * processed, or NULL when the slot is idle.
232 * @queue_node: List node for placing this node in the @queue list of
233 * &struct atmel_mci.
234 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
235 * @flags: Random state bits associated with the slot.
236 * @detect_pin: GPIO pin used for card detection, or negative if not
237 * available.
238 * @wp_pin: GPIO pin used for card write protect sending, or negative
239 * if not available.
240 * @detect_is_active_high: The state of the detect pin when it is active.
241 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
242 */
243struct atmel_mci_slot {
244 struct mmc_host *mmc;
245 struct atmel_mci *host;
246
247 u32 sdc_reg;
248 u32 sdio_irq;
249
250 struct mmc_request *mrq;
251 struct list_head queue_node;
252
253 unsigned int clock;
254 unsigned long flags;
255#define ATMCI_CARD_PRESENT 0
256#define ATMCI_CARD_NEED_INIT 1
257#define ATMCI_SHUTDOWN 2
258
259 int detect_pin;
260 int wp_pin;
261 bool detect_is_active_high;
262
263 struct timer_list detect_timer;
264};
265
266#define atmci_test_and_clear_pending(host, event) \
267 test_and_clear_bit(event, &host->pending_events)
268#define atmci_set_completed(host, event) \
269 set_bit(event, &host->completed_events)
270#define atmci_set_pending(host, event) \
271 set_bit(event, &host->pending_events)
272
273/*
274 * The debugfs stuff below is mostly optimized away when
275 * CONFIG_DEBUG_FS is not set.
276 */
277static int atmci_req_show(struct seq_file *s, void *v)
278{
279 struct atmel_mci_slot *slot = s->private;
280 struct mmc_request *mrq;
281 struct mmc_command *cmd;
282 struct mmc_command *stop;
283 struct mmc_data *data;
284
285 /* Make sure we get a consistent snapshot */
286 spin_lock_bh(&slot->host->lock);
287 mrq = slot->mrq;
288
289 if (mrq) {
290 cmd = mrq->cmd;
291 data = mrq->data;
292 stop = mrq->stop;
293
294 if (cmd)
295 seq_printf(s,
296 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
297 cmd->opcode, cmd->arg, cmd->flags,
298 cmd->resp[0], cmd->resp[1], cmd->resp[2],
299 cmd->resp[3], cmd->error);
300 if (data)
301 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
302 data->bytes_xfered, data->blocks,
303 data->blksz, data->flags, data->error);
304 if (stop)
305 seq_printf(s,
306 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
307 stop->opcode, stop->arg, stop->flags,
308 stop->resp[0], stop->resp[1], stop->resp[2],
309 stop->resp[3], stop->error);
310 }
311
312 spin_unlock_bh(&slot->host->lock);
313
314 return 0;
315}
316
317static int atmci_req_open(struct inode *inode, struct file *file)
318{
319 return single_open(file, atmci_req_show, inode->i_private);
320}
321
322static const struct file_operations atmci_req_fops = {
323 .owner = THIS_MODULE,
324 .open = atmci_req_open,
325 .read = seq_read,
326 .llseek = seq_lseek,
327 .release = single_release,
328};
329
330static void atmci_show_status_reg(struct seq_file *s,
331 const char *regname, u32 value)
332{
333 static const char *sr_bit[] = {
334 [0] = "CMDRDY",
335 [1] = "RXRDY",
336 [2] = "TXRDY",
337 [3] = "BLKE",
338 [4] = "DTIP",
339 [5] = "NOTBUSY",
340 [6] = "ENDRX",
341 [7] = "ENDTX",
342 [8] = "SDIOIRQA",
343 [9] = "SDIOIRQB",
344 [12] = "SDIOWAIT",
345 [14] = "RXBUFF",
346 [15] = "TXBUFE",
347 [16] = "RINDE",
348 [17] = "RDIRE",
349 [18] = "RCRCE",
350 [19] = "RENDE",
351 [20] = "RTOE",
352 [21] = "DCRCE",
353 [22] = "DTOE",
354 [23] = "CSTOE",
355 [24] = "BLKOVRE",
356 [25] = "DMADONE",
357 [26] = "FIFOEMPTY",
358 [27] = "XFRDONE",
359 [30] = "OVRE",
360 [31] = "UNRE",
361 };
362 unsigned int i;
363
364 seq_printf(s, "%s:\t0x%08x", regname, value);
365 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
366 if (value & (1 << i)) {
367 if (sr_bit[i])
368 seq_printf(s, " %s", sr_bit[i]);
369 else
370 seq_puts(s, " UNKNOWN");
371 }
372 }
373 seq_putc(s, '\n');
374}
375
376static int atmci_regs_show(struct seq_file *s, void *v)
377{
378 struct atmel_mci *host = s->private;
379 u32 *buf;
380 int ret = 0;
381
382
383 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
384 if (!buf)
385 return -ENOMEM;
386
387 /*
388 * Grab a more or less consistent snapshot. Note that we're
389 * not disabling interrupts, so IMR and SR may not be
390 * consistent.
391 */
392 ret = clk_prepare_enable(host->mck);
393 if (ret)
394 goto out;
395
396 spin_lock_bh(&host->lock);
397 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
398 spin_unlock_bh(&host->lock);
399
400 clk_disable_unprepare(host->mck);
401
402 seq_printf(s, "MR:\t0x%08x%s%s ",
403 buf[ATMCI_MR / 4],
404 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
405 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
406 if (host->caps.has_odd_clk_div)
407 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
408 ((buf[ATMCI_MR / 4] & 0xff) << 1)
409 | ((buf[ATMCI_MR / 4] >> 16) & 1));
410 else
411 seq_printf(s, "CLKDIV=%u\n",
412 (buf[ATMCI_MR / 4] & 0xff));
413 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
414 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
415 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
416 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
417 buf[ATMCI_BLKR / 4],
418 buf[ATMCI_BLKR / 4] & 0xffff,
419 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
420 if (host->caps.has_cstor_reg)
421 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
422
423 /* Don't read RSPR and RDR; it will consume the data there */
424
425 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
426 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
427
428 if (host->caps.has_dma_conf_reg) {
429 u32 val;
430
431 val = buf[ATMCI_DMA / 4];
432 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
433 val, val & 3,
434 ((val >> 4) & 3) ?
435 1 << (((val >> 4) & 3) + 1) : 1,
436 val & ATMCI_DMAEN ? " DMAEN" : "");
437 }
438 if (host->caps.has_cfg_reg) {
439 u32 val;
440
441 val = buf[ATMCI_CFG / 4];
442 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
443 val,
444 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
445 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
446 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
447 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
448 }
449
450out:
451 kfree(buf);
452
453 return ret;
454}
455
456static int atmci_regs_open(struct inode *inode, struct file *file)
457{
458 return single_open(file, atmci_regs_show, inode->i_private);
459}
460
461static const struct file_operations atmci_regs_fops = {
462 .owner = THIS_MODULE,
463 .open = atmci_regs_open,
464 .read = seq_read,
465 .llseek = seq_lseek,
466 .release = single_release,
467};
468
469static void atmci_init_debugfs(struct atmel_mci_slot *slot)
470{
471 struct mmc_host *mmc = slot->mmc;
472 struct atmel_mci *host = slot->host;
473 struct dentry *root;
474 struct dentry *node;
475
476 root = mmc->debugfs_root;
477 if (!root)
478 return;
479
480 node = debugfs_create_file("regs", S_IRUSR, root, host,
481 &atmci_regs_fops);
482 if (IS_ERR(node))
483 return;
484 if (!node)
485 goto err;
486
487 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
488 if (!node)
489 goto err;
490
491 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
492 if (!node)
493 goto err;
494
495 node = debugfs_create_x32("pending_events", S_IRUSR, root,
496 (u32 *)&host->pending_events);
497 if (!node)
498 goto err;
499
500 node = debugfs_create_x32("completed_events", S_IRUSR, root,
501 (u32 *)&host->completed_events);
502 if (!node)
503 goto err;
504
505 return;
506
507err:
508 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
509}
510
511#if defined(CONFIG_OF)
512static const struct of_device_id atmci_dt_ids[] = {
513 { .compatible = "atmel,hsmci" },
514 { /* sentinel */ }
515};
516
517MODULE_DEVICE_TABLE(of, atmci_dt_ids);
518
519static struct mci_platform_data*
520atmci_of_init(struct platform_device *pdev)
521{
522 struct device_node *np = pdev->dev.of_node;
523 struct device_node *cnp;
524 struct mci_platform_data *pdata;
525 u32 slot_id;
526
527 if (!np) {
528 dev_err(&pdev->dev, "device node not found\n");
529 return ERR_PTR(-EINVAL);
530 }
531
532 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
533 if (!pdata) {
534 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
535 return ERR_PTR(-ENOMEM);
536 }
537
538 for_each_child_of_node(np, cnp) {
539 if (of_property_read_u32(cnp, "reg", &slot_id)) {
540 dev_warn(&pdev->dev, "reg property is missing for %s\n",
541 cnp->full_name);
542 continue;
543 }
544
545 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
546 dev_warn(&pdev->dev, "can't have more than %d slots\n",
547 ATMCI_MAX_NR_SLOTS);
548 break;
549 }
550
551 if (of_property_read_u32(cnp, "bus-width",
552 &pdata->slot[slot_id].bus_width))
553 pdata->slot[slot_id].bus_width = 1;
554
555 pdata->slot[slot_id].detect_pin =
556 of_get_named_gpio(cnp, "cd-gpios", 0);
557
558 pdata->slot[slot_id].detect_is_active_high =
559 of_property_read_bool(cnp, "cd-inverted");
560
561 pdata->slot[slot_id].wp_pin =
562 of_get_named_gpio(cnp, "wp-gpios", 0);
563 }
564
565 return pdata;
566}
567#else /* CONFIG_OF */
568static inline struct mci_platform_data*
569atmci_of_init(struct platform_device *dev)
570{
571 return ERR_PTR(-EINVAL);
572}
573#endif
574
575static inline unsigned int atmci_get_version(struct atmel_mci *host)
576{
577 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
578}
579
580static void atmci_timeout_timer(unsigned long data)
581{
582 struct atmel_mci *host;
583
584 host = (struct atmel_mci *)data;
585
586 dev_dbg(&host->pdev->dev, "software timeout\n");
587
588 if (host->mrq->cmd->data) {
589 host->mrq->cmd->data->error = -ETIMEDOUT;
590 host->data = NULL;
591 /*
592 * With some SDIO modules, sometimes DMA transfer hangs. If
593 * stop_transfer() is not called then the DMA request is not
594 * removed, following ones are queued and never computed.
595 */
596 if (host->state == STATE_DATA_XFER)
597 host->stop_transfer(host);
598 } else {
599 host->mrq->cmd->error = -ETIMEDOUT;
600 host->cmd = NULL;
601 }
602 host->need_reset = 1;
603 host->state = STATE_END_REQUEST;
604 smp_wmb();
605 tasklet_schedule(&host->tasklet);
606}
607
608static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
609 unsigned int ns)
610{
611 /*
612 * It is easier here to use us instead of ns for the timeout,
613 * it prevents from overflows during calculation.
614 */
615 unsigned int us = DIV_ROUND_UP(ns, 1000);
616
617 /* Maximum clock frequency is host->bus_hz/2 */
618 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
619}
620
621static void atmci_set_timeout(struct atmel_mci *host,
622 struct atmel_mci_slot *slot, struct mmc_data *data)
623{
624 static unsigned dtomul_to_shift[] = {
625 0, 4, 7, 8, 10, 12, 16, 20
626 };
627 unsigned timeout;
628 unsigned dtocyc;
629 unsigned dtomul;
630
631 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
632 + data->timeout_clks;
633
634 for (dtomul = 0; dtomul < 8; dtomul++) {
635 unsigned shift = dtomul_to_shift[dtomul];
636 dtocyc = (timeout + (1 << shift) - 1) >> shift;
637 if (dtocyc < 15)
638 break;
639 }
640
641 if (dtomul >= 8) {
642 dtomul = 7;
643 dtocyc = 15;
644 }
645
646 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
647 dtocyc << dtomul_to_shift[dtomul]);
648 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
649}
650
651/*
652 * Return mask with command flags to be enabled for this command.
653 */
654static u32 atmci_prepare_command(struct mmc_host *mmc,
655 struct mmc_command *cmd)
656{
657 struct mmc_data *data;
658 u32 cmdr;
659
660 cmd->error = -EINPROGRESS;
661
662 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
663
664 if (cmd->flags & MMC_RSP_PRESENT) {
665 if (cmd->flags & MMC_RSP_136)
666 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
667 else
668 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
669 }
670
671 /*
672 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
673 * it's too difficult to determine whether this is an ACMD or
674 * not. Better make it 64.
675 */
676 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
677
678 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
679 cmdr |= ATMCI_CMDR_OPDCMD;
680
681 data = cmd->data;
682 if (data) {
683 cmdr |= ATMCI_CMDR_START_XFER;
684
685 if (cmd->opcode == SD_IO_RW_EXTENDED) {
686 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
687 } else {
688 if (data->flags & MMC_DATA_STREAM)
689 cmdr |= ATMCI_CMDR_STREAM;
690 else if (data->blocks > 1)
691 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
692 else
693 cmdr |= ATMCI_CMDR_BLOCK;
694 }
695
696 if (data->flags & MMC_DATA_READ)
697 cmdr |= ATMCI_CMDR_TRDIR_READ;
698 }
699
700 return cmdr;
701}
702
703static void atmci_send_command(struct atmel_mci *host,
704 struct mmc_command *cmd, u32 cmd_flags)
705{
706 WARN_ON(host->cmd);
707 host->cmd = cmd;
708
709 dev_vdbg(&host->pdev->dev,
710 "start command: ARGR=0x%08x CMDR=0x%08x\n",
711 cmd->arg, cmd_flags);
712
713 atmci_writel(host, ATMCI_ARGR, cmd->arg);
714 atmci_writel(host, ATMCI_CMDR, cmd_flags);
715}
716
717static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
718{
719 dev_dbg(&host->pdev->dev, "send stop command\n");
720 atmci_send_command(host, data->stop, host->stop_cmdr);
721 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
722}
723
724/*
725 * Configure given PDC buffer taking care of alignement issues.
726 * Update host->data_size and host->sg.
727 */
728static void atmci_pdc_set_single_buf(struct atmel_mci *host,
729 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
730{
731 u32 pointer_reg, counter_reg;
732 unsigned int buf_size;
733
734 if (dir == XFER_RECEIVE) {
735 pointer_reg = ATMEL_PDC_RPR;
736 counter_reg = ATMEL_PDC_RCR;
737 } else {
738 pointer_reg = ATMEL_PDC_TPR;
739 counter_reg = ATMEL_PDC_TCR;
740 }
741
742 if (buf_nb == PDC_SECOND_BUF) {
743 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
744 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
745 }
746
747 if (!host->caps.has_rwproof) {
748 buf_size = host->buf_size;
749 atmci_writel(host, pointer_reg, host->buf_phys_addr);
750 } else {
751 buf_size = sg_dma_len(host->sg);
752 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
753 }
754
755 if (host->data_size <= buf_size) {
756 if (host->data_size & 0x3) {
757 /* If size is different from modulo 4, transfer bytes */
758 atmci_writel(host, counter_reg, host->data_size);
759 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
760 } else {
761 /* Else transfer 32-bits words */
762 atmci_writel(host, counter_reg, host->data_size / 4);
763 }
764 host->data_size = 0;
765 } else {
766 /* We assume the size of a page is 32-bits aligned */
767 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
768 host->data_size -= sg_dma_len(host->sg);
769 if (host->data_size)
770 host->sg = sg_next(host->sg);
771 }
772}
773
774/*
775 * Configure PDC buffer according to the data size ie configuring one or two
776 * buffers. Don't use this function if you want to configure only the second
777 * buffer. In this case, use atmci_pdc_set_single_buf.
778 */
779static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
780{
781 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
782 if (host->data_size)
783 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
784}
785
786/*
787 * Unmap sg lists, called when transfer is finished.
788 */
789static void atmci_pdc_cleanup(struct atmel_mci *host)
790{
791 struct mmc_data *data = host->data;
792
793 if (data)
794 dma_unmap_sg(&host->pdev->dev,
795 data->sg, data->sg_len,
796 ((data->flags & MMC_DATA_WRITE)
797 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
798}
799
800/*
801 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
802 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
803 * interrupt needed for both transfer directions.
804 */
805static void atmci_pdc_complete(struct atmel_mci *host)
806{
807 int transfer_size = host->data->blocks * host->data->blksz;
808 int i;
809
810 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
811
812 if ((!host->caps.has_rwproof)
813 && (host->data->flags & MMC_DATA_READ)) {
814 if (host->caps.has_bad_data_ordering)
815 for (i = 0; i < transfer_size; i++)
816 host->buffer[i] = swab32(host->buffer[i]);
817 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
818 host->buffer, transfer_size);
819 }
820
821 atmci_pdc_cleanup(host);
822
823 /*
824 * If the card was removed, data will be NULL. No point trying
825 * to send the stop command or waiting for NBUSY in this case.
826 */
827 if (host->data) {
828 dev_dbg(&host->pdev->dev,
829 "(%s) set pending xfer complete\n", __func__);
830 atmci_set_pending(host, EVENT_XFER_COMPLETE);
831 tasklet_schedule(&host->tasklet);
832 }
833}
834
835static void atmci_dma_cleanup(struct atmel_mci *host)
836{
837 struct mmc_data *data = host->data;
838
839 if (data)
840 dma_unmap_sg(host->dma.chan->device->dev,
841 data->sg, data->sg_len,
842 ((data->flags & MMC_DATA_WRITE)
843 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
844}
845
846/*
847 * This function is called by the DMA driver from tasklet context.
848 */
849static void atmci_dma_complete(void *arg)
850{
851 struct atmel_mci *host = arg;
852 struct mmc_data *data = host->data;
853
854 dev_vdbg(&host->pdev->dev, "DMA complete\n");
855
856 if (host->caps.has_dma_conf_reg)
857 /* Disable DMA hardware handshaking on MCI */
858 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
859
860 atmci_dma_cleanup(host);
861
862 /*
863 * If the card was removed, data will be NULL. No point trying
864 * to send the stop command or waiting for NBUSY in this case.
865 */
866 if (data) {
867 dev_dbg(&host->pdev->dev,
868 "(%s) set pending xfer complete\n", __func__);
869 atmci_set_pending(host, EVENT_XFER_COMPLETE);
870 tasklet_schedule(&host->tasklet);
871
872 /*
873 * Regardless of what the documentation says, we have
874 * to wait for NOTBUSY even after block read
875 * operations.
876 *
877 * When the DMA transfer is complete, the controller
878 * may still be reading the CRC from the card, i.e.
879 * the data transfer is still in progress and we
880 * haven't seen all the potential error bits yet.
881 *
882 * The interrupt handler will schedule a different
883 * tasklet to finish things up when the data transfer
884 * is completely done.
885 *
886 * We may not complete the mmc request here anyway
887 * because the mmc layer may call back and cause us to
888 * violate the "don't submit new operations from the
889 * completion callback" rule of the dma engine
890 * framework.
891 */
892 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
893 }
894}
895
896/*
897 * Returns a mask of interrupt flags to be enabled after the whole
898 * request has been prepared.
899 */
900static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
901{
902 u32 iflags;
903
904 data->error = -EINPROGRESS;
905
906 host->sg = data->sg;
907 host->sg_len = data->sg_len;
908 host->data = data;
909 host->data_chan = NULL;
910
911 iflags = ATMCI_DATA_ERROR_FLAGS;
912
913 /*
914 * Errata: MMC data write operation with less than 12
915 * bytes is impossible.
916 *
917 * Errata: MCI Transmit Data Register (TDR) FIFO
918 * corruption when length is not multiple of 4.
919 */
920 if (data->blocks * data->blksz < 12
921 || (data->blocks * data->blksz) & 3)
922 host->need_reset = true;
923
924 host->pio_offset = 0;
925 if (data->flags & MMC_DATA_READ)
926 iflags |= ATMCI_RXRDY;
927 else
928 iflags |= ATMCI_TXRDY;
929
930 return iflags;
931}
932
933/*
934 * Set interrupt flags and set block length into the MCI mode register even
935 * if this value is also accessible in the MCI block register. It seems to be
936 * necessary before the High Speed MCI version. It also map sg and configure
937 * PDC registers.
938 */
939static u32
940atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
941{
942 u32 iflags, tmp;
943 unsigned int sg_len;
944 enum dma_data_direction dir;
945 int i;
946
947 data->error = -EINPROGRESS;
948
949 host->data = data;
950 host->sg = data->sg;
951 iflags = ATMCI_DATA_ERROR_FLAGS;
952
953 /* Enable pdc mode */
954 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
955
956 if (data->flags & MMC_DATA_READ) {
957 dir = DMA_FROM_DEVICE;
958 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
959 } else {
960 dir = DMA_TO_DEVICE;
961 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
962 }
963
964 /* Set BLKLEN */
965 tmp = atmci_readl(host, ATMCI_MR);
966 tmp &= 0x0000ffff;
967 tmp |= ATMCI_BLKLEN(data->blksz);
968 atmci_writel(host, ATMCI_MR, tmp);
969
970 /* Configure PDC */
971 host->data_size = data->blocks * data->blksz;
972 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
973
974 if ((!host->caps.has_rwproof)
975 && (host->data->flags & MMC_DATA_WRITE)) {
976 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
977 host->buffer, host->data_size);
978 if (host->caps.has_bad_data_ordering)
979 for (i = 0; i < host->data_size; i++)
980 host->buffer[i] = swab32(host->buffer[i]);
981 }
982
983 if (host->data_size)
984 atmci_pdc_set_both_buf(host,
985 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
986
987 return iflags;
988}
989
990static u32
991atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
992{
993 struct dma_chan *chan;
994 struct dma_async_tx_descriptor *desc;
995 struct scatterlist *sg;
996 unsigned int i;
997 enum dma_data_direction direction;
998 enum dma_transfer_direction slave_dirn;
999 unsigned int sglen;
1000 u32 maxburst;
1001 u32 iflags;
1002
1003 data->error = -EINPROGRESS;
1004
1005 WARN_ON(host->data);
1006 host->sg = NULL;
1007 host->data = data;
1008
1009 iflags = ATMCI_DATA_ERROR_FLAGS;
1010
1011 /*
1012 * We don't do DMA on "complex" transfers, i.e. with
1013 * non-word-aligned buffers or lengths. Also, we don't bother
1014 * with all the DMA setup overhead for short transfers.
1015 */
1016 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1017 return atmci_prepare_data(host, data);
1018 if (data->blksz & 3)
1019 return atmci_prepare_data(host, data);
1020
1021 for_each_sg(data->sg, sg, data->sg_len, i) {
1022 if (sg->offset & 3 || sg->length & 3)
1023 return atmci_prepare_data(host, data);
1024 }
1025
1026 /* If we don't have a channel, we can't do DMA */
1027 chan = host->dma.chan;
1028 if (chan)
1029 host->data_chan = chan;
1030
1031 if (!chan)
1032 return -ENODEV;
1033
1034 if (data->flags & MMC_DATA_READ) {
1035 direction = DMA_FROM_DEVICE;
1036 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1037 maxburst = atmci_convert_chksize(host->dma_conf.src_maxburst);
1038 } else {
1039 direction = DMA_TO_DEVICE;
1040 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1041 maxburst = atmci_convert_chksize(host->dma_conf.dst_maxburst);
1042 }
1043
1044 if (host->caps.has_dma_conf_reg)
1045 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1046 ATMCI_DMAEN);
1047
1048 sglen = dma_map_sg(chan->device->dev, data->sg,
1049 data->sg_len, direction);
1050
1051 dmaengine_slave_config(chan, &host->dma_conf);
1052 desc = dmaengine_prep_slave_sg(chan,
1053 data->sg, sglen, slave_dirn,
1054 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1055 if (!desc)
1056 goto unmap_exit;
1057
1058 host->dma.data_desc = desc;
1059 desc->callback = atmci_dma_complete;
1060 desc->callback_param = host;
1061
1062 return iflags;
1063unmap_exit:
1064 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
1065 return -ENOMEM;
1066}
1067
1068static void
1069atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1070{
1071 return;
1072}
1073
1074/*
1075 * Start PDC according to transfer direction.
1076 */
1077static void
1078atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1079{
1080 if (data->flags & MMC_DATA_READ)
1081 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1082 else
1083 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1084}
1085
1086static void
1087atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1088{
1089 struct dma_chan *chan = host->data_chan;
1090 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
1091
1092 if (chan) {
1093 dmaengine_submit(desc);
1094 dma_async_issue_pending(chan);
1095 }
1096}
1097
1098static void atmci_stop_transfer(struct atmel_mci *host)
1099{
1100 dev_dbg(&host->pdev->dev,
1101 "(%s) set pending xfer complete\n", __func__);
1102 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1103 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1104}
1105
1106/*
1107 * Stop data transfer because error(s) occurred.
1108 */
1109static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1110{
1111 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1112}
1113
1114static void atmci_stop_transfer_dma(struct atmel_mci *host)
1115{
1116 struct dma_chan *chan = host->data_chan;
1117
1118 if (chan) {
1119 dmaengine_terminate_all(chan);
1120 atmci_dma_cleanup(host);
1121 } else {
1122 /* Data transfer was stopped by the interrupt handler */
1123 dev_dbg(&host->pdev->dev,
1124 "(%s) set pending xfer complete\n", __func__);
1125 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1126 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1127 }
1128}
1129
1130/*
1131 * Start a request: prepare data if needed, prepare the command and activate
1132 * interrupts.
1133 */
1134static void atmci_start_request(struct atmel_mci *host,
1135 struct atmel_mci_slot *slot)
1136{
1137 struct mmc_request *mrq;
1138 struct mmc_command *cmd;
1139 struct mmc_data *data;
1140 u32 iflags;
1141 u32 cmdflags;
1142
1143 mrq = slot->mrq;
1144 host->cur_slot = slot;
1145 host->mrq = mrq;
1146
1147 host->pending_events = 0;
1148 host->completed_events = 0;
1149 host->cmd_status = 0;
1150 host->data_status = 0;
1151
1152 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1153
1154 if (host->need_reset || host->caps.need_reset_after_xfer) {
1155 iflags = atmci_readl(host, ATMCI_IMR);
1156 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1157 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1158 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1159 atmci_writel(host, ATMCI_MR, host->mode_reg);
1160 if (host->caps.has_cfg_reg)
1161 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1162 atmci_writel(host, ATMCI_IER, iflags);
1163 host->need_reset = false;
1164 }
1165 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1166
1167 iflags = atmci_readl(host, ATMCI_IMR);
1168 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1169 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1170 iflags);
1171
1172 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1173 /* Send init sequence (74 clock cycles) */
1174 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1175 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1176 cpu_relax();
1177 }
1178 iflags = 0;
1179 data = mrq->data;
1180 if (data) {
1181 atmci_set_timeout(host, slot, data);
1182
1183 /* Must set block count/size before sending command */
1184 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1185 | ATMCI_BLKLEN(data->blksz));
1186 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1187 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1188
1189 iflags |= host->prepare_data(host, data);
1190 }
1191
1192 iflags |= ATMCI_CMDRDY;
1193 cmd = mrq->cmd;
1194 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1195
1196 /*
1197 * DMA transfer should be started before sending the command to avoid
1198 * unexpected errors especially for read operations in SDIO mode.
1199 * Unfortunately, in PDC mode, command has to be sent before starting
1200 * the transfer.
1201 */
1202 if (host->submit_data != &atmci_submit_data_dma)
1203 atmci_send_command(host, cmd, cmdflags);
1204
1205 if (data)
1206 host->submit_data(host, data);
1207
1208 if (host->submit_data == &atmci_submit_data_dma)
1209 atmci_send_command(host, cmd, cmdflags);
1210
1211 if (mrq->stop) {
1212 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1213 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1214 if (!(data->flags & MMC_DATA_WRITE))
1215 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1216 if (data->flags & MMC_DATA_STREAM)
1217 host->stop_cmdr |= ATMCI_CMDR_STREAM;
1218 else
1219 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1220 }
1221
1222 /*
1223 * We could have enabled interrupts earlier, but I suspect
1224 * that would open up a nice can of interesting race
1225 * conditions (e.g. command and data complete, but stop not
1226 * prepared yet.)
1227 */
1228 atmci_writel(host, ATMCI_IER, iflags);
1229
1230 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
1231}
1232
1233static void atmci_queue_request(struct atmel_mci *host,
1234 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1235{
1236 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1237 host->state);
1238
1239 spin_lock_bh(&host->lock);
1240 slot->mrq = mrq;
1241 if (host->state == STATE_IDLE) {
1242 host->state = STATE_SENDING_CMD;
1243 atmci_start_request(host, slot);
1244 } else {
1245 dev_dbg(&host->pdev->dev, "queue request\n");
1246 list_add_tail(&slot->queue_node, &host->queue);
1247 }
1248 spin_unlock_bh(&host->lock);
1249}
1250
1251static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1252{
1253 struct atmel_mci_slot *slot = mmc_priv(mmc);
1254 struct atmel_mci *host = slot->host;
1255 struct mmc_data *data;
1256
1257 WARN_ON(slot->mrq);
1258 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1259
1260 /*
1261 * We may "know" the card is gone even though there's still an
1262 * electrical connection. If so, we really need to communicate
1263 * this to the MMC core since there won't be any more
1264 * interrupts as the card is completely removed. Otherwise,
1265 * the MMC core might believe the card is still there even
1266 * though the card was just removed very slowly.
1267 */
1268 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1269 mrq->cmd->error = -ENOMEDIUM;
1270 mmc_request_done(mmc, mrq);
1271 return;
1272 }
1273
1274 /* We don't support multiple blocks of weird lengths. */
1275 data = mrq->data;
1276 if (data && data->blocks > 1 && data->blksz & 3) {
1277 mrq->cmd->error = -EINVAL;
1278 mmc_request_done(mmc, mrq);
1279 }
1280
1281 atmci_queue_request(host, slot, mrq);
1282}
1283
1284static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1285{
1286 struct atmel_mci_slot *slot = mmc_priv(mmc);
1287 struct atmel_mci *host = slot->host;
1288 unsigned int i;
1289 bool unprepare_clk;
1290
1291 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1292 switch (ios->bus_width) {
1293 case MMC_BUS_WIDTH_1:
1294 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1295 break;
1296 case MMC_BUS_WIDTH_4:
1297 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1298 break;
1299 }
1300
1301 if (ios->clock) {
1302 unsigned int clock_min = ~0U;
1303 u32 clkdiv;
1304
1305 clk_prepare(host->mck);
1306 unprepare_clk = true;
1307
1308 spin_lock_bh(&host->lock);
1309 if (!host->mode_reg) {
1310 clk_enable(host->mck);
1311 unprepare_clk = false;
1312 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1313 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1314 if (host->caps.has_cfg_reg)
1315 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1316 }
1317
1318 /*
1319 * Use mirror of ios->clock to prevent race with mmc
1320 * core ios update when finding the minimum.
1321 */
1322 slot->clock = ios->clock;
1323 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1324 if (host->slot[i] && host->slot[i]->clock
1325 && host->slot[i]->clock < clock_min)
1326 clock_min = host->slot[i]->clock;
1327 }
1328
1329 /* Calculate clock divider */
1330 if (host->caps.has_odd_clk_div) {
1331 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1332 if (clkdiv > 511) {
1333 dev_warn(&mmc->class_dev,
1334 "clock %u too slow; using %lu\n",
1335 clock_min, host->bus_hz / (511 + 2));
1336 clkdiv = 511;
1337 }
1338 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1339 | ATMCI_MR_CLKODD(clkdiv & 1);
1340 } else {
1341 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1342 if (clkdiv > 255) {
1343 dev_warn(&mmc->class_dev,
1344 "clock %u too slow; using %lu\n",
1345 clock_min, host->bus_hz / (2 * 256));
1346 clkdiv = 255;
1347 }
1348 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1349 }
1350
1351 /*
1352 * WRPROOF and RDPROOF prevent overruns/underruns by
1353 * stopping the clock when the FIFO is full/empty.
1354 * This state is not expected to last for long.
1355 */
1356 if (host->caps.has_rwproof)
1357 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1358
1359 if (host->caps.has_cfg_reg) {
1360 /* setup High Speed mode in relation with card capacity */
1361 if (ios->timing == MMC_TIMING_SD_HS)
1362 host->cfg_reg |= ATMCI_CFG_HSMODE;
1363 else
1364 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1365 }
1366
1367 if (list_empty(&host->queue)) {
1368 atmci_writel(host, ATMCI_MR, host->mode_reg);
1369 if (host->caps.has_cfg_reg)
1370 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1371 } else {
1372 host->need_clock_update = true;
1373 }
1374
1375 spin_unlock_bh(&host->lock);
1376 } else {
1377 bool any_slot_active = false;
1378
1379 unprepare_clk = false;
1380
1381 spin_lock_bh(&host->lock);
1382 slot->clock = 0;
1383 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1384 if (host->slot[i] && host->slot[i]->clock) {
1385 any_slot_active = true;
1386 break;
1387 }
1388 }
1389 if (!any_slot_active) {
1390 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1391 if (host->mode_reg) {
1392 atmci_readl(host, ATMCI_MR);
1393 clk_disable(host->mck);
1394 unprepare_clk = true;
1395 }
1396 host->mode_reg = 0;
1397 }
1398 spin_unlock_bh(&host->lock);
1399 }
1400
1401 if (unprepare_clk)
1402 clk_unprepare(host->mck);
1403
1404 switch (ios->power_mode) {
1405 case MMC_POWER_OFF:
1406 if (!IS_ERR(mmc->supply.vmmc))
1407 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1408 break;
1409 case MMC_POWER_UP:
1410 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1411 if (!IS_ERR(mmc->supply.vmmc))
1412 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1413 break;
1414 default:
1415 /*
1416 * TODO: None of the currently available AVR32-based
1417 * boards allow MMC power to be turned off. Implement
1418 * power control when this can be tested properly.
1419 *
1420 * We also need to hook this into the clock management
1421 * somehow so that newly inserted cards aren't
1422 * subjected to a fast clock before we have a chance
1423 * to figure out what the maximum rate is. Currently,
1424 * there's no way to avoid this, and there never will
1425 * be for boards that don't support power control.
1426 */
1427 break;
1428 }
1429}
1430
1431static int atmci_get_ro(struct mmc_host *mmc)
1432{
1433 int read_only = -ENOSYS;
1434 struct atmel_mci_slot *slot = mmc_priv(mmc);
1435
1436 if (gpio_is_valid(slot->wp_pin)) {
1437 read_only = gpio_get_value(slot->wp_pin);
1438 dev_dbg(&mmc->class_dev, "card is %s\n",
1439 read_only ? "read-only" : "read-write");
1440 }
1441
1442 return read_only;
1443}
1444
1445static int atmci_get_cd(struct mmc_host *mmc)
1446{
1447 int present = -ENOSYS;
1448 struct atmel_mci_slot *slot = mmc_priv(mmc);
1449
1450 if (gpio_is_valid(slot->detect_pin)) {
1451 present = !(gpio_get_value(slot->detect_pin) ^
1452 slot->detect_is_active_high);
1453 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1454 present ? "" : "not ");
1455 }
1456
1457 return present;
1458}
1459
1460static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1461{
1462 struct atmel_mci_slot *slot = mmc_priv(mmc);
1463 struct atmel_mci *host = slot->host;
1464
1465 if (enable)
1466 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1467 else
1468 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1469}
1470
1471static const struct mmc_host_ops atmci_ops = {
1472 .request = atmci_request,
1473 .set_ios = atmci_set_ios,
1474 .get_ro = atmci_get_ro,
1475 .get_cd = atmci_get_cd,
1476 .enable_sdio_irq = atmci_enable_sdio_irq,
1477};
1478
1479/* Called with host->lock held */
1480static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1481 __releases(&host->lock)
1482 __acquires(&host->lock)
1483{
1484 struct atmel_mci_slot *slot = NULL;
1485 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1486
1487 WARN_ON(host->cmd || host->data);
1488
1489 /*
1490 * Update the MMC clock rate if necessary. This may be
1491 * necessary if set_ios() is called when a different slot is
1492 * busy transferring data.
1493 */
1494 if (host->need_clock_update) {
1495 atmci_writel(host, ATMCI_MR, host->mode_reg);
1496 if (host->caps.has_cfg_reg)
1497 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1498 }
1499
1500 host->cur_slot->mrq = NULL;
1501 host->mrq = NULL;
1502 if (!list_empty(&host->queue)) {
1503 slot = list_entry(host->queue.next,
1504 struct atmel_mci_slot, queue_node);
1505 list_del(&slot->queue_node);
1506 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1507 mmc_hostname(slot->mmc));
1508 host->state = STATE_SENDING_CMD;
1509 atmci_start_request(host, slot);
1510 } else {
1511 dev_vdbg(&host->pdev->dev, "list empty\n");
1512 host->state = STATE_IDLE;
1513 }
1514
1515 del_timer(&host->timer);
1516
1517 spin_unlock(&host->lock);
1518 mmc_request_done(prev_mmc, mrq);
1519 spin_lock(&host->lock);
1520}
1521
1522static void atmci_command_complete(struct atmel_mci *host,
1523 struct mmc_command *cmd)
1524{
1525 u32 status = host->cmd_status;
1526
1527 /* Read the response from the card (up to 16 bytes) */
1528 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1529 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1530 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1531 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1532
1533 if (status & ATMCI_RTOE)
1534 cmd->error = -ETIMEDOUT;
1535 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1536 cmd->error = -EILSEQ;
1537 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1538 cmd->error = -EIO;
1539 else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1540 if (host->caps.need_blksz_mul_4) {
1541 cmd->error = -EINVAL;
1542 host->need_reset = 1;
1543 }
1544 } else
1545 cmd->error = 0;
1546}
1547
1548static void atmci_detect_change(unsigned long data)
1549{
1550 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1551 bool present;
1552 bool present_old;
1553
1554 /*
1555 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1556 * freeing the interrupt. We must not re-enable the interrupt
1557 * if it has been freed, and if we're shutting down, it
1558 * doesn't really matter whether the card is present or not.
1559 */
1560 smp_rmb();
1561 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1562 return;
1563
1564 enable_irq(gpio_to_irq(slot->detect_pin));
1565 present = !(gpio_get_value(slot->detect_pin) ^
1566 slot->detect_is_active_high);
1567 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1568
1569 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1570 present, present_old);
1571
1572 if (present != present_old) {
1573 struct atmel_mci *host = slot->host;
1574 struct mmc_request *mrq;
1575
1576 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1577 present ? "inserted" : "removed");
1578
1579 spin_lock(&host->lock);
1580
1581 if (!present)
1582 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1583 else
1584 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1585
1586 /* Clean up queue if present */
1587 mrq = slot->mrq;
1588 if (mrq) {
1589 if (mrq == host->mrq) {
1590 /*
1591 * Reset controller to terminate any ongoing
1592 * commands or data transfers.
1593 */
1594 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1595 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1596 atmci_writel(host, ATMCI_MR, host->mode_reg);
1597 if (host->caps.has_cfg_reg)
1598 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1599
1600 host->data = NULL;
1601 host->cmd = NULL;
1602
1603 switch (host->state) {
1604 case STATE_IDLE:
1605 break;
1606 case STATE_SENDING_CMD:
1607 mrq->cmd->error = -ENOMEDIUM;
1608 if (mrq->data)
1609 host->stop_transfer(host);
1610 break;
1611 case STATE_DATA_XFER:
1612 mrq->data->error = -ENOMEDIUM;
1613 host->stop_transfer(host);
1614 break;
1615 case STATE_WAITING_NOTBUSY:
1616 mrq->data->error = -ENOMEDIUM;
1617 break;
1618 case STATE_SENDING_STOP:
1619 mrq->stop->error = -ENOMEDIUM;
1620 break;
1621 case STATE_END_REQUEST:
1622 break;
1623 }
1624
1625 atmci_request_end(host, mrq);
1626 } else {
1627 list_del(&slot->queue_node);
1628 mrq->cmd->error = -ENOMEDIUM;
1629 if (mrq->data)
1630 mrq->data->error = -ENOMEDIUM;
1631 if (mrq->stop)
1632 mrq->stop->error = -ENOMEDIUM;
1633
1634 spin_unlock(&host->lock);
1635 mmc_request_done(slot->mmc, mrq);
1636 spin_lock(&host->lock);
1637 }
1638 }
1639 spin_unlock(&host->lock);
1640
1641 mmc_detect_change(slot->mmc, 0);
1642 }
1643}
1644
1645static void atmci_tasklet_func(unsigned long priv)
1646{
1647 struct atmel_mci *host = (struct atmel_mci *)priv;
1648 struct mmc_request *mrq = host->mrq;
1649 struct mmc_data *data = host->data;
1650 enum atmel_mci_state state = host->state;
1651 enum atmel_mci_state prev_state;
1652 u32 status;
1653
1654 spin_lock(&host->lock);
1655
1656 state = host->state;
1657
1658 dev_vdbg(&host->pdev->dev,
1659 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1660 state, host->pending_events, host->completed_events,
1661 atmci_readl(host, ATMCI_IMR));
1662
1663 do {
1664 prev_state = state;
1665 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1666
1667 switch (state) {
1668 case STATE_IDLE:
1669 break;
1670
1671 case STATE_SENDING_CMD:
1672 /*
1673 * Command has been sent, we are waiting for command
1674 * ready. Then we have three next states possible:
1675 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1676 * command needing it or DATA_XFER if there is data.
1677 */
1678 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1679 if (!atmci_test_and_clear_pending(host,
1680 EVENT_CMD_RDY))
1681 break;
1682
1683 dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1684 host->cmd = NULL;
1685 atmci_set_completed(host, EVENT_CMD_RDY);
1686 atmci_command_complete(host, mrq->cmd);
1687 if (mrq->data) {
1688 dev_dbg(&host->pdev->dev,
1689 "command with data transfer");
1690 /*
1691 * If there is a command error don't start
1692 * data transfer.
1693 */
1694 if (mrq->cmd->error) {
1695 host->stop_transfer(host);
1696 host->data = NULL;
1697 atmci_writel(host, ATMCI_IDR,
1698 ATMCI_TXRDY | ATMCI_RXRDY
1699 | ATMCI_DATA_ERROR_FLAGS);
1700 state = STATE_END_REQUEST;
1701 } else
1702 state = STATE_DATA_XFER;
1703 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1704 dev_dbg(&host->pdev->dev,
1705 "command response need waiting notbusy");
1706 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1707 state = STATE_WAITING_NOTBUSY;
1708 } else
1709 state = STATE_END_REQUEST;
1710
1711 break;
1712
1713 case STATE_DATA_XFER:
1714 if (atmci_test_and_clear_pending(host,
1715 EVENT_DATA_ERROR)) {
1716 dev_dbg(&host->pdev->dev, "set completed data error\n");
1717 atmci_set_completed(host, EVENT_DATA_ERROR);
1718 state = STATE_END_REQUEST;
1719 break;
1720 }
1721
1722 /*
1723 * A data transfer is in progress. The event expected
1724 * to move to the next state depends of data transfer
1725 * type (PDC or DMA). Once transfer done we can move
1726 * to the next step which is WAITING_NOTBUSY in write
1727 * case and directly SENDING_STOP in read case.
1728 */
1729 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1730 if (!atmci_test_and_clear_pending(host,
1731 EVENT_XFER_COMPLETE))
1732 break;
1733
1734 dev_dbg(&host->pdev->dev,
1735 "(%s) set completed xfer complete\n",
1736 __func__);
1737 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1738
1739 if (host->caps.need_notbusy_for_read_ops ||
1740 (host->data->flags & MMC_DATA_WRITE)) {
1741 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1742 state = STATE_WAITING_NOTBUSY;
1743 } else if (host->mrq->stop) {
1744 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
1745 atmci_send_stop_cmd(host, data);
1746 state = STATE_SENDING_STOP;
1747 } else {
1748 host->data = NULL;
1749 data->bytes_xfered = data->blocks * data->blksz;
1750 data->error = 0;
1751 state = STATE_END_REQUEST;
1752 }
1753 break;
1754
1755 case STATE_WAITING_NOTBUSY:
1756 /*
1757 * We can be in the state for two reasons: a command
1758 * requiring waiting not busy signal (stop command
1759 * included) or a write operation. In the latest case,
1760 * we need to send a stop command.
1761 */
1762 dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1763 if (!atmci_test_and_clear_pending(host,
1764 EVENT_NOTBUSY))
1765 break;
1766
1767 dev_dbg(&host->pdev->dev, "set completed not busy\n");
1768 atmci_set_completed(host, EVENT_NOTBUSY);
1769
1770 if (host->data) {
1771 /*
1772 * For some commands such as CMD53, even if
1773 * there is data transfer, there is no stop
1774 * command to send.
1775 */
1776 if (host->mrq->stop) {
1777 atmci_writel(host, ATMCI_IER,
1778 ATMCI_CMDRDY);
1779 atmci_send_stop_cmd(host, data);
1780 state = STATE_SENDING_STOP;
1781 } else {
1782 host->data = NULL;
1783 data->bytes_xfered = data->blocks
1784 * data->blksz;
1785 data->error = 0;
1786 state = STATE_END_REQUEST;
1787 }
1788 } else
1789 state = STATE_END_REQUEST;
1790 break;
1791
1792 case STATE_SENDING_STOP:
1793 /*
1794 * In this state, it is important to set host->data to
1795 * NULL (which is tested in the waiting notbusy state)
1796 * in order to go to the end request state instead of
1797 * sending stop again.
1798 */
1799 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1800 if (!atmci_test_and_clear_pending(host,
1801 EVENT_CMD_RDY))
1802 break;
1803
1804 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1805 host->cmd = NULL;
1806 data->bytes_xfered = data->blocks * data->blksz;
1807 data->error = 0;
1808 atmci_command_complete(host, mrq->stop);
1809 if (mrq->stop->error) {
1810 host->stop_transfer(host);
1811 atmci_writel(host, ATMCI_IDR,
1812 ATMCI_TXRDY | ATMCI_RXRDY
1813 | ATMCI_DATA_ERROR_FLAGS);
1814 state = STATE_END_REQUEST;
1815 } else {
1816 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1817 state = STATE_WAITING_NOTBUSY;
1818 }
1819 host->data = NULL;
1820 break;
1821
1822 case STATE_END_REQUEST:
1823 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1824 | ATMCI_DATA_ERROR_FLAGS);
1825 status = host->data_status;
1826 if (unlikely(status)) {
1827 host->stop_transfer(host);
1828 host->data = NULL;
1829 if (data) {
1830 if (status & ATMCI_DTOE) {
1831 data->error = -ETIMEDOUT;
1832 } else if (status & ATMCI_DCRCE) {
1833 data->error = -EILSEQ;
1834 } else {
1835 data->error = -EIO;
1836 }
1837 }
1838 }
1839
1840 atmci_request_end(host, host->mrq);
1841 state = STATE_IDLE;
1842 break;
1843 }
1844 } while (state != prev_state);
1845
1846 host->state = state;
1847
1848 spin_unlock(&host->lock);
1849}
1850
1851static void atmci_read_data_pio(struct atmel_mci *host)
1852{
1853 struct scatterlist *sg = host->sg;
1854 void *buf = sg_virt(sg);
1855 unsigned int offset = host->pio_offset;
1856 struct mmc_data *data = host->data;
1857 u32 value;
1858 u32 status;
1859 unsigned int nbytes = 0;
1860
1861 do {
1862 value = atmci_readl(host, ATMCI_RDR);
1863 if (likely(offset + 4 <= sg->length)) {
1864 put_unaligned(value, (u32 *)(buf + offset));
1865
1866 offset += 4;
1867 nbytes += 4;
1868
1869 if (offset == sg->length) {
1870 flush_dcache_page(sg_page(sg));
1871 host->sg = sg = sg_next(sg);
1872 host->sg_len--;
1873 if (!sg || !host->sg_len)
1874 goto done;
1875
1876 offset = 0;
1877 buf = sg_virt(sg);
1878 }
1879 } else {
1880 unsigned int remaining = sg->length - offset;
1881 memcpy(buf + offset, &value, remaining);
1882 nbytes += remaining;
1883
1884 flush_dcache_page(sg_page(sg));
1885 host->sg = sg = sg_next(sg);
1886 host->sg_len--;
1887 if (!sg || !host->sg_len)
1888 goto done;
1889
1890 offset = 4 - remaining;
1891 buf = sg_virt(sg);
1892 memcpy(buf, (u8 *)&value + remaining, offset);
1893 nbytes += offset;
1894 }
1895
1896 status = atmci_readl(host, ATMCI_SR);
1897 if (status & ATMCI_DATA_ERROR_FLAGS) {
1898 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1899 | ATMCI_DATA_ERROR_FLAGS));
1900 host->data_status = status;
1901 data->bytes_xfered += nbytes;
1902 return;
1903 }
1904 } while (status & ATMCI_RXRDY);
1905
1906 host->pio_offset = offset;
1907 data->bytes_xfered += nbytes;
1908
1909 return;
1910
1911done:
1912 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1913 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1914 data->bytes_xfered += nbytes;
1915 smp_wmb();
1916 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1917}
1918
1919static void atmci_write_data_pio(struct atmel_mci *host)
1920{
1921 struct scatterlist *sg = host->sg;
1922 void *buf = sg_virt(sg);
1923 unsigned int offset = host->pio_offset;
1924 struct mmc_data *data = host->data;
1925 u32 value;
1926 u32 status;
1927 unsigned int nbytes = 0;
1928
1929 do {
1930 if (likely(offset + 4 <= sg->length)) {
1931 value = get_unaligned((u32 *)(buf + offset));
1932 atmci_writel(host, ATMCI_TDR, value);
1933
1934 offset += 4;
1935 nbytes += 4;
1936 if (offset == sg->length) {
1937 host->sg = sg = sg_next(sg);
1938 host->sg_len--;
1939 if (!sg || !host->sg_len)
1940 goto done;
1941
1942 offset = 0;
1943 buf = sg_virt(sg);
1944 }
1945 } else {
1946 unsigned int remaining = sg->length - offset;
1947
1948 value = 0;
1949 memcpy(&value, buf + offset, remaining);
1950 nbytes += remaining;
1951
1952 host->sg = sg = sg_next(sg);
1953 host->sg_len--;
1954 if (!sg || !host->sg_len) {
1955 atmci_writel(host, ATMCI_TDR, value);
1956 goto done;
1957 }
1958
1959 offset = 4 - remaining;
1960 buf = sg_virt(sg);
1961 memcpy((u8 *)&value + remaining, buf, offset);
1962 atmci_writel(host, ATMCI_TDR, value);
1963 nbytes += offset;
1964 }
1965
1966 status = atmci_readl(host, ATMCI_SR);
1967 if (status & ATMCI_DATA_ERROR_FLAGS) {
1968 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
1969 | ATMCI_DATA_ERROR_FLAGS));
1970 host->data_status = status;
1971 data->bytes_xfered += nbytes;
1972 return;
1973 }
1974 } while (status & ATMCI_TXRDY);
1975
1976 host->pio_offset = offset;
1977 data->bytes_xfered += nbytes;
1978
1979 return;
1980
1981done:
1982 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1983 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1984 data->bytes_xfered += nbytes;
1985 smp_wmb();
1986 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1987}
1988
1989static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1990{
1991 int i;
1992
1993 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1994 struct atmel_mci_slot *slot = host->slot[i];
1995 if (slot && (status & slot->sdio_irq)) {
1996 mmc_signal_sdio_irq(slot->mmc);
1997 }
1998 }
1999}
2000
2001
2002static irqreturn_t atmci_interrupt(int irq, void *dev_id)
2003{
2004 struct atmel_mci *host = dev_id;
2005 u32 status, mask, pending;
2006 unsigned int pass_count = 0;
2007
2008 do {
2009 status = atmci_readl(host, ATMCI_SR);
2010 mask = atmci_readl(host, ATMCI_IMR);
2011 pending = status & mask;
2012 if (!pending)
2013 break;
2014
2015 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2016 dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2017 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2018 | ATMCI_RXRDY | ATMCI_TXRDY
2019 | ATMCI_ENDRX | ATMCI_ENDTX
2020 | ATMCI_RXBUFF | ATMCI_TXBUFE);
2021
2022 host->data_status = status;
2023 dev_dbg(&host->pdev->dev, "set pending data error\n");
2024 smp_wmb();
2025 atmci_set_pending(host, EVENT_DATA_ERROR);
2026 tasklet_schedule(&host->tasklet);
2027 }
2028
2029 if (pending & ATMCI_TXBUFE) {
2030 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2031 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2032 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2033 /*
2034 * We can receive this interruption before having configured
2035 * the second pdc buffer, so we need to reconfigure first and
2036 * second buffers again
2037 */
2038 if (host->data_size) {
2039 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2040 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2041 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2042 } else {
2043 atmci_pdc_complete(host);
2044 }
2045 } else if (pending & ATMCI_ENDTX) {
2046 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2047 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2048
2049 if (host->data_size) {
2050 atmci_pdc_set_single_buf(host,
2051 XFER_TRANSMIT, PDC_SECOND_BUF);
2052 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2053 }
2054 }
2055
2056 if (pending & ATMCI_RXBUFF) {
2057 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2058 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2059 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2060 /*
2061 * We can receive this interruption before having configured
2062 * the second pdc buffer, so we need to reconfigure first and
2063 * second buffers again
2064 */
2065 if (host->data_size) {
2066 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2067 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2068 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2069 } else {
2070 atmci_pdc_complete(host);
2071 }
2072 } else if (pending & ATMCI_ENDRX) {
2073 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2074 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2075
2076 if (host->data_size) {
2077 atmci_pdc_set_single_buf(host,
2078 XFER_RECEIVE, PDC_SECOND_BUF);
2079 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2080 }
2081 }
2082
2083 /*
2084 * First mci IPs, so mainly the ones having pdc, have some
2085 * issues with the notbusy signal. You can't get it after
2086 * data transmission if you have not sent a stop command.
2087 * The appropriate workaround is to use the BLKE signal.
2088 */
2089 if (pending & ATMCI_BLKE) {
2090 dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2091 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2092 smp_wmb();
2093 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2094 atmci_set_pending(host, EVENT_NOTBUSY);
2095 tasklet_schedule(&host->tasklet);
2096 }
2097
2098 if (pending & ATMCI_NOTBUSY) {
2099 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2100 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2101 smp_wmb();
2102 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2103 atmci_set_pending(host, EVENT_NOTBUSY);
2104 tasklet_schedule(&host->tasklet);
2105 }
2106
2107 if (pending & ATMCI_RXRDY)
2108 atmci_read_data_pio(host);
2109 if (pending & ATMCI_TXRDY)
2110 atmci_write_data_pio(host);
2111
2112 if (pending & ATMCI_CMDRDY) {
2113 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2114 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2115 host->cmd_status = status;
2116 smp_wmb();
2117 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2118 atmci_set_pending(host, EVENT_CMD_RDY);
2119 tasklet_schedule(&host->tasklet);
2120 }
2121
2122 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2123 atmci_sdio_interrupt(host, status);
2124
2125 } while (pass_count++ < 5);
2126
2127 return pass_count ? IRQ_HANDLED : IRQ_NONE;
2128}
2129
2130static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2131{
2132 struct atmel_mci_slot *slot = dev_id;
2133
2134 /*
2135 * Disable interrupts until the pin has stabilized and check
2136 * the state then. Use mod_timer() since we may be in the
2137 * middle of the timer routine when this interrupt triggers.
2138 */
2139 disable_irq_nosync(irq);
2140 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2141
2142 return IRQ_HANDLED;
2143}
2144
2145static int __init atmci_init_slot(struct atmel_mci *host,
2146 struct mci_slot_pdata *slot_data, unsigned int id,
2147 u32 sdc_reg, u32 sdio_irq)
2148{
2149 struct mmc_host *mmc;
2150 struct atmel_mci_slot *slot;
2151
2152 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2153 if (!mmc)
2154 return -ENOMEM;
2155
2156 slot = mmc_priv(mmc);
2157 slot->mmc = mmc;
2158 slot->host = host;
2159 slot->detect_pin = slot_data->detect_pin;
2160 slot->wp_pin = slot_data->wp_pin;
2161 slot->detect_is_active_high = slot_data->detect_is_active_high;
2162 slot->sdc_reg = sdc_reg;
2163 slot->sdio_irq = sdio_irq;
2164
2165 dev_dbg(&mmc->class_dev,
2166 "slot[%u]: bus_width=%u, detect_pin=%d, "
2167 "detect_is_active_high=%s, wp_pin=%d\n",
2168 id, slot_data->bus_width, slot_data->detect_pin,
2169 slot_data->detect_is_active_high ? "true" : "false",
2170 slot_data->wp_pin);
2171
2172 mmc->ops = &atmci_ops;
2173 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2174 mmc->f_max = host->bus_hz / 2;
2175 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2176 if (sdio_irq)
2177 mmc->caps |= MMC_CAP_SDIO_IRQ;
2178 if (host->caps.has_highspeed)
2179 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2180 /*
2181 * Without the read/write proof capability, it is strongly suggested to
2182 * use only one bit for data to prevent fifo underruns and overruns
2183 * which will corrupt data.
2184 */
2185 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
2186 mmc->caps |= MMC_CAP_4_BIT_DATA;
2187
2188 if (atmci_get_version(host) < 0x200) {
2189 mmc->max_segs = 256;
2190 mmc->max_blk_size = 4095;
2191 mmc->max_blk_count = 256;
2192 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2193 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2194 } else {
2195 mmc->max_segs = 64;
2196 mmc->max_req_size = 32768 * 512;
2197 mmc->max_blk_size = 32768;
2198 mmc->max_blk_count = 512;
2199 }
2200
2201 /* Assume card is present initially */
2202 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2203 if (gpio_is_valid(slot->detect_pin)) {
2204 if (gpio_request(slot->detect_pin, "mmc_detect")) {
2205 dev_dbg(&mmc->class_dev, "no detect pin available\n");
2206 slot->detect_pin = -EBUSY;
2207 } else if (gpio_get_value(slot->detect_pin) ^
2208 slot->detect_is_active_high) {
2209 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2210 }
2211 }
2212
2213 if (!gpio_is_valid(slot->detect_pin))
2214 mmc->caps |= MMC_CAP_NEEDS_POLL;
2215
2216 if (gpio_is_valid(slot->wp_pin)) {
2217 if (gpio_request(slot->wp_pin, "mmc_wp")) {
2218 dev_dbg(&mmc->class_dev, "no WP pin available\n");
2219 slot->wp_pin = -EBUSY;
2220 }
2221 }
2222
2223 host->slot[id] = slot;
2224 mmc_regulator_get_supply(mmc);
2225 mmc_add_host(mmc);
2226
2227 if (gpio_is_valid(slot->detect_pin)) {
2228 int ret;
2229
2230 setup_timer(&slot->detect_timer, atmci_detect_change,
2231 (unsigned long)slot);
2232
2233 ret = request_irq(gpio_to_irq(slot->detect_pin),
2234 atmci_detect_interrupt,
2235 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2236 "mmc-detect", slot);
2237 if (ret) {
2238 dev_dbg(&mmc->class_dev,
2239 "could not request IRQ %d for detect pin\n",
2240 gpio_to_irq(slot->detect_pin));
2241 gpio_free(slot->detect_pin);
2242 slot->detect_pin = -EBUSY;
2243 }
2244 }
2245
2246 atmci_init_debugfs(slot);
2247
2248 return 0;
2249}
2250
2251static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
2252 unsigned int id)
2253{
2254 /* Debugfs stuff is cleaned up by mmc core */
2255
2256 set_bit(ATMCI_SHUTDOWN, &slot->flags);
2257 smp_wmb();
2258
2259 mmc_remove_host(slot->mmc);
2260
2261 if (gpio_is_valid(slot->detect_pin)) {
2262 int pin = slot->detect_pin;
2263
2264 free_irq(gpio_to_irq(pin), slot);
2265 del_timer_sync(&slot->detect_timer);
2266 gpio_free(pin);
2267 }
2268 if (gpio_is_valid(slot->wp_pin))
2269 gpio_free(slot->wp_pin);
2270
2271 slot->host->slot[id] = NULL;
2272 mmc_free_host(slot->mmc);
2273}
2274
2275static bool atmci_filter(struct dma_chan *chan, void *pdata)
2276{
2277 struct mci_platform_data *sl_pdata = pdata;
2278 struct mci_dma_data *sl;
2279
2280 if (!sl_pdata)
2281 return false;
2282
2283 sl = sl_pdata->dma_slave;
2284 if (sl && find_slave_dev(sl) == chan->device->dev) {
2285 chan->private = slave_data_ptr(sl);
2286 return true;
2287 } else {
2288 return false;
2289 }
2290}
2291
2292static bool atmci_configure_dma(struct atmel_mci *host)
2293{
2294 struct mci_platform_data *pdata;
2295 dma_cap_mask_t mask;
2296
2297 if (host == NULL)
2298 return false;
2299
2300 pdata = host->pdev->dev.platform_data;
2301
2302 dma_cap_zero(mask);
2303 dma_cap_set(DMA_SLAVE, mask);
2304
2305 host->dma.chan = dma_request_slave_channel_compat(mask, atmci_filter, pdata,
2306 &host->pdev->dev, "rxtx");
2307 if (!host->dma.chan) {
2308 dev_warn(&host->pdev->dev, "no DMA channel available\n");
2309 return false;
2310 } else {
2311 dev_info(&host->pdev->dev,
2312 "using %s for DMA transfers\n",
2313 dma_chan_name(host->dma.chan));
2314
2315 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2316 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2317 host->dma_conf.src_maxburst = 1;
2318 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2319 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2320 host->dma_conf.dst_maxburst = 1;
2321 host->dma_conf.device_fc = false;
2322 return true;
2323 }
2324}
2325
2326/*
2327 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2328 * HSMCI provides DMA support and a new config register but no more supports
2329 * PDC.
2330 */
2331static void __init atmci_get_cap(struct atmel_mci *host)
2332{
2333 unsigned int version;
2334
2335 version = atmci_get_version(host);
2336 dev_info(&host->pdev->dev,
2337 "version: 0x%x\n", version);
2338
2339 host->caps.has_dma_conf_reg = 0;
2340 host->caps.has_pdc = ATMCI_PDC_CONNECTED;
2341 host->caps.has_cfg_reg = 0;
2342 host->caps.has_cstor_reg = 0;
2343 host->caps.has_highspeed = 0;
2344 host->caps.has_rwproof = 0;
2345 host->caps.has_odd_clk_div = 0;
2346 host->caps.has_bad_data_ordering = 1;
2347 host->caps.need_reset_after_xfer = 1;
2348 host->caps.need_blksz_mul_4 = 1;
2349 host->caps.need_notbusy_for_read_ops = 0;
2350
2351 /* keep only major version number */
2352 switch (version & 0xf00) {
2353 case 0x500:
2354 host->caps.has_odd_clk_div = 1;
2355 case 0x400:
2356 case 0x300:
2357 host->caps.has_dma_conf_reg = 1;
2358 host->caps.has_pdc = 0;
2359 host->caps.has_cfg_reg = 1;
2360 host->caps.has_cstor_reg = 1;
2361 host->caps.has_highspeed = 1;
2362 case 0x200:
2363 host->caps.has_rwproof = 1;
2364 host->caps.need_blksz_mul_4 = 0;
2365 host->caps.need_notbusy_for_read_ops = 1;
2366 case 0x100:
2367 host->caps.has_bad_data_ordering = 0;
2368 host->caps.need_reset_after_xfer = 0;
2369 case 0x0:
2370 break;
2371 default:
2372 host->caps.has_pdc = 0;
2373 dev_warn(&host->pdev->dev,
2374 "Unmanaged mci version, set minimum capabilities\n");
2375 break;
2376 }
2377}
2378
2379static int __init atmci_probe(struct platform_device *pdev)
2380{
2381 struct mci_platform_data *pdata;
2382 struct atmel_mci *host;
2383 struct resource *regs;
2384 unsigned int nr_slots;
2385 int irq;
2386 int ret;
2387
2388 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2389 if (!regs)
2390 return -ENXIO;
2391 pdata = pdev->dev.platform_data;
2392 if (!pdata) {
2393 pdata = atmci_of_init(pdev);
2394 if (IS_ERR(pdata)) {
2395 dev_err(&pdev->dev, "platform data not available\n");
2396 return PTR_ERR(pdata);
2397 }
2398 }
2399
2400 irq = platform_get_irq(pdev, 0);
2401 if (irq < 0)
2402 return irq;
2403
2404 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
2405 if (!host)
2406 return -ENOMEM;
2407
2408 host->pdev = pdev;
2409 spin_lock_init(&host->lock);
2410 INIT_LIST_HEAD(&host->queue);
2411
2412 host->mck = clk_get(&pdev->dev, "mci_clk");
2413 if (IS_ERR(host->mck)) {
2414 ret = PTR_ERR(host->mck);
2415 goto err_clk_get;
2416 }
2417
2418 ret = -ENOMEM;
2419 host->regs = ioremap(regs->start, resource_size(regs));
2420 if (!host->regs)
2421 goto err_ioremap;
2422
2423 ret = clk_prepare_enable(host->mck);
2424 if (ret)
2425 goto err_request_irq;
2426 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2427 host->bus_hz = clk_get_rate(host->mck);
2428 clk_disable_unprepare(host->mck);
2429
2430 host->mapbase = regs->start;
2431
2432 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2433
2434 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2435 if (ret)
2436 goto err_request_irq;
2437
2438 /* Get MCI capabilities and set operations according to it */
2439 atmci_get_cap(host);
2440 if (atmci_configure_dma(host)) {
2441 host->prepare_data = &atmci_prepare_data_dma;
2442 host->submit_data = &atmci_submit_data_dma;
2443 host->stop_transfer = &atmci_stop_transfer_dma;
2444 } else if (host->caps.has_pdc) {
2445 dev_info(&pdev->dev, "using PDC\n");
2446 host->prepare_data = &atmci_prepare_data_pdc;
2447 host->submit_data = &atmci_submit_data_pdc;
2448 host->stop_transfer = &atmci_stop_transfer_pdc;
2449 } else {
2450 dev_info(&pdev->dev, "using PIO\n");
2451 host->prepare_data = &atmci_prepare_data;
2452 host->submit_data = &atmci_submit_data;
2453 host->stop_transfer = &atmci_stop_transfer;
2454 }
2455
2456 platform_set_drvdata(pdev, host);
2457
2458 setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
2459
2460 /* We need at least one slot to succeed */
2461 nr_slots = 0;
2462 ret = -ENODEV;
2463 if (pdata->slot[0].bus_width) {
2464 ret = atmci_init_slot(host, &pdata->slot[0],
2465 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2466 if (!ret) {
2467 nr_slots++;
2468 host->buf_size = host->slot[0]->mmc->max_req_size;
2469 }
2470 }
2471 if (pdata->slot[1].bus_width) {
2472 ret = atmci_init_slot(host, &pdata->slot[1],
2473 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2474 if (!ret) {
2475 nr_slots++;
2476 if (host->slot[1]->mmc->max_req_size > host->buf_size)
2477 host->buf_size =
2478 host->slot[1]->mmc->max_req_size;
2479 }
2480 }
2481
2482 if (!nr_slots) {
2483 dev_err(&pdev->dev, "init failed: no slot defined\n");
2484 goto err_init_slot;
2485 }
2486
2487 if (!host->caps.has_rwproof) {
2488 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2489 &host->buf_phys_addr,
2490 GFP_KERNEL);
2491 if (!host->buffer) {
2492 ret = -ENOMEM;
2493 dev_err(&pdev->dev, "buffer allocation failed\n");
2494 goto err_init_slot;
2495 }
2496 }
2497
2498 dev_info(&pdev->dev,
2499 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2500 host->mapbase, irq, nr_slots);
2501
2502 return 0;
2503
2504err_init_slot:
2505 if (host->dma.chan)
2506 dma_release_channel(host->dma.chan);
2507 free_irq(irq, host);
2508err_request_irq:
2509 iounmap(host->regs);
2510err_ioremap:
2511 clk_put(host->mck);
2512err_clk_get:
2513 kfree(host);
2514 return ret;
2515}
2516
2517static int __exit atmci_remove(struct platform_device *pdev)
2518{
2519 struct atmel_mci *host = platform_get_drvdata(pdev);
2520 unsigned int i;
2521
2522 if (host->buffer)
2523 dma_free_coherent(&pdev->dev, host->buf_size,
2524 host->buffer, host->buf_phys_addr);
2525
2526 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2527 if (host->slot[i])
2528 atmci_cleanup_slot(host->slot[i], i);
2529 }
2530
2531 clk_prepare_enable(host->mck);
2532 atmci_writel(host, ATMCI_IDR, ~0UL);
2533 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2534 atmci_readl(host, ATMCI_SR);
2535 clk_disable_unprepare(host->mck);
2536
2537 if (host->dma.chan)
2538 dma_release_channel(host->dma.chan);
2539
2540 free_irq(platform_get_irq(pdev, 0), host);
2541 iounmap(host->regs);
2542
2543 clk_put(host->mck);
2544 kfree(host);
2545
2546 return 0;
2547}
2548
2549static struct platform_driver atmci_driver = {
2550 .remove = __exit_p(atmci_remove),
2551 .driver = {
2552 .name = "atmel_mci",
2553 .of_match_table = of_match_ptr(atmci_dt_ids),
2554 },
2555};
2556
2557static int __init atmci_init(void)
2558{
2559 return platform_driver_probe(&atmci_driver, atmci_probe);
2560}
2561
2562static void __exit atmci_exit(void)
2563{
2564 platform_driver_unregister(&atmci_driver);
2565}
2566
2567late_initcall(atmci_init); /* try to load after dma driver when built-in */
2568module_exit(atmci_exit);
2569
2570MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2571MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2572MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Atmel MultiMedia Card Interface driver
4 *
5 * Copyright (C) 2004-2008 Atmel Corporation
6 */
7#include <linux/blkdev.h>
8#include <linux/clk.h>
9#include <linux/debugfs.h>
10#include <linux/device.h>
11#include <linux/dmaengine.h>
12#include <linux/dma-mapping.h>
13#include <linux/err.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/ioport.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/irq.h>
21#include <linux/gpio/consumer.h>
22#include <linux/platform_device.h>
23#include <linux/scatterlist.h>
24#include <linux/seq_file.h>
25#include <linux/slab.h>
26#include <linux/stat.h>
27#include <linux/types.h>
28
29#include <linux/mmc/host.h>
30#include <linux/mmc/sdio.h>
31
32#include <linux/atmel_pdc.h>
33#include <linux/pm.h>
34#include <linux/pm_runtime.h>
35#include <linux/pinctrl/consumer.h>
36
37#include <asm/cacheflush.h>
38#include <asm/io.h>
39#include <asm/unaligned.h>
40
41#define ATMCI_MAX_NR_SLOTS 2
42
43/*
44 * Superset of MCI IP registers integrated in Atmel AT91 Processor
45 * Registers and bitfields marked with [2] are only available in MCI2
46 */
47
48/* MCI Register Definitions */
49#define ATMCI_CR 0x0000 /* Control */
50#define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */
51#define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */
52#define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */
53#define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */
54#define ATMCI_CR_SWRST BIT(7) /* Software Reset */
55#define ATMCI_MR 0x0004 /* Mode */
56#define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
57#define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
58#define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */
59#define ATMCI_MR_WRPROOF BIT(12) /* Write Proof */
60#define ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */
61#define ATMCI_MR_PDCPADV BIT(14) /* Padding Value */
62#define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */
63#define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */
64#define ATMCI_DTOR 0x0008 /* Data Timeout */
65#define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
66#define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
67#define ATMCI_SDCR 0x000c /* SD Card / SDIO */
68#define ATMCI_SDCSEL_SLOT_A (0 << 0) /* Select SD slot A */
69#define ATMCI_SDCSEL_SLOT_B (1 << 0) /* Select SD slot A */
70#define ATMCI_SDCSEL_MASK (3 << 0)
71#define ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */
72#define ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */
73#define ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */
74#define ATMCI_SDCBUS_MASK (3 << 6)
75#define ATMCI_ARGR 0x0010 /* Command Argument */
76#define ATMCI_CMDR 0x0014 /* Command */
77#define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
78#define ATMCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */
79#define ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */
80#define ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */
81#define ATMCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization command */
82#define ATMCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized command */
83#define ATMCI_CMDR_SPCMD_INT (4 << 8) /* Interrupt command */
84#define ATMCI_CMDR_SPCMD_INTRESP (5 << 8) /* Interrupt response */
85#define ATMCI_CMDR_OPDCMD (1 << 11) /* Open Drain */
86#define ATMCI_CMDR_MAXLAT_5CYC (0 << 12) /* Max latency 5 cycles */
87#define ATMCI_CMDR_MAXLAT_64CYC (1 << 12) /* Max latency 64 cycles */
88#define ATMCI_CMDR_START_XFER (1 << 16) /* Start data transfer */
89#define ATMCI_CMDR_STOP_XFER (2 << 16) /* Stop data transfer */
90#define ATMCI_CMDR_TRDIR_WRITE (0 << 18) /* Write data */
91#define ATMCI_CMDR_TRDIR_READ (1 << 18) /* Read data */
92#define ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */
93#define ATMCI_CMDR_MULTI_BLOCK (1 << 19) /* Multi-block transfer */
94#define ATMCI_CMDR_STREAM (2 << 19) /* MMC Stream transfer */
95#define ATMCI_CMDR_SDIO_BYTE (4 << 19) /* SDIO Byte transfer */
96#define ATMCI_CMDR_SDIO_BLOCK (5 << 19) /* SDIO Block transfer */
97#define ATMCI_CMDR_SDIO_SUSPEND (1 << 24) /* SDIO Suspend Command */
98#define ATMCI_CMDR_SDIO_RESUME (2 << 24) /* SDIO Resume Command */
99#define ATMCI_BLKR 0x0018 /* Block */
100#define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */
101#define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
102#define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
103#define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
104#define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
105#define ATMCI_RSPR 0x0020 /* Response 0 */
106#define ATMCI_RSPR1 0x0024 /* Response 1 */
107#define ATMCI_RSPR2 0x0028 /* Response 2 */
108#define ATMCI_RSPR3 0x002c /* Response 3 */
109#define ATMCI_RDR 0x0030 /* Receive Data */
110#define ATMCI_TDR 0x0034 /* Transmit Data */
111#define ATMCI_SR 0x0040 /* Status */
112#define ATMCI_IER 0x0044 /* Interrupt Enable */
113#define ATMCI_IDR 0x0048 /* Interrupt Disable */
114#define ATMCI_IMR 0x004c /* Interrupt Mask */
115#define ATMCI_CMDRDY BIT(0) /* Command Ready */
116#define ATMCI_RXRDY BIT(1) /* Receiver Ready */
117#define ATMCI_TXRDY BIT(2) /* Transmitter Ready */
118#define ATMCI_BLKE BIT(3) /* Data Block Ended */
119#define ATMCI_DTIP BIT(4) /* Data Transfer In Progress */
120#define ATMCI_NOTBUSY BIT(5) /* Data Not Busy */
121#define ATMCI_ENDRX BIT(6) /* End of RX Buffer */
122#define ATMCI_ENDTX BIT(7) /* End of TX Buffer */
123#define ATMCI_SDIOIRQA BIT(8) /* SDIO IRQ in slot A */
124#define ATMCI_SDIOIRQB BIT(9) /* SDIO IRQ in slot B */
125#define ATMCI_SDIOWAIT BIT(12) /* SDIO Read Wait Operation Status */
126#define ATMCI_CSRCV BIT(13) /* CE-ATA Completion Signal Received */
127#define ATMCI_RXBUFF BIT(14) /* RX Buffer Full */
128#define ATMCI_TXBUFE BIT(15) /* TX Buffer Empty */
129#define ATMCI_RINDE BIT(16) /* Response Index Error */
130#define ATMCI_RDIRE BIT(17) /* Response Direction Error */
131#define ATMCI_RCRCE BIT(18) /* Response CRC Error */
132#define ATMCI_RENDE BIT(19) /* Response End Bit Error */
133#define ATMCI_RTOE BIT(20) /* Response Time-Out Error */
134#define ATMCI_DCRCE BIT(21) /* Data CRC Error */
135#define ATMCI_DTOE BIT(22) /* Data Time-Out Error */
136#define ATMCI_CSTOE BIT(23) /* Completion Signal Time-out Error */
137#define ATMCI_BLKOVRE BIT(24) /* DMA Block Overrun Error */
138#define ATMCI_DMADONE BIT(25) /* DMA Transfer Done */
139#define ATMCI_FIFOEMPTY BIT(26) /* FIFO Empty Flag */
140#define ATMCI_XFRDONE BIT(27) /* Transfer Done Flag */
141#define ATMCI_ACKRCV BIT(28) /* Boot Operation Acknowledge Received */
142#define ATMCI_ACKRCVE BIT(29) /* Boot Operation Acknowledge Error */
143#define ATMCI_OVRE BIT(30) /* RX Overrun Error */
144#define ATMCI_UNRE BIT(31) /* TX Underrun Error */
145#define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
146#define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
147#define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
148#define ATMCI_DMAEN BIT(8) /* DMA Hardware Handshaking Enable */
149#define ATMCI_CFG 0x0054 /* Configuration[2] */
150#define ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */
151#define ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */
152#define ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */
153#define ATMCI_CFG_LSYNC BIT(12) /* Synchronize on the last block */
154#define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
155#define ATMCI_WP_EN BIT(0) /* WP Enable */
156#define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */
157#define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
158#define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
159#define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
160#define ATMCI_VERSION 0x00FC /* Version */
161#define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
162
163/* This is not including the FIFO Aperture on MCI2 */
164#define ATMCI_REGS_SIZE 0x100
165
166/* Register access macros */
167#define atmci_readl(port, reg) \
168 __raw_readl((port)->regs + reg)
169#define atmci_writel(port, reg, value) \
170 __raw_writel((value), (port)->regs + reg)
171
172#define ATMCI_CMD_TIMEOUT_MS 2000
173#define AUTOSUSPEND_DELAY 50
174
175#define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
176#define ATMCI_DMA_THRESHOLD 16
177
178enum {
179 EVENT_CMD_RDY = 0,
180 EVENT_XFER_COMPLETE,
181 EVENT_NOTBUSY,
182 EVENT_DATA_ERROR,
183};
184
185enum atmel_mci_state {
186 STATE_IDLE = 0,
187 STATE_SENDING_CMD,
188 STATE_DATA_XFER,
189 STATE_WAITING_NOTBUSY,
190 STATE_SENDING_STOP,
191 STATE_END_REQUEST,
192};
193
194enum atmci_xfer_dir {
195 XFER_RECEIVE = 0,
196 XFER_TRANSMIT,
197};
198
199enum atmci_pdc_buf {
200 PDC_FIRST_BUF = 0,
201 PDC_SECOND_BUF,
202};
203
204/**
205 * struct mci_slot_pdata - board-specific per-slot configuration
206 * @bus_width: Number of data lines wired up the slot
207 * @detect_pin: GPIO pin wired to the card detect switch
208 * @wp_pin: GPIO pin wired to the write protect sensor
209 * @non_removable: The slot is not removable, only detect once
210 *
211 * If a given slot is not present on the board, @bus_width should be
212 * set to 0. The other fields are ignored in this case.
213 *
214 * Any pins that aren't available should be set to a negative value.
215 *
216 * Note that support for multiple slots is experimental -- some cards
217 * might get upset if we don't get the clock management exactly right.
218 * But in most cases, it should work just fine.
219 */
220struct mci_slot_pdata {
221 unsigned int bus_width;
222 struct gpio_desc *detect_pin;
223 struct gpio_desc *wp_pin;
224 bool non_removable;
225};
226
227/**
228 * struct mci_platform_data - board-specific MMC/SDcard configuration
229 * @dma_slave: DMA slave interface to use in data transfers.
230 * @dma_filter: Filtering function to filter the DMA channel
231 * @slot: Per-slot configuration data.
232 */
233struct mci_platform_data {
234 void *dma_slave;
235 dma_filter_fn dma_filter;
236 struct mci_slot_pdata slot[ATMCI_MAX_NR_SLOTS];
237};
238
239struct atmel_mci_caps {
240 bool has_dma_conf_reg;
241 bool has_pdc;
242 bool has_cfg_reg;
243 bool has_cstor_reg;
244 bool has_highspeed;
245 bool has_rwproof;
246 bool has_odd_clk_div;
247 bool has_bad_data_ordering;
248 bool need_reset_after_xfer;
249 bool need_blksz_mul_4;
250 bool need_notbusy_for_read_ops;
251};
252
253struct atmel_mci_dma {
254 struct dma_chan *chan;
255 struct dma_async_tx_descriptor *data_desc;
256};
257
258/**
259 * struct atmel_mci - MMC controller state shared between all slots
260 * @lock: Spinlock protecting the queue and associated data.
261 * @regs: Pointer to MMIO registers.
262 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
263 * @sg_len: Size of the scatterlist
264 * @pio_offset: Offset into the current scatterlist entry.
265 * @buffer: Buffer used if we don't have the r/w proof capability. We
266 * don't have the time to switch pdc buffers so we have to use only
267 * one buffer for the full transaction.
268 * @buf_size: size of the buffer.
269 * @buf_phys_addr: buffer address needed for pdc.
270 * @cur_slot: The slot which is currently using the controller.
271 * @mrq: The request currently being processed on @cur_slot,
272 * or NULL if the controller is idle.
273 * @cmd: The command currently being sent to the card, or NULL.
274 * @data: The data currently being transferred, or NULL if no data
275 * transfer is in progress.
276 * @data_size: just data->blocks * data->blksz.
277 * @dma: DMA client state.
278 * @data_chan: DMA channel being used for the current data transfer.
279 * @dma_conf: Configuration for the DMA slave
280 * @cmd_status: Snapshot of SR taken upon completion of the current
281 * command. Only valid when EVENT_CMD_COMPLETE is pending.
282 * @data_status: Snapshot of SR taken upon completion of the current
283 * data transfer. Only valid when EVENT_DATA_COMPLETE or
284 * EVENT_DATA_ERROR is pending.
285 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
286 * to be sent.
287 * @tasklet: Tasklet running the request state machine.
288 * @pending_events: Bitmask of events flagged by the interrupt handler
289 * to be processed by the tasklet.
290 * @completed_events: Bitmask of events which the state machine has
291 * processed.
292 * @state: Tasklet state.
293 * @queue: List of slots waiting for access to the controller.
294 * @need_clock_update: Update the clock rate before the next request.
295 * @need_reset: Reset controller before next request.
296 * @timer: Timer to balance the data timeout error flag which cannot rise.
297 * @mode_reg: Value of the MR register.
298 * @cfg_reg: Value of the CFG register.
299 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
300 * rate and timeout calculations.
301 * @mapbase: Physical address of the MMIO registers.
302 * @mck: The peripheral bus clock hooked up to the MMC controller.
303 * @pdev: Platform device associated with the MMC controller.
304 * @slot: Slots sharing this MMC controller.
305 * @caps: MCI capabilities depending on MCI version.
306 * @prepare_data: function to setup MCI before data transfer which
307 * depends on MCI capabilities.
308 * @submit_data: function to start data transfer which depends on MCI
309 * capabilities.
310 * @stop_transfer: function to stop data transfer which depends on MCI
311 * capabilities.
312 *
313 * Locking
314 * =======
315 *
316 * @lock is a softirq-safe spinlock protecting @queue as well as
317 * @cur_slot, @mrq and @state. These must always be updated
318 * at the same time while holding @lock.
319 *
320 * @lock also protects mode_reg and need_clock_update since these are
321 * used to synchronize mode register updates with the queue
322 * processing.
323 *
324 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
325 * and must always be written at the same time as the slot is added to
326 * @queue.
327 *
328 * @pending_events and @completed_events are accessed using atomic bit
329 * operations, so they don't need any locking.
330 *
331 * None of the fields touched by the interrupt handler need any
332 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
333 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
334 * interrupts must be disabled and @data_status updated with a
335 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
336 * CMDRDY interrupt must be disabled and @cmd_status updated with a
337 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
338 * bytes_xfered field of @data must be written. This is ensured by
339 * using barriers.
340 */
341struct atmel_mci {
342 spinlock_t lock;
343 void __iomem *regs;
344
345 struct scatterlist *sg;
346 unsigned int sg_len;
347 unsigned int pio_offset;
348 unsigned int *buffer;
349 unsigned int buf_size;
350 dma_addr_t buf_phys_addr;
351
352 struct atmel_mci_slot *cur_slot;
353 struct mmc_request *mrq;
354 struct mmc_command *cmd;
355 struct mmc_data *data;
356 unsigned int data_size;
357
358 struct atmel_mci_dma dma;
359 struct dma_chan *data_chan;
360 struct dma_slave_config dma_conf;
361
362 u32 cmd_status;
363 u32 data_status;
364 u32 stop_cmdr;
365
366 struct tasklet_struct tasklet;
367 unsigned long pending_events;
368 unsigned long completed_events;
369 enum atmel_mci_state state;
370 struct list_head queue;
371
372 bool need_clock_update;
373 bool need_reset;
374 struct timer_list timer;
375 u32 mode_reg;
376 u32 cfg_reg;
377 unsigned long bus_hz;
378 unsigned long mapbase;
379 struct clk *mck;
380 struct platform_device *pdev;
381
382 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
383
384 struct atmel_mci_caps caps;
385
386 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
387 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
388 void (*stop_transfer)(struct atmel_mci *host);
389};
390
391/**
392 * struct atmel_mci_slot - MMC slot state
393 * @mmc: The mmc_host representing this slot.
394 * @host: The MMC controller this slot is using.
395 * @sdc_reg: Value of SDCR to be written before using this slot.
396 * @sdio_irq: SDIO irq mask for this slot.
397 * @mrq: mmc_request currently being processed or waiting to be
398 * processed, or NULL when the slot is idle.
399 * @queue_node: List node for placing this node in the @queue list of
400 * &struct atmel_mci.
401 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
402 * @flags: Random state bits associated with the slot.
403 * @detect_pin: GPIO pin used for card detection, or negative if not
404 * available.
405 * @wp_pin: GPIO pin used for card write protect sending, or negative
406 * if not available.
407 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
408 */
409struct atmel_mci_slot {
410 struct mmc_host *mmc;
411 struct atmel_mci *host;
412
413 u32 sdc_reg;
414 u32 sdio_irq;
415
416 struct mmc_request *mrq;
417 struct list_head queue_node;
418
419 unsigned int clock;
420 unsigned long flags;
421#define ATMCI_CARD_PRESENT 0
422#define ATMCI_CARD_NEED_INIT 1
423#define ATMCI_SHUTDOWN 2
424
425 struct gpio_desc *detect_pin;
426 struct gpio_desc *wp_pin;
427
428 struct timer_list detect_timer;
429};
430
431#define atmci_test_and_clear_pending(host, event) \
432 test_and_clear_bit(event, &host->pending_events)
433#define atmci_set_completed(host, event) \
434 set_bit(event, &host->completed_events)
435#define atmci_set_pending(host, event) \
436 set_bit(event, &host->pending_events)
437
438/*
439 * The debugfs stuff below is mostly optimized away when
440 * CONFIG_DEBUG_FS is not set.
441 */
442static int atmci_req_show(struct seq_file *s, void *v)
443{
444 struct atmel_mci_slot *slot = s->private;
445 struct mmc_request *mrq;
446 struct mmc_command *cmd;
447 struct mmc_command *stop;
448 struct mmc_data *data;
449
450 /* Make sure we get a consistent snapshot */
451 spin_lock_bh(&slot->host->lock);
452 mrq = slot->mrq;
453
454 if (mrq) {
455 cmd = mrq->cmd;
456 data = mrq->data;
457 stop = mrq->stop;
458
459 if (cmd)
460 seq_printf(s,
461 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
462 cmd->opcode, cmd->arg, cmd->flags,
463 cmd->resp[0], cmd->resp[1], cmd->resp[2],
464 cmd->resp[3], cmd->error);
465 if (data)
466 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
467 data->bytes_xfered, data->blocks,
468 data->blksz, data->flags, data->error);
469 if (stop)
470 seq_printf(s,
471 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
472 stop->opcode, stop->arg, stop->flags,
473 stop->resp[0], stop->resp[1], stop->resp[2],
474 stop->resp[3], stop->error);
475 }
476
477 spin_unlock_bh(&slot->host->lock);
478
479 return 0;
480}
481
482DEFINE_SHOW_ATTRIBUTE(atmci_req);
483
484static void atmci_show_status_reg(struct seq_file *s,
485 const char *regname, u32 value)
486{
487 static const char *sr_bit[] = {
488 [0] = "CMDRDY",
489 [1] = "RXRDY",
490 [2] = "TXRDY",
491 [3] = "BLKE",
492 [4] = "DTIP",
493 [5] = "NOTBUSY",
494 [6] = "ENDRX",
495 [7] = "ENDTX",
496 [8] = "SDIOIRQA",
497 [9] = "SDIOIRQB",
498 [12] = "SDIOWAIT",
499 [14] = "RXBUFF",
500 [15] = "TXBUFE",
501 [16] = "RINDE",
502 [17] = "RDIRE",
503 [18] = "RCRCE",
504 [19] = "RENDE",
505 [20] = "RTOE",
506 [21] = "DCRCE",
507 [22] = "DTOE",
508 [23] = "CSTOE",
509 [24] = "BLKOVRE",
510 [25] = "DMADONE",
511 [26] = "FIFOEMPTY",
512 [27] = "XFRDONE",
513 [30] = "OVRE",
514 [31] = "UNRE",
515 };
516 unsigned int i;
517
518 seq_printf(s, "%s:\t0x%08x", regname, value);
519 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
520 if (value & (1 << i)) {
521 if (sr_bit[i])
522 seq_printf(s, " %s", sr_bit[i]);
523 else
524 seq_puts(s, " UNKNOWN");
525 }
526 }
527 seq_putc(s, '\n');
528}
529
530static int atmci_regs_show(struct seq_file *s, void *v)
531{
532 struct atmel_mci *host = s->private;
533 u32 *buf;
534 int ret = 0;
535
536
537 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
538 if (!buf)
539 return -ENOMEM;
540
541 pm_runtime_get_sync(&host->pdev->dev);
542
543 /*
544 * Grab a more or less consistent snapshot. Note that we're
545 * not disabling interrupts, so IMR and SR may not be
546 * consistent.
547 */
548 spin_lock_bh(&host->lock);
549 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
550 spin_unlock_bh(&host->lock);
551
552 pm_runtime_mark_last_busy(&host->pdev->dev);
553 pm_runtime_put_autosuspend(&host->pdev->dev);
554
555 seq_printf(s, "MR:\t0x%08x%s%s ",
556 buf[ATMCI_MR / 4],
557 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
558 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
559 if (host->caps.has_odd_clk_div)
560 seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
561 ((buf[ATMCI_MR / 4] & 0xff) << 1)
562 | ((buf[ATMCI_MR / 4] >> 16) & 1));
563 else
564 seq_printf(s, "CLKDIV=%u\n",
565 (buf[ATMCI_MR / 4] & 0xff));
566 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
567 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
568 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
569 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
570 buf[ATMCI_BLKR / 4],
571 buf[ATMCI_BLKR / 4] & 0xffff,
572 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
573 if (host->caps.has_cstor_reg)
574 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
575
576 /* Don't read RSPR and RDR; it will consume the data there */
577
578 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
579 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
580
581 if (host->caps.has_dma_conf_reg) {
582 u32 val;
583
584 val = buf[ATMCI_DMA / 4];
585 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
586 val, val & 3,
587 ((val >> 4) & 3) ?
588 1 << (((val >> 4) & 3) + 1) : 1,
589 val & ATMCI_DMAEN ? " DMAEN" : "");
590 }
591 if (host->caps.has_cfg_reg) {
592 u32 val;
593
594 val = buf[ATMCI_CFG / 4];
595 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
596 val,
597 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
598 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
599 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
600 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
601 }
602
603 kfree(buf);
604
605 return ret;
606}
607
608DEFINE_SHOW_ATTRIBUTE(atmci_regs);
609
610static void atmci_init_debugfs(struct atmel_mci_slot *slot)
611{
612 struct mmc_host *mmc = slot->mmc;
613 struct atmel_mci *host = slot->host;
614 struct dentry *root;
615
616 root = mmc->debugfs_root;
617 if (!root)
618 return;
619
620 debugfs_create_file("regs", S_IRUSR, root, host, &atmci_regs_fops);
621 debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
622 debugfs_create_u32("state", S_IRUSR, root, &host->state);
623 debugfs_create_xul("pending_events", S_IRUSR, root,
624 &host->pending_events);
625 debugfs_create_xul("completed_events", S_IRUSR, root,
626 &host->completed_events);
627}
628
629#if defined(CONFIG_OF)
630static const struct of_device_id atmci_dt_ids[] = {
631 { .compatible = "atmel,hsmci" },
632 { /* sentinel */ }
633};
634
635MODULE_DEVICE_TABLE(of, atmci_dt_ids);
636
637static struct mci_platform_data*
638atmci_of_init(struct platform_device *pdev)
639{
640 struct device_node *np = pdev->dev.of_node;
641 struct device_node *cnp;
642 struct mci_platform_data *pdata;
643 u32 slot_id;
644 int err;
645
646 if (!np) {
647 dev_err(&pdev->dev, "device node not found\n");
648 return ERR_PTR(-EINVAL);
649 }
650
651 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
652 if (!pdata)
653 return ERR_PTR(-ENOMEM);
654
655 for_each_child_of_node(np, cnp) {
656 if (of_property_read_u32(cnp, "reg", &slot_id)) {
657 dev_warn(&pdev->dev, "reg property is missing for %pOF\n",
658 cnp);
659 continue;
660 }
661
662 if (slot_id >= ATMCI_MAX_NR_SLOTS) {
663 dev_warn(&pdev->dev, "can't have more than %d slots\n",
664 ATMCI_MAX_NR_SLOTS);
665 of_node_put(cnp);
666 break;
667 }
668
669 if (of_property_read_u32(cnp, "bus-width",
670 &pdata->slot[slot_id].bus_width))
671 pdata->slot[slot_id].bus_width = 1;
672
673 pdata->slot[slot_id].detect_pin =
674 devm_fwnode_gpiod_get(&pdev->dev, of_fwnode_handle(cnp),
675 "cd", GPIOD_IN, "cd-gpios");
676 err = PTR_ERR_OR_ZERO(pdata->slot[slot_id].detect_pin);
677 if (err) {
678 if (err != -ENOENT) {
679 of_node_put(cnp);
680 return ERR_PTR(err);
681 }
682 pdata->slot[slot_id].detect_pin = NULL;
683 }
684
685 pdata->slot[slot_id].non_removable =
686 of_property_read_bool(cnp, "non-removable");
687
688 pdata->slot[slot_id].wp_pin =
689 devm_fwnode_gpiod_get(&pdev->dev, of_fwnode_handle(cnp),
690 "wp", GPIOD_IN, "wp-gpios");
691 err = PTR_ERR_OR_ZERO(pdata->slot[slot_id].wp_pin);
692 if (err) {
693 if (err != -ENOENT) {
694 of_node_put(cnp);
695 return ERR_PTR(err);
696 }
697 pdata->slot[slot_id].wp_pin = NULL;
698 }
699 }
700
701 return pdata;
702}
703#else /* CONFIG_OF */
704static inline struct mci_platform_data*
705atmci_of_init(struct platform_device *dev)
706{
707 return ERR_PTR(-EINVAL);
708}
709#endif
710
711static inline unsigned int atmci_get_version(struct atmel_mci *host)
712{
713 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
714}
715
716/*
717 * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
718 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
719 * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
720 * 8 -> 3, 16 -> 4.
721 *
722 * This can be done by finding most significant bit set.
723 */
724static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
725 unsigned int maxburst)
726{
727 unsigned int version = atmci_get_version(host);
728 unsigned int offset = 2;
729
730 if (version >= 0x600)
731 offset = 1;
732
733 if (maxburst > 1)
734 return fls(maxburst) - offset;
735 else
736 return 0;
737}
738
739static void atmci_timeout_timer(struct timer_list *t)
740{
741 struct atmel_mci *host;
742
743 host = from_timer(host, t, timer);
744
745 dev_dbg(&host->pdev->dev, "software timeout\n");
746
747 if (host->mrq->cmd->data) {
748 host->mrq->cmd->data->error = -ETIMEDOUT;
749 host->data = NULL;
750 /*
751 * With some SDIO modules, sometimes DMA transfer hangs. If
752 * stop_transfer() is not called then the DMA request is not
753 * removed, following ones are queued and never computed.
754 */
755 if (host->state == STATE_DATA_XFER)
756 host->stop_transfer(host);
757 } else {
758 host->mrq->cmd->error = -ETIMEDOUT;
759 host->cmd = NULL;
760 }
761 host->need_reset = 1;
762 host->state = STATE_END_REQUEST;
763 smp_wmb();
764 tasklet_schedule(&host->tasklet);
765}
766
767static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
768 unsigned int ns)
769{
770 /*
771 * It is easier here to use us instead of ns for the timeout,
772 * it prevents from overflows during calculation.
773 */
774 unsigned int us = DIV_ROUND_UP(ns, 1000);
775
776 /* Maximum clock frequency is host->bus_hz/2 */
777 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
778}
779
780static void atmci_set_timeout(struct atmel_mci *host,
781 struct atmel_mci_slot *slot, struct mmc_data *data)
782{
783 static unsigned dtomul_to_shift[] = {
784 0, 4, 7, 8, 10, 12, 16, 20
785 };
786 unsigned timeout;
787 unsigned dtocyc;
788 unsigned dtomul;
789
790 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
791 + data->timeout_clks;
792
793 for (dtomul = 0; dtomul < 8; dtomul++) {
794 unsigned shift = dtomul_to_shift[dtomul];
795 dtocyc = (timeout + (1 << shift) - 1) >> shift;
796 if (dtocyc < 15)
797 break;
798 }
799
800 if (dtomul >= 8) {
801 dtomul = 7;
802 dtocyc = 15;
803 }
804
805 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
806 dtocyc << dtomul_to_shift[dtomul]);
807 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
808}
809
810/*
811 * Return mask with command flags to be enabled for this command.
812 */
813static u32 atmci_prepare_command(struct mmc_host *mmc,
814 struct mmc_command *cmd)
815{
816 struct mmc_data *data;
817 u32 cmdr;
818
819 cmd->error = -EINPROGRESS;
820
821 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
822
823 if (cmd->flags & MMC_RSP_PRESENT) {
824 if (cmd->flags & MMC_RSP_136)
825 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
826 else
827 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
828 }
829
830 /*
831 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
832 * it's too difficult to determine whether this is an ACMD or
833 * not. Better make it 64.
834 */
835 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
836
837 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
838 cmdr |= ATMCI_CMDR_OPDCMD;
839
840 data = cmd->data;
841 if (data) {
842 cmdr |= ATMCI_CMDR_START_XFER;
843
844 if (cmd->opcode == SD_IO_RW_EXTENDED) {
845 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
846 } else {
847 if (data->blocks > 1)
848 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
849 else
850 cmdr |= ATMCI_CMDR_BLOCK;
851 }
852
853 if (data->flags & MMC_DATA_READ)
854 cmdr |= ATMCI_CMDR_TRDIR_READ;
855 }
856
857 return cmdr;
858}
859
860static void atmci_send_command(struct atmel_mci *host,
861 struct mmc_command *cmd, u32 cmd_flags)
862{
863 unsigned int timeout_ms = cmd->busy_timeout ? cmd->busy_timeout :
864 ATMCI_CMD_TIMEOUT_MS;
865
866 WARN_ON(host->cmd);
867 host->cmd = cmd;
868
869 dev_vdbg(&host->pdev->dev,
870 "start command: ARGR=0x%08x CMDR=0x%08x\n",
871 cmd->arg, cmd_flags);
872
873 atmci_writel(host, ATMCI_ARGR, cmd->arg);
874 atmci_writel(host, ATMCI_CMDR, cmd_flags);
875
876 mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout_ms));
877}
878
879static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
880{
881 dev_dbg(&host->pdev->dev, "send stop command\n");
882 atmci_send_command(host, data->stop, host->stop_cmdr);
883 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
884}
885
886/*
887 * Configure given PDC buffer taking care of alignement issues.
888 * Update host->data_size and host->sg.
889 */
890static void atmci_pdc_set_single_buf(struct atmel_mci *host,
891 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
892{
893 u32 pointer_reg, counter_reg;
894 unsigned int buf_size;
895
896 if (dir == XFER_RECEIVE) {
897 pointer_reg = ATMEL_PDC_RPR;
898 counter_reg = ATMEL_PDC_RCR;
899 } else {
900 pointer_reg = ATMEL_PDC_TPR;
901 counter_reg = ATMEL_PDC_TCR;
902 }
903
904 if (buf_nb == PDC_SECOND_BUF) {
905 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
906 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
907 }
908
909 if (!host->caps.has_rwproof) {
910 buf_size = host->buf_size;
911 atmci_writel(host, pointer_reg, host->buf_phys_addr);
912 } else {
913 buf_size = sg_dma_len(host->sg);
914 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
915 }
916
917 if (host->data_size <= buf_size) {
918 if (host->data_size & 0x3) {
919 /* If size is different from modulo 4, transfer bytes */
920 atmci_writel(host, counter_reg, host->data_size);
921 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
922 } else {
923 /* Else transfer 32-bits words */
924 atmci_writel(host, counter_reg, host->data_size / 4);
925 }
926 host->data_size = 0;
927 } else {
928 /* We assume the size of a page is 32-bits aligned */
929 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
930 host->data_size -= sg_dma_len(host->sg);
931 if (host->data_size)
932 host->sg = sg_next(host->sg);
933 }
934}
935
936/*
937 * Configure PDC buffer according to the data size ie configuring one or two
938 * buffers. Don't use this function if you want to configure only the second
939 * buffer. In this case, use atmci_pdc_set_single_buf.
940 */
941static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
942{
943 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
944 if (host->data_size)
945 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
946}
947
948/*
949 * Unmap sg lists, called when transfer is finished.
950 */
951static void atmci_pdc_cleanup(struct atmel_mci *host)
952{
953 struct mmc_data *data = host->data;
954
955 if (data)
956 dma_unmap_sg(&host->pdev->dev,
957 data->sg, data->sg_len,
958 mmc_get_dma_dir(data));
959}
960
961/*
962 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
963 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
964 * interrupt needed for both transfer directions.
965 */
966static void atmci_pdc_complete(struct atmel_mci *host)
967{
968 int transfer_size = host->data->blocks * host->data->blksz;
969 int i;
970
971 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
972
973 if ((!host->caps.has_rwproof)
974 && (host->data->flags & MMC_DATA_READ)) {
975 if (host->caps.has_bad_data_ordering)
976 for (i = 0; i < transfer_size; i++)
977 host->buffer[i] = swab32(host->buffer[i]);
978 sg_copy_from_buffer(host->data->sg, host->data->sg_len,
979 host->buffer, transfer_size);
980 }
981
982 atmci_pdc_cleanup(host);
983
984 dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
985 atmci_set_pending(host, EVENT_XFER_COMPLETE);
986 tasklet_schedule(&host->tasklet);
987}
988
989static void atmci_dma_cleanup(struct atmel_mci *host)
990{
991 struct mmc_data *data = host->data;
992
993 if (data)
994 dma_unmap_sg(host->dma.chan->device->dev,
995 data->sg, data->sg_len,
996 mmc_get_dma_dir(data));
997}
998
999/*
1000 * This function is called by the DMA driver from tasklet context.
1001 */
1002static void atmci_dma_complete(void *arg)
1003{
1004 struct atmel_mci *host = arg;
1005 struct mmc_data *data = host->data;
1006
1007 dev_vdbg(&host->pdev->dev, "DMA complete\n");
1008
1009 if (host->caps.has_dma_conf_reg)
1010 /* Disable DMA hardware handshaking on MCI */
1011 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
1012
1013 atmci_dma_cleanup(host);
1014
1015 /*
1016 * If the card was removed, data will be NULL. No point trying
1017 * to send the stop command or waiting for NBUSY in this case.
1018 */
1019 if (data) {
1020 dev_dbg(&host->pdev->dev,
1021 "(%s) set pending xfer complete\n", __func__);
1022 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1023 tasklet_schedule(&host->tasklet);
1024
1025 /*
1026 * Regardless of what the documentation says, we have
1027 * to wait for NOTBUSY even after block read
1028 * operations.
1029 *
1030 * When the DMA transfer is complete, the controller
1031 * may still be reading the CRC from the card, i.e.
1032 * the data transfer is still in progress and we
1033 * haven't seen all the potential error bits yet.
1034 *
1035 * The interrupt handler will schedule a different
1036 * tasklet to finish things up when the data transfer
1037 * is completely done.
1038 *
1039 * We may not complete the mmc request here anyway
1040 * because the mmc layer may call back and cause us to
1041 * violate the "don't submit new operations from the
1042 * completion callback" rule of the dma engine
1043 * framework.
1044 */
1045 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1046 }
1047}
1048
1049/*
1050 * Returns a mask of interrupt flags to be enabled after the whole
1051 * request has been prepared.
1052 */
1053static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
1054{
1055 u32 iflags;
1056
1057 data->error = -EINPROGRESS;
1058
1059 host->sg = data->sg;
1060 host->sg_len = data->sg_len;
1061 host->data = data;
1062 host->data_chan = NULL;
1063
1064 iflags = ATMCI_DATA_ERROR_FLAGS;
1065
1066 /*
1067 * Errata: MMC data write operation with less than 12
1068 * bytes is impossible.
1069 *
1070 * Errata: MCI Transmit Data Register (TDR) FIFO
1071 * corruption when length is not multiple of 4.
1072 */
1073 if (data->blocks * data->blksz < 12
1074 || (data->blocks * data->blksz) & 3)
1075 host->need_reset = true;
1076
1077 host->pio_offset = 0;
1078 if (data->flags & MMC_DATA_READ)
1079 iflags |= ATMCI_RXRDY;
1080 else
1081 iflags |= ATMCI_TXRDY;
1082
1083 return iflags;
1084}
1085
1086/*
1087 * Set interrupt flags and set block length into the MCI mode register even
1088 * if this value is also accessible in the MCI block register. It seems to be
1089 * necessary before the High Speed MCI version. It also map sg and configure
1090 * PDC registers.
1091 */
1092static u32
1093atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1094{
1095 u32 iflags, tmp;
1096 int i;
1097
1098 data->error = -EINPROGRESS;
1099
1100 host->data = data;
1101 host->sg = data->sg;
1102 iflags = ATMCI_DATA_ERROR_FLAGS;
1103
1104 /* Enable pdc mode */
1105 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
1106
1107 if (data->flags & MMC_DATA_READ)
1108 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
1109 else
1110 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
1111
1112 /* Set BLKLEN */
1113 tmp = atmci_readl(host, ATMCI_MR);
1114 tmp &= 0x0000ffff;
1115 tmp |= ATMCI_BLKLEN(data->blksz);
1116 atmci_writel(host, ATMCI_MR, tmp);
1117
1118 /* Configure PDC */
1119 host->data_size = data->blocks * data->blksz;
1120 dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
1121 mmc_get_dma_dir(data));
1122
1123 if ((!host->caps.has_rwproof)
1124 && (host->data->flags & MMC_DATA_WRITE)) {
1125 sg_copy_to_buffer(host->data->sg, host->data->sg_len,
1126 host->buffer, host->data_size);
1127 if (host->caps.has_bad_data_ordering)
1128 for (i = 0; i < host->data_size; i++)
1129 host->buffer[i] = swab32(host->buffer[i]);
1130 }
1131
1132 if (host->data_size)
1133 atmci_pdc_set_both_buf(host, data->flags & MMC_DATA_READ ?
1134 XFER_RECEIVE : XFER_TRANSMIT);
1135 return iflags;
1136}
1137
1138static u32
1139atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
1140{
1141 struct dma_chan *chan;
1142 struct dma_async_tx_descriptor *desc;
1143 struct scatterlist *sg;
1144 unsigned int i;
1145 enum dma_transfer_direction slave_dirn;
1146 unsigned int sglen;
1147 u32 maxburst;
1148 u32 iflags;
1149
1150 data->error = -EINPROGRESS;
1151
1152 WARN_ON(host->data);
1153 host->sg = NULL;
1154 host->data = data;
1155
1156 iflags = ATMCI_DATA_ERROR_FLAGS;
1157
1158 /*
1159 * We don't do DMA on "complex" transfers, i.e. with
1160 * non-word-aligned buffers or lengths. Also, we don't bother
1161 * with all the DMA setup overhead for short transfers.
1162 */
1163 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1164 return atmci_prepare_data(host, data);
1165 if (data->blksz & 3)
1166 return atmci_prepare_data(host, data);
1167
1168 for_each_sg(data->sg, sg, data->sg_len, i) {
1169 if (sg->offset & 3 || sg->length & 3)
1170 return atmci_prepare_data(host, data);
1171 }
1172
1173 /* If we don't have a channel, we can't do DMA */
1174 if (!host->dma.chan)
1175 return -ENODEV;
1176
1177 chan = host->dma.chan;
1178 host->data_chan = chan;
1179
1180 if (data->flags & MMC_DATA_READ) {
1181 host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1182 maxburst = atmci_convert_chksize(host,
1183 host->dma_conf.src_maxburst);
1184 } else {
1185 host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1186 maxburst = atmci_convert_chksize(host,
1187 host->dma_conf.dst_maxburst);
1188 }
1189
1190 if (host->caps.has_dma_conf_reg)
1191 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1192 ATMCI_DMAEN);
1193
1194 sglen = dma_map_sg(chan->device->dev, data->sg,
1195 data->sg_len, mmc_get_dma_dir(data));
1196
1197 dmaengine_slave_config(chan, &host->dma_conf);
1198 desc = dmaengine_prep_slave_sg(chan,
1199 data->sg, sglen, slave_dirn,
1200 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1201 if (!desc)
1202 goto unmap_exit;
1203
1204 host->dma.data_desc = desc;
1205 desc->callback = atmci_dma_complete;
1206 desc->callback_param = host;
1207
1208 return iflags;
1209unmap_exit:
1210 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
1211 mmc_get_dma_dir(data));
1212 return -ENOMEM;
1213}
1214
1215static void
1216atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1217{
1218 return;
1219}
1220
1221/*
1222 * Start PDC according to transfer direction.
1223 */
1224static void
1225atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1226{
1227 if (data->flags & MMC_DATA_READ)
1228 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1229 else
1230 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1231}
1232
1233static void
1234atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
1235{
1236 struct dma_chan *chan = host->data_chan;
1237 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
1238
1239 if (chan) {
1240 dmaengine_submit(desc);
1241 dma_async_issue_pending(chan);
1242 }
1243}
1244
1245static void atmci_stop_transfer(struct atmel_mci *host)
1246{
1247 dev_dbg(&host->pdev->dev,
1248 "(%s) set pending xfer complete\n", __func__);
1249 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1250 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1251}
1252
1253/*
1254 * Stop data transfer because error(s) occurred.
1255 */
1256static void atmci_stop_transfer_pdc(struct atmel_mci *host)
1257{
1258 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1259}
1260
1261static void atmci_stop_transfer_dma(struct atmel_mci *host)
1262{
1263 struct dma_chan *chan = host->data_chan;
1264
1265 if (chan) {
1266 dmaengine_terminate_all(chan);
1267 atmci_dma_cleanup(host);
1268 } else {
1269 /* Data transfer was stopped by the interrupt handler */
1270 dev_dbg(&host->pdev->dev,
1271 "(%s) set pending xfer complete\n", __func__);
1272 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1273 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1274 }
1275}
1276
1277/*
1278 * Start a request: prepare data if needed, prepare the command and activate
1279 * interrupts.
1280 */
1281static void atmci_start_request(struct atmel_mci *host,
1282 struct atmel_mci_slot *slot)
1283{
1284 struct mmc_request *mrq;
1285 struct mmc_command *cmd;
1286 struct mmc_data *data;
1287 u32 iflags;
1288 u32 cmdflags;
1289
1290 mrq = slot->mrq;
1291 host->cur_slot = slot;
1292 host->mrq = mrq;
1293
1294 host->pending_events = 0;
1295 host->completed_events = 0;
1296 host->cmd_status = 0;
1297 host->data_status = 0;
1298
1299 dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
1300
1301 if (host->need_reset || host->caps.need_reset_after_xfer) {
1302 iflags = atmci_readl(host, ATMCI_IMR);
1303 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
1304 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1305 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1306 atmci_writel(host, ATMCI_MR, host->mode_reg);
1307 if (host->caps.has_cfg_reg)
1308 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1309 atmci_writel(host, ATMCI_IER, iflags);
1310 host->need_reset = false;
1311 }
1312 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
1313
1314 iflags = atmci_readl(host, ATMCI_IMR);
1315 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1316 dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1317 iflags);
1318
1319 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1320 /* Send init sequence (74 clock cycles) */
1321 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
1322 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1323 cpu_relax();
1324 }
1325 iflags = 0;
1326 data = mrq->data;
1327 if (data) {
1328 atmci_set_timeout(host, slot, data);
1329
1330 /* Must set block count/size before sending command */
1331 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1332 | ATMCI_BLKLEN(data->blksz));
1333 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1334 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1335
1336 iflags |= host->prepare_data(host, data);
1337 }
1338
1339 iflags |= ATMCI_CMDRDY;
1340 cmd = mrq->cmd;
1341 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1342
1343 /*
1344 * DMA transfer should be started before sending the command to avoid
1345 * unexpected errors especially for read operations in SDIO mode.
1346 * Unfortunately, in PDC mode, command has to be sent before starting
1347 * the transfer.
1348 */
1349 if (host->submit_data != &atmci_submit_data_dma)
1350 atmci_send_command(host, cmd, cmdflags);
1351
1352 if (data)
1353 host->submit_data(host, data);
1354
1355 if (host->submit_data == &atmci_submit_data_dma)
1356 atmci_send_command(host, cmd, cmdflags);
1357
1358 if (mrq->stop) {
1359 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1360 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1361 if (!(data->flags & MMC_DATA_WRITE))
1362 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1363 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1364 }
1365
1366 /*
1367 * We could have enabled interrupts earlier, but I suspect
1368 * that would open up a nice can of interesting race
1369 * conditions (e.g. command and data complete, but stop not
1370 * prepared yet.)
1371 */
1372 atmci_writel(host, ATMCI_IER, iflags);
1373}
1374
1375static void atmci_queue_request(struct atmel_mci *host,
1376 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1377{
1378 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1379 host->state);
1380
1381 spin_lock_bh(&host->lock);
1382 slot->mrq = mrq;
1383 if (host->state == STATE_IDLE) {
1384 host->state = STATE_SENDING_CMD;
1385 atmci_start_request(host, slot);
1386 } else {
1387 dev_dbg(&host->pdev->dev, "queue request\n");
1388 list_add_tail(&slot->queue_node, &host->queue);
1389 }
1390 spin_unlock_bh(&host->lock);
1391}
1392
1393static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1394{
1395 struct atmel_mci_slot *slot = mmc_priv(mmc);
1396 struct atmel_mci *host = slot->host;
1397 struct mmc_data *data;
1398
1399 WARN_ON(slot->mrq);
1400 dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1401
1402 /*
1403 * We may "know" the card is gone even though there's still an
1404 * electrical connection. If so, we really need to communicate
1405 * this to the MMC core since there won't be any more
1406 * interrupts as the card is completely removed. Otherwise,
1407 * the MMC core might believe the card is still there even
1408 * though the card was just removed very slowly.
1409 */
1410 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1411 mrq->cmd->error = -ENOMEDIUM;
1412 mmc_request_done(mmc, mrq);
1413 return;
1414 }
1415
1416 /* We don't support multiple blocks of weird lengths. */
1417 data = mrq->data;
1418 if (data && data->blocks > 1 && data->blksz & 3) {
1419 mrq->cmd->error = -EINVAL;
1420 mmc_request_done(mmc, mrq);
1421 }
1422
1423 atmci_queue_request(host, slot, mrq);
1424}
1425
1426static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1427{
1428 struct atmel_mci_slot *slot = mmc_priv(mmc);
1429 struct atmel_mci *host = slot->host;
1430 unsigned int i;
1431
1432 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1433 switch (ios->bus_width) {
1434 case MMC_BUS_WIDTH_1:
1435 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1436 break;
1437 case MMC_BUS_WIDTH_4:
1438 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1439 break;
1440 case MMC_BUS_WIDTH_8:
1441 slot->sdc_reg |= ATMCI_SDCBUS_8BIT;
1442 break;
1443 }
1444
1445 if (ios->clock) {
1446 unsigned int clock_min = ~0U;
1447 int clkdiv;
1448
1449 spin_lock_bh(&host->lock);
1450 if (!host->mode_reg) {
1451 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1452 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1453 if (host->caps.has_cfg_reg)
1454 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1455 }
1456
1457 /*
1458 * Use mirror of ios->clock to prevent race with mmc
1459 * core ios update when finding the minimum.
1460 */
1461 slot->clock = ios->clock;
1462 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1463 if (host->slot[i] && host->slot[i]->clock
1464 && host->slot[i]->clock < clock_min)
1465 clock_min = host->slot[i]->clock;
1466 }
1467
1468 /* Calculate clock divider */
1469 if (host->caps.has_odd_clk_div) {
1470 clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
1471 if (clkdiv < 0) {
1472 dev_warn(&mmc->class_dev,
1473 "clock %u too fast; using %lu\n",
1474 clock_min, host->bus_hz / 2);
1475 clkdiv = 0;
1476 } else if (clkdiv > 511) {
1477 dev_warn(&mmc->class_dev,
1478 "clock %u too slow; using %lu\n",
1479 clock_min, host->bus_hz / (511 + 2));
1480 clkdiv = 511;
1481 }
1482 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1483 | ATMCI_MR_CLKODD(clkdiv & 1);
1484 } else {
1485 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1486 if (clkdiv > 255) {
1487 dev_warn(&mmc->class_dev,
1488 "clock %u too slow; using %lu\n",
1489 clock_min, host->bus_hz / (2 * 256));
1490 clkdiv = 255;
1491 }
1492 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1493 }
1494
1495 /*
1496 * WRPROOF and RDPROOF prevent overruns/underruns by
1497 * stopping the clock when the FIFO is full/empty.
1498 * This state is not expected to last for long.
1499 */
1500 if (host->caps.has_rwproof)
1501 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1502
1503 if (host->caps.has_cfg_reg) {
1504 /* setup High Speed mode in relation with card capacity */
1505 if (ios->timing == MMC_TIMING_SD_HS)
1506 host->cfg_reg |= ATMCI_CFG_HSMODE;
1507 else
1508 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1509 }
1510
1511 if (list_empty(&host->queue)) {
1512 atmci_writel(host, ATMCI_MR, host->mode_reg);
1513 if (host->caps.has_cfg_reg)
1514 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1515 } else {
1516 host->need_clock_update = true;
1517 }
1518
1519 spin_unlock_bh(&host->lock);
1520 } else {
1521 bool any_slot_active = false;
1522
1523 spin_lock_bh(&host->lock);
1524 slot->clock = 0;
1525 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1526 if (host->slot[i] && host->slot[i]->clock) {
1527 any_slot_active = true;
1528 break;
1529 }
1530 }
1531 if (!any_slot_active) {
1532 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1533 if (host->mode_reg) {
1534 atmci_readl(host, ATMCI_MR);
1535 }
1536 host->mode_reg = 0;
1537 }
1538 spin_unlock_bh(&host->lock);
1539 }
1540
1541 switch (ios->power_mode) {
1542 case MMC_POWER_OFF:
1543 if (!IS_ERR(mmc->supply.vmmc))
1544 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1545 break;
1546 case MMC_POWER_UP:
1547 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1548 if (!IS_ERR(mmc->supply.vmmc))
1549 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1550 break;
1551 default:
1552 break;
1553 }
1554}
1555
1556static int atmci_get_ro(struct mmc_host *mmc)
1557{
1558 int read_only = -ENOSYS;
1559 struct atmel_mci_slot *slot = mmc_priv(mmc);
1560
1561 if (slot->wp_pin) {
1562 read_only = gpiod_get_value(slot->wp_pin);
1563 dev_dbg(&mmc->class_dev, "card is %s\n",
1564 read_only ? "read-only" : "read-write");
1565 }
1566
1567 return read_only;
1568}
1569
1570static int atmci_get_cd(struct mmc_host *mmc)
1571{
1572 int present = -ENOSYS;
1573 struct atmel_mci_slot *slot = mmc_priv(mmc);
1574
1575 if (slot->detect_pin) {
1576 present = gpiod_get_value_cansleep(slot->detect_pin);
1577 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1578 present ? "" : "not ");
1579 }
1580
1581 return present;
1582}
1583
1584static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1585{
1586 struct atmel_mci_slot *slot = mmc_priv(mmc);
1587 struct atmel_mci *host = slot->host;
1588
1589 if (enable)
1590 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1591 else
1592 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1593}
1594
1595static const struct mmc_host_ops atmci_ops = {
1596 .request = atmci_request,
1597 .set_ios = atmci_set_ios,
1598 .get_ro = atmci_get_ro,
1599 .get_cd = atmci_get_cd,
1600 .enable_sdio_irq = atmci_enable_sdio_irq,
1601};
1602
1603/* Called with host->lock held */
1604static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1605 __releases(&host->lock)
1606 __acquires(&host->lock)
1607{
1608 struct atmel_mci_slot *slot = NULL;
1609 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1610
1611 WARN_ON(host->cmd || host->data);
1612
1613 del_timer(&host->timer);
1614
1615 /*
1616 * Update the MMC clock rate if necessary. This may be
1617 * necessary if set_ios() is called when a different slot is
1618 * busy transferring data.
1619 */
1620 if (host->need_clock_update) {
1621 atmci_writel(host, ATMCI_MR, host->mode_reg);
1622 if (host->caps.has_cfg_reg)
1623 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1624 }
1625
1626 host->cur_slot->mrq = NULL;
1627 host->mrq = NULL;
1628 if (!list_empty(&host->queue)) {
1629 slot = list_entry(host->queue.next,
1630 struct atmel_mci_slot, queue_node);
1631 list_del(&slot->queue_node);
1632 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1633 mmc_hostname(slot->mmc));
1634 host->state = STATE_SENDING_CMD;
1635 atmci_start_request(host, slot);
1636 } else {
1637 dev_vdbg(&host->pdev->dev, "list empty\n");
1638 host->state = STATE_IDLE;
1639 }
1640
1641 spin_unlock(&host->lock);
1642 mmc_request_done(prev_mmc, mrq);
1643 spin_lock(&host->lock);
1644}
1645
1646static void atmci_command_complete(struct atmel_mci *host,
1647 struct mmc_command *cmd)
1648{
1649 u32 status = host->cmd_status;
1650
1651 /* Read the response from the card (up to 16 bytes) */
1652 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1653 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1654 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1655 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1656
1657 if (status & ATMCI_RTOE)
1658 cmd->error = -ETIMEDOUT;
1659 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1660 cmd->error = -EILSEQ;
1661 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1662 cmd->error = -EIO;
1663 else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
1664 if (host->caps.need_blksz_mul_4) {
1665 cmd->error = -EINVAL;
1666 host->need_reset = 1;
1667 }
1668 } else
1669 cmd->error = 0;
1670}
1671
1672static void atmci_detect_change(struct timer_list *t)
1673{
1674 struct atmel_mci_slot *slot = from_timer(slot, t, detect_timer);
1675 bool present;
1676 bool present_old;
1677
1678 /*
1679 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1680 * freeing the interrupt. We must not re-enable the interrupt
1681 * if it has been freed, and if we're shutting down, it
1682 * doesn't really matter whether the card is present or not.
1683 */
1684 smp_rmb();
1685 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1686 return;
1687
1688 enable_irq(gpiod_to_irq(slot->detect_pin));
1689 present = gpiod_get_value_cansleep(slot->detect_pin);
1690 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1691
1692 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1693 present, present_old);
1694
1695 if (present != present_old) {
1696 struct atmel_mci *host = slot->host;
1697 struct mmc_request *mrq;
1698
1699 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1700 present ? "inserted" : "removed");
1701
1702 spin_lock(&host->lock);
1703
1704 if (!present)
1705 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1706 else
1707 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1708
1709 /* Clean up queue if present */
1710 mrq = slot->mrq;
1711 if (mrq) {
1712 if (mrq == host->mrq) {
1713 /*
1714 * Reset controller to terminate any ongoing
1715 * commands or data transfers.
1716 */
1717 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1718 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1719 atmci_writel(host, ATMCI_MR, host->mode_reg);
1720 if (host->caps.has_cfg_reg)
1721 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1722
1723 host->data = NULL;
1724 host->cmd = NULL;
1725
1726 switch (host->state) {
1727 case STATE_IDLE:
1728 break;
1729 case STATE_SENDING_CMD:
1730 mrq->cmd->error = -ENOMEDIUM;
1731 if (mrq->data)
1732 host->stop_transfer(host);
1733 break;
1734 case STATE_DATA_XFER:
1735 mrq->data->error = -ENOMEDIUM;
1736 host->stop_transfer(host);
1737 break;
1738 case STATE_WAITING_NOTBUSY:
1739 mrq->data->error = -ENOMEDIUM;
1740 break;
1741 case STATE_SENDING_STOP:
1742 mrq->stop->error = -ENOMEDIUM;
1743 break;
1744 case STATE_END_REQUEST:
1745 break;
1746 }
1747
1748 atmci_request_end(host, mrq);
1749 } else {
1750 list_del(&slot->queue_node);
1751 mrq->cmd->error = -ENOMEDIUM;
1752 if (mrq->data)
1753 mrq->data->error = -ENOMEDIUM;
1754 if (mrq->stop)
1755 mrq->stop->error = -ENOMEDIUM;
1756
1757 spin_unlock(&host->lock);
1758 mmc_request_done(slot->mmc, mrq);
1759 spin_lock(&host->lock);
1760 }
1761 }
1762 spin_unlock(&host->lock);
1763
1764 mmc_detect_change(slot->mmc, 0);
1765 }
1766}
1767
1768static void atmci_tasklet_func(struct tasklet_struct *t)
1769{
1770 struct atmel_mci *host = from_tasklet(host, t, tasklet);
1771 struct mmc_request *mrq = host->mrq;
1772 struct mmc_data *data = host->data;
1773 enum atmel_mci_state state = host->state;
1774 enum atmel_mci_state prev_state;
1775 u32 status;
1776
1777 spin_lock(&host->lock);
1778
1779 state = host->state;
1780
1781 dev_vdbg(&host->pdev->dev,
1782 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1783 state, host->pending_events, host->completed_events,
1784 atmci_readl(host, ATMCI_IMR));
1785
1786 do {
1787 prev_state = state;
1788 dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1789
1790 switch (state) {
1791 case STATE_IDLE:
1792 break;
1793
1794 case STATE_SENDING_CMD:
1795 /*
1796 * Command has been sent, we are waiting for command
1797 * ready. Then we have three next states possible:
1798 * END_REQUEST by default, WAITING_NOTBUSY if it's a
1799 * command needing it or DATA_XFER if there is data.
1800 */
1801 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1802 if (!atmci_test_and_clear_pending(host,
1803 EVENT_CMD_RDY))
1804 break;
1805
1806 dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
1807 host->cmd = NULL;
1808 atmci_set_completed(host, EVENT_CMD_RDY);
1809 atmci_command_complete(host, mrq->cmd);
1810 if (mrq->data) {
1811 dev_dbg(&host->pdev->dev,
1812 "command with data transfer");
1813 /*
1814 * If there is a command error don't start
1815 * data transfer.
1816 */
1817 if (mrq->cmd->error) {
1818 host->stop_transfer(host);
1819 host->data = NULL;
1820 atmci_writel(host, ATMCI_IDR,
1821 ATMCI_TXRDY | ATMCI_RXRDY
1822 | ATMCI_DATA_ERROR_FLAGS);
1823 state = STATE_END_REQUEST;
1824 } else
1825 state = STATE_DATA_XFER;
1826 } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
1827 dev_dbg(&host->pdev->dev,
1828 "command response need waiting notbusy");
1829 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1830 state = STATE_WAITING_NOTBUSY;
1831 } else
1832 state = STATE_END_REQUEST;
1833
1834 break;
1835
1836 case STATE_DATA_XFER:
1837 if (atmci_test_and_clear_pending(host,
1838 EVENT_DATA_ERROR)) {
1839 dev_dbg(&host->pdev->dev, "set completed data error\n");
1840 atmci_set_completed(host, EVENT_DATA_ERROR);
1841 state = STATE_END_REQUEST;
1842 break;
1843 }
1844
1845 /*
1846 * A data transfer is in progress. The event expected
1847 * to move to the next state depends of data transfer
1848 * type (PDC or DMA). Once transfer done we can move
1849 * to the next step which is WAITING_NOTBUSY in write
1850 * case and directly SENDING_STOP in read case.
1851 */
1852 dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1853 if (!atmci_test_and_clear_pending(host,
1854 EVENT_XFER_COMPLETE))
1855 break;
1856
1857 dev_dbg(&host->pdev->dev,
1858 "(%s) set completed xfer complete\n",
1859 __func__);
1860 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1861
1862 if (host->caps.need_notbusy_for_read_ops ||
1863 (host->data->flags & MMC_DATA_WRITE)) {
1864 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1865 state = STATE_WAITING_NOTBUSY;
1866 } else if (host->mrq->stop) {
1867 atmci_send_stop_cmd(host, data);
1868 state = STATE_SENDING_STOP;
1869 } else {
1870 host->data = NULL;
1871 data->bytes_xfered = data->blocks * data->blksz;
1872 data->error = 0;
1873 state = STATE_END_REQUEST;
1874 }
1875 break;
1876
1877 case STATE_WAITING_NOTBUSY:
1878 /*
1879 * We can be in the state for two reasons: a command
1880 * requiring waiting not busy signal (stop command
1881 * included) or a write operation. In the latest case,
1882 * we need to send a stop command.
1883 */
1884 dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1885 if (!atmci_test_and_clear_pending(host,
1886 EVENT_NOTBUSY))
1887 break;
1888
1889 dev_dbg(&host->pdev->dev, "set completed not busy\n");
1890 atmci_set_completed(host, EVENT_NOTBUSY);
1891
1892 if (host->data) {
1893 /*
1894 * For some commands such as CMD53, even if
1895 * there is data transfer, there is no stop
1896 * command to send.
1897 */
1898 if (host->mrq->stop) {
1899 atmci_send_stop_cmd(host, data);
1900 state = STATE_SENDING_STOP;
1901 } else {
1902 host->data = NULL;
1903 data->bytes_xfered = data->blocks
1904 * data->blksz;
1905 data->error = 0;
1906 state = STATE_END_REQUEST;
1907 }
1908 } else
1909 state = STATE_END_REQUEST;
1910 break;
1911
1912 case STATE_SENDING_STOP:
1913 /*
1914 * In this state, it is important to set host->data to
1915 * NULL (which is tested in the waiting notbusy state)
1916 * in order to go to the end request state instead of
1917 * sending stop again.
1918 */
1919 dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1920 if (!atmci_test_and_clear_pending(host,
1921 EVENT_CMD_RDY))
1922 break;
1923
1924 dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1925 host->cmd = NULL;
1926 data->bytes_xfered = data->blocks * data->blksz;
1927 data->error = 0;
1928 atmci_command_complete(host, mrq->stop);
1929 if (mrq->stop->error) {
1930 host->stop_transfer(host);
1931 atmci_writel(host, ATMCI_IDR,
1932 ATMCI_TXRDY | ATMCI_RXRDY
1933 | ATMCI_DATA_ERROR_FLAGS);
1934 state = STATE_END_REQUEST;
1935 } else {
1936 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1937 state = STATE_WAITING_NOTBUSY;
1938 }
1939 host->data = NULL;
1940 break;
1941
1942 case STATE_END_REQUEST:
1943 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1944 | ATMCI_DATA_ERROR_FLAGS);
1945 status = host->data_status;
1946 if (unlikely(status)) {
1947 host->stop_transfer(host);
1948 host->data = NULL;
1949 if (data) {
1950 if (status & ATMCI_DTOE) {
1951 data->error = -ETIMEDOUT;
1952 } else if (status & ATMCI_DCRCE) {
1953 data->error = -EILSEQ;
1954 } else {
1955 data->error = -EIO;
1956 }
1957 }
1958 }
1959
1960 atmci_request_end(host, host->mrq);
1961 goto unlock; /* atmci_request_end() sets host->state */
1962 break;
1963 }
1964 } while (state != prev_state);
1965
1966 host->state = state;
1967
1968unlock:
1969 spin_unlock(&host->lock);
1970}
1971
1972static void atmci_read_data_pio(struct atmel_mci *host)
1973{
1974 struct scatterlist *sg = host->sg;
1975 unsigned int offset = host->pio_offset;
1976 struct mmc_data *data = host->data;
1977 u32 value;
1978 u32 status;
1979 unsigned int nbytes = 0;
1980
1981 do {
1982 value = atmci_readl(host, ATMCI_RDR);
1983 if (likely(offset + 4 <= sg->length)) {
1984 sg_pcopy_from_buffer(sg, 1, &value, sizeof(u32), offset);
1985
1986 offset += 4;
1987 nbytes += 4;
1988
1989 if (offset == sg->length) {
1990 flush_dcache_page(sg_page(sg));
1991 host->sg = sg = sg_next(sg);
1992 host->sg_len--;
1993 if (!sg || !host->sg_len)
1994 goto done;
1995
1996 offset = 0;
1997 }
1998 } else {
1999 unsigned int remaining = sg->length - offset;
2000
2001 sg_pcopy_from_buffer(sg, 1, &value, remaining, offset);
2002 nbytes += remaining;
2003
2004 flush_dcache_page(sg_page(sg));
2005 host->sg = sg = sg_next(sg);
2006 host->sg_len--;
2007 if (!sg || !host->sg_len)
2008 goto done;
2009
2010 offset = 4 - remaining;
2011 sg_pcopy_from_buffer(sg, 1, (u8 *)&value + remaining,
2012 offset, 0);
2013 nbytes += offset;
2014 }
2015
2016 status = atmci_readl(host, ATMCI_SR);
2017 if (status & ATMCI_DATA_ERROR_FLAGS) {
2018 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
2019 | ATMCI_DATA_ERROR_FLAGS));
2020 host->data_status = status;
2021 data->bytes_xfered += nbytes;
2022 return;
2023 }
2024 } while (status & ATMCI_RXRDY);
2025
2026 host->pio_offset = offset;
2027 data->bytes_xfered += nbytes;
2028
2029 return;
2030
2031done:
2032 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
2033 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2034 data->bytes_xfered += nbytes;
2035 smp_wmb();
2036 atmci_set_pending(host, EVENT_XFER_COMPLETE);
2037}
2038
2039static void atmci_write_data_pio(struct atmel_mci *host)
2040{
2041 struct scatterlist *sg = host->sg;
2042 unsigned int offset = host->pio_offset;
2043 struct mmc_data *data = host->data;
2044 u32 value;
2045 u32 status;
2046 unsigned int nbytes = 0;
2047
2048 do {
2049 if (likely(offset + 4 <= sg->length)) {
2050 sg_pcopy_to_buffer(sg, 1, &value, sizeof(u32), offset);
2051 atmci_writel(host, ATMCI_TDR, value);
2052
2053 offset += 4;
2054 nbytes += 4;
2055 if (offset == sg->length) {
2056 host->sg = sg = sg_next(sg);
2057 host->sg_len--;
2058 if (!sg || !host->sg_len)
2059 goto done;
2060
2061 offset = 0;
2062 }
2063 } else {
2064 unsigned int remaining = sg->length - offset;
2065
2066 value = 0;
2067 sg_pcopy_to_buffer(sg, 1, &value, remaining, offset);
2068 nbytes += remaining;
2069
2070 host->sg = sg = sg_next(sg);
2071 host->sg_len--;
2072 if (!sg || !host->sg_len) {
2073 atmci_writel(host, ATMCI_TDR, value);
2074 goto done;
2075 }
2076
2077 offset = 4 - remaining;
2078 sg_pcopy_to_buffer(sg, 1, (u8 *)&value + remaining,
2079 offset, 0);
2080 atmci_writel(host, ATMCI_TDR, value);
2081 nbytes += offset;
2082 }
2083
2084 status = atmci_readl(host, ATMCI_SR);
2085 if (status & ATMCI_DATA_ERROR_FLAGS) {
2086 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
2087 | ATMCI_DATA_ERROR_FLAGS));
2088 host->data_status = status;
2089 data->bytes_xfered += nbytes;
2090 return;
2091 }
2092 } while (status & ATMCI_TXRDY);
2093
2094 host->pio_offset = offset;
2095 data->bytes_xfered += nbytes;
2096
2097 return;
2098
2099done:
2100 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
2101 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
2102 data->bytes_xfered += nbytes;
2103 smp_wmb();
2104 atmci_set_pending(host, EVENT_XFER_COMPLETE);
2105}
2106
2107static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
2108{
2109 int i;
2110
2111 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2112 struct atmel_mci_slot *slot = host->slot[i];
2113 if (slot && (status & slot->sdio_irq)) {
2114 mmc_signal_sdio_irq(slot->mmc);
2115 }
2116 }
2117}
2118
2119
2120static irqreturn_t atmci_interrupt(int irq, void *dev_id)
2121{
2122 struct atmel_mci *host = dev_id;
2123 u32 status, mask, pending;
2124 unsigned int pass_count = 0;
2125
2126 do {
2127 status = atmci_readl(host, ATMCI_SR);
2128 mask = atmci_readl(host, ATMCI_IMR);
2129 pending = status & mask;
2130 if (!pending)
2131 break;
2132
2133 if (pending & ATMCI_DATA_ERROR_FLAGS) {
2134 dev_dbg(&host->pdev->dev, "IRQ: data error\n");
2135 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2136 | ATMCI_RXRDY | ATMCI_TXRDY
2137 | ATMCI_ENDRX | ATMCI_ENDTX
2138 | ATMCI_RXBUFF | ATMCI_TXBUFE);
2139
2140 host->data_status = status;
2141 dev_dbg(&host->pdev->dev, "set pending data error\n");
2142 smp_wmb();
2143 atmci_set_pending(host, EVENT_DATA_ERROR);
2144 tasklet_schedule(&host->tasklet);
2145 }
2146
2147 if (pending & ATMCI_TXBUFE) {
2148 dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2149 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
2150 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2151 /*
2152 * We can receive this interruption before having configured
2153 * the second pdc buffer, so we need to reconfigure first and
2154 * second buffers again
2155 */
2156 if (host->data_size) {
2157 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
2158 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2159 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2160 } else {
2161 atmci_pdc_complete(host);
2162 }
2163 } else if (pending & ATMCI_ENDTX) {
2164 dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
2165 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2166
2167 if (host->data_size) {
2168 atmci_pdc_set_single_buf(host,
2169 XFER_TRANSMIT, PDC_SECOND_BUF);
2170 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2171 }
2172 }
2173
2174 if (pending & ATMCI_RXBUFF) {
2175 dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
2176 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
2177 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2178 /*
2179 * We can receive this interruption before having configured
2180 * the second pdc buffer, so we need to reconfigure first and
2181 * second buffers again
2182 */
2183 if (host->data_size) {
2184 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
2185 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2186 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
2187 } else {
2188 atmci_pdc_complete(host);
2189 }
2190 } else if (pending & ATMCI_ENDRX) {
2191 dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2192 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2193
2194 if (host->data_size) {
2195 atmci_pdc_set_single_buf(host,
2196 XFER_RECEIVE, PDC_SECOND_BUF);
2197 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2198 }
2199 }
2200
2201 /*
2202 * First mci IPs, so mainly the ones having pdc, have some
2203 * issues with the notbusy signal. You can't get it after
2204 * data transmission if you have not sent a stop command.
2205 * The appropriate workaround is to use the BLKE signal.
2206 */
2207 if (pending & ATMCI_BLKE) {
2208 dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2209 atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2210 smp_wmb();
2211 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2212 atmci_set_pending(host, EVENT_NOTBUSY);
2213 tasklet_schedule(&host->tasklet);
2214 }
2215
2216 if (pending & ATMCI_NOTBUSY) {
2217 dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2218 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2219 smp_wmb();
2220 dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2221 atmci_set_pending(host, EVENT_NOTBUSY);
2222 tasklet_schedule(&host->tasklet);
2223 }
2224
2225 if (pending & ATMCI_RXRDY)
2226 atmci_read_data_pio(host);
2227 if (pending & ATMCI_TXRDY)
2228 atmci_write_data_pio(host);
2229
2230 if (pending & ATMCI_CMDRDY) {
2231 dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2232 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2233 host->cmd_status = status;
2234 smp_wmb();
2235 dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2236 atmci_set_pending(host, EVENT_CMD_RDY);
2237 tasklet_schedule(&host->tasklet);
2238 }
2239
2240 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
2241 atmci_sdio_interrupt(host, status);
2242
2243 } while (pass_count++ < 5);
2244
2245 return pass_count ? IRQ_HANDLED : IRQ_NONE;
2246}
2247
2248static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
2249{
2250 struct atmel_mci_slot *slot = dev_id;
2251
2252 /*
2253 * Disable interrupts until the pin has stabilized and check
2254 * the state then. Use mod_timer() since we may be in the
2255 * middle of the timer routine when this interrupt triggers.
2256 */
2257 disable_irq_nosync(irq);
2258 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
2259
2260 return IRQ_HANDLED;
2261}
2262
2263static int atmci_init_slot(struct atmel_mci *host,
2264 struct mci_slot_pdata *slot_data, unsigned int id,
2265 u32 sdc_reg, u32 sdio_irq)
2266{
2267 struct mmc_host *mmc;
2268 struct atmel_mci_slot *slot;
2269 int ret;
2270
2271 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2272 if (!mmc)
2273 return -ENOMEM;
2274
2275 slot = mmc_priv(mmc);
2276 slot->mmc = mmc;
2277 slot->host = host;
2278 slot->detect_pin = slot_data->detect_pin;
2279 slot->wp_pin = slot_data->wp_pin;
2280 slot->sdc_reg = sdc_reg;
2281 slot->sdio_irq = sdio_irq;
2282
2283 dev_dbg(&mmc->class_dev,
2284 "slot[%u]: bus_width=%u, detect_pin=%d, "
2285 "detect_is_active_high=%s, wp_pin=%d\n",
2286 id, slot_data->bus_width, desc_to_gpio(slot_data->detect_pin),
2287 !gpiod_is_active_low(slot_data->detect_pin) ? "true" : "false",
2288 desc_to_gpio(slot_data->wp_pin));
2289
2290 mmc->ops = &atmci_ops;
2291 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2292 mmc->f_max = host->bus_hz / 2;
2293 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2294 if (sdio_irq)
2295 mmc->caps |= MMC_CAP_SDIO_IRQ;
2296 if (host->caps.has_highspeed)
2297 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
2298 /*
2299 * Without the read/write proof capability, it is strongly suggested to
2300 * use only one bit for data to prevent fifo underruns and overruns
2301 * which will corrupt data.
2302 */
2303 if ((slot_data->bus_width >= 4) && host->caps.has_rwproof) {
2304 mmc->caps |= MMC_CAP_4_BIT_DATA;
2305 if (slot_data->bus_width >= 8)
2306 mmc->caps |= MMC_CAP_8_BIT_DATA;
2307 }
2308
2309 if (atmci_get_version(host) < 0x200) {
2310 mmc->max_segs = 256;
2311 mmc->max_blk_size = 4095;
2312 mmc->max_blk_count = 256;
2313 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2314 mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
2315 } else {
2316 mmc->max_segs = 64;
2317 mmc->max_req_size = 32768 * 512;
2318 mmc->max_blk_size = 32768;
2319 mmc->max_blk_count = 512;
2320 }
2321
2322 /* Assume card is present initially */
2323 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2324 if (slot->detect_pin) {
2325 if (!gpiod_get_value_cansleep(slot->detect_pin))
2326 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2327 } else {
2328 dev_dbg(&mmc->class_dev, "no detect pin available\n");
2329 }
2330
2331 if (!slot->detect_pin) {
2332 if (slot_data->non_removable)
2333 mmc->caps |= MMC_CAP_NONREMOVABLE;
2334 else
2335 mmc->caps |= MMC_CAP_NEEDS_POLL;
2336 }
2337
2338 if (!slot->wp_pin)
2339 dev_dbg(&mmc->class_dev, "no WP pin available\n");
2340
2341 host->slot[id] = slot;
2342 mmc_regulator_get_supply(mmc);
2343 ret = mmc_add_host(mmc);
2344 if (ret) {
2345 mmc_free_host(mmc);
2346 return ret;
2347 }
2348
2349 if (slot->detect_pin) {
2350 timer_setup(&slot->detect_timer, atmci_detect_change, 0);
2351
2352 ret = request_irq(gpiod_to_irq(slot->detect_pin),
2353 atmci_detect_interrupt,
2354 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2355 "mmc-detect", slot);
2356 if (ret) {
2357 dev_dbg(&mmc->class_dev,
2358 "could not request IRQ %d for detect pin\n",
2359 gpiod_to_irq(slot->detect_pin));
2360 slot->detect_pin = NULL;
2361 }
2362 }
2363
2364 atmci_init_debugfs(slot);
2365
2366 return 0;
2367}
2368
2369static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
2370 unsigned int id)
2371{
2372 /* Debugfs stuff is cleaned up by mmc core */
2373
2374 set_bit(ATMCI_SHUTDOWN, &slot->flags);
2375 smp_wmb();
2376
2377 mmc_remove_host(slot->mmc);
2378
2379 if (slot->detect_pin) {
2380 free_irq(gpiod_to_irq(slot->detect_pin), slot);
2381 del_timer_sync(&slot->detect_timer);
2382 }
2383
2384 slot->host->slot[id] = NULL;
2385 mmc_free_host(slot->mmc);
2386}
2387
2388static int atmci_configure_dma(struct atmel_mci *host)
2389{
2390 host->dma.chan = dma_request_chan(&host->pdev->dev, "rxtx");
2391
2392 if (PTR_ERR(host->dma.chan) == -ENODEV) {
2393 struct mci_platform_data *pdata = host->pdev->dev.platform_data;
2394 dma_cap_mask_t mask;
2395
2396 if (!pdata || !pdata->dma_filter)
2397 return -ENODEV;
2398
2399 dma_cap_zero(mask);
2400 dma_cap_set(DMA_SLAVE, mask);
2401
2402 host->dma.chan = dma_request_channel(mask, pdata->dma_filter,
2403 pdata->dma_slave);
2404 if (!host->dma.chan)
2405 host->dma.chan = ERR_PTR(-ENODEV);
2406 }
2407
2408 if (IS_ERR(host->dma.chan))
2409 return PTR_ERR(host->dma.chan);
2410
2411 dev_info(&host->pdev->dev, "using %s for DMA transfers\n",
2412 dma_chan_name(host->dma.chan));
2413
2414 host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2415 host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2416 host->dma_conf.src_maxburst = 1;
2417 host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2418 host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2419 host->dma_conf.dst_maxburst = 1;
2420 host->dma_conf.device_fc = false;
2421
2422 return 0;
2423}
2424
2425/*
2426 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2427 * HSMCI provides DMA support and a new config register but no more supports
2428 * PDC.
2429 */
2430static void atmci_get_cap(struct atmel_mci *host)
2431{
2432 unsigned int version;
2433
2434 version = atmci_get_version(host);
2435 dev_info(&host->pdev->dev,
2436 "version: 0x%x\n", version);
2437
2438 host->caps.has_dma_conf_reg = false;
2439 host->caps.has_pdc = true;
2440 host->caps.has_cfg_reg = false;
2441 host->caps.has_cstor_reg = false;
2442 host->caps.has_highspeed = false;
2443 host->caps.has_rwproof = false;
2444 host->caps.has_odd_clk_div = false;
2445 host->caps.has_bad_data_ordering = true;
2446 host->caps.need_reset_after_xfer = true;
2447 host->caps.need_blksz_mul_4 = true;
2448 host->caps.need_notbusy_for_read_ops = false;
2449
2450 /* keep only major version number */
2451 switch (version & 0xf00) {
2452 case 0x600:
2453 case 0x500:
2454 host->caps.has_odd_clk_div = true;
2455 fallthrough;
2456 case 0x400:
2457 case 0x300:
2458 host->caps.has_dma_conf_reg = true;
2459 host->caps.has_pdc = false;
2460 host->caps.has_cfg_reg = true;
2461 host->caps.has_cstor_reg = true;
2462 host->caps.has_highspeed = true;
2463 fallthrough;
2464 case 0x200:
2465 host->caps.has_rwproof = true;
2466 host->caps.need_blksz_mul_4 = false;
2467 host->caps.need_notbusy_for_read_ops = true;
2468 fallthrough;
2469 case 0x100:
2470 host->caps.has_bad_data_ordering = false;
2471 host->caps.need_reset_after_xfer = false;
2472 fallthrough;
2473 case 0x0:
2474 break;
2475 default:
2476 host->caps.has_pdc = false;
2477 dev_warn(&host->pdev->dev,
2478 "Unmanaged mci version, set minimum capabilities\n");
2479 break;
2480 }
2481}
2482
2483static int atmci_probe(struct platform_device *pdev)
2484{
2485 struct mci_platform_data *pdata;
2486 struct atmel_mci *host;
2487 struct resource *regs;
2488 unsigned int nr_slots;
2489 int irq;
2490 int ret, i;
2491
2492 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2493 if (!regs)
2494 return -ENXIO;
2495 pdata = pdev->dev.platform_data;
2496 if (!pdata) {
2497 pdata = atmci_of_init(pdev);
2498 if (IS_ERR(pdata)) {
2499 dev_err(&pdev->dev, "platform data not available\n");
2500 return PTR_ERR(pdata);
2501 }
2502 }
2503
2504 irq = platform_get_irq(pdev, 0);
2505 if (irq < 0)
2506 return irq;
2507
2508 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2509 if (!host)
2510 return -ENOMEM;
2511
2512 host->pdev = pdev;
2513 spin_lock_init(&host->lock);
2514 INIT_LIST_HEAD(&host->queue);
2515
2516 host->mck = devm_clk_get(&pdev->dev, "mci_clk");
2517 if (IS_ERR(host->mck))
2518 return PTR_ERR(host->mck);
2519
2520 host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
2521 if (!host->regs)
2522 return -ENOMEM;
2523
2524 ret = clk_prepare_enable(host->mck);
2525 if (ret)
2526 return ret;
2527
2528 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2529 host->bus_hz = clk_get_rate(host->mck);
2530
2531 host->mapbase = regs->start;
2532
2533 tasklet_setup(&host->tasklet, atmci_tasklet_func);
2534
2535 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2536 if (ret) {
2537 clk_disable_unprepare(host->mck);
2538 return ret;
2539 }
2540
2541 /* Get MCI capabilities and set operations according to it */
2542 atmci_get_cap(host);
2543 ret = atmci_configure_dma(host);
2544 if (ret == -EPROBE_DEFER)
2545 goto err_dma_probe_defer;
2546 if (ret == 0) {
2547 host->prepare_data = &atmci_prepare_data_dma;
2548 host->submit_data = &atmci_submit_data_dma;
2549 host->stop_transfer = &atmci_stop_transfer_dma;
2550 } else if (host->caps.has_pdc) {
2551 dev_info(&pdev->dev, "using PDC\n");
2552 host->prepare_data = &atmci_prepare_data_pdc;
2553 host->submit_data = &atmci_submit_data_pdc;
2554 host->stop_transfer = &atmci_stop_transfer_pdc;
2555 } else {
2556 dev_info(&pdev->dev, "using PIO\n");
2557 host->prepare_data = &atmci_prepare_data;
2558 host->submit_data = &atmci_submit_data;
2559 host->stop_transfer = &atmci_stop_transfer;
2560 }
2561
2562 platform_set_drvdata(pdev, host);
2563
2564 timer_setup(&host->timer, atmci_timeout_timer, 0);
2565
2566 pm_runtime_get_noresume(&pdev->dev);
2567 pm_runtime_set_active(&pdev->dev);
2568 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY);
2569 pm_runtime_use_autosuspend(&pdev->dev);
2570 pm_runtime_enable(&pdev->dev);
2571
2572 /* We need at least one slot to succeed */
2573 nr_slots = 0;
2574 ret = -ENODEV;
2575 if (pdata->slot[0].bus_width) {
2576 ret = atmci_init_slot(host, &pdata->slot[0],
2577 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2578 if (!ret) {
2579 nr_slots++;
2580 host->buf_size = host->slot[0]->mmc->max_req_size;
2581 }
2582 }
2583 if (pdata->slot[1].bus_width) {
2584 ret = atmci_init_slot(host, &pdata->slot[1],
2585 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2586 if (!ret) {
2587 nr_slots++;
2588 if (host->slot[1]->mmc->max_req_size > host->buf_size)
2589 host->buf_size =
2590 host->slot[1]->mmc->max_req_size;
2591 }
2592 }
2593
2594 if (!nr_slots) {
2595 dev_err(&pdev->dev, "init failed: no slot defined\n");
2596 goto err_init_slot;
2597 }
2598
2599 if (!host->caps.has_rwproof) {
2600 host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
2601 &host->buf_phys_addr,
2602 GFP_KERNEL);
2603 if (!host->buffer) {
2604 ret = -ENOMEM;
2605 dev_err(&pdev->dev, "buffer allocation failed\n");
2606 goto err_dma_alloc;
2607 }
2608 }
2609
2610 dev_info(&pdev->dev,
2611 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2612 host->mapbase, irq, nr_slots);
2613
2614 pm_runtime_mark_last_busy(&host->pdev->dev);
2615 pm_runtime_put_autosuspend(&pdev->dev);
2616
2617 return 0;
2618
2619err_dma_alloc:
2620 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2621 if (host->slot[i])
2622 atmci_cleanup_slot(host->slot[i], i);
2623 }
2624err_init_slot:
2625 clk_disable_unprepare(host->mck);
2626
2627 pm_runtime_disable(&pdev->dev);
2628 pm_runtime_put_noidle(&pdev->dev);
2629
2630 del_timer_sync(&host->timer);
2631 if (!IS_ERR(host->dma.chan))
2632 dma_release_channel(host->dma.chan);
2633err_dma_probe_defer:
2634 free_irq(irq, host);
2635 return ret;
2636}
2637
2638static void atmci_remove(struct platform_device *pdev)
2639{
2640 struct atmel_mci *host = platform_get_drvdata(pdev);
2641 unsigned int i;
2642
2643 pm_runtime_get_sync(&pdev->dev);
2644
2645 if (host->buffer)
2646 dma_free_coherent(&pdev->dev, host->buf_size,
2647 host->buffer, host->buf_phys_addr);
2648
2649 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2650 if (host->slot[i])
2651 atmci_cleanup_slot(host->slot[i], i);
2652 }
2653
2654 atmci_writel(host, ATMCI_IDR, ~0UL);
2655 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2656 atmci_readl(host, ATMCI_SR);
2657
2658 del_timer_sync(&host->timer);
2659 if (!IS_ERR(host->dma.chan))
2660 dma_release_channel(host->dma.chan);
2661
2662 free_irq(platform_get_irq(pdev, 0), host);
2663
2664 clk_disable_unprepare(host->mck);
2665
2666 pm_runtime_disable(&pdev->dev);
2667 pm_runtime_put_noidle(&pdev->dev);
2668}
2669
2670#ifdef CONFIG_PM
2671static int atmci_runtime_suspend(struct device *dev)
2672{
2673 struct atmel_mci *host = dev_get_drvdata(dev);
2674
2675 clk_disable_unprepare(host->mck);
2676
2677 pinctrl_pm_select_sleep_state(dev);
2678
2679 return 0;
2680}
2681
2682static int atmci_runtime_resume(struct device *dev)
2683{
2684 struct atmel_mci *host = dev_get_drvdata(dev);
2685
2686 pinctrl_select_default_state(dev);
2687
2688 return clk_prepare_enable(host->mck);
2689}
2690#endif
2691
2692static const struct dev_pm_ops atmci_dev_pm_ops = {
2693 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2694 pm_runtime_force_resume)
2695 SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL)
2696};
2697
2698static struct platform_driver atmci_driver = {
2699 .probe = atmci_probe,
2700 .remove_new = atmci_remove,
2701 .driver = {
2702 .name = "atmel_mci",
2703 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2704 .of_match_table = of_match_ptr(atmci_dt_ids),
2705 .pm = &atmci_dev_pm_ops,
2706 },
2707};
2708module_platform_driver(atmci_driver);
2709
2710MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2711MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2712MODULE_LICENSE("GPL v2");