Loading...
1/*
2 * GPIO controller in LSI ZEVIO SoCs.
3 *
4 * Author: Fabian Vogt <fabian@ritter-vogt.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/spinlock.h>
12#include <linux/errno.h>
13#include <linux/module.h>
14#include <linux/bitops.h>
15#include <linux/io.h>
16#include <linux/of_device.h>
17#include <linux/of_gpio.h>
18#include <linux/slab.h>
19#include <linux/gpio.h>
20
21/*
22 * Memory layout:
23 * This chip has four gpio sections, each controls 8 GPIOs.
24 * Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10.
25 * Disclaimer: Reverse engineered!
26 * For more information refer to:
27 * http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#90000000_-_General_Purpose_I.2FO_.28GPIO.29
28 *
29 * 0x00-0x3F: Section 0
30 * +0x00: Masked interrupt status (read-only)
31 * +0x04: R: Interrupt status W: Reset interrupt status
32 * +0x08: R: Interrupt mask W: Mask interrupt
33 * +0x0C: W: Unmask interrupt (write-only)
34 * +0x10: Direction: I/O=1/0
35 * +0x14: Output
36 * +0x18: Input (read-only)
37 * +0x20: R: Level interrupt W: Set as level interrupt
38 * 0x40-0x7F: Section 1
39 * 0x80-0xBF: Section 2
40 * 0xC0-0xFF: Section 3
41 */
42
43#define ZEVIO_GPIO_SECTION_SIZE 0x40
44
45/* Offsets to various registers */
46#define ZEVIO_GPIO_INT_MASKED_STATUS 0x00
47#define ZEVIO_GPIO_INT_STATUS 0x04
48#define ZEVIO_GPIO_INT_UNMASK 0x08
49#define ZEVIO_GPIO_INT_MASK 0x0C
50#define ZEVIO_GPIO_DIRECTION 0x10
51#define ZEVIO_GPIO_OUTPUT 0x14
52#define ZEVIO_GPIO_INPUT 0x18
53#define ZEVIO_GPIO_INT_STICKY 0x20
54
55#define to_zevio_gpio(chip) container_of(to_of_mm_gpio_chip(chip), \
56 struct zevio_gpio, chip)
57
58/* Bit number of GPIO in its section */
59#define ZEVIO_GPIO_BIT(gpio) (gpio&7)
60
61struct zevio_gpio {
62 spinlock_t lock;
63 struct of_mm_gpio_chip chip;
64};
65
66static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin,
67 unsigned port_offset)
68{
69 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
70 return readl(IOMEM(c->chip.regs + section_offset + port_offset));
71}
72
73static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin,
74 unsigned port_offset, u32 val)
75{
76 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
77 writel(val, IOMEM(c->chip.regs + section_offset + port_offset));
78}
79
80/* Functions for struct gpio_chip */
81static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin)
82{
83 struct zevio_gpio *controller = to_zevio_gpio(chip);
84
85 /* Only reading allowed, so no spinlock needed */
86 u32 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT);
87
88 return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1;
89}
90
91static void zevio_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
92{
93 struct zevio_gpio *controller = to_zevio_gpio(chip);
94 u32 val;
95
96 spin_lock(&controller->lock);
97 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
98 if (value)
99 val |= BIT(ZEVIO_GPIO_BIT(pin));
100 else
101 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
102
103 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
104 spin_unlock(&controller->lock);
105}
106
107static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
108{
109 struct zevio_gpio *controller = to_zevio_gpio(chip);
110 u32 val;
111
112 spin_lock(&controller->lock);
113
114 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
115 val |= BIT(ZEVIO_GPIO_BIT(pin));
116 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
117
118 spin_unlock(&controller->lock);
119
120 return 0;
121}
122
123static int zevio_gpio_direction_output(struct gpio_chip *chip,
124 unsigned pin, int value)
125{
126 struct zevio_gpio *controller = to_zevio_gpio(chip);
127 u32 val;
128
129 spin_lock(&controller->lock);
130 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
131 if (value)
132 val |= BIT(ZEVIO_GPIO_BIT(pin));
133 else
134 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
135
136 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
137 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
138 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
139 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
140
141 spin_unlock(&controller->lock);
142
143 return 0;
144}
145
146static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
147{
148 /*
149 * TODO: Implement IRQs.
150 * Not implemented yet due to weird lockups
151 */
152
153 return -ENXIO;
154}
155
156static struct gpio_chip zevio_gpio_chip = {
157 .direction_input = zevio_gpio_direction_input,
158 .direction_output = zevio_gpio_direction_output,
159 .set = zevio_gpio_set,
160 .get = zevio_gpio_get,
161 .to_irq = zevio_gpio_to_irq,
162 .base = 0,
163 .owner = THIS_MODULE,
164 .ngpio = 32,
165 .of_gpio_n_cells = 2,
166};
167
168/* Initialization */
169static int zevio_gpio_probe(struct platform_device *pdev)
170{
171 struct zevio_gpio *controller;
172 int status, i;
173
174 controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL);
175 if (!controller) {
176 dev_err(&pdev->dev, "not enough free memory\n");
177 return -ENOMEM;
178 }
179
180 /* Copy our reference */
181 controller->chip.gc = zevio_gpio_chip;
182 controller->chip.gc.dev = &pdev->dev;
183
184 status = of_mm_gpiochip_add(pdev->dev.of_node, &(controller->chip));
185 if (status) {
186 dev_err(&pdev->dev, "failed to add gpiochip: %d\n", status);
187 return status;
188 }
189
190 spin_lock_init(&controller->lock);
191
192 /* Disable interrupts, they only cause errors */
193 for (i = 0; i < controller->chip.gc.ngpio; i += 8)
194 zevio_gpio_port_set(controller, i, ZEVIO_GPIO_INT_MASK, 0xFF);
195
196 dev_dbg(controller->chip.gc.dev, "ZEVIO GPIO controller set up!\n");
197
198 return 0;
199}
200
201static struct of_device_id zevio_gpio_of_match[] = {
202 { .compatible = "lsi,zevio-gpio", },
203 { },
204};
205
206MODULE_DEVICE_TABLE(of, zevio_gpio_of_match);
207
208static struct platform_driver zevio_gpio_driver = {
209 .driver = {
210 .name = "gpio-zevio",
211 .owner = THIS_MODULE,
212 .of_match_table = of_match_ptr(zevio_gpio_of_match),
213 },
214 .probe = zevio_gpio_probe,
215};
216module_platform_driver(zevio_gpio_driver);
217
218MODULE_LICENSE("GPL");
219MODULE_AUTHOR("Fabian Vogt <fabian@ritter-vogt.de>");
220MODULE_DESCRIPTION("LSI ZEVIO SoC GPIO driver");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO controller in LSI ZEVIO SoCs.
4 *
5 * Author: Fabian Vogt <fabian@ritter-vogt.de>
6 */
7
8#include <linux/bitops.h>
9#include <linux/errno.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/mod_devicetable.h>
13#include <linux/platform_device.h>
14#include <linux/slab.h>
15#include <linux/spinlock.h>
16
17#include <linux/gpio/driver.h>
18
19/*
20 * Memory layout:
21 * This chip has four gpio sections, each controls 8 GPIOs.
22 * Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10.
23 * Disclaimer: Reverse engineered!
24 * For more information refer to:
25 * http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#90000000_-_General_Purpose_I.2FO_.28GPIO.29
26 *
27 * 0x00-0x3F: Section 0
28 * +0x00: Masked interrupt status (read-only)
29 * +0x04: R: Interrupt status W: Reset interrupt status
30 * +0x08: R: Interrupt mask W: Mask interrupt
31 * +0x0C: W: Unmask interrupt (write-only)
32 * +0x10: Direction: I/O=1/0
33 * +0x14: Output
34 * +0x18: Input (read-only)
35 * +0x20: R: Level interrupt W: Set as level interrupt
36 * 0x40-0x7F: Section 1
37 * 0x80-0xBF: Section 2
38 * 0xC0-0xFF: Section 3
39 */
40
41#define ZEVIO_GPIO_SECTION_SIZE 0x40
42
43/* Offsets to various registers */
44#define ZEVIO_GPIO_INT_MASKED_STATUS 0x00
45#define ZEVIO_GPIO_INT_STATUS 0x04
46#define ZEVIO_GPIO_INT_UNMASK 0x08
47#define ZEVIO_GPIO_INT_MASK 0x0C
48#define ZEVIO_GPIO_DIRECTION 0x10
49#define ZEVIO_GPIO_OUTPUT 0x14
50#define ZEVIO_GPIO_INPUT 0x18
51#define ZEVIO_GPIO_INT_STICKY 0x20
52
53/* Bit number of GPIO in its section */
54#define ZEVIO_GPIO_BIT(gpio) (gpio&7)
55
56struct zevio_gpio {
57 struct gpio_chip chip;
58 spinlock_t lock;
59 void __iomem *regs;
60};
61
62static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin,
63 unsigned port_offset)
64{
65 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
66 return readl(IOMEM(c->regs + section_offset + port_offset));
67}
68
69static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin,
70 unsigned port_offset, u32 val)
71{
72 unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
73 writel(val, IOMEM(c->regs + section_offset + port_offset));
74}
75
76/* Functions for struct gpio_chip */
77static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin)
78{
79 struct zevio_gpio *controller = gpiochip_get_data(chip);
80 u32 val, dir;
81
82 spin_lock(&controller->lock);
83 dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
84 if (dir & BIT(ZEVIO_GPIO_BIT(pin)))
85 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT);
86 else
87 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
88 spin_unlock(&controller->lock);
89
90 return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1;
91}
92
93static void zevio_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
94{
95 struct zevio_gpio *controller = gpiochip_get_data(chip);
96 u32 val;
97
98 spin_lock(&controller->lock);
99 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
100 if (value)
101 val |= BIT(ZEVIO_GPIO_BIT(pin));
102 else
103 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
104
105 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
106 spin_unlock(&controller->lock);
107}
108
109static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
110{
111 struct zevio_gpio *controller = gpiochip_get_data(chip);
112 u32 val;
113
114 spin_lock(&controller->lock);
115
116 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
117 val |= BIT(ZEVIO_GPIO_BIT(pin));
118 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
119
120 spin_unlock(&controller->lock);
121
122 return 0;
123}
124
125static int zevio_gpio_direction_output(struct gpio_chip *chip,
126 unsigned pin, int value)
127{
128 struct zevio_gpio *controller = gpiochip_get_data(chip);
129 u32 val;
130
131 spin_lock(&controller->lock);
132 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
133 if (value)
134 val |= BIT(ZEVIO_GPIO_BIT(pin));
135 else
136 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
137
138 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
139 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
140 val &= ~BIT(ZEVIO_GPIO_BIT(pin));
141 zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
142
143 spin_unlock(&controller->lock);
144
145 return 0;
146}
147
148static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
149{
150 /*
151 * TODO: Implement IRQs.
152 * Not implemented yet due to weird lockups
153 */
154
155 return -ENXIO;
156}
157
158static const struct gpio_chip zevio_gpio_chip = {
159 .direction_input = zevio_gpio_direction_input,
160 .direction_output = zevio_gpio_direction_output,
161 .set = zevio_gpio_set,
162 .get = zevio_gpio_get,
163 .to_irq = zevio_gpio_to_irq,
164 .base = 0,
165 .owner = THIS_MODULE,
166 .ngpio = 32,
167};
168
169/* Initialization */
170static int zevio_gpio_probe(struct platform_device *pdev)
171{
172 struct zevio_gpio *controller;
173 int status, i;
174
175 controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL);
176 if (!controller)
177 return -ENOMEM;
178
179 /* Copy our reference */
180 controller->chip = zevio_gpio_chip;
181 controller->chip.parent = &pdev->dev;
182
183 controller->regs = devm_platform_ioremap_resource(pdev, 0);
184 if (IS_ERR(controller->regs))
185 return dev_err_probe(&pdev->dev, PTR_ERR(controller->regs),
186 "failed to ioremap memory resource\n");
187
188 status = devm_gpiochip_add_data(&pdev->dev, &controller->chip, controller);
189 if (status) {
190 dev_err(&pdev->dev, "failed to add gpiochip: %d\n", status);
191 return status;
192 }
193
194 spin_lock_init(&controller->lock);
195
196 /* Disable interrupts, they only cause errors */
197 for (i = 0; i < controller->chip.ngpio; i += 8)
198 zevio_gpio_port_set(controller, i, ZEVIO_GPIO_INT_MASK, 0xFF);
199
200 dev_dbg(controller->chip.parent, "ZEVIO GPIO controller set up!\n");
201
202 return 0;
203}
204
205static const struct of_device_id zevio_gpio_of_match[] = {
206 { .compatible = "lsi,zevio-gpio", },
207 { },
208};
209
210static struct platform_driver zevio_gpio_driver = {
211 .driver = {
212 .name = "gpio-zevio",
213 .of_match_table = zevio_gpio_of_match,
214 .suppress_bind_attrs = true,
215 },
216 .probe = zevio_gpio_probe,
217};
218builtin_platform_driver(zevio_gpio_driver);