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1/*
2 * SH7269 Setup
3 *
4 * Copyright (C) 2012 Renesas Electronics Europe Ltd
5 * Copyright (C) 2012 Phil Edworthy
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/serial.h>
14#include <linux/serial_sci.h>
15#include <linux/usb/r8a66597.h>
16#include <linux/sh_timer.h>
17#include <linux/io.h>
18
19enum {
20 UNUSED = 0,
21
22 /* interrupt sources */
23 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
24 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
25
26 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
27 DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
28 USB, VDC4, CMT0, CMT1, BSC, WDT,
29 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
30 MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
31 PWMT1, PWMT2, ADC_ADI,
32 SSIF0, SSII1, SSII2, SSII3, SSII4, SSII5,
33 RSPDIF,
34 IIC30, IIC31, IIC32, IIC33,
35 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
36 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
37 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
38 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
39 SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
40 SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
41 SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
42 SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
43 RCAN0, RCAN1, RCAN2,
44 RSPIC0, RSPIC1,
45 IEBC, CD_ROMD,
46 NFMC,
47 SDHI0, SDHI1,
48 RTC,
49 SRCC0, SRCC1, SRCC2,
50
51 /* interrupt groups */
52 PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
53};
54
55static struct intc_vect vectors[] __initdata = {
56 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
57 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
58 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
59 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
60
61 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
62 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
63 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
64 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
65
66 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
67 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
68 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
69 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
70 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
71 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
72 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
73 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
74 INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
75 INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
76 INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
77 INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
78 INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
79 INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
80 INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
81 INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
82
83 INTC_IRQ(USB, 170),
84
85 INTC_IRQ(VDC4, 171), INTC_IRQ(VDC4, 172),
86 INTC_IRQ(VDC4, 173), INTC_IRQ(VDC4, 174),
87 INTC_IRQ(VDC4, 175), INTC_IRQ(VDC4, 176),
88 INTC_IRQ(VDC4, 177), INTC_IRQ(VDC4, 177),
89
90 INTC_IRQ(CMT0, 188), INTC_IRQ(CMT1, 189),
91
92 INTC_IRQ(BSC, 190), INTC_IRQ(WDT, 191),
93
94 INTC_IRQ(MTU0_ABCD, 192), INTC_IRQ(MTU0_ABCD, 193),
95 INTC_IRQ(MTU0_ABCD, 194), INTC_IRQ(MTU0_ABCD, 195),
96 INTC_IRQ(MTU0_VEF, 196), INTC_IRQ(MTU0_VEF, 197),
97 INTC_IRQ(MTU0_VEF, 198),
98 INTC_IRQ(MTU1_AB, 199), INTC_IRQ(MTU1_AB, 200),
99 INTC_IRQ(MTU1_VU, 201), INTC_IRQ(MTU1_VU, 202),
100 INTC_IRQ(MTU2_AB, 203), INTC_IRQ(MTU2_AB, 204),
101 INTC_IRQ(MTU2_VU, 205), INTC_IRQ(MTU2_VU, 206),
102 INTC_IRQ(MTU3_ABCD, 207), INTC_IRQ(MTU3_ABCD, 208),
103 INTC_IRQ(MTU3_ABCD, 209), INTC_IRQ(MTU3_ABCD, 210),
104 INTC_IRQ(MTU3_TCI3V, 211),
105 INTC_IRQ(MTU4_ABCD, 212), INTC_IRQ(MTU4_ABCD, 213),
106 INTC_IRQ(MTU4_ABCD, 214), INTC_IRQ(MTU4_ABCD, 215),
107 INTC_IRQ(MTU4_TCI4V, 216),
108
109 INTC_IRQ(PWMT1, 217), INTC_IRQ(PWMT2, 218),
110
111 INTC_IRQ(ADC_ADI, 223),
112
113 INTC_IRQ(SSIF0, 224), INTC_IRQ(SSIF0, 225),
114 INTC_IRQ(SSIF0, 226),
115 INTC_IRQ(SSII1, 227), INTC_IRQ(SSII1, 228),
116 INTC_IRQ(SSII2, 229), INTC_IRQ(SSII2, 230),
117 INTC_IRQ(SSII3, 231), INTC_IRQ(SSII3, 232),
118 INTC_IRQ(SSII4, 233), INTC_IRQ(SSII4, 234),
119 INTC_IRQ(SSII5, 235), INTC_IRQ(SSII5, 236),
120
121 INTC_IRQ(RSPDIF, 237),
122
123 INTC_IRQ(IIC30, 238), INTC_IRQ(IIC30, 239),
124 INTC_IRQ(IIC30, 240), INTC_IRQ(IIC30, 241),
125 INTC_IRQ(IIC30, 242),
126 INTC_IRQ(IIC31, 243), INTC_IRQ(IIC31, 244),
127 INTC_IRQ(IIC31, 245), INTC_IRQ(IIC31, 246),
128 INTC_IRQ(IIC31, 247),
129 INTC_IRQ(IIC32, 248), INTC_IRQ(IIC32, 249),
130 INTC_IRQ(IIC32, 250), INTC_IRQ(IIC32, 251),
131 INTC_IRQ(IIC32, 252),
132 INTC_IRQ(IIC33, 253), INTC_IRQ(IIC33, 254),
133 INTC_IRQ(IIC33, 255), INTC_IRQ(IIC33, 256),
134 INTC_IRQ(IIC33, 257),
135
136 INTC_IRQ(SCIF0_BRI, 258), INTC_IRQ(SCIF0_ERI, 259),
137 INTC_IRQ(SCIF0_RXI, 260), INTC_IRQ(SCIF0_TXI, 261),
138 INTC_IRQ(SCIF1_BRI, 262), INTC_IRQ(SCIF1_ERI, 263),
139 INTC_IRQ(SCIF1_RXI, 264), INTC_IRQ(SCIF1_TXI, 265),
140 INTC_IRQ(SCIF2_BRI, 266), INTC_IRQ(SCIF2_ERI, 267),
141 INTC_IRQ(SCIF2_RXI, 268), INTC_IRQ(SCIF2_TXI, 269),
142 INTC_IRQ(SCIF3_BRI, 270), INTC_IRQ(SCIF3_ERI, 271),
143 INTC_IRQ(SCIF3_RXI, 272), INTC_IRQ(SCIF3_TXI, 273),
144 INTC_IRQ(SCIF4_BRI, 274), INTC_IRQ(SCIF4_ERI, 275),
145 INTC_IRQ(SCIF4_RXI, 276), INTC_IRQ(SCIF4_TXI, 277),
146 INTC_IRQ(SCIF5_BRI, 278), INTC_IRQ(SCIF5_ERI, 279),
147 INTC_IRQ(SCIF5_RXI, 280), INTC_IRQ(SCIF5_TXI, 281),
148 INTC_IRQ(SCIF6_BRI, 282), INTC_IRQ(SCIF6_ERI, 283),
149 INTC_IRQ(SCIF6_RXI, 284), INTC_IRQ(SCIF6_TXI, 285),
150 INTC_IRQ(SCIF7_BRI, 286), INTC_IRQ(SCIF7_ERI, 287),
151 INTC_IRQ(SCIF7_RXI, 288), INTC_IRQ(SCIF7_TXI, 289),
152
153 INTC_IRQ(RCAN0, 291), INTC_IRQ(RCAN0, 292),
154 INTC_IRQ(RCAN0, 293), INTC_IRQ(RCAN0, 294),
155 INTC_IRQ(RCAN0, 295),
156 INTC_IRQ(RCAN1, 296), INTC_IRQ(RCAN1, 297),
157 INTC_IRQ(RCAN1, 298), INTC_IRQ(RCAN1, 299),
158 INTC_IRQ(RCAN1, 300),
159 INTC_IRQ(RCAN2, 301), INTC_IRQ(RCAN2, 302),
160 INTC_IRQ(RCAN2, 303), INTC_IRQ(RCAN2, 304),
161 INTC_IRQ(RCAN2, 305),
162
163 INTC_IRQ(RSPIC0, 306), INTC_IRQ(RSPIC0, 307),
164 INTC_IRQ(RSPIC0, 308),
165 INTC_IRQ(RSPIC1, 309), INTC_IRQ(RSPIC1, 310),
166 INTC_IRQ(RSPIC1, 311),
167
168 INTC_IRQ(IEBC, 318),
169
170 INTC_IRQ(CD_ROMD, 319), INTC_IRQ(CD_ROMD, 320),
171 INTC_IRQ(CD_ROMD, 321), INTC_IRQ(CD_ROMD, 322),
172 INTC_IRQ(CD_ROMD, 323), INTC_IRQ(CD_ROMD, 324),
173
174 INTC_IRQ(NFMC, 325), INTC_IRQ(NFMC, 326),
175 INTC_IRQ(NFMC, 327), INTC_IRQ(NFMC, 328),
176
177 INTC_IRQ(SDHI0, 332), INTC_IRQ(SDHI0, 333),
178 INTC_IRQ(SDHI0, 334),
179 INTC_IRQ(SDHI1, 335), INTC_IRQ(SDHI1, 336),
180 INTC_IRQ(SDHI1, 337),
181
182 INTC_IRQ(RTC, 338), INTC_IRQ(RTC, 339),
183 INTC_IRQ(RTC, 340),
184
185 INTC_IRQ(SRCC0, 341), INTC_IRQ(SRCC0, 342),
186 INTC_IRQ(SRCC0, 343), INTC_IRQ(SRCC0, 344),
187 INTC_IRQ(SRCC0, 345),
188 INTC_IRQ(SRCC1, 346), INTC_IRQ(SRCC1, 347),
189 INTC_IRQ(SRCC1, 348), INTC_IRQ(SRCC1, 349),
190 INTC_IRQ(SRCC1, 350),
191 INTC_IRQ(SRCC2, 351), INTC_IRQ(SRCC2, 352),
192 INTC_IRQ(SRCC2, 353), INTC_IRQ(SRCC2, 354),
193 INTC_IRQ(SRCC2, 355),
194};
195
196static struct intc_group groups[] __initdata = {
197 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
198 PINT4, PINT5, PINT6, PINT7),
199 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
200 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
201 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
202 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
203 INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
204 INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
205 INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
206 INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
207};
208
209static struct intc_prio_reg prio_registers[] __initdata = {
210 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
211 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
212 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
213 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
214 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
215 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9,
216 DMAC10, DMAC11 } },
217 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
218 DMAC14, DMAC15 } },
219 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC4, VDC4, VDC4 } },
220 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { 0, 0, 0, 0 } },
221 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { CMT0, CMT1, BSC, WDT } },
222 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU0_ABCD, MTU0_VEF,
223 MTU1_AB, MTU1_VU } },
224 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { MTU2_AB, MTU2_VU,
225 MTU3_ABCD, MTU3_TCI3V } },
226 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { MTU4_ABCD, MTU4_TCI4V,
227 PWMT1, PWMT2 } },
228 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { 0, 0, 0, 0 } },
229 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { ADC_ADI, SSIF0, SSII1, SSII2 } },
230 { 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SSII3, SSII4, SSII5, RSPDIF} },
231 { 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { IIC30, IIC31, IIC32, IIC33 } },
232 { 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
233 { 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
234 { 0xfffe0c20, 0, 16, 4, /* IPR22 */ { 0, RCAN0, RCAN1, RCAN2 } },
235 { 0xfffe0c22, 0, 16, 4, /* IPR23 */ { RSPIC0, RSPIC1, 0, 0 } },
236 { 0xfffe0c24, 0, 16, 4, /* IPR24 */ { IEBC, CD_ROMD, NFMC, 0 } },
237 { 0xfffe0c26, 0, 16, 4, /* IPR25 */ { SDHI0, SDHI1, RTC, 0 } },
238 { 0xfffe0c28, 0, 16, 4, /* IPR26 */ { SRCC0, SRCC1, SRCC2, 0 } },
239};
240
241static struct intc_mask_reg mask_registers[] __initdata = {
242 { 0xfffe0808, 0, 16, /* PINTER */
243 { 0, 0, 0, 0, 0, 0, 0, 0,
244 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
245};
246
247static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups,
248 mask_registers, prio_registers, NULL);
249
250static struct plat_sci_port scif0_platform_data = {
251 .flags = UPF_BOOT_AUTOCONF,
252 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
253 SCSCR_REIE | SCSCR_TOIE,
254 .type = PORT_SCIF,
255 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
256};
257
258static struct resource scif0_resources[] = {
259 DEFINE_RES_MEM(0xe8007000, 0x100),
260 DEFINE_RES_IRQ(259),
261 DEFINE_RES_IRQ(260),
262 DEFINE_RES_IRQ(261),
263 DEFINE_RES_IRQ(258),
264};
265
266static struct platform_device scif0_device = {
267 .name = "sh-sci",
268 .id = 0,
269 .resource = scif0_resources,
270 .num_resources = ARRAY_SIZE(scif0_resources),
271 .dev = {
272 .platform_data = &scif0_platform_data,
273 },
274};
275
276static struct plat_sci_port scif1_platform_data = {
277 .flags = UPF_BOOT_AUTOCONF,
278 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
279 SCSCR_REIE | SCSCR_TOIE,
280 .type = PORT_SCIF,
281 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
282};
283
284static struct resource scif1_resources[] = {
285 DEFINE_RES_MEM(0xe8007800, 0x100),
286 DEFINE_RES_IRQ(263),
287 DEFINE_RES_IRQ(264),
288 DEFINE_RES_IRQ(265),
289 DEFINE_RES_IRQ(262),
290};
291
292static struct platform_device scif1_device = {
293 .name = "sh-sci",
294 .id = 1,
295 .resource = scif1_resources,
296 .num_resources = ARRAY_SIZE(scif1_resources),
297 .dev = {
298 .platform_data = &scif1_platform_data,
299 },
300};
301
302static struct plat_sci_port scif2_platform_data = {
303 .flags = UPF_BOOT_AUTOCONF,
304 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
305 SCSCR_REIE | SCSCR_TOIE,
306 .type = PORT_SCIF,
307 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
308};
309
310static struct resource scif2_resources[] = {
311 DEFINE_RES_MEM(0xe8008000, 0x100),
312 DEFINE_RES_IRQ(267),
313 DEFINE_RES_IRQ(268),
314 DEFINE_RES_IRQ(269),
315 DEFINE_RES_IRQ(266),
316};
317
318static struct platform_device scif2_device = {
319 .name = "sh-sci",
320 .id = 2,
321 .resource = scif2_resources,
322 .num_resources = ARRAY_SIZE(scif2_resources),
323 .dev = {
324 .platform_data = &scif2_platform_data,
325 },
326};
327
328static struct plat_sci_port scif3_platform_data = {
329 .flags = UPF_BOOT_AUTOCONF,
330 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
331 SCSCR_REIE | SCSCR_TOIE,
332 .type = PORT_SCIF,
333 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
334};
335
336static struct resource scif3_resources[] = {
337 DEFINE_RES_MEM(0xe8008800, 0x100),
338 DEFINE_RES_IRQ(271),
339 DEFINE_RES_IRQ(272),
340 DEFINE_RES_IRQ(273),
341 DEFINE_RES_IRQ(270),
342};
343
344static struct platform_device scif3_device = {
345 .name = "sh-sci",
346 .id = 3,
347 .resource = scif3_resources,
348 .num_resources = ARRAY_SIZE(scif3_resources),
349 .dev = {
350 .platform_data = &scif3_platform_data,
351 },
352};
353
354static struct plat_sci_port scif4_platform_data = {
355 .flags = UPF_BOOT_AUTOCONF,
356 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
357 SCSCR_REIE | SCSCR_TOIE,
358 .type = PORT_SCIF,
359 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
360};
361
362static struct resource scif4_resources[] = {
363 DEFINE_RES_MEM(0xe8009000, 0x100),
364 DEFINE_RES_IRQ(275),
365 DEFINE_RES_IRQ(276),
366 DEFINE_RES_IRQ(277),
367 DEFINE_RES_IRQ(274),
368};
369
370static struct platform_device scif4_device = {
371 .name = "sh-sci",
372 .id = 4,
373 .resource = scif4_resources,
374 .num_resources = ARRAY_SIZE(scif4_resources),
375 .dev = {
376 .platform_data = &scif4_platform_data,
377 },
378};
379
380static struct plat_sci_port scif5_platform_data = {
381 .flags = UPF_BOOT_AUTOCONF,
382 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
383 SCSCR_REIE | SCSCR_TOIE,
384 .type = PORT_SCIF,
385 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
386};
387
388static struct resource scif5_resources[] = {
389 DEFINE_RES_MEM(0xe8009800, 0x100),
390 DEFINE_RES_IRQ(279),
391 DEFINE_RES_IRQ(280),
392 DEFINE_RES_IRQ(281),
393 DEFINE_RES_IRQ(278),
394};
395
396static struct platform_device scif5_device = {
397 .name = "sh-sci",
398 .id = 5,
399 .resource = scif5_resources,
400 .num_resources = ARRAY_SIZE(scif5_resources),
401 .dev = {
402 .platform_data = &scif5_platform_data,
403 },
404};
405
406static struct plat_sci_port scif6_platform_data = {
407 .flags = UPF_BOOT_AUTOCONF,
408 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
409 SCSCR_REIE | SCSCR_TOIE,
410 .type = PORT_SCIF,
411 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
412};
413
414static struct resource scif6_resources[] = {
415 DEFINE_RES_MEM(0xe800a000, 0x100),
416 DEFINE_RES_IRQ(283),
417 DEFINE_RES_IRQ(284),
418 DEFINE_RES_IRQ(285),
419 DEFINE_RES_IRQ(282),
420};
421
422static struct platform_device scif6_device = {
423 .name = "sh-sci",
424 .id = 6,
425 .resource = scif6_resources,
426 .num_resources = ARRAY_SIZE(scif6_resources),
427 .dev = {
428 .platform_data = &scif6_platform_data,
429 },
430};
431
432static struct plat_sci_port scif7_platform_data = {
433 .flags = UPF_BOOT_AUTOCONF,
434 .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
435 SCSCR_REIE | SCSCR_TOIE,
436 .type = PORT_SCIF,
437 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
438};
439
440static struct resource scif7_resources[] = {
441 DEFINE_RES_MEM(0xe800a800, 0x100),
442 DEFINE_RES_IRQ(287),
443 DEFINE_RES_IRQ(288),
444 DEFINE_RES_IRQ(289),
445 DEFINE_RES_IRQ(286),
446};
447
448static struct platform_device scif7_device = {
449 .name = "sh-sci",
450 .id = 7,
451 .resource = scif7_resources,
452 .num_resources = ARRAY_SIZE(scif7_resources),
453 .dev = {
454 .platform_data = &scif7_platform_data,
455 },
456};
457
458static struct sh_timer_config cmt0_platform_data = {
459 .channel_offset = 0x02,
460 .timer_bit = 0,
461 .clockevent_rating = 125,
462 .clocksource_rating = 0, /* disabled due to code generation issues */
463};
464
465static struct resource cmt0_resources[] = {
466 [0] = {
467 .start = 0xfffec002,
468 .end = 0xfffec007,
469 .flags = IORESOURCE_MEM,
470 },
471 [1] = {
472 .start = 188,
473 .flags = IORESOURCE_IRQ,
474 },
475};
476
477static struct platform_device cmt0_device = {
478 .name = "sh_cmt",
479 .id = 0,
480 .dev = {
481 .platform_data = &cmt0_platform_data,
482 },
483 .resource = cmt0_resources,
484 .num_resources = ARRAY_SIZE(cmt0_resources),
485};
486
487static struct sh_timer_config cmt1_platform_data = {
488 .channel_offset = 0x08,
489 .timer_bit = 1,
490 .clockevent_rating = 125,
491 .clocksource_rating = 0, /* disabled due to code generation issues */
492};
493
494static struct resource cmt1_resources[] = {
495 [0] = {
496 .start = 0xfffec008,
497 .end = 0xfffec00d,
498 .flags = IORESOURCE_MEM,
499 },
500 [1] = {
501 .start = 189,
502 .flags = IORESOURCE_IRQ,
503 },
504};
505
506static struct platform_device cmt1_device = {
507 .name = "sh_cmt",
508 .id = 1,
509 .dev = {
510 .platform_data = &cmt1_platform_data,
511 },
512 .resource = cmt1_resources,
513 .num_resources = ARRAY_SIZE(cmt1_resources),
514};
515
516static struct sh_timer_config mtu2_0_platform_data = {
517 .channel_offset = -0x80,
518 .timer_bit = 0,
519 .clockevent_rating = 200,
520};
521
522static struct resource mtu2_0_resources[] = {
523 [0] = {
524 .start = 0xfffe4300,
525 .end = 0xfffe4326,
526 .flags = IORESOURCE_MEM,
527 },
528 [1] = {
529 .start = 192,
530 .flags = IORESOURCE_IRQ,
531 },
532};
533
534static struct platform_device mtu2_0_device = {
535 .name = "sh_mtu2",
536 .id = 0,
537 .dev = {
538 .platform_data = &mtu2_0_platform_data,
539 },
540 .resource = mtu2_0_resources,
541 .num_resources = ARRAY_SIZE(mtu2_0_resources),
542};
543
544static struct sh_timer_config mtu2_1_platform_data = {
545 .channel_offset = -0x100,
546 .timer_bit = 1,
547 .clockevent_rating = 200,
548};
549
550static struct resource mtu2_1_resources[] = {
551 [0] = {
552 .start = 0xfffe4380,
553 .end = 0xfffe4390,
554 .flags = IORESOURCE_MEM,
555 },
556 [1] = {
557 .start = 203,
558 .flags = IORESOURCE_IRQ,
559 },
560};
561
562static struct platform_device mtu2_1_device = {
563 .name = "sh_mtu2",
564 .id = 1,
565 .dev = {
566 .platform_data = &mtu2_1_platform_data,
567 },
568 .resource = mtu2_1_resources,
569 .num_resources = ARRAY_SIZE(mtu2_1_resources),
570};
571
572static struct resource rtc_resources[] = {
573 [0] = {
574 .start = 0xfffe6000,
575 .end = 0xfffe6000 + 0x30 - 1,
576 .flags = IORESOURCE_IO,
577 },
578 [1] = {
579 /* Shared Period/Carry/Alarm IRQ */
580 .start = 338,
581 .flags = IORESOURCE_IRQ,
582 },
583};
584
585static struct platform_device rtc_device = {
586 .name = "sh-rtc",
587 .id = -1,
588 .num_resources = ARRAY_SIZE(rtc_resources),
589 .resource = rtc_resources,
590};
591
592/* USB Host */
593static struct r8a66597_platdata r8a66597_data = {
594 .on_chip = 1,
595 .endian = 1,
596};
597
598static struct resource r8a66597_usb_host_resources[] = {
599 [0] = {
600 .start = 0xe8010000,
601 .end = 0xe80100e4,
602 .flags = IORESOURCE_MEM,
603 },
604 [1] = {
605 .start = 170,
606 .end = 170,
607 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
608 },
609};
610
611static struct platform_device r8a66597_usb_host_device = {
612 .name = "r8a66597_hcd",
613 .id = 0,
614 .dev = {
615 .dma_mask = NULL, /* not use dma */
616 .coherent_dma_mask = 0xffffffff,
617 .platform_data = &r8a66597_data,
618 },
619 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
620 .resource = r8a66597_usb_host_resources,
621};
622
623static struct platform_device *sh7269_devices[] __initdata = {
624 &scif0_device,
625 &scif1_device,
626 &scif2_device,
627 &scif3_device,
628 &scif4_device,
629 &scif5_device,
630 &scif6_device,
631 &scif7_device,
632 &cmt0_device,
633 &cmt1_device,
634 &mtu2_0_device,
635 &mtu2_1_device,
636 &rtc_device,
637 &r8a66597_usb_host_device,
638};
639
640static int __init sh7269_devices_setup(void)
641{
642 return platform_add_devices(sh7269_devices,
643 ARRAY_SIZE(sh7269_devices));
644}
645arch_initcall(sh7269_devices_setup);
646
647void __init plat_irq_setup(void)
648{
649 register_intc_controller(&intc_desc);
650}
651
652static struct platform_device *sh7269_early_devices[] __initdata = {
653 &scif0_device,
654 &scif1_device,
655 &scif2_device,
656 &scif3_device,
657 &scif4_device,
658 &scif5_device,
659 &scif6_device,
660 &scif7_device,
661 &cmt0_device,
662 &cmt1_device,
663 &mtu2_0_device,
664 &mtu2_1_device,
665};
666
667void __init plat_early_device_setup(void)
668{
669 early_platform_add_devices(sh7269_early_devices,
670 ARRAY_SIZE(sh7269_early_devices));
671}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SH7269 Setup
4 *
5 * Copyright (C) 2012 Renesas Electronics Europe Ltd
6 * Copyright (C) 2012 Phil Edworthy
7 */
8#include <linux/platform_device.h>
9#include <linux/init.h>
10#include <linux/serial.h>
11#include <linux/serial_sci.h>
12#include <linux/usb/r8a66597.h>
13#include <linux/sh_timer.h>
14#include <linux/io.h>
15#include <asm/platform_early.h>
16
17enum {
18 UNUSED = 0,
19
20 /* interrupt sources */
21 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
22 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
23
24 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
25 DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
26 USB, VDC4, CMT0, CMT1, BSC, WDT,
27 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
28 MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
29 PWMT1, PWMT2, ADC_ADI,
30 SSIF0, SSII1, SSII2, SSII3, SSII4, SSII5,
31 RSPDIF,
32 IIC30, IIC31, IIC32, IIC33,
33 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
34 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
35 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
36 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
37 SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
38 SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
39 SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
40 SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
41 RCAN0, RCAN1, RCAN2,
42 RSPIC0, RSPIC1,
43 IEBC, CD_ROMD,
44 NFMC,
45 SDHI0, SDHI1,
46 RTC,
47 SRCC0, SRCC1, SRCC2,
48
49 /* interrupt groups */
50 PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
51};
52
53static struct intc_vect vectors[] __initdata = {
54 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
55 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
56 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
57 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
58
59 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
60 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
61 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
62 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
63
64 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
65 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
66 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
67 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
68 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
69 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
70 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
71 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
72 INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
73 INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
74 INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
75 INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
76 INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
77 INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
78 INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
79 INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
80
81 INTC_IRQ(USB, 170),
82
83 INTC_IRQ(VDC4, 171), INTC_IRQ(VDC4, 172),
84 INTC_IRQ(VDC4, 173), INTC_IRQ(VDC4, 174),
85 INTC_IRQ(VDC4, 175), INTC_IRQ(VDC4, 176),
86 INTC_IRQ(VDC4, 177), INTC_IRQ(VDC4, 177),
87
88 INTC_IRQ(CMT0, 188), INTC_IRQ(CMT1, 189),
89
90 INTC_IRQ(BSC, 190), INTC_IRQ(WDT, 191),
91
92 INTC_IRQ(MTU0_ABCD, 192), INTC_IRQ(MTU0_ABCD, 193),
93 INTC_IRQ(MTU0_ABCD, 194), INTC_IRQ(MTU0_ABCD, 195),
94 INTC_IRQ(MTU0_VEF, 196), INTC_IRQ(MTU0_VEF, 197),
95 INTC_IRQ(MTU0_VEF, 198),
96 INTC_IRQ(MTU1_AB, 199), INTC_IRQ(MTU1_AB, 200),
97 INTC_IRQ(MTU1_VU, 201), INTC_IRQ(MTU1_VU, 202),
98 INTC_IRQ(MTU2_AB, 203), INTC_IRQ(MTU2_AB, 204),
99 INTC_IRQ(MTU2_VU, 205), INTC_IRQ(MTU2_VU, 206),
100 INTC_IRQ(MTU3_ABCD, 207), INTC_IRQ(MTU3_ABCD, 208),
101 INTC_IRQ(MTU3_ABCD, 209), INTC_IRQ(MTU3_ABCD, 210),
102 INTC_IRQ(MTU3_TCI3V, 211),
103 INTC_IRQ(MTU4_ABCD, 212), INTC_IRQ(MTU4_ABCD, 213),
104 INTC_IRQ(MTU4_ABCD, 214), INTC_IRQ(MTU4_ABCD, 215),
105 INTC_IRQ(MTU4_TCI4V, 216),
106
107 INTC_IRQ(PWMT1, 217), INTC_IRQ(PWMT2, 218),
108
109 INTC_IRQ(ADC_ADI, 223),
110
111 INTC_IRQ(SSIF0, 224), INTC_IRQ(SSIF0, 225),
112 INTC_IRQ(SSIF0, 226),
113 INTC_IRQ(SSII1, 227), INTC_IRQ(SSII1, 228),
114 INTC_IRQ(SSII2, 229), INTC_IRQ(SSII2, 230),
115 INTC_IRQ(SSII3, 231), INTC_IRQ(SSII3, 232),
116 INTC_IRQ(SSII4, 233), INTC_IRQ(SSII4, 234),
117 INTC_IRQ(SSII5, 235), INTC_IRQ(SSII5, 236),
118
119 INTC_IRQ(RSPDIF, 237),
120
121 INTC_IRQ(IIC30, 238), INTC_IRQ(IIC30, 239),
122 INTC_IRQ(IIC30, 240), INTC_IRQ(IIC30, 241),
123 INTC_IRQ(IIC30, 242),
124 INTC_IRQ(IIC31, 243), INTC_IRQ(IIC31, 244),
125 INTC_IRQ(IIC31, 245), INTC_IRQ(IIC31, 246),
126 INTC_IRQ(IIC31, 247),
127 INTC_IRQ(IIC32, 248), INTC_IRQ(IIC32, 249),
128 INTC_IRQ(IIC32, 250), INTC_IRQ(IIC32, 251),
129 INTC_IRQ(IIC32, 252),
130 INTC_IRQ(IIC33, 253), INTC_IRQ(IIC33, 254),
131 INTC_IRQ(IIC33, 255), INTC_IRQ(IIC33, 256),
132 INTC_IRQ(IIC33, 257),
133
134 INTC_IRQ(SCIF0_BRI, 258), INTC_IRQ(SCIF0_ERI, 259),
135 INTC_IRQ(SCIF0_RXI, 260), INTC_IRQ(SCIF0_TXI, 261),
136 INTC_IRQ(SCIF1_BRI, 262), INTC_IRQ(SCIF1_ERI, 263),
137 INTC_IRQ(SCIF1_RXI, 264), INTC_IRQ(SCIF1_TXI, 265),
138 INTC_IRQ(SCIF2_BRI, 266), INTC_IRQ(SCIF2_ERI, 267),
139 INTC_IRQ(SCIF2_RXI, 268), INTC_IRQ(SCIF2_TXI, 269),
140 INTC_IRQ(SCIF3_BRI, 270), INTC_IRQ(SCIF3_ERI, 271),
141 INTC_IRQ(SCIF3_RXI, 272), INTC_IRQ(SCIF3_TXI, 273),
142 INTC_IRQ(SCIF4_BRI, 274), INTC_IRQ(SCIF4_ERI, 275),
143 INTC_IRQ(SCIF4_RXI, 276), INTC_IRQ(SCIF4_TXI, 277),
144 INTC_IRQ(SCIF5_BRI, 278), INTC_IRQ(SCIF5_ERI, 279),
145 INTC_IRQ(SCIF5_RXI, 280), INTC_IRQ(SCIF5_TXI, 281),
146 INTC_IRQ(SCIF6_BRI, 282), INTC_IRQ(SCIF6_ERI, 283),
147 INTC_IRQ(SCIF6_RXI, 284), INTC_IRQ(SCIF6_TXI, 285),
148 INTC_IRQ(SCIF7_BRI, 286), INTC_IRQ(SCIF7_ERI, 287),
149 INTC_IRQ(SCIF7_RXI, 288), INTC_IRQ(SCIF7_TXI, 289),
150
151 INTC_IRQ(RCAN0, 291), INTC_IRQ(RCAN0, 292),
152 INTC_IRQ(RCAN0, 293), INTC_IRQ(RCAN0, 294),
153 INTC_IRQ(RCAN0, 295),
154 INTC_IRQ(RCAN1, 296), INTC_IRQ(RCAN1, 297),
155 INTC_IRQ(RCAN1, 298), INTC_IRQ(RCAN1, 299),
156 INTC_IRQ(RCAN1, 300),
157 INTC_IRQ(RCAN2, 301), INTC_IRQ(RCAN2, 302),
158 INTC_IRQ(RCAN2, 303), INTC_IRQ(RCAN2, 304),
159 INTC_IRQ(RCAN2, 305),
160
161 INTC_IRQ(RSPIC0, 306), INTC_IRQ(RSPIC0, 307),
162 INTC_IRQ(RSPIC0, 308),
163 INTC_IRQ(RSPIC1, 309), INTC_IRQ(RSPIC1, 310),
164 INTC_IRQ(RSPIC1, 311),
165
166 INTC_IRQ(IEBC, 318),
167
168 INTC_IRQ(CD_ROMD, 319), INTC_IRQ(CD_ROMD, 320),
169 INTC_IRQ(CD_ROMD, 321), INTC_IRQ(CD_ROMD, 322),
170 INTC_IRQ(CD_ROMD, 323), INTC_IRQ(CD_ROMD, 324),
171
172 INTC_IRQ(NFMC, 325), INTC_IRQ(NFMC, 326),
173 INTC_IRQ(NFMC, 327), INTC_IRQ(NFMC, 328),
174
175 INTC_IRQ(SDHI0, 332), INTC_IRQ(SDHI0, 333),
176 INTC_IRQ(SDHI0, 334),
177 INTC_IRQ(SDHI1, 335), INTC_IRQ(SDHI1, 336),
178 INTC_IRQ(SDHI1, 337),
179
180 INTC_IRQ(RTC, 338), INTC_IRQ(RTC, 339),
181 INTC_IRQ(RTC, 340),
182
183 INTC_IRQ(SRCC0, 341), INTC_IRQ(SRCC0, 342),
184 INTC_IRQ(SRCC0, 343), INTC_IRQ(SRCC0, 344),
185 INTC_IRQ(SRCC0, 345),
186 INTC_IRQ(SRCC1, 346), INTC_IRQ(SRCC1, 347),
187 INTC_IRQ(SRCC1, 348), INTC_IRQ(SRCC1, 349),
188 INTC_IRQ(SRCC1, 350),
189 INTC_IRQ(SRCC2, 351), INTC_IRQ(SRCC2, 352),
190 INTC_IRQ(SRCC2, 353), INTC_IRQ(SRCC2, 354),
191 INTC_IRQ(SRCC2, 355),
192};
193
194static struct intc_group groups[] __initdata = {
195 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
196 PINT4, PINT5, PINT6, PINT7),
197 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
198 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
199 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
200 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
201 INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
202 INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
203 INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
204 INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
205};
206
207static struct intc_prio_reg prio_registers[] __initdata = {
208 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
209 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
210 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
211 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
212 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
213 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9,
214 DMAC10, DMAC11 } },
215 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
216 DMAC14, DMAC15 } },
217 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC4, VDC4, VDC4 } },
218 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { 0, 0, 0, 0 } },
219 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { CMT0, CMT1, BSC, WDT } },
220 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU0_ABCD, MTU0_VEF,
221 MTU1_AB, MTU1_VU } },
222 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { MTU2_AB, MTU2_VU,
223 MTU3_ABCD, MTU3_TCI3V } },
224 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { MTU4_ABCD, MTU4_TCI4V,
225 PWMT1, PWMT2 } },
226 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { 0, 0, 0, 0 } },
227 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { ADC_ADI, SSIF0, SSII1, SSII2 } },
228 { 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SSII3, SSII4, SSII5, RSPDIF} },
229 { 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { IIC30, IIC31, IIC32, IIC33 } },
230 { 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
231 { 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
232 { 0xfffe0c20, 0, 16, 4, /* IPR22 */ { 0, RCAN0, RCAN1, RCAN2 } },
233 { 0xfffe0c22, 0, 16, 4, /* IPR23 */ { RSPIC0, RSPIC1, 0, 0 } },
234 { 0xfffe0c24, 0, 16, 4, /* IPR24 */ { IEBC, CD_ROMD, NFMC, 0 } },
235 { 0xfffe0c26, 0, 16, 4, /* IPR25 */ { SDHI0, SDHI1, RTC, 0 } },
236 { 0xfffe0c28, 0, 16, 4, /* IPR26 */ { SRCC0, SRCC1, SRCC2, 0 } },
237};
238
239static struct intc_mask_reg mask_registers[] __initdata = {
240 { 0xfffe0808, 0, 16, /* PINTER */
241 { 0, 0, 0, 0, 0, 0, 0, 0,
242 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
243};
244
245static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups,
246 mask_registers, prio_registers, NULL);
247
248static struct plat_sci_port scif0_platform_data = {
249 .scscr = SCSCR_REIE,
250 .type = PORT_SCIF,
251 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
252};
253
254static struct resource scif0_resources[] = {
255 DEFINE_RES_MEM(0xe8007000, 0x100),
256 DEFINE_RES_IRQ(259),
257 DEFINE_RES_IRQ(260),
258 DEFINE_RES_IRQ(261),
259 DEFINE_RES_IRQ(258),
260};
261
262static struct platform_device scif0_device = {
263 .name = "sh-sci",
264 .id = 0,
265 .resource = scif0_resources,
266 .num_resources = ARRAY_SIZE(scif0_resources),
267 .dev = {
268 .platform_data = &scif0_platform_data,
269 },
270};
271
272static struct plat_sci_port scif1_platform_data = {
273 .scscr = SCSCR_REIE,
274 .type = PORT_SCIF,
275 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
276};
277
278static struct resource scif1_resources[] = {
279 DEFINE_RES_MEM(0xe8007800, 0x100),
280 DEFINE_RES_IRQ(263),
281 DEFINE_RES_IRQ(264),
282 DEFINE_RES_IRQ(265),
283 DEFINE_RES_IRQ(262),
284};
285
286static struct platform_device scif1_device = {
287 .name = "sh-sci",
288 .id = 1,
289 .resource = scif1_resources,
290 .num_resources = ARRAY_SIZE(scif1_resources),
291 .dev = {
292 .platform_data = &scif1_platform_data,
293 },
294};
295
296static struct plat_sci_port scif2_platform_data = {
297 .scscr = SCSCR_REIE,
298 .type = PORT_SCIF,
299 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
300};
301
302static struct resource scif2_resources[] = {
303 DEFINE_RES_MEM(0xe8008000, 0x100),
304 DEFINE_RES_IRQ(267),
305 DEFINE_RES_IRQ(268),
306 DEFINE_RES_IRQ(269),
307 DEFINE_RES_IRQ(266),
308};
309
310static struct platform_device scif2_device = {
311 .name = "sh-sci",
312 .id = 2,
313 .resource = scif2_resources,
314 .num_resources = ARRAY_SIZE(scif2_resources),
315 .dev = {
316 .platform_data = &scif2_platform_data,
317 },
318};
319
320static struct plat_sci_port scif3_platform_data = {
321 .scscr = SCSCR_REIE,
322 .type = PORT_SCIF,
323 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
324};
325
326static struct resource scif3_resources[] = {
327 DEFINE_RES_MEM(0xe8008800, 0x100),
328 DEFINE_RES_IRQ(271),
329 DEFINE_RES_IRQ(272),
330 DEFINE_RES_IRQ(273),
331 DEFINE_RES_IRQ(270),
332};
333
334static struct platform_device scif3_device = {
335 .name = "sh-sci",
336 .id = 3,
337 .resource = scif3_resources,
338 .num_resources = ARRAY_SIZE(scif3_resources),
339 .dev = {
340 .platform_data = &scif3_platform_data,
341 },
342};
343
344static struct plat_sci_port scif4_platform_data = {
345 .scscr = SCSCR_REIE,
346 .type = PORT_SCIF,
347 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
348};
349
350static struct resource scif4_resources[] = {
351 DEFINE_RES_MEM(0xe8009000, 0x100),
352 DEFINE_RES_IRQ(275),
353 DEFINE_RES_IRQ(276),
354 DEFINE_RES_IRQ(277),
355 DEFINE_RES_IRQ(274),
356};
357
358static struct platform_device scif4_device = {
359 .name = "sh-sci",
360 .id = 4,
361 .resource = scif4_resources,
362 .num_resources = ARRAY_SIZE(scif4_resources),
363 .dev = {
364 .platform_data = &scif4_platform_data,
365 },
366};
367
368static struct plat_sci_port scif5_platform_data = {
369 .scscr = SCSCR_REIE,
370 .type = PORT_SCIF,
371 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
372};
373
374static struct resource scif5_resources[] = {
375 DEFINE_RES_MEM(0xe8009800, 0x100),
376 DEFINE_RES_IRQ(279),
377 DEFINE_RES_IRQ(280),
378 DEFINE_RES_IRQ(281),
379 DEFINE_RES_IRQ(278),
380};
381
382static struct platform_device scif5_device = {
383 .name = "sh-sci",
384 .id = 5,
385 .resource = scif5_resources,
386 .num_resources = ARRAY_SIZE(scif5_resources),
387 .dev = {
388 .platform_data = &scif5_platform_data,
389 },
390};
391
392static struct plat_sci_port scif6_platform_data = {
393 .scscr = SCSCR_REIE,
394 .type = PORT_SCIF,
395 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
396};
397
398static struct resource scif6_resources[] = {
399 DEFINE_RES_MEM(0xe800a000, 0x100),
400 DEFINE_RES_IRQ(283),
401 DEFINE_RES_IRQ(284),
402 DEFINE_RES_IRQ(285),
403 DEFINE_RES_IRQ(282),
404};
405
406static struct platform_device scif6_device = {
407 .name = "sh-sci",
408 .id = 6,
409 .resource = scif6_resources,
410 .num_resources = ARRAY_SIZE(scif6_resources),
411 .dev = {
412 .platform_data = &scif6_platform_data,
413 },
414};
415
416static struct plat_sci_port scif7_platform_data = {
417 .scscr = SCSCR_REIE,
418 .type = PORT_SCIF,
419 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
420};
421
422static struct resource scif7_resources[] = {
423 DEFINE_RES_MEM(0xe800a800, 0x100),
424 DEFINE_RES_IRQ(287),
425 DEFINE_RES_IRQ(288),
426 DEFINE_RES_IRQ(289),
427 DEFINE_RES_IRQ(286),
428};
429
430static struct platform_device scif7_device = {
431 .name = "sh-sci",
432 .id = 7,
433 .resource = scif7_resources,
434 .num_resources = ARRAY_SIZE(scif7_resources),
435 .dev = {
436 .platform_data = &scif7_platform_data,
437 },
438};
439
440static struct sh_timer_config cmt_platform_data = {
441 .channels_mask = 3,
442};
443
444static struct resource cmt_resources[] = {
445 DEFINE_RES_MEM(0xfffec000, 0x10),
446 DEFINE_RES_IRQ(188),
447 DEFINE_RES_IRQ(189),
448};
449
450static struct platform_device cmt_device = {
451 .name = "sh-cmt-16",
452 .id = 0,
453 .dev = {
454 .platform_data = &cmt_platform_data,
455 },
456 .resource = cmt_resources,
457 .num_resources = ARRAY_SIZE(cmt_resources),
458};
459
460static struct resource mtu2_resources[] = {
461 DEFINE_RES_MEM(0xfffe4000, 0x400),
462 DEFINE_RES_IRQ_NAMED(192, "tgi0a"),
463 DEFINE_RES_IRQ_NAMED(203, "tgi1a"),
464};
465
466static struct platform_device mtu2_device = {
467 .name = "sh-mtu2",
468 .id = -1,
469 .resource = mtu2_resources,
470 .num_resources = ARRAY_SIZE(mtu2_resources),
471};
472
473static struct resource rtc_resources[] = {
474 [0] = {
475 .start = 0xfffe6000,
476 .end = 0xfffe6000 + 0x30 - 1,
477 .flags = IORESOURCE_IO,
478 },
479 [1] = {
480 /* Shared Period/Carry/Alarm IRQ */
481 .start = 338,
482 .flags = IORESOURCE_IRQ,
483 },
484};
485
486static struct platform_device rtc_device = {
487 .name = "sh-rtc",
488 .id = -1,
489 .num_resources = ARRAY_SIZE(rtc_resources),
490 .resource = rtc_resources,
491};
492
493/* USB Host */
494static struct r8a66597_platdata r8a66597_data = {
495 .on_chip = 1,
496 .endian = 1,
497};
498
499static struct resource r8a66597_usb_host_resources[] = {
500 [0] = {
501 .start = 0xe8010000,
502 .end = 0xe80100e4,
503 .flags = IORESOURCE_MEM,
504 },
505 [1] = {
506 .start = 170,
507 .end = 170,
508 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
509 },
510};
511
512static struct platform_device r8a66597_usb_host_device = {
513 .name = "r8a66597_hcd",
514 .id = 0,
515 .dev = {
516 .dma_mask = NULL, /* not use dma */
517 .coherent_dma_mask = 0xffffffff,
518 .platform_data = &r8a66597_data,
519 },
520 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
521 .resource = r8a66597_usb_host_resources,
522};
523
524static struct platform_device *sh7269_devices[] __initdata = {
525 &scif0_device,
526 &scif1_device,
527 &scif2_device,
528 &scif3_device,
529 &scif4_device,
530 &scif5_device,
531 &scif6_device,
532 &scif7_device,
533 &cmt_device,
534 &mtu2_device,
535 &rtc_device,
536 &r8a66597_usb_host_device,
537};
538
539static int __init sh7269_devices_setup(void)
540{
541 return platform_add_devices(sh7269_devices,
542 ARRAY_SIZE(sh7269_devices));
543}
544arch_initcall(sh7269_devices_setup);
545
546void __init plat_irq_setup(void)
547{
548 register_intc_controller(&intc_desc);
549}
550
551static struct platform_device *sh7269_early_devices[] __initdata = {
552 &scif0_device,
553 &scif1_device,
554 &scif2_device,
555 &scif3_device,
556 &scif4_device,
557 &scif5_device,
558 &scif6_device,
559 &scif7_device,
560 &cmt_device,
561 &mtu2_device,
562};
563
564void __init plat_early_device_setup(void)
565{
566 sh_early_platform_add_devices(sh7269_early_devices,
567 ARRAY_SIZE(sh7269_early_devices));
568}