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1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
9 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
10 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
11 */
12
13#ifndef _RT305X_REGS_H_
14#define _RT305X_REGS_H_
15
16enum rt305x_soc_type {
17 RT305X_SOC_UNKNOWN = 0,
18 RT305X_SOC_RT3050,
19 RT305X_SOC_RT3052,
20 RT305X_SOC_RT3350,
21 RT305X_SOC_RT3352,
22 RT305X_SOC_RT5350,
23};
24
25extern enum rt305x_soc_type rt305x_soc;
26
27static inline int soc_is_rt3050(void)
28{
29 return rt305x_soc == RT305X_SOC_RT3050;
30}
31
32static inline int soc_is_rt3052(void)
33{
34 return rt305x_soc == RT305X_SOC_RT3052;
35}
36
37static inline int soc_is_rt305x(void)
38{
39 return soc_is_rt3050() || soc_is_rt3052();
40}
41
42static inline int soc_is_rt3350(void)
43{
44 return rt305x_soc == RT305X_SOC_RT3350;
45}
46
47static inline int soc_is_rt3352(void)
48{
49 return rt305x_soc == RT305X_SOC_RT3352;
50}
51
52static inline int soc_is_rt5350(void)
53{
54 return rt305x_soc == RT305X_SOC_RT5350;
55}
56
57#define RT305X_SYSC_BASE 0x10000000
58
59#define SYSC_REG_CHIP_NAME0 0x00
60#define SYSC_REG_CHIP_NAME1 0x04
61#define SYSC_REG_CHIP_ID 0x0c
62#define SYSC_REG_SYSTEM_CONFIG 0x10
63
64#define RT3052_CHIP_NAME0 0x30335452
65#define RT3052_CHIP_NAME1 0x20203235
66
67#define RT3350_CHIP_NAME0 0x33335452
68#define RT3350_CHIP_NAME1 0x20203035
69
70#define RT3352_CHIP_NAME0 0x33335452
71#define RT3352_CHIP_NAME1 0x20203235
72
73#define RT5350_CHIP_NAME0 0x33355452
74#define RT5350_CHIP_NAME1 0x20203035
75
76#define CHIP_ID_ID_MASK 0xff
77#define CHIP_ID_ID_SHIFT 8
78#define CHIP_ID_REV_MASK 0xff
79
80#define RT305X_SYSCFG_CPUCLK_SHIFT 18
81#define RT305X_SYSCFG_CPUCLK_MASK 0x1
82#define RT305X_SYSCFG_CPUCLK_LOW 0x0
83#define RT305X_SYSCFG_CPUCLK_HIGH 0x1
84
85#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
86#define RT305X_SYSCFG_CPUCLK_MASK 0x1
87#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1
88
89#define RT3352_SYSCFG0_CPUCLK_SHIFT 8
90#define RT3352_SYSCFG0_CPUCLK_MASK 0x1
91#define RT3352_SYSCFG0_CPUCLK_LOW 0x0
92#define RT3352_SYSCFG0_CPUCLK_HIGH 0x1
93
94#define RT5350_SYSCFG0_CPUCLK_SHIFT 8
95#define RT5350_SYSCFG0_CPUCLK_MASK 0x3
96#define RT5350_SYSCFG0_CPUCLK_360 0x0
97#define RT5350_SYSCFG0_CPUCLK_320 0x2
98#define RT5350_SYSCFG0_CPUCLK_300 0x3
99
100#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12
101#define RT5350_SYSCFG0_DRAM_SIZE_MASK 7
102#define RT5350_SYSCFG0_DRAM_SIZE_2M 0
103#define RT5350_SYSCFG0_DRAM_SIZE_8M 1
104#define RT5350_SYSCFG0_DRAM_SIZE_16M 2
105#define RT5350_SYSCFG0_DRAM_SIZE_32M 3
106#define RT5350_SYSCFG0_DRAM_SIZE_64M 4
107
108/* multi function gpio pins */
109#define RT305X_GPIO_I2C_SD 1
110#define RT305X_GPIO_I2C_SCLK 2
111#define RT305X_GPIO_SPI_EN 3
112#define RT305X_GPIO_SPI_CLK 4
113/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
114#define RT305X_GPIO_7 7
115#define RT305X_GPIO_10 10
116#define RT305X_GPIO_14 14
117#define RT305X_GPIO_UART1_TXD 15
118#define RT305X_GPIO_UART1_RXD 16
119#define RT305X_GPIO_JTAG_TDO 17
120#define RT305X_GPIO_JTAG_TDI 18
121#define RT305X_GPIO_MDIO_MDC 22
122#define RT305X_GPIO_MDIO_MDIO 23
123#define RT305X_GPIO_SDRAM_MD16 24
124#define RT305X_GPIO_SDRAM_MD31 39
125#define RT305X_GPIO_GE0_TXD0 40
126#define RT305X_GPIO_GE0_RXCLK 51
127
128#define RT305X_GPIO_MODE_I2C BIT(0)
129#define RT305X_GPIO_MODE_SPI BIT(1)
130#define RT305X_GPIO_MODE_UART0_SHIFT 2
131#define RT305X_GPIO_MODE_UART0_MASK 0x7
132#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
133#define RT305X_GPIO_MODE_UARTF 0x0
134#define RT305X_GPIO_MODE_PCM_UARTF 0x1
135#define RT305X_GPIO_MODE_PCM_I2S 0x2
136#define RT305X_GPIO_MODE_I2S_UARTF 0x3
137#define RT305X_GPIO_MODE_PCM_GPIO 0x4
138#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
139#define RT305X_GPIO_MODE_GPIO_I2S 0x6
140#define RT305X_GPIO_MODE_GPIO 0x7
141#define RT305X_GPIO_MODE_UART1 BIT(5)
142#define RT305X_GPIO_MODE_JTAG BIT(6)
143#define RT305X_GPIO_MODE_MDIO BIT(7)
144#define RT305X_GPIO_MODE_SDRAM BIT(8)
145#define RT305X_GPIO_MODE_RGMII BIT(9)
146
147#define RT3352_SYSC_REG_SYSCFG0 0x010
148#define RT3352_SYSC_REG_SYSCFG1 0x014
149#define RT3352_SYSC_REG_CLKCFG1 0x030
150#define RT3352_SYSC_REG_RSTCTRL 0x034
151#define RT3352_SYSC_REG_USB_PS 0x05c
152
153#define RT3352_CLKCFG0_XTAL_SEL BIT(20)
154#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
155#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
156#define RT3352_RSTCTRL_UHST BIT(22)
157#define RT3352_RSTCTRL_UDEV BIT(25)
158#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
159
160#define RT305X_SDRAM_BASE 0x00000000
161#define RT305X_MEM_SIZE_MIN 2
162#define RT305X_MEM_SIZE_MAX 64
163#define RT3352_MEM_SIZE_MIN 2
164#define RT3352_MEM_SIZE_MAX 256
165
166#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 *
4 * Parts of this file are based on Ralink's 2.6.21 BSP
5 *
6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Copyright (C) 2013 John Crispin <john@phrozen.org>
9 */
10
11#ifndef _RT305X_REGS_H_
12#define _RT305X_REGS_H_
13
14extern enum ralink_soc_type ralink_soc;
15
16static inline int soc_is_rt3050(void)
17{
18 return ralink_soc == RT305X_SOC_RT3050;
19}
20
21static inline int soc_is_rt3052(void)
22{
23 return ralink_soc == RT305X_SOC_RT3052;
24}
25
26static inline int soc_is_rt305x(void)
27{
28 return soc_is_rt3050() || soc_is_rt3052();
29}
30
31static inline int soc_is_rt3350(void)
32{
33 return ralink_soc == RT305X_SOC_RT3350;
34}
35
36static inline int soc_is_rt3352(void)
37{
38 return ralink_soc == RT305X_SOC_RT3352;
39}
40
41static inline int soc_is_rt5350(void)
42{
43 return ralink_soc == RT305X_SOC_RT5350;
44}
45
46#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(x)))
47#define RT305X_SYSC_BASE IOMEM(0x10000000)
48
49#define SYSC_REG_CHIP_NAME0 0x00
50#define SYSC_REG_CHIP_NAME1 0x04
51#define SYSC_REG_CHIP_ID 0x0c
52#define SYSC_REG_SYSTEM_CONFIG 0x10
53
54#define RT3052_CHIP_NAME0 0x30335452
55#define RT3052_CHIP_NAME1 0x20203235
56
57#define RT3350_CHIP_NAME0 0x33335452
58#define RT3350_CHIP_NAME1 0x20203035
59
60#define RT3352_CHIP_NAME0 0x33335452
61#define RT3352_CHIP_NAME1 0x20203235
62
63#define RT5350_CHIP_NAME0 0x33355452
64#define RT5350_CHIP_NAME1 0x20203035
65
66#define CHIP_ID_ID_MASK 0xff
67#define CHIP_ID_ID_SHIFT 8
68#define CHIP_ID_REV_MASK 0xff
69
70#define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT 2
71#define RT305X_SYSCFG_SRAM_CS0_MODE_WDT 0x1
72
73#define RT5350_SYSCFG0_DRAM_SIZE_SHIFT 12
74#define RT5350_SYSCFG0_DRAM_SIZE_MASK 7
75#define RT5350_SYSCFG0_DRAM_SIZE_2M 0
76#define RT5350_SYSCFG0_DRAM_SIZE_8M 1
77#define RT5350_SYSCFG0_DRAM_SIZE_16M 2
78#define RT5350_SYSCFG0_DRAM_SIZE_32M 3
79#define RT5350_SYSCFG0_DRAM_SIZE_64M 4
80
81/* multi function gpio pins */
82#define RT305X_GPIO_I2C_SD 1
83#define RT305X_GPIO_I2C_SCLK 2
84#define RT305X_GPIO_SPI_EN 3
85#define RT305X_GPIO_SPI_CLK 4
86/* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
87#define RT305X_GPIO_7 7
88#define RT305X_GPIO_10 10
89#define RT305X_GPIO_14 14
90#define RT305X_GPIO_UART1_TXD 15
91#define RT305X_GPIO_UART1_RXD 16
92#define RT305X_GPIO_JTAG_TDO 17
93#define RT305X_GPIO_JTAG_TDI 18
94#define RT305X_GPIO_MDIO_MDC 22
95#define RT305X_GPIO_MDIO_MDIO 23
96#define RT305X_GPIO_SDRAM_MD16 24
97#define RT305X_GPIO_SDRAM_MD31 39
98#define RT305X_GPIO_GE0_TXD0 40
99#define RT305X_GPIO_GE0_RXCLK 51
100
101#define RT3352_SYSC_REG_SYSCFG0 0x010
102#define RT3352_SYSC_REG_SYSCFG1 0x014
103#define RT3352_SYSC_REG_RSTCTRL 0x034
104#define RT3352_SYSC_REG_USB_PS 0x05c
105
106#define RT3352_RSTCTRL_UHST BIT(22)
107#define RT3352_RSTCTRL_UDEV BIT(25)
108#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
109
110#define RT305X_SDRAM_BASE 0x00000000
111#define RT305X_MEM_SIZE_MIN 2
112#define RT305X_MEM_SIZE_MAX 64
113#define RT3352_MEM_SIZE_MIN 2
114#define RT3352_MEM_SIZE_MAX 256
115
116#endif