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1/*
2 * Intel SMP support routines.
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * (c) 2002,2003 Andi Kleen, SuSE Labs.
7 *
8 * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
9 *
10 * This code is released under the GNU General Public License version 2 or
11 * later.
12 */
13
14#include <linux/init.h>
15
16#include <linux/mm.h>
17#include <linux/delay.h>
18#include <linux/spinlock.h>
19#include <linux/export.h>
20#include <linux/kernel_stat.h>
21#include <linux/mc146818rtc.h>
22#include <linux/cache.h>
23#include <linux/interrupt.h>
24#include <linux/cpu.h>
25#include <linux/gfp.h>
26
27#include <asm/mtrr.h>
28#include <asm/tlbflush.h>
29#include <asm/mmu_context.h>
30#include <asm/proto.h>
31#include <asm/apic.h>
32#include <asm/nmi.h>
33#include <asm/trace/irq_vectors.h>
34/*
35 * Some notes on x86 processor bugs affecting SMP operation:
36 *
37 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
38 * The Linux implications for SMP are handled as follows:
39 *
40 * Pentium III / [Xeon]
41 * None of the E1AP-E3AP errata are visible to the user.
42 *
43 * E1AP. see PII A1AP
44 * E2AP. see PII A2AP
45 * E3AP. see PII A3AP
46 *
47 * Pentium II / [Xeon]
48 * None of the A1AP-A3AP errata are visible to the user.
49 *
50 * A1AP. see PPro 1AP
51 * A2AP. see PPro 2AP
52 * A3AP. see PPro 7AP
53 *
54 * Pentium Pro
55 * None of 1AP-9AP errata are visible to the normal user,
56 * except occasional delivery of 'spurious interrupt' as trap #15.
57 * This is very rare and a non-problem.
58 *
59 * 1AP. Linux maps APIC as non-cacheable
60 * 2AP. worked around in hardware
61 * 3AP. fixed in C0 and above steppings microcode update.
62 * Linux does not use excessive STARTUP_IPIs.
63 * 4AP. worked around in hardware
64 * 5AP. symmetric IO mode (normal Linux operation) not affected.
65 * 'noapic' mode has vector 0xf filled out properly.
66 * 6AP. 'noapic' mode might be affected - fixed in later steppings
67 * 7AP. We do not assume writes to the LVT deassering IRQs
68 * 8AP. We do not enable low power mode (deep sleep) during MP bootup
69 * 9AP. We do not use mixed mode
70 *
71 * Pentium
72 * There is a marginal case where REP MOVS on 100MHz SMP
73 * machines with B stepping processors can fail. XXX should provide
74 * an L1cache=Writethrough or L1cache=off option.
75 *
76 * B stepping CPUs may hang. There are hardware work arounds
77 * for this. We warn about it in case your board doesn't have the work
78 * arounds. Basically that's so I can tell anyone with a B stepping
79 * CPU and SMP problems "tough".
80 *
81 * Specific items [From Pentium Processor Specification Update]
82 *
83 * 1AP. Linux doesn't use remote read
84 * 2AP. Linux doesn't trust APIC errors
85 * 3AP. We work around this
86 * 4AP. Linux never generated 3 interrupts of the same priority
87 * to cause a lost local interrupt.
88 * 5AP. Remote read is never used
89 * 6AP. not affected - worked around in hardware
90 * 7AP. not affected - worked around in hardware
91 * 8AP. worked around in hardware - we get explicit CS errors if not
92 * 9AP. only 'noapic' mode affected. Might generate spurious
93 * interrupts, we log only the first one and count the
94 * rest silently.
95 * 10AP. not affected - worked around in hardware
96 * 11AP. Linux reads the APIC between writes to avoid this, as per
97 * the documentation. Make sure you preserve this as it affects
98 * the C stepping chips too.
99 * 12AP. not affected - worked around in hardware
100 * 13AP. not affected - worked around in hardware
101 * 14AP. we always deassert INIT during bootup
102 * 15AP. not affected - worked around in hardware
103 * 16AP. not affected - worked around in hardware
104 * 17AP. not affected - worked around in hardware
105 * 18AP. not affected - worked around in hardware
106 * 19AP. not affected - worked around in BIOS
107 *
108 * If this sounds worrying believe me these bugs are either ___RARE___,
109 * or are signal timing bugs worked around in hardware and there's
110 * about nothing of note with C stepping upwards.
111 */
112
113static atomic_t stopping_cpu = ATOMIC_INIT(-1);
114static bool smp_no_nmi_ipi = false;
115
116/*
117 * this function sends a 'reschedule' IPI to another CPU.
118 * it goes straight through and wastes no time serializing
119 * anything. Worst case is that we lose a reschedule ...
120 */
121static void native_smp_send_reschedule(int cpu)
122{
123 if (unlikely(cpu_is_offline(cpu))) {
124 WARN_ON(1);
125 return;
126 }
127 apic->send_IPI_mask(cpumask_of(cpu), RESCHEDULE_VECTOR);
128}
129
130void native_send_call_func_single_ipi(int cpu)
131{
132 apic->send_IPI_mask(cpumask_of(cpu), CALL_FUNCTION_SINGLE_VECTOR);
133}
134
135void native_send_call_func_ipi(const struct cpumask *mask)
136{
137 cpumask_var_t allbutself;
138
139 if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) {
140 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
141 return;
142 }
143
144 cpumask_copy(allbutself, cpu_online_mask);
145 cpumask_clear_cpu(smp_processor_id(), allbutself);
146
147 if (cpumask_equal(mask, allbutself) &&
148 cpumask_equal(cpu_online_mask, cpu_callout_mask))
149 apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR);
150 else
151 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
152
153 free_cpumask_var(allbutself);
154}
155
156static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
157{
158 /* We are registered on stopping cpu too, avoid spurious NMI */
159 if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
160 return NMI_HANDLED;
161
162 stop_this_cpu(NULL);
163
164 return NMI_HANDLED;
165}
166
167/*
168 * this function calls the 'stop' function on all other CPUs in the system.
169 */
170
171asmlinkage __visible void smp_reboot_interrupt(void)
172{
173 ack_APIC_irq();
174 irq_enter();
175 stop_this_cpu(NULL);
176 irq_exit();
177}
178
179static void native_stop_other_cpus(int wait)
180{
181 unsigned long flags;
182 unsigned long timeout;
183
184 if (reboot_force)
185 return;
186
187 /*
188 * Use an own vector here because smp_call_function
189 * does lots of things not suitable in a panic situation.
190 */
191
192 /*
193 * We start by using the REBOOT_VECTOR irq.
194 * The irq is treated as a sync point to allow critical
195 * regions of code on other cpus to release their spin locks
196 * and re-enable irqs. Jumping straight to an NMI might
197 * accidentally cause deadlocks with further shutdown/panic
198 * code. By syncing, we give the cpus up to one second to
199 * finish their work before we force them off with the NMI.
200 */
201 if (num_online_cpus() > 1) {
202 /* did someone beat us here? */
203 if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1)
204 return;
205
206 /* sync above data before sending IRQ */
207 wmb();
208
209 apic->send_IPI_allbutself(REBOOT_VECTOR);
210
211 /*
212 * Don't wait longer than a second if the caller
213 * didn't ask us to wait.
214 */
215 timeout = USEC_PER_SEC;
216 while (num_online_cpus() > 1 && (wait || timeout--))
217 udelay(1);
218 }
219
220 /* if the REBOOT_VECTOR didn't work, try with the NMI */
221 if ((num_online_cpus() > 1) && (!smp_no_nmi_ipi)) {
222 if (register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
223 NMI_FLAG_FIRST, "smp_stop"))
224 /* Note: we ignore failures here */
225 /* Hope the REBOOT_IRQ is good enough */
226 goto finish;
227
228 /* sync above data before sending IRQ */
229 wmb();
230
231 pr_emerg("Shutting down cpus with NMI\n");
232
233 apic->send_IPI_allbutself(NMI_VECTOR);
234
235 /*
236 * Don't wait longer than a 10 ms if the caller
237 * didn't ask us to wait.
238 */
239 timeout = USEC_PER_MSEC * 10;
240 while (num_online_cpus() > 1 && (wait || timeout--))
241 udelay(1);
242 }
243
244finish:
245 local_irq_save(flags);
246 disable_local_APIC();
247 local_irq_restore(flags);
248}
249
250/*
251 * Reschedule call back.
252 */
253static inline void __smp_reschedule_interrupt(void)
254{
255 inc_irq_stat(irq_resched_count);
256 scheduler_ipi();
257}
258
259__visible void smp_reschedule_interrupt(struct pt_regs *regs)
260{
261 ack_APIC_irq();
262 __smp_reschedule_interrupt();
263 /*
264 * KVM uses this interrupt to force a cpu out of guest mode
265 */
266}
267
268static inline void smp_entering_irq(void)
269{
270 ack_APIC_irq();
271 irq_enter();
272}
273
274__visible void smp_trace_reschedule_interrupt(struct pt_regs *regs)
275{
276 /*
277 * Need to call irq_enter() before calling the trace point.
278 * __smp_reschedule_interrupt() calls irq_enter/exit() too (in
279 * scheduler_ipi(). This is OK, since those functions are allowed
280 * to nest.
281 */
282 smp_entering_irq();
283 trace_reschedule_entry(RESCHEDULE_VECTOR);
284 __smp_reschedule_interrupt();
285 trace_reschedule_exit(RESCHEDULE_VECTOR);
286 exiting_irq();
287 /*
288 * KVM uses this interrupt to force a cpu out of guest mode
289 */
290}
291
292static inline void __smp_call_function_interrupt(void)
293{
294 generic_smp_call_function_interrupt();
295 inc_irq_stat(irq_call_count);
296}
297
298__visible void smp_call_function_interrupt(struct pt_regs *regs)
299{
300 smp_entering_irq();
301 __smp_call_function_interrupt();
302 exiting_irq();
303}
304
305__visible void smp_trace_call_function_interrupt(struct pt_regs *regs)
306{
307 smp_entering_irq();
308 trace_call_function_entry(CALL_FUNCTION_VECTOR);
309 __smp_call_function_interrupt();
310 trace_call_function_exit(CALL_FUNCTION_VECTOR);
311 exiting_irq();
312}
313
314static inline void __smp_call_function_single_interrupt(void)
315{
316 generic_smp_call_function_single_interrupt();
317 inc_irq_stat(irq_call_count);
318}
319
320__visible void smp_call_function_single_interrupt(struct pt_regs *regs)
321{
322 smp_entering_irq();
323 __smp_call_function_single_interrupt();
324 exiting_irq();
325}
326
327__visible void smp_trace_call_function_single_interrupt(struct pt_regs *regs)
328{
329 smp_entering_irq();
330 trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR);
331 __smp_call_function_single_interrupt();
332 trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR);
333 exiting_irq();
334}
335
336static int __init nonmi_ipi_setup(char *str)
337{
338 smp_no_nmi_ipi = true;
339 return 1;
340}
341
342__setup("nonmi_ipi", nonmi_ipi_setup);
343
344struct smp_ops smp_ops = {
345 .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
346 .smp_prepare_cpus = native_smp_prepare_cpus,
347 .smp_cpus_done = native_smp_cpus_done,
348
349 .stop_other_cpus = native_stop_other_cpus,
350 .smp_send_reschedule = native_smp_send_reschedule,
351
352 .cpu_up = native_cpu_up,
353 .cpu_die = native_cpu_die,
354 .cpu_disable = native_cpu_disable,
355 .play_dead = native_play_dead,
356
357 .send_call_func_ipi = native_send_call_func_ipi,
358 .send_call_func_single_ipi = native_send_call_func_single_ipi,
359};
360EXPORT_SYMBOL_GPL(smp_ops);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Intel SMP support routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * (c) 2002,2003 Andi Kleen, SuSE Labs.
8 *
9 * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
10 */
11
12#include <linux/init.h>
13
14#include <linux/mm.h>
15#include <linux/delay.h>
16#include <linux/spinlock.h>
17#include <linux/export.h>
18#include <linux/kernel_stat.h>
19#include <linux/mc146818rtc.h>
20#include <linux/cache.h>
21#include <linux/interrupt.h>
22#include <linux/cpu.h>
23#include <linux/gfp.h>
24#include <linux/kexec.h>
25
26#include <asm/mtrr.h>
27#include <asm/tlbflush.h>
28#include <asm/mmu_context.h>
29#include <asm/proto.h>
30#include <asm/apic.h>
31#include <asm/cpu.h>
32#include <asm/idtentry.h>
33#include <asm/nmi.h>
34#include <asm/mce.h>
35#include <asm/trace/irq_vectors.h>
36#include <asm/kexec.h>
37#include <asm/reboot.h>
38
39/*
40 * Some notes on x86 processor bugs affecting SMP operation:
41 *
42 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
43 * The Linux implications for SMP are handled as follows:
44 *
45 * Pentium III / [Xeon]
46 * None of the E1AP-E3AP errata are visible to the user.
47 *
48 * E1AP. see PII A1AP
49 * E2AP. see PII A2AP
50 * E3AP. see PII A3AP
51 *
52 * Pentium II / [Xeon]
53 * None of the A1AP-A3AP errata are visible to the user.
54 *
55 * A1AP. see PPro 1AP
56 * A2AP. see PPro 2AP
57 * A3AP. see PPro 7AP
58 *
59 * Pentium Pro
60 * None of 1AP-9AP errata are visible to the normal user,
61 * except occasional delivery of 'spurious interrupt' as trap #15.
62 * This is very rare and a non-problem.
63 *
64 * 1AP. Linux maps APIC as non-cacheable
65 * 2AP. worked around in hardware
66 * 3AP. fixed in C0 and above steppings microcode update.
67 * Linux does not use excessive STARTUP_IPIs.
68 * 4AP. worked around in hardware
69 * 5AP. symmetric IO mode (normal Linux operation) not affected.
70 * 'noapic' mode has vector 0xf filled out properly.
71 * 6AP. 'noapic' mode might be affected - fixed in later steppings
72 * 7AP. We do not assume writes to the LVT deasserting IRQs
73 * 8AP. We do not enable low power mode (deep sleep) during MP bootup
74 * 9AP. We do not use mixed mode
75 *
76 * Pentium
77 * There is a marginal case where REP MOVS on 100MHz SMP
78 * machines with B stepping processors can fail. XXX should provide
79 * an L1cache=Writethrough or L1cache=off option.
80 *
81 * B stepping CPUs may hang. There are hardware work arounds
82 * for this. We warn about it in case your board doesn't have the work
83 * arounds. Basically that's so I can tell anyone with a B stepping
84 * CPU and SMP problems "tough".
85 *
86 * Specific items [From Pentium Processor Specification Update]
87 *
88 * 1AP. Linux doesn't use remote read
89 * 2AP. Linux doesn't trust APIC errors
90 * 3AP. We work around this
91 * 4AP. Linux never generated 3 interrupts of the same priority
92 * to cause a lost local interrupt.
93 * 5AP. Remote read is never used
94 * 6AP. not affected - worked around in hardware
95 * 7AP. not affected - worked around in hardware
96 * 8AP. worked around in hardware - we get explicit CS errors if not
97 * 9AP. only 'noapic' mode affected. Might generate spurious
98 * interrupts, we log only the first one and count the
99 * rest silently.
100 * 10AP. not affected - worked around in hardware
101 * 11AP. Linux reads the APIC between writes to avoid this, as per
102 * the documentation. Make sure you preserve this as it affects
103 * the C stepping chips too.
104 * 12AP. not affected - worked around in hardware
105 * 13AP. not affected - worked around in hardware
106 * 14AP. we always deassert INIT during bootup
107 * 15AP. not affected - worked around in hardware
108 * 16AP. not affected - worked around in hardware
109 * 17AP. not affected - worked around in hardware
110 * 18AP. not affected - worked around in hardware
111 * 19AP. not affected - worked around in BIOS
112 *
113 * If this sounds worrying believe me these bugs are either ___RARE___,
114 * or are signal timing bugs worked around in hardware and there's
115 * about nothing of note with C stepping upwards.
116 */
117
118static atomic_t stopping_cpu = ATOMIC_INIT(-1);
119static bool smp_no_nmi_ipi = false;
120
121static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
122{
123 /* We are registered on stopping cpu too, avoid spurious NMI */
124 if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
125 return NMI_HANDLED;
126
127 cpu_emergency_disable_virtualization();
128 stop_this_cpu(NULL);
129
130 return NMI_HANDLED;
131}
132
133/*
134 * this function calls the 'stop' function on all other CPUs in the system.
135 */
136DEFINE_IDTENTRY_SYSVEC(sysvec_reboot)
137{
138 apic_eoi();
139 cpu_emergency_disable_virtualization();
140 stop_this_cpu(NULL);
141}
142
143static int register_stop_handler(void)
144{
145 return register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
146 NMI_FLAG_FIRST, "smp_stop");
147}
148
149static void native_stop_other_cpus(int wait)
150{
151 unsigned int cpu = smp_processor_id();
152 unsigned long flags, timeout;
153
154 if (reboot_force)
155 return;
156
157 /* Only proceed if this is the first CPU to reach this code */
158 if (atomic_cmpxchg(&stopping_cpu, -1, cpu) != -1)
159 return;
160
161 /* For kexec, ensure that offline CPUs are out of MWAIT and in HLT */
162 if (kexec_in_progress)
163 smp_kick_mwait_play_dead();
164
165 /*
166 * 1) Send an IPI on the reboot vector to all other CPUs.
167 *
168 * The other CPUs should react on it after leaving critical
169 * sections and re-enabling interrupts. They might still hold
170 * locks, but there is nothing which can be done about that.
171 *
172 * 2) Wait for all other CPUs to report that they reached the
173 * HLT loop in stop_this_cpu()
174 *
175 * 3) If #2 timed out send an NMI to the CPUs which did not
176 * yet report
177 *
178 * 4) Wait for all other CPUs to report that they reached the
179 * HLT loop in stop_this_cpu()
180 *
181 * #3 can obviously race against a CPU reaching the HLT loop late.
182 * That CPU will have reported already and the "have all CPUs
183 * reached HLT" condition will be true despite the fact that the
184 * other CPU is still handling the NMI. Again, there is no
185 * protection against that as "disabled" APICs still respond to
186 * NMIs.
187 */
188 cpumask_copy(&cpus_stop_mask, cpu_online_mask);
189 cpumask_clear_cpu(cpu, &cpus_stop_mask);
190
191 if (!cpumask_empty(&cpus_stop_mask)) {
192 apic_send_IPI_allbutself(REBOOT_VECTOR);
193
194 /*
195 * Don't wait longer than a second for IPI completion. The
196 * wait request is not checked here because that would
197 * prevent an NMI shutdown attempt in case that not all
198 * CPUs reach shutdown state.
199 */
200 timeout = USEC_PER_SEC;
201 while (!cpumask_empty(&cpus_stop_mask) && timeout--)
202 udelay(1);
203 }
204
205 /* if the REBOOT_VECTOR didn't work, try with the NMI */
206 if (!cpumask_empty(&cpus_stop_mask)) {
207 /*
208 * If NMI IPI is enabled, try to register the stop handler
209 * and send the IPI. In any case try to wait for the other
210 * CPUs to stop.
211 */
212 if (!smp_no_nmi_ipi && !register_stop_handler()) {
213 pr_emerg("Shutting down cpus with NMI\n");
214
215 for_each_cpu(cpu, &cpus_stop_mask)
216 __apic_send_IPI(cpu, NMI_VECTOR);
217 }
218 /*
219 * Don't wait longer than 10 ms if the caller didn't
220 * request it. If wait is true, the machine hangs here if
221 * one or more CPUs do not reach shutdown state.
222 */
223 timeout = USEC_PER_MSEC * 10;
224 while (!cpumask_empty(&cpus_stop_mask) && (wait || timeout--))
225 udelay(1);
226 }
227
228 local_irq_save(flags);
229 disable_local_APIC();
230 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
231 local_irq_restore(flags);
232
233 /*
234 * Ensure that the cpus_stop_mask cache lines are invalidated on
235 * the other CPUs. See comment vs. SME in stop_this_cpu().
236 */
237 cpumask_clear(&cpus_stop_mask);
238}
239
240/*
241 * Reschedule call back. KVM uses this interrupt to force a cpu out of
242 * guest mode.
243 */
244DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_reschedule_ipi)
245{
246 apic_eoi();
247 trace_reschedule_entry(RESCHEDULE_VECTOR);
248 inc_irq_stat(irq_resched_count);
249 scheduler_ipi();
250 trace_reschedule_exit(RESCHEDULE_VECTOR);
251}
252
253DEFINE_IDTENTRY_SYSVEC(sysvec_call_function)
254{
255 apic_eoi();
256 trace_call_function_entry(CALL_FUNCTION_VECTOR);
257 inc_irq_stat(irq_call_count);
258 generic_smp_call_function_interrupt();
259 trace_call_function_exit(CALL_FUNCTION_VECTOR);
260}
261
262DEFINE_IDTENTRY_SYSVEC(sysvec_call_function_single)
263{
264 apic_eoi();
265 trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR);
266 inc_irq_stat(irq_call_count);
267 generic_smp_call_function_single_interrupt();
268 trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR);
269}
270
271static int __init nonmi_ipi_setup(char *str)
272{
273 smp_no_nmi_ipi = true;
274 return 1;
275}
276
277__setup("nonmi_ipi", nonmi_ipi_setup);
278
279struct smp_ops smp_ops = {
280 .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu,
281 .smp_prepare_cpus = native_smp_prepare_cpus,
282 .smp_cpus_done = native_smp_cpus_done,
283
284 .stop_other_cpus = native_stop_other_cpus,
285#if defined(CONFIG_KEXEC_CORE)
286 .crash_stop_other_cpus = kdump_nmi_shootdown_cpus,
287#endif
288 .smp_send_reschedule = native_smp_send_reschedule,
289
290 .kick_ap_alive = native_kick_ap,
291 .cpu_disable = native_cpu_disable,
292 .play_dead = native_play_dead,
293
294 .send_call_func_ipi = native_send_call_func_ipi,
295 .send_call_func_single_ipi = native_send_call_func_single_ipi,
296};
297EXPORT_SYMBOL_GPL(smp_ops);