1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Rockchip Generic Register Files setup
  4 *
  5 * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
  6 */
  7
  8#include <linux/err.h>
  9#include <linux/mfd/syscon.h>
 10#include <linux/of_device.h>
 11#include <linux/platform_device.h>
 12#include <linux/regmap.h>
 13
 14#define HIWORD_UPDATE(val, mask, shift) \
 15		((val) << (shift) | (mask) << ((shift) + 16))
 16
 17struct rockchip_grf_value {
 18	const char *desc;
 19	u32 reg;
 20	u32 val;
 21};
 22
 23struct rockchip_grf_info {
 24	const struct rockchip_grf_value *values;
 25	int num_values;
 26};
 27
 28#define RK3036_GRF_SOC_CON0		0x140
 29
 30static const struct rockchip_grf_value rk3036_defaults[] __initconst = {
 31	/*
 32	 * Disable auto jtag/sdmmc switching that causes issues with the
 33	 * clock-framework and the mmc controllers making them unreliable.
 34	 */
 35	{ "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
 36};
 37
 38static const struct rockchip_grf_info rk3036_grf __initconst = {
 39	.values = rk3036_defaults,
 40	.num_values = ARRAY_SIZE(rk3036_defaults),
 41};
 42
 43#define RK3128_GRF_SOC_CON0		0x140
 44
 45static const struct rockchip_grf_value rk3128_defaults[] __initconst = {
 46	{ "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
 47};
 48
 49static const struct rockchip_grf_info rk3128_grf __initconst = {
 50	.values = rk3128_defaults,
 51	.num_values = ARRAY_SIZE(rk3128_defaults),
 52};
 53
 54#define RK3228_GRF_SOC_CON6		0x418
 55
 56static const struct rockchip_grf_value rk3228_defaults[] __initconst = {
 57	{ "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
 58};
 59
 60static const struct rockchip_grf_info rk3228_grf __initconst = {
 61	.values = rk3228_defaults,
 62	.num_values = ARRAY_SIZE(rk3228_defaults),
 63};
 64
 65#define RK3288_GRF_SOC_CON0		0x244
 66#define RK3288_GRF_SOC_CON2		0x24c
 67
 68static const struct rockchip_grf_value rk3288_defaults[] __initconst = {
 69	{ "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
 70	{ "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
 71};
 72
 73static const struct rockchip_grf_info rk3288_grf __initconst = {
 74	.values = rk3288_defaults,
 75	.num_values = ARRAY_SIZE(rk3288_defaults),
 76};
 77
 78#define RK3328_GRF_SOC_CON4		0x410
 79
 80static const struct rockchip_grf_value rk3328_defaults[] __initconst = {
 81	{ "jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12) },
 82};
 83
 84static const struct rockchip_grf_info rk3328_grf __initconst = {
 85	.values = rk3328_defaults,
 86	.num_values = ARRAY_SIZE(rk3328_defaults),
 87};
 88
 89#define RK3368_GRF_SOC_CON15		0x43c
 90
 91static const struct rockchip_grf_value rk3368_defaults[] __initconst = {
 92	{ "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) },
 93};
 94
 95static const struct rockchip_grf_info rk3368_grf __initconst = {
 96	.values = rk3368_defaults,
 97	.num_values = ARRAY_SIZE(rk3368_defaults),
 98};
 99
100#define RK3399_GRF_SOC_CON7		0xe21c
101
102static const struct rockchip_grf_value rk3399_defaults[] __initconst = {
103	{ "jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12) },
104};
105
106static const struct rockchip_grf_info rk3399_grf __initconst = {
107	.values = rk3399_defaults,
108	.num_values = ARRAY_SIZE(rk3399_defaults),
109};
110
111#define RK3566_GRF_USB3OTG0_CON1	0x0104
112
113static const struct rockchip_grf_value rk3566_defaults[] __initconst = {
114	{ "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) },
115	{ "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) },
116	{ "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) },
117};
118
119static const struct rockchip_grf_info rk3566_pipegrf __initconst = {
120	.values = rk3566_defaults,
121	.num_values = ARRAY_SIZE(rk3566_defaults),
122};
123
124
125static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
126	{
127		.compatible = "rockchip,rk3036-grf",
128		.data = (void *)&rk3036_grf,
129	}, {
130		.compatible = "rockchip,rk3128-grf",
131		.data = (void *)&rk3128_grf,
132	}, {
133		.compatible = "rockchip,rk3228-grf",
134		.data = (void *)&rk3228_grf,
135	}, {
136		.compatible = "rockchip,rk3288-grf",
137		.data = (void *)&rk3288_grf,
138	}, {
139		.compatible = "rockchip,rk3328-grf",
140		.data = (void *)&rk3328_grf,
141	}, {
142		.compatible = "rockchip,rk3368-grf",
143		.data = (void *)&rk3368_grf,
144	}, {
145		.compatible = "rockchip,rk3399-grf",
146		.data = (void *)&rk3399_grf,
147	}, {
148		.compatible = "rockchip,rk3566-pipe-grf",
149		.data = (void *)&rk3566_pipegrf,
150	},
151	{ /* sentinel */ },
152};
153
154static int __init rockchip_grf_init(void)
155{
156	const struct rockchip_grf_info *grf_info;
157	const struct of_device_id *match;
158	struct device_node *np;
159	struct regmap *grf;
160	int ret, i;
161
162	np = of_find_matching_node_and_match(NULL, rockchip_grf_dt_match,
163					     &match);
164	if (!np)
165		return -ENODEV;
166	if (!match || !match->data) {
167		pr_err("%s: missing grf data\n", __func__);
168		of_node_put(np);
169		return -EINVAL;
170	}
171
172	grf_info = match->data;
173
174	grf = syscon_node_to_regmap(np);
175	of_node_put(np);
176	if (IS_ERR(grf)) {
177		pr_err("%s: could not get grf syscon\n", __func__);
178		return PTR_ERR(grf);
179	}
180
181	for (i = 0; i < grf_info->num_values; i++) {
182		const struct rockchip_grf_value *val = &grf_info->values[i];
183
184		pr_debug("%s: adjusting %s in %#6x to %#10x\n", __func__,
185			val->desc, val->reg, val->val);
186		ret = regmap_write(grf, val->reg, val->val);
187		if (ret < 0)
188			pr_err("%s: write to %#6x failed with %d\n",
189			       __func__, val->reg, ret);
190	}
191
192	return 0;
193}
194postcore_initcall(rockchip_grf_init);