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1/*
2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/signal.h>
11#include <linux/slab.h>
12#include <linux/module.h>
13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
16#include <linux/ethtool.h>
17#include <linux/usb.h>
18#include <linux/crc32.h>
19#include <linux/if_vlan.h>
20#include <linux/uaccess.h>
21#include <linux/list.h>
22#include <linux/ip.h>
23#include <linux/ipv6.h>
24#include <net/ip6_checksum.h>
25
26/* Version Information */
27#define DRIVER_VERSION "v1.06.0 (2014/03/03)"
28#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
29#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
30#define MODULENAME "r8152"
31
32#define R8152_PHY_ID 32
33
34#define PLA_IDR 0xc000
35#define PLA_RCR 0xc010
36#define PLA_RMS 0xc016
37#define PLA_RXFIFO_CTRL0 0xc0a0
38#define PLA_RXFIFO_CTRL1 0xc0a4
39#define PLA_RXFIFO_CTRL2 0xc0a8
40#define PLA_FMC 0xc0b4
41#define PLA_CFG_WOL 0xc0b6
42#define PLA_TEREDO_CFG 0xc0bc
43#define PLA_MAR 0xcd00
44#define PLA_BACKUP 0xd000
45#define PAL_BDC_CR 0xd1a0
46#define PLA_TEREDO_TIMER 0xd2cc
47#define PLA_REALWOW_TIMER 0xd2e8
48#define PLA_LEDSEL 0xdd90
49#define PLA_LED_FEATURE 0xdd92
50#define PLA_PHYAR 0xde00
51#define PLA_BOOT_CTRL 0xe004
52#define PLA_GPHY_INTR_IMR 0xe022
53#define PLA_EEE_CR 0xe040
54#define PLA_EEEP_CR 0xe080
55#define PLA_MAC_PWR_CTRL 0xe0c0
56#define PLA_MAC_PWR_CTRL2 0xe0ca
57#define PLA_MAC_PWR_CTRL3 0xe0cc
58#define PLA_MAC_PWR_CTRL4 0xe0ce
59#define PLA_WDT6_CTRL 0xe428
60#define PLA_TCR0 0xe610
61#define PLA_TCR1 0xe612
62#define PLA_TXFIFO_CTRL 0xe618
63#define PLA_RSTTALLY 0xe800
64#define PLA_CR 0xe813
65#define PLA_CRWECR 0xe81c
66#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
67#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
68#define PLA_CONFIG5 0xe822
69#define PLA_PHY_PWR 0xe84c
70#define PLA_OOB_CTRL 0xe84f
71#define PLA_CPCR 0xe854
72#define PLA_MISC_0 0xe858
73#define PLA_MISC_1 0xe85a
74#define PLA_OCP_GPHY_BASE 0xe86c
75#define PLA_TALLYCNT 0xe890
76#define PLA_SFF_STS_7 0xe8de
77#define PLA_PHYSTATUS 0xe908
78#define PLA_BP_BA 0xfc26
79#define PLA_BP_0 0xfc28
80#define PLA_BP_1 0xfc2a
81#define PLA_BP_2 0xfc2c
82#define PLA_BP_3 0xfc2e
83#define PLA_BP_4 0xfc30
84#define PLA_BP_5 0xfc32
85#define PLA_BP_6 0xfc34
86#define PLA_BP_7 0xfc36
87#define PLA_BP_EN 0xfc38
88
89#define USB_U2P3_CTRL 0xb460
90#define USB_DEV_STAT 0xb808
91#define USB_USB_CTRL 0xd406
92#define USB_PHY_CTRL 0xd408
93#define USB_TX_AGG 0xd40a
94#define USB_RX_BUF_TH 0xd40c
95#define USB_USB_TIMER 0xd428
96#define USB_RX_EARLY_AGG 0xd42c
97#define USB_PM_CTRL_STATUS 0xd432
98#define USB_TX_DMA 0xd434
99#define USB_TOLERANCE 0xd490
100#define USB_LPM_CTRL 0xd41a
101#define USB_UPS_CTRL 0xd800
102#define USB_MISC_0 0xd81a
103#define USB_POWER_CUT 0xd80a
104#define USB_AFE_CTRL2 0xd824
105#define USB_WDT11_CTRL 0xe43c
106#define USB_BP_BA 0xfc26
107#define USB_BP_0 0xfc28
108#define USB_BP_1 0xfc2a
109#define USB_BP_2 0xfc2c
110#define USB_BP_3 0xfc2e
111#define USB_BP_4 0xfc30
112#define USB_BP_5 0xfc32
113#define USB_BP_6 0xfc34
114#define USB_BP_7 0xfc36
115#define USB_BP_EN 0xfc38
116
117/* OCP Registers */
118#define OCP_ALDPS_CONFIG 0x2010
119#define OCP_EEE_CONFIG1 0x2080
120#define OCP_EEE_CONFIG2 0x2092
121#define OCP_EEE_CONFIG3 0x2094
122#define OCP_BASE_MII 0xa400
123#define OCP_EEE_AR 0xa41a
124#define OCP_EEE_DATA 0xa41c
125#define OCP_PHY_STATUS 0xa420
126#define OCP_POWER_CFG 0xa430
127#define OCP_EEE_CFG 0xa432
128#define OCP_SRAM_ADDR 0xa436
129#define OCP_SRAM_DATA 0xa438
130#define OCP_DOWN_SPEED 0xa442
131#define OCP_EEE_CFG2 0xa5d0
132#define OCP_ADC_CFG 0xbc06
133
134/* SRAM Register */
135#define SRAM_LPF_CFG 0x8012
136#define SRAM_10M_AMP1 0x8080
137#define SRAM_10M_AMP2 0x8082
138#define SRAM_IMPEDANCE 0x8084
139
140/* PLA_RCR */
141#define RCR_AAP 0x00000001
142#define RCR_APM 0x00000002
143#define RCR_AM 0x00000004
144#define RCR_AB 0x00000008
145#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
146
147/* PLA_RXFIFO_CTRL0 */
148#define RXFIFO_THR1_NORMAL 0x00080002
149#define RXFIFO_THR1_OOB 0x01800003
150
151/* PLA_RXFIFO_CTRL1 */
152#define RXFIFO_THR2_FULL 0x00000060
153#define RXFIFO_THR2_HIGH 0x00000038
154#define RXFIFO_THR2_OOB 0x0000004a
155#define RXFIFO_THR2_NORMAL 0x00a0
156
157/* PLA_RXFIFO_CTRL2 */
158#define RXFIFO_THR3_FULL 0x00000078
159#define RXFIFO_THR3_HIGH 0x00000048
160#define RXFIFO_THR3_OOB 0x0000005a
161#define RXFIFO_THR3_NORMAL 0x0110
162
163/* PLA_TXFIFO_CTRL */
164#define TXFIFO_THR_NORMAL 0x00400008
165#define TXFIFO_THR_NORMAL2 0x01000008
166
167/* PLA_FMC */
168#define FMC_FCR_MCU_EN 0x0001
169
170/* PLA_EEEP_CR */
171#define EEEP_CR_EEEP_TX 0x0002
172
173/* PLA_WDT6_CTRL */
174#define WDT6_SET_MODE 0x0010
175
176/* PLA_TCR0 */
177#define TCR0_TX_EMPTY 0x0800
178#define TCR0_AUTO_FIFO 0x0080
179
180/* PLA_TCR1 */
181#define VERSION_MASK 0x7cf0
182
183/* PLA_RSTTALLY */
184#define TALLY_RESET 0x0001
185
186/* PLA_CR */
187#define CR_RST 0x10
188#define CR_RE 0x08
189#define CR_TE 0x04
190
191/* PLA_CRWECR */
192#define CRWECR_NORAML 0x00
193#define CRWECR_CONFIG 0xc0
194
195/* PLA_OOB_CTRL */
196#define NOW_IS_OOB 0x80
197#define TXFIFO_EMPTY 0x20
198#define RXFIFO_EMPTY 0x10
199#define LINK_LIST_READY 0x02
200#define DIS_MCU_CLROOB 0x01
201#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
202
203/* PLA_MISC_1 */
204#define RXDY_GATED_EN 0x0008
205
206/* PLA_SFF_STS_7 */
207#define RE_INIT_LL 0x8000
208#define MCU_BORW_EN 0x4000
209
210/* PLA_CPCR */
211#define CPCR_RX_VLAN 0x0040
212
213/* PLA_CFG_WOL */
214#define MAGIC_EN 0x0001
215
216/* PLA_TEREDO_CFG */
217#define TEREDO_SEL 0x8000
218#define TEREDO_WAKE_MASK 0x7f00
219#define TEREDO_RS_EVENT_MASK 0x00fe
220#define OOB_TEREDO_EN 0x0001
221
222/* PAL_BDC_CR */
223#define ALDPS_PROXY_MODE 0x0001
224
225/* PLA_CONFIG34 */
226#define LINK_ON_WAKE_EN 0x0010
227#define LINK_OFF_WAKE_EN 0x0008
228
229/* PLA_CONFIG5 */
230#define BWF_EN 0x0040
231#define MWF_EN 0x0020
232#define UWF_EN 0x0010
233#define LAN_WAKE_EN 0x0002
234
235/* PLA_LED_FEATURE */
236#define LED_MODE_MASK 0x0700
237
238/* PLA_PHY_PWR */
239#define TX_10M_IDLE_EN 0x0080
240#define PFM_PWM_SWITCH 0x0040
241
242/* PLA_MAC_PWR_CTRL */
243#define D3_CLK_GATED_EN 0x00004000
244#define MCU_CLK_RATIO 0x07010f07
245#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
246#define ALDPS_SPDWN_RATIO 0x0f87
247
248/* PLA_MAC_PWR_CTRL2 */
249#define EEE_SPDWN_RATIO 0x8007
250
251/* PLA_MAC_PWR_CTRL3 */
252#define PKT_AVAIL_SPDWN_EN 0x0100
253#define SUSPEND_SPDWN_EN 0x0004
254#define U1U2_SPDWN_EN 0x0002
255#define L1_SPDWN_EN 0x0001
256
257/* PLA_MAC_PWR_CTRL4 */
258#define PWRSAVE_SPDWN_EN 0x1000
259#define RXDV_SPDWN_EN 0x0800
260#define TX10MIDLE_EN 0x0100
261#define TP100_SPDWN_EN 0x0020
262#define TP500_SPDWN_EN 0x0010
263#define TP1000_SPDWN_EN 0x0008
264#define EEE_SPDWN_EN 0x0001
265
266/* PLA_GPHY_INTR_IMR */
267#define GPHY_STS_MSK 0x0001
268#define SPEED_DOWN_MSK 0x0002
269#define SPDWN_RXDV_MSK 0x0004
270#define SPDWN_LINKCHG_MSK 0x0008
271
272/* PLA_PHYAR */
273#define PHYAR_FLAG 0x80000000
274
275/* PLA_EEE_CR */
276#define EEE_RX_EN 0x0001
277#define EEE_TX_EN 0x0002
278
279/* PLA_BOOT_CTRL */
280#define AUTOLOAD_DONE 0x0002
281
282/* USB_DEV_STAT */
283#define STAT_SPEED_MASK 0x0006
284#define STAT_SPEED_HIGH 0x0000
285#define STAT_SPEED_FULL 0x0001
286
287/* USB_TX_AGG */
288#define TX_AGG_MAX_THRESHOLD 0x03
289
290/* USB_RX_BUF_TH */
291#define RX_THR_SUPPER 0x0c350180
292#define RX_THR_HIGH 0x7a120180
293#define RX_THR_SLOW 0xffff0180
294
295/* USB_TX_DMA */
296#define TEST_MODE_DISABLE 0x00000001
297#define TX_SIZE_ADJUST1 0x00000100
298
299/* USB_UPS_CTRL */
300#define POWER_CUT 0x0100
301
302/* USB_PM_CTRL_STATUS */
303#define RESUME_INDICATE 0x0001
304
305/* USB_USB_CTRL */
306#define RX_AGG_DISABLE 0x0010
307
308/* USB_U2P3_CTRL */
309#define U2P3_ENABLE 0x0001
310
311/* USB_POWER_CUT */
312#define PWR_EN 0x0001
313#define PHASE2_EN 0x0008
314
315/* USB_MISC_0 */
316#define PCUT_STATUS 0x0001
317
318/* USB_RX_EARLY_AGG */
319#define EARLY_AGG_SUPPER 0x0e832981
320#define EARLY_AGG_HIGH 0x0e837a12
321#define EARLY_AGG_SLOW 0x0e83ffff
322
323/* USB_WDT11_CTRL */
324#define TIMER11_EN 0x0001
325
326/* USB_LPM_CTRL */
327#define LPM_TIMER_MASK 0x0c
328#define LPM_TIMER_500MS 0x04 /* 500 ms */
329#define LPM_TIMER_500US 0x0c /* 500 us */
330
331/* USB_AFE_CTRL2 */
332#define SEN_VAL_MASK 0xf800
333#define SEN_VAL_NORMAL 0xa000
334#define SEL_RXIDLE 0x0100
335
336/* OCP_ALDPS_CONFIG */
337#define ENPWRSAVE 0x8000
338#define ENPDNPS 0x0200
339#define LINKENA 0x0100
340#define DIS_SDSAVE 0x0010
341
342/* OCP_PHY_STATUS */
343#define PHY_STAT_MASK 0x0007
344#define PHY_STAT_LAN_ON 3
345#define PHY_STAT_PWRDN 5
346
347/* OCP_POWER_CFG */
348#define EEE_CLKDIV_EN 0x8000
349#define EN_ALDPS 0x0004
350#define EN_10M_PLLOFF 0x0001
351
352/* OCP_EEE_CONFIG1 */
353#define RG_TXLPI_MSK_HFDUP 0x8000
354#define RG_MATCLR_EN 0x4000
355#define EEE_10_CAP 0x2000
356#define EEE_NWAY_EN 0x1000
357#define TX_QUIET_EN 0x0200
358#define RX_QUIET_EN 0x0100
359#define SDRISETIME 0x0010 /* bit 4 ~ 6 */
360#define RG_RXLPI_MSK_HFDUP 0x0008
361#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
362
363/* OCP_EEE_CONFIG2 */
364#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
365#define RG_DACQUIET_EN 0x0400
366#define RG_LDVQUIET_EN 0x0200
367#define RG_CKRSEL 0x0020
368#define RG_EEEPRG_EN 0x0010
369
370/* OCP_EEE_CONFIG3 */
371#define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
372#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
373#define MSK_PH 0x0006 /* bit 0 ~ 3 */
374
375/* OCP_EEE_AR */
376/* bit[15:14] function */
377#define FUN_ADDR 0x0000
378#define FUN_DATA 0x4000
379/* bit[4:0] device addr */
380#define DEVICE_ADDR 0x0007
381
382/* OCP_EEE_DATA */
383#define EEE_ADDR 0x003C
384#define EEE_DATA 0x0002
385
386/* OCP_EEE_CFG */
387#define CTAP_SHORT_EN 0x0040
388#define EEE10_EN 0x0010
389
390/* OCP_DOWN_SPEED */
391#define EN_10M_BGOFF 0x0080
392
393/* OCP_EEE_CFG2 */
394#define MY1000_EEE 0x0004
395#define MY100_EEE 0x0002
396
397/* OCP_ADC_CFG */
398#define CKADSEL_L 0x0100
399#define ADC_EN 0x0080
400#define EN_EMI_L 0x0040
401
402/* SRAM_LPF_CFG */
403#define LPF_AUTO_TUNE 0x8000
404
405/* SRAM_10M_AMP1 */
406#define GDAC_IB_UPALL 0x0008
407
408/* SRAM_10M_AMP2 */
409#define AMP_DN 0x0200
410
411/* SRAM_IMPEDANCE */
412#define RX_DRIVING_MASK 0x6000
413
414enum rtl_register_content {
415 _1000bps = 0x10,
416 _100bps = 0x08,
417 _10bps = 0x04,
418 LINK_STATUS = 0x02,
419 FULL_DUP = 0x01,
420};
421
422#define RTL8152_MAX_TX 10
423#define RTL8152_MAX_RX 10
424#define INTBUFSIZE 2
425#define CRC_SIZE 4
426#define TX_ALIGN 4
427#define RX_ALIGN 8
428
429#define INTR_LINK 0x0004
430
431#define RTL8152_REQT_READ 0xc0
432#define RTL8152_REQT_WRITE 0x40
433#define RTL8152_REQ_GET_REGS 0x05
434#define RTL8152_REQ_SET_REGS 0x05
435
436#define BYTE_EN_DWORD 0xff
437#define BYTE_EN_WORD 0x33
438#define BYTE_EN_BYTE 0x11
439#define BYTE_EN_SIX_BYTES 0x3f
440#define BYTE_EN_START_MASK 0x0f
441#define BYTE_EN_END_MASK 0xf0
442
443#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
444#define RTL8152_TX_TIMEOUT (HZ)
445
446/* rtl8152 flags */
447enum rtl8152_flags {
448 RTL8152_UNPLUG = 0,
449 RTL8152_SET_RX_MODE,
450 WORK_ENABLE,
451 RTL8152_LINK_CHG,
452 SELECTIVE_SUSPEND,
453 PHY_RESET,
454 SCHEDULE_TASKLET,
455};
456
457/* Define these values to match your device */
458#define VENDOR_ID_REALTEK 0x0bda
459#define PRODUCT_ID_RTL8152 0x8152
460#define PRODUCT_ID_RTL8153 0x8153
461
462#define VENDOR_ID_SAMSUNG 0x04e8
463#define PRODUCT_ID_SAMSUNG 0xa101
464
465#define MCU_TYPE_PLA 0x0100
466#define MCU_TYPE_USB 0x0000
467
468#define REALTEK_USB_DEVICE(vend, prod) \
469 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
470
471struct tally_counter {
472 __le64 tx_packets;
473 __le64 rx_packets;
474 __le64 tx_errors;
475 __le32 rx_errors;
476 __le16 rx_missed;
477 __le16 align_errors;
478 __le32 tx_one_collision;
479 __le32 tx_multi_collision;
480 __le64 rx_unicast;
481 __le64 rx_broadcast;
482 __le32 rx_multicast;
483 __le16 tx_aborted;
484 __le16 tx_underun;
485};
486
487struct rx_desc {
488 __le32 opts1;
489#define RX_LEN_MASK 0x7fff
490
491 __le32 opts2;
492#define RD_UDP_CS (1 << 23)
493#define RD_TCP_CS (1 << 22)
494#define RD_IPV6_CS (1 << 20)
495#define RD_IPV4_CS (1 << 19)
496
497 __le32 opts3;
498#define IPF (1 << 23) /* IP checksum fail */
499#define UDPF (1 << 22) /* UDP checksum fail */
500#define TCPF (1 << 21) /* TCP checksum fail */
501
502 __le32 opts4;
503 __le32 opts5;
504 __le32 opts6;
505};
506
507struct tx_desc {
508 __le32 opts1;
509#define TX_FS (1 << 31) /* First segment of a packet */
510#define TX_LS (1 << 30) /* Final segment of a packet */
511#define GTSENDV4 (1 << 28)
512#define GTSENDV6 (1 << 27)
513#define GTTCPHO_SHIFT 18
514#define GTTCPHO_MAX 0x7fU
515#define TX_LEN_MAX 0x3ffffU
516
517 __le32 opts2;
518#define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
519#define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
520#define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
521#define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
522#define MSS_SHIFT 17
523#define MSS_MAX 0x7ffU
524#define TCPHO_SHIFT 17
525#define TCPHO_MAX 0x7ffU
526};
527
528struct r8152;
529
530struct rx_agg {
531 struct list_head list;
532 struct urb *urb;
533 struct r8152 *context;
534 void *buffer;
535 void *head;
536};
537
538struct tx_agg {
539 struct list_head list;
540 struct urb *urb;
541 struct r8152 *context;
542 void *buffer;
543 void *head;
544 u32 skb_num;
545 u32 skb_len;
546};
547
548struct r8152 {
549 unsigned long flags;
550 struct usb_device *udev;
551 struct tasklet_struct tl;
552 struct usb_interface *intf;
553 struct net_device *netdev;
554 struct urb *intr_urb;
555 struct tx_agg tx_info[RTL8152_MAX_TX];
556 struct rx_agg rx_info[RTL8152_MAX_RX];
557 struct list_head rx_done, tx_free;
558 struct sk_buff_head tx_queue;
559 spinlock_t rx_lock, tx_lock;
560 struct delayed_work schedule;
561 struct mii_if_info mii;
562
563 struct rtl_ops {
564 void (*init)(struct r8152 *);
565 int (*enable)(struct r8152 *);
566 void (*disable)(struct r8152 *);
567 void (*up)(struct r8152 *);
568 void (*down)(struct r8152 *);
569 void (*unload)(struct r8152 *);
570 } rtl_ops;
571
572 int intr_interval;
573 u32 saved_wolopts;
574 u32 msg_enable;
575 u32 tx_qlen;
576 u16 ocp_base;
577 u8 *intr_buff;
578 u8 version;
579 u8 speed;
580};
581
582enum rtl_version {
583 RTL_VER_UNKNOWN = 0,
584 RTL_VER_01,
585 RTL_VER_02,
586 RTL_VER_03,
587 RTL_VER_04,
588 RTL_VER_05,
589 RTL_VER_MAX
590};
591
592enum tx_csum_stat {
593 TX_CSUM_SUCCESS = 0,
594 TX_CSUM_TSO,
595 TX_CSUM_NONE
596};
597
598/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
599 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
600 */
601static const int multicast_filter_limit = 32;
602static unsigned int rx_buf_sz = 16384;
603
604#define RTL_LIMITED_TSO_SIZE (rx_buf_sz - sizeof(struct tx_desc) - \
605 VLAN_ETH_HLEN - VLAN_HLEN)
606
607static
608int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
609{
610 int ret;
611 void *tmp;
612
613 tmp = kmalloc(size, GFP_KERNEL);
614 if (!tmp)
615 return -ENOMEM;
616
617 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
618 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
619 value, index, tmp, size, 500);
620
621 memcpy(data, tmp, size);
622 kfree(tmp);
623
624 return ret;
625}
626
627static
628int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
629{
630 int ret;
631 void *tmp;
632
633 tmp = kmalloc(size, GFP_KERNEL);
634 if (!tmp)
635 return -ENOMEM;
636
637 memcpy(tmp, data, size);
638
639 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
640 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
641 value, index, tmp, size, 500);
642
643 kfree(tmp);
644
645 return ret;
646}
647
648static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
649 void *data, u16 type)
650{
651 u16 limit = 64;
652 int ret = 0;
653
654 if (test_bit(RTL8152_UNPLUG, &tp->flags))
655 return -ENODEV;
656
657 /* both size and indix must be 4 bytes align */
658 if ((size & 3) || !size || (index & 3) || !data)
659 return -EPERM;
660
661 if ((u32)index + (u32)size > 0xffff)
662 return -EPERM;
663
664 while (size) {
665 if (size > limit) {
666 ret = get_registers(tp, index, type, limit, data);
667 if (ret < 0)
668 break;
669
670 index += limit;
671 data += limit;
672 size -= limit;
673 } else {
674 ret = get_registers(tp, index, type, size, data);
675 if (ret < 0)
676 break;
677
678 index += size;
679 data += size;
680 size = 0;
681 break;
682 }
683 }
684
685 return ret;
686}
687
688static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
689 u16 size, void *data, u16 type)
690{
691 int ret;
692 u16 byteen_start, byteen_end, byen;
693 u16 limit = 512;
694
695 if (test_bit(RTL8152_UNPLUG, &tp->flags))
696 return -ENODEV;
697
698 /* both size and indix must be 4 bytes align */
699 if ((size & 3) || !size || (index & 3) || !data)
700 return -EPERM;
701
702 if ((u32)index + (u32)size > 0xffff)
703 return -EPERM;
704
705 byteen_start = byteen & BYTE_EN_START_MASK;
706 byteen_end = byteen & BYTE_EN_END_MASK;
707
708 byen = byteen_start | (byteen_start << 4);
709 ret = set_registers(tp, index, type | byen, 4, data);
710 if (ret < 0)
711 goto error1;
712
713 index += 4;
714 data += 4;
715 size -= 4;
716
717 if (size) {
718 size -= 4;
719
720 while (size) {
721 if (size > limit) {
722 ret = set_registers(tp, index,
723 type | BYTE_EN_DWORD,
724 limit, data);
725 if (ret < 0)
726 goto error1;
727
728 index += limit;
729 data += limit;
730 size -= limit;
731 } else {
732 ret = set_registers(tp, index,
733 type | BYTE_EN_DWORD,
734 size, data);
735 if (ret < 0)
736 goto error1;
737
738 index += size;
739 data += size;
740 size = 0;
741 break;
742 }
743 }
744
745 byen = byteen_end | (byteen_end >> 4);
746 ret = set_registers(tp, index, type | byen, 4, data);
747 if (ret < 0)
748 goto error1;
749 }
750
751error1:
752 return ret;
753}
754
755static inline
756int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
757{
758 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
759}
760
761static inline
762int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
763{
764 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
765}
766
767static inline
768int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
769{
770 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
771}
772
773static inline
774int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
775{
776 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
777}
778
779static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
780{
781 __le32 data;
782
783 generic_ocp_read(tp, index, sizeof(data), &data, type);
784
785 return __le32_to_cpu(data);
786}
787
788static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
789{
790 __le32 tmp = __cpu_to_le32(data);
791
792 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
793}
794
795static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
796{
797 u32 data;
798 __le32 tmp;
799 u8 shift = index & 2;
800
801 index &= ~3;
802
803 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
804
805 data = __le32_to_cpu(tmp);
806 data >>= (shift * 8);
807 data &= 0xffff;
808
809 return (u16)data;
810}
811
812static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
813{
814 u32 mask = 0xffff;
815 __le32 tmp;
816 u16 byen = BYTE_EN_WORD;
817 u8 shift = index & 2;
818
819 data &= mask;
820
821 if (index & 2) {
822 byen <<= shift;
823 mask <<= (shift * 8);
824 data <<= (shift * 8);
825 index &= ~3;
826 }
827
828 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
829
830 data |= __le32_to_cpu(tmp) & ~mask;
831 tmp = __cpu_to_le32(data);
832
833 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
834}
835
836static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
837{
838 u32 data;
839 __le32 tmp;
840 u8 shift = index & 3;
841
842 index &= ~3;
843
844 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
845
846 data = __le32_to_cpu(tmp);
847 data >>= (shift * 8);
848 data &= 0xff;
849
850 return (u8)data;
851}
852
853static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
854{
855 u32 mask = 0xff;
856 __le32 tmp;
857 u16 byen = BYTE_EN_BYTE;
858 u8 shift = index & 3;
859
860 data &= mask;
861
862 if (index & 3) {
863 byen <<= shift;
864 mask <<= (shift * 8);
865 data <<= (shift * 8);
866 index &= ~3;
867 }
868
869 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
870
871 data |= __le32_to_cpu(tmp) & ~mask;
872 tmp = __cpu_to_le32(data);
873
874 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
875}
876
877static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
878{
879 u16 ocp_base, ocp_index;
880
881 ocp_base = addr & 0xf000;
882 if (ocp_base != tp->ocp_base) {
883 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
884 tp->ocp_base = ocp_base;
885 }
886
887 ocp_index = (addr & 0x0fff) | 0xb000;
888 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
889}
890
891static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
892{
893 u16 ocp_base, ocp_index;
894
895 ocp_base = addr & 0xf000;
896 if (ocp_base != tp->ocp_base) {
897 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
898 tp->ocp_base = ocp_base;
899 }
900
901 ocp_index = (addr & 0x0fff) | 0xb000;
902 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
903}
904
905static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
906{
907 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
908}
909
910static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
911{
912 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
913}
914
915static void sram_write(struct r8152 *tp, u16 addr, u16 data)
916{
917 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
918 ocp_reg_write(tp, OCP_SRAM_DATA, data);
919}
920
921static u16 sram_read(struct r8152 *tp, u16 addr)
922{
923 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
924 return ocp_reg_read(tp, OCP_SRAM_DATA);
925}
926
927static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
928{
929 struct r8152 *tp = netdev_priv(netdev);
930 int ret;
931
932 if (test_bit(RTL8152_UNPLUG, &tp->flags))
933 return -ENODEV;
934
935 if (phy_id != R8152_PHY_ID)
936 return -EINVAL;
937
938 ret = usb_autopm_get_interface(tp->intf);
939 if (ret < 0)
940 goto out;
941
942 ret = r8152_mdio_read(tp, reg);
943
944 usb_autopm_put_interface(tp->intf);
945
946out:
947 return ret;
948}
949
950static
951void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
952{
953 struct r8152 *tp = netdev_priv(netdev);
954
955 if (test_bit(RTL8152_UNPLUG, &tp->flags))
956 return;
957
958 if (phy_id != R8152_PHY_ID)
959 return;
960
961 if (usb_autopm_get_interface(tp->intf) < 0)
962 return;
963
964 r8152_mdio_write(tp, reg, val);
965
966 usb_autopm_put_interface(tp->intf);
967}
968
969static
970int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
971
972static inline void set_ethernet_addr(struct r8152 *tp)
973{
974 struct net_device *dev = tp->netdev;
975 int ret;
976 u8 node_id[8] = {0};
977
978 if (tp->version == RTL_VER_01)
979 ret = pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id);
980 else
981 ret = pla_ocp_read(tp, PLA_BACKUP, sizeof(node_id), node_id);
982
983 if (ret < 0) {
984 netif_notice(tp, probe, dev, "inet addr fail\n");
985 } else {
986 if (tp->version != RTL_VER_01) {
987 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR,
988 CRWECR_CONFIG);
989 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES,
990 sizeof(node_id), node_id);
991 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR,
992 CRWECR_NORAML);
993 }
994
995 memcpy(dev->dev_addr, node_id, dev->addr_len);
996 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
997 }
998}
999
1000static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1001{
1002 struct r8152 *tp = netdev_priv(netdev);
1003 struct sockaddr *addr = p;
1004
1005 if (!is_valid_ether_addr(addr->sa_data))
1006 return -EADDRNOTAVAIL;
1007
1008 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1009
1010 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1011 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1012 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1013
1014 return 0;
1015}
1016
1017static void read_bulk_callback(struct urb *urb)
1018{
1019 struct net_device *netdev;
1020 int status = urb->status;
1021 struct rx_agg *agg;
1022 struct r8152 *tp;
1023 int result;
1024
1025 agg = urb->context;
1026 if (!agg)
1027 return;
1028
1029 tp = agg->context;
1030 if (!tp)
1031 return;
1032
1033 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1034 return;
1035
1036 if (!test_bit(WORK_ENABLE, &tp->flags))
1037 return;
1038
1039 netdev = tp->netdev;
1040
1041 /* When link down, the driver would cancel all bulks. */
1042 /* This avoid the re-submitting bulk */
1043 if (!netif_carrier_ok(netdev))
1044 return;
1045
1046 usb_mark_last_busy(tp->udev);
1047
1048 switch (status) {
1049 case 0:
1050 if (urb->actual_length < ETH_ZLEN)
1051 break;
1052
1053 spin_lock(&tp->rx_lock);
1054 list_add_tail(&agg->list, &tp->rx_done);
1055 spin_unlock(&tp->rx_lock);
1056 tasklet_schedule(&tp->tl);
1057 return;
1058 case -ESHUTDOWN:
1059 set_bit(RTL8152_UNPLUG, &tp->flags);
1060 netif_device_detach(tp->netdev);
1061 return;
1062 case -ENOENT:
1063 return; /* the urb is in unlink state */
1064 case -ETIME:
1065 if (net_ratelimit())
1066 netdev_warn(netdev, "maybe reset is needed?\n");
1067 break;
1068 default:
1069 if (net_ratelimit())
1070 netdev_warn(netdev, "Rx status %d\n", status);
1071 break;
1072 }
1073
1074 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1075 if (result == -ENODEV) {
1076 netif_device_detach(tp->netdev);
1077 } else if (result) {
1078 spin_lock(&tp->rx_lock);
1079 list_add_tail(&agg->list, &tp->rx_done);
1080 spin_unlock(&tp->rx_lock);
1081 tasklet_schedule(&tp->tl);
1082 }
1083}
1084
1085static void write_bulk_callback(struct urb *urb)
1086{
1087 struct net_device_stats *stats;
1088 struct net_device *netdev;
1089 struct tx_agg *agg;
1090 struct r8152 *tp;
1091 int status = urb->status;
1092
1093 agg = urb->context;
1094 if (!agg)
1095 return;
1096
1097 tp = agg->context;
1098 if (!tp)
1099 return;
1100
1101 netdev = tp->netdev;
1102 stats = &netdev->stats;
1103 if (status) {
1104 if (net_ratelimit())
1105 netdev_warn(netdev, "Tx status %d\n", status);
1106 stats->tx_errors += agg->skb_num;
1107 } else {
1108 stats->tx_packets += agg->skb_num;
1109 stats->tx_bytes += agg->skb_len;
1110 }
1111
1112 spin_lock(&tp->tx_lock);
1113 list_add_tail(&agg->list, &tp->tx_free);
1114 spin_unlock(&tp->tx_lock);
1115
1116 usb_autopm_put_interface_async(tp->intf);
1117
1118 if (!netif_carrier_ok(netdev))
1119 return;
1120
1121 if (!test_bit(WORK_ENABLE, &tp->flags))
1122 return;
1123
1124 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1125 return;
1126
1127 if (!skb_queue_empty(&tp->tx_queue))
1128 tasklet_schedule(&tp->tl);
1129}
1130
1131static void intr_callback(struct urb *urb)
1132{
1133 struct r8152 *tp;
1134 __le16 *d;
1135 int status = urb->status;
1136 int res;
1137
1138 tp = urb->context;
1139 if (!tp)
1140 return;
1141
1142 if (!test_bit(WORK_ENABLE, &tp->flags))
1143 return;
1144
1145 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1146 return;
1147
1148 switch (status) {
1149 case 0: /* success */
1150 break;
1151 case -ECONNRESET: /* unlink */
1152 case -ESHUTDOWN:
1153 netif_device_detach(tp->netdev);
1154 case -ENOENT:
1155 return;
1156 case -EOVERFLOW:
1157 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1158 goto resubmit;
1159 /* -EPIPE: should clear the halt */
1160 default:
1161 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1162 goto resubmit;
1163 }
1164
1165 d = urb->transfer_buffer;
1166 if (INTR_LINK & __le16_to_cpu(d[0])) {
1167 if (!(tp->speed & LINK_STATUS)) {
1168 set_bit(RTL8152_LINK_CHG, &tp->flags);
1169 schedule_delayed_work(&tp->schedule, 0);
1170 }
1171 } else {
1172 if (tp->speed & LINK_STATUS) {
1173 set_bit(RTL8152_LINK_CHG, &tp->flags);
1174 schedule_delayed_work(&tp->schedule, 0);
1175 }
1176 }
1177
1178resubmit:
1179 res = usb_submit_urb(urb, GFP_ATOMIC);
1180 if (res == -ENODEV)
1181 netif_device_detach(tp->netdev);
1182 else if (res)
1183 netif_err(tp, intr, tp->netdev,
1184 "can't resubmit intr, status %d\n", res);
1185}
1186
1187static inline void *rx_agg_align(void *data)
1188{
1189 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1190}
1191
1192static inline void *tx_agg_align(void *data)
1193{
1194 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1195}
1196
1197static void free_all_mem(struct r8152 *tp)
1198{
1199 int i;
1200
1201 for (i = 0; i < RTL8152_MAX_RX; i++) {
1202 usb_free_urb(tp->rx_info[i].urb);
1203 tp->rx_info[i].urb = NULL;
1204
1205 kfree(tp->rx_info[i].buffer);
1206 tp->rx_info[i].buffer = NULL;
1207 tp->rx_info[i].head = NULL;
1208 }
1209
1210 for (i = 0; i < RTL8152_MAX_TX; i++) {
1211 usb_free_urb(tp->tx_info[i].urb);
1212 tp->tx_info[i].urb = NULL;
1213
1214 kfree(tp->tx_info[i].buffer);
1215 tp->tx_info[i].buffer = NULL;
1216 tp->tx_info[i].head = NULL;
1217 }
1218
1219 usb_free_urb(tp->intr_urb);
1220 tp->intr_urb = NULL;
1221
1222 kfree(tp->intr_buff);
1223 tp->intr_buff = NULL;
1224}
1225
1226static int alloc_all_mem(struct r8152 *tp)
1227{
1228 struct net_device *netdev = tp->netdev;
1229 struct usb_interface *intf = tp->intf;
1230 struct usb_host_interface *alt = intf->cur_altsetting;
1231 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1232 struct urb *urb;
1233 int node, i;
1234 u8 *buf;
1235
1236 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1237
1238 spin_lock_init(&tp->rx_lock);
1239 spin_lock_init(&tp->tx_lock);
1240 INIT_LIST_HEAD(&tp->rx_done);
1241 INIT_LIST_HEAD(&tp->tx_free);
1242 skb_queue_head_init(&tp->tx_queue);
1243
1244 for (i = 0; i < RTL8152_MAX_RX; i++) {
1245 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1246 if (!buf)
1247 goto err1;
1248
1249 if (buf != rx_agg_align(buf)) {
1250 kfree(buf);
1251 buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL,
1252 node);
1253 if (!buf)
1254 goto err1;
1255 }
1256
1257 urb = usb_alloc_urb(0, GFP_KERNEL);
1258 if (!urb) {
1259 kfree(buf);
1260 goto err1;
1261 }
1262
1263 INIT_LIST_HEAD(&tp->rx_info[i].list);
1264 tp->rx_info[i].context = tp;
1265 tp->rx_info[i].urb = urb;
1266 tp->rx_info[i].buffer = buf;
1267 tp->rx_info[i].head = rx_agg_align(buf);
1268 }
1269
1270 for (i = 0; i < RTL8152_MAX_TX; i++) {
1271 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1272 if (!buf)
1273 goto err1;
1274
1275 if (buf != tx_agg_align(buf)) {
1276 kfree(buf);
1277 buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL,
1278 node);
1279 if (!buf)
1280 goto err1;
1281 }
1282
1283 urb = usb_alloc_urb(0, GFP_KERNEL);
1284 if (!urb) {
1285 kfree(buf);
1286 goto err1;
1287 }
1288
1289 INIT_LIST_HEAD(&tp->tx_info[i].list);
1290 tp->tx_info[i].context = tp;
1291 tp->tx_info[i].urb = urb;
1292 tp->tx_info[i].buffer = buf;
1293 tp->tx_info[i].head = tx_agg_align(buf);
1294
1295 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1296 }
1297
1298 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1299 if (!tp->intr_urb)
1300 goto err1;
1301
1302 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1303 if (!tp->intr_buff)
1304 goto err1;
1305
1306 tp->intr_interval = (int)ep_intr->desc.bInterval;
1307 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1308 tp->intr_buff, INTBUFSIZE, intr_callback,
1309 tp, tp->intr_interval);
1310
1311 return 0;
1312
1313err1:
1314 free_all_mem(tp);
1315 return -ENOMEM;
1316}
1317
1318static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1319{
1320 struct tx_agg *agg = NULL;
1321 unsigned long flags;
1322
1323 if (list_empty(&tp->tx_free))
1324 return NULL;
1325
1326 spin_lock_irqsave(&tp->tx_lock, flags);
1327 if (!list_empty(&tp->tx_free)) {
1328 struct list_head *cursor;
1329
1330 cursor = tp->tx_free.next;
1331 list_del_init(cursor);
1332 agg = list_entry(cursor, struct tx_agg, list);
1333 }
1334 spin_unlock_irqrestore(&tp->tx_lock, flags);
1335
1336 return agg;
1337}
1338
1339static inline __be16 get_protocol(struct sk_buff *skb)
1340{
1341 __be16 protocol;
1342
1343 if (skb->protocol == htons(ETH_P_8021Q))
1344 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1345 else
1346 protocol = skb->protocol;
1347
1348 return protocol;
1349}
1350
1351/*
1352 * r8152_csum_workaround()
1353 * The hw limites the value the transport offset. When the offset is out of the
1354 * range, calculate the checksum by sw.
1355 */
1356static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1357 struct sk_buff_head *list)
1358{
1359 if (skb_shinfo(skb)->gso_size) {
1360 netdev_features_t features = tp->netdev->features;
1361 struct sk_buff_head seg_list;
1362 struct sk_buff *segs, *nskb;
1363
1364 features &= ~(NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO);
1365 segs = skb_gso_segment(skb, features);
1366 if (IS_ERR(segs) || !segs)
1367 goto drop;
1368
1369 __skb_queue_head_init(&seg_list);
1370
1371 do {
1372 nskb = segs;
1373 segs = segs->next;
1374 nskb->next = NULL;
1375 __skb_queue_tail(&seg_list, nskb);
1376 } while (segs);
1377
1378 skb_queue_splice(&seg_list, list);
1379 dev_kfree_skb(skb);
1380 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1381 if (skb_checksum_help(skb) < 0)
1382 goto drop;
1383
1384 __skb_queue_head(list, skb);
1385 } else {
1386 struct net_device_stats *stats;
1387
1388drop:
1389 stats = &tp->netdev->stats;
1390 stats->tx_dropped++;
1391 dev_kfree_skb(skb);
1392 }
1393}
1394
1395/*
1396 * msdn_giant_send_check()
1397 * According to the document of microsoft, the TCP Pseudo Header excludes the
1398 * packet length for IPv6 TCP large packets.
1399 */
1400static int msdn_giant_send_check(struct sk_buff *skb)
1401{
1402 const struct ipv6hdr *ipv6h;
1403 struct tcphdr *th;
1404 int ret;
1405
1406 ret = skb_cow_head(skb, 0);
1407 if (ret)
1408 return ret;
1409
1410 ipv6h = ipv6_hdr(skb);
1411 th = tcp_hdr(skb);
1412
1413 th->check = 0;
1414 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1415
1416 return ret;
1417}
1418
1419static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1420 struct sk_buff *skb, u32 len, u32 transport_offset)
1421{
1422 u32 mss = skb_shinfo(skb)->gso_size;
1423 u32 opts1, opts2 = 0;
1424 int ret = TX_CSUM_SUCCESS;
1425
1426 WARN_ON_ONCE(len > TX_LEN_MAX);
1427
1428 opts1 = len | TX_FS | TX_LS;
1429
1430 if (mss) {
1431 if (transport_offset > GTTCPHO_MAX) {
1432 netif_warn(tp, tx_err, tp->netdev,
1433 "Invalid transport offset 0x%x for TSO\n",
1434 transport_offset);
1435 ret = TX_CSUM_TSO;
1436 goto unavailable;
1437 }
1438
1439 switch (get_protocol(skb)) {
1440 case htons(ETH_P_IP):
1441 opts1 |= GTSENDV4;
1442 break;
1443
1444 case htons(ETH_P_IPV6):
1445 if (msdn_giant_send_check(skb)) {
1446 ret = TX_CSUM_TSO;
1447 goto unavailable;
1448 }
1449 opts1 |= GTSENDV6;
1450 break;
1451
1452 default:
1453 WARN_ON_ONCE(1);
1454 break;
1455 }
1456
1457 opts1 |= transport_offset << GTTCPHO_SHIFT;
1458 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1459 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1460 u8 ip_protocol;
1461
1462 if (transport_offset > TCPHO_MAX) {
1463 netif_warn(tp, tx_err, tp->netdev,
1464 "Invalid transport offset 0x%x\n",
1465 transport_offset);
1466 ret = TX_CSUM_NONE;
1467 goto unavailable;
1468 }
1469
1470 switch (get_protocol(skb)) {
1471 case htons(ETH_P_IP):
1472 opts2 |= IPV4_CS;
1473 ip_protocol = ip_hdr(skb)->protocol;
1474 break;
1475
1476 case htons(ETH_P_IPV6):
1477 opts2 |= IPV6_CS;
1478 ip_protocol = ipv6_hdr(skb)->nexthdr;
1479 break;
1480
1481 default:
1482 ip_protocol = IPPROTO_RAW;
1483 break;
1484 }
1485
1486 if (ip_protocol == IPPROTO_TCP)
1487 opts2 |= TCP_CS;
1488 else if (ip_protocol == IPPROTO_UDP)
1489 opts2 |= UDP_CS;
1490 else
1491 WARN_ON_ONCE(1);
1492
1493 opts2 |= transport_offset << TCPHO_SHIFT;
1494 }
1495
1496 desc->opts2 = cpu_to_le32(opts2);
1497 desc->opts1 = cpu_to_le32(opts1);
1498
1499unavailable:
1500 return ret;
1501}
1502
1503static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1504{
1505 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1506 int remain, ret;
1507 u8 *tx_data;
1508
1509 __skb_queue_head_init(&skb_head);
1510 spin_lock(&tx_queue->lock);
1511 skb_queue_splice_init(tx_queue, &skb_head);
1512 spin_unlock(&tx_queue->lock);
1513
1514 tx_data = agg->head;
1515 agg->skb_num = agg->skb_len = 0;
1516 remain = rx_buf_sz;
1517
1518 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1519 struct tx_desc *tx_desc;
1520 struct sk_buff *skb;
1521 unsigned int len;
1522 u32 offset;
1523
1524 skb = __skb_dequeue(&skb_head);
1525 if (!skb)
1526 break;
1527
1528 len = skb->len + sizeof(*tx_desc);
1529
1530 if (len > remain) {
1531 __skb_queue_head(&skb_head, skb);
1532 break;
1533 }
1534
1535 tx_data = tx_agg_align(tx_data);
1536 tx_desc = (struct tx_desc *)tx_data;
1537
1538 offset = (u32)skb_transport_offset(skb);
1539
1540 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1541 r8152_csum_workaround(tp, skb, &skb_head);
1542 continue;
1543 }
1544
1545 tx_data += sizeof(*tx_desc);
1546
1547 len = skb->len;
1548 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1549 struct net_device_stats *stats = &tp->netdev->stats;
1550
1551 stats->tx_dropped++;
1552 dev_kfree_skb_any(skb);
1553 tx_data -= sizeof(*tx_desc);
1554 continue;
1555 }
1556
1557 tx_data += len;
1558 agg->skb_len += len;
1559 agg->skb_num++;
1560
1561 dev_kfree_skb_any(skb);
1562
1563 remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1564 }
1565
1566 if (!skb_queue_empty(&skb_head)) {
1567 spin_lock(&tx_queue->lock);
1568 skb_queue_splice(&skb_head, tx_queue);
1569 spin_unlock(&tx_queue->lock);
1570 }
1571
1572 netif_tx_lock(tp->netdev);
1573
1574 if (netif_queue_stopped(tp->netdev) &&
1575 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1576 netif_wake_queue(tp->netdev);
1577
1578 netif_tx_unlock(tp->netdev);
1579
1580 ret = usb_autopm_get_interface_async(tp->intf);
1581 if (ret < 0)
1582 goto out_tx_fill;
1583
1584 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1585 agg->head, (int)(tx_data - (u8 *)agg->head),
1586 (usb_complete_t)write_bulk_callback, agg);
1587
1588 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1589 if (ret < 0)
1590 usb_autopm_put_interface_async(tp->intf);
1591
1592out_tx_fill:
1593 return ret;
1594}
1595
1596static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1597{
1598 u8 checksum = CHECKSUM_NONE;
1599 u32 opts2, opts3;
1600
1601 if (tp->version == RTL_VER_01)
1602 goto return_result;
1603
1604 opts2 = le32_to_cpu(rx_desc->opts2);
1605 opts3 = le32_to_cpu(rx_desc->opts3);
1606
1607 if (opts2 & RD_IPV4_CS) {
1608 if (opts3 & IPF)
1609 checksum = CHECKSUM_NONE;
1610 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1611 checksum = CHECKSUM_NONE;
1612 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1613 checksum = CHECKSUM_NONE;
1614 else
1615 checksum = CHECKSUM_UNNECESSARY;
1616 } else if (RD_IPV6_CS) {
1617 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1618 checksum = CHECKSUM_UNNECESSARY;
1619 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1620 checksum = CHECKSUM_UNNECESSARY;
1621 }
1622
1623return_result:
1624 return checksum;
1625}
1626
1627static void rx_bottom(struct r8152 *tp)
1628{
1629 unsigned long flags;
1630 struct list_head *cursor, *next, rx_queue;
1631
1632 if (list_empty(&tp->rx_done))
1633 return;
1634
1635 INIT_LIST_HEAD(&rx_queue);
1636 spin_lock_irqsave(&tp->rx_lock, flags);
1637 list_splice_init(&tp->rx_done, &rx_queue);
1638 spin_unlock_irqrestore(&tp->rx_lock, flags);
1639
1640 list_for_each_safe(cursor, next, &rx_queue) {
1641 struct rx_desc *rx_desc;
1642 struct rx_agg *agg;
1643 int len_used = 0;
1644 struct urb *urb;
1645 u8 *rx_data;
1646 int ret;
1647
1648 list_del_init(cursor);
1649
1650 agg = list_entry(cursor, struct rx_agg, list);
1651 urb = agg->urb;
1652 if (urb->actual_length < ETH_ZLEN)
1653 goto submit;
1654
1655 rx_desc = agg->head;
1656 rx_data = agg->head;
1657 len_used += sizeof(struct rx_desc);
1658
1659 while (urb->actual_length > len_used) {
1660 struct net_device *netdev = tp->netdev;
1661 struct net_device_stats *stats = &netdev->stats;
1662 unsigned int pkt_len;
1663 struct sk_buff *skb;
1664
1665 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1666 if (pkt_len < ETH_ZLEN)
1667 break;
1668
1669 len_used += pkt_len;
1670 if (urb->actual_length < len_used)
1671 break;
1672
1673 pkt_len -= CRC_SIZE;
1674 rx_data += sizeof(struct rx_desc);
1675
1676 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1677 if (!skb) {
1678 stats->rx_dropped++;
1679 goto find_next_rx;
1680 }
1681
1682 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1683 memcpy(skb->data, rx_data, pkt_len);
1684 skb_put(skb, pkt_len);
1685 skb->protocol = eth_type_trans(skb, netdev);
1686 netif_receive_skb(skb);
1687 stats->rx_packets++;
1688 stats->rx_bytes += pkt_len;
1689
1690find_next_rx:
1691 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1692 rx_desc = (struct rx_desc *)rx_data;
1693 len_used = (int)(rx_data - (u8 *)agg->head);
1694 len_used += sizeof(struct rx_desc);
1695 }
1696
1697submit:
1698 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1699 if (ret && ret != -ENODEV) {
1700 spin_lock_irqsave(&tp->rx_lock, flags);
1701 list_add_tail(&agg->list, &tp->rx_done);
1702 spin_unlock_irqrestore(&tp->rx_lock, flags);
1703 tasklet_schedule(&tp->tl);
1704 }
1705 }
1706}
1707
1708static void tx_bottom(struct r8152 *tp)
1709{
1710 int res;
1711
1712 do {
1713 struct tx_agg *agg;
1714
1715 if (skb_queue_empty(&tp->tx_queue))
1716 break;
1717
1718 agg = r8152_get_tx_agg(tp);
1719 if (!agg)
1720 break;
1721
1722 res = r8152_tx_agg_fill(tp, agg);
1723 if (res) {
1724 struct net_device *netdev = tp->netdev;
1725
1726 if (res == -ENODEV) {
1727 netif_device_detach(netdev);
1728 } else {
1729 struct net_device_stats *stats = &netdev->stats;
1730 unsigned long flags;
1731
1732 netif_warn(tp, tx_err, netdev,
1733 "failed tx_urb %d\n", res);
1734 stats->tx_dropped += agg->skb_num;
1735
1736 spin_lock_irqsave(&tp->tx_lock, flags);
1737 list_add_tail(&agg->list, &tp->tx_free);
1738 spin_unlock_irqrestore(&tp->tx_lock, flags);
1739 }
1740 }
1741 } while (res == 0);
1742}
1743
1744static void bottom_half(unsigned long data)
1745{
1746 struct r8152 *tp;
1747
1748 tp = (struct r8152 *)data;
1749
1750 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1751 return;
1752
1753 if (!test_bit(WORK_ENABLE, &tp->flags))
1754 return;
1755
1756 /* When link down, the driver would cancel all bulks. */
1757 /* This avoid the re-submitting bulk */
1758 if (!netif_carrier_ok(tp->netdev))
1759 return;
1760
1761 rx_bottom(tp);
1762 tx_bottom(tp);
1763}
1764
1765static
1766int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1767{
1768 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1769 agg->head, rx_buf_sz,
1770 (usb_complete_t)read_bulk_callback, agg);
1771
1772 return usb_submit_urb(agg->urb, mem_flags);
1773}
1774
1775static void rtl_drop_queued_tx(struct r8152 *tp)
1776{
1777 struct net_device_stats *stats = &tp->netdev->stats;
1778 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1779 struct sk_buff *skb;
1780
1781 if (skb_queue_empty(tx_queue))
1782 return;
1783
1784 __skb_queue_head_init(&skb_head);
1785 spin_lock_bh(&tx_queue->lock);
1786 skb_queue_splice_init(tx_queue, &skb_head);
1787 spin_unlock_bh(&tx_queue->lock);
1788
1789 while ((skb = __skb_dequeue(&skb_head))) {
1790 dev_kfree_skb(skb);
1791 stats->tx_dropped++;
1792 }
1793}
1794
1795static void rtl8152_tx_timeout(struct net_device *netdev)
1796{
1797 struct r8152 *tp = netdev_priv(netdev);
1798 int i;
1799
1800 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1801 for (i = 0; i < RTL8152_MAX_TX; i++)
1802 usb_unlink_urb(tp->tx_info[i].urb);
1803}
1804
1805static void rtl8152_set_rx_mode(struct net_device *netdev)
1806{
1807 struct r8152 *tp = netdev_priv(netdev);
1808
1809 if (tp->speed & LINK_STATUS) {
1810 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1811 schedule_delayed_work(&tp->schedule, 0);
1812 }
1813}
1814
1815static void _rtl8152_set_rx_mode(struct net_device *netdev)
1816{
1817 struct r8152 *tp = netdev_priv(netdev);
1818 u32 mc_filter[2]; /* Multicast hash filter */
1819 __le32 tmp[2];
1820 u32 ocp_data;
1821
1822 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1823 netif_stop_queue(netdev);
1824 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1825 ocp_data &= ~RCR_ACPT_ALL;
1826 ocp_data |= RCR_AB | RCR_APM;
1827
1828 if (netdev->flags & IFF_PROMISC) {
1829 /* Unconditionally log net taps. */
1830 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1831 ocp_data |= RCR_AM | RCR_AAP;
1832 mc_filter[1] = mc_filter[0] = 0xffffffff;
1833 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1834 (netdev->flags & IFF_ALLMULTI)) {
1835 /* Too many to filter perfectly -- accept all multicasts. */
1836 ocp_data |= RCR_AM;
1837 mc_filter[1] = mc_filter[0] = 0xffffffff;
1838 } else {
1839 struct netdev_hw_addr *ha;
1840
1841 mc_filter[1] = mc_filter[0] = 0;
1842 netdev_for_each_mc_addr(ha, netdev) {
1843 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1844 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1845 ocp_data |= RCR_AM;
1846 }
1847 }
1848
1849 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1850 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1851
1852 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1853 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1854 netif_wake_queue(netdev);
1855}
1856
1857static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1858 struct net_device *netdev)
1859{
1860 struct r8152 *tp = netdev_priv(netdev);
1861
1862 skb_tx_timestamp(skb);
1863
1864 skb_queue_tail(&tp->tx_queue, skb);
1865
1866 if (!list_empty(&tp->tx_free)) {
1867 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1868 set_bit(SCHEDULE_TASKLET, &tp->flags);
1869 schedule_delayed_work(&tp->schedule, 0);
1870 } else {
1871 usb_mark_last_busy(tp->udev);
1872 tasklet_schedule(&tp->tl);
1873 }
1874 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen)
1875 netif_stop_queue(netdev);
1876
1877 return NETDEV_TX_OK;
1878}
1879
1880static void r8152b_reset_packet_filter(struct r8152 *tp)
1881{
1882 u32 ocp_data;
1883
1884 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1885 ocp_data &= ~FMC_FCR_MCU_EN;
1886 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1887 ocp_data |= FMC_FCR_MCU_EN;
1888 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1889}
1890
1891static void rtl8152_nic_reset(struct r8152 *tp)
1892{
1893 int i;
1894
1895 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1896
1897 for (i = 0; i < 1000; i++) {
1898 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1899 break;
1900 udelay(100);
1901 }
1902}
1903
1904static void set_tx_qlen(struct r8152 *tp)
1905{
1906 struct net_device *netdev = tp->netdev;
1907
1908 tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1909 sizeof(struct tx_desc));
1910}
1911
1912static inline u8 rtl8152_get_speed(struct r8152 *tp)
1913{
1914 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1915}
1916
1917static void rtl_set_eee_plus(struct r8152 *tp)
1918{
1919 u32 ocp_data;
1920 u8 speed;
1921
1922 speed = rtl8152_get_speed(tp);
1923 if (speed & _10bps) {
1924 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1925 ocp_data |= EEEP_CR_EEEP_TX;
1926 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1927 } else {
1928 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1929 ocp_data &= ~EEEP_CR_EEEP_TX;
1930 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1931 }
1932}
1933
1934static void rxdy_gated_en(struct r8152 *tp, bool enable)
1935{
1936 u32 ocp_data;
1937
1938 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1939 if (enable)
1940 ocp_data |= RXDY_GATED_EN;
1941 else
1942 ocp_data &= ~RXDY_GATED_EN;
1943 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1944}
1945
1946static int rtl_enable(struct r8152 *tp)
1947{
1948 u32 ocp_data;
1949 int i, ret;
1950
1951 r8152b_reset_packet_filter(tp);
1952
1953 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
1954 ocp_data |= CR_RE | CR_TE;
1955 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
1956
1957 rxdy_gated_en(tp, false);
1958
1959 INIT_LIST_HEAD(&tp->rx_done);
1960 ret = 0;
1961 for (i = 0; i < RTL8152_MAX_RX; i++) {
1962 INIT_LIST_HEAD(&tp->rx_info[i].list);
1963 ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1964 }
1965
1966 return ret;
1967}
1968
1969static int rtl8152_enable(struct r8152 *tp)
1970{
1971 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1972 return -ENODEV;
1973
1974 set_tx_qlen(tp);
1975 rtl_set_eee_plus(tp);
1976
1977 return rtl_enable(tp);
1978}
1979
1980static void r8153_set_rx_agg(struct r8152 *tp)
1981{
1982 u8 speed;
1983
1984 speed = rtl8152_get_speed(tp);
1985 if (speed & _1000bps) {
1986 if (tp->udev->speed == USB_SPEED_SUPER) {
1987 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1988 RX_THR_SUPPER);
1989 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1990 EARLY_AGG_SUPPER);
1991 } else {
1992 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
1993 RX_THR_HIGH);
1994 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
1995 EARLY_AGG_HIGH);
1996 }
1997 } else {
1998 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
1999 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2000 EARLY_AGG_SLOW);
2001 }
2002}
2003
2004static int rtl8153_enable(struct r8152 *tp)
2005{
2006 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2007 return -ENODEV;
2008
2009 set_tx_qlen(tp);
2010 rtl_set_eee_plus(tp);
2011 r8153_set_rx_agg(tp);
2012
2013 return rtl_enable(tp);
2014}
2015
2016static void rtl8152_disable(struct r8152 *tp)
2017{
2018 u32 ocp_data;
2019 int i;
2020
2021 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2022 rtl_drop_queued_tx(tp);
2023 return;
2024 }
2025
2026 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2027 ocp_data &= ~RCR_ACPT_ALL;
2028 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2029
2030 rtl_drop_queued_tx(tp);
2031
2032 for (i = 0; i < RTL8152_MAX_TX; i++)
2033 usb_kill_urb(tp->tx_info[i].urb);
2034
2035 rxdy_gated_en(tp, true);
2036
2037 for (i = 0; i < 1000; i++) {
2038 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2039 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2040 break;
2041 mdelay(1);
2042 }
2043
2044 for (i = 0; i < 1000; i++) {
2045 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2046 break;
2047 mdelay(1);
2048 }
2049
2050 for (i = 0; i < RTL8152_MAX_RX; i++)
2051 usb_kill_urb(tp->rx_info[i].urb);
2052
2053 rtl8152_nic_reset(tp);
2054}
2055
2056static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2057{
2058 u32 ocp_data;
2059
2060 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2061 if (enable)
2062 ocp_data |= POWER_CUT;
2063 else
2064 ocp_data &= ~POWER_CUT;
2065 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2066
2067 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2068 ocp_data &= ~RESUME_INDICATE;
2069 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2070}
2071
2072#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2073
2074static u32 __rtl_get_wol(struct r8152 *tp)
2075{
2076 u32 ocp_data;
2077 u32 wolopts = 0;
2078
2079 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2080 if (!(ocp_data & LAN_WAKE_EN))
2081 return 0;
2082
2083 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2084 if (ocp_data & LINK_ON_WAKE_EN)
2085 wolopts |= WAKE_PHY;
2086
2087 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2088 if (ocp_data & UWF_EN)
2089 wolopts |= WAKE_UCAST;
2090 if (ocp_data & BWF_EN)
2091 wolopts |= WAKE_BCAST;
2092 if (ocp_data & MWF_EN)
2093 wolopts |= WAKE_MCAST;
2094
2095 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2096 if (ocp_data & MAGIC_EN)
2097 wolopts |= WAKE_MAGIC;
2098
2099 return wolopts;
2100}
2101
2102static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2103{
2104 u32 ocp_data;
2105
2106 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2107
2108 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2109 ocp_data &= ~LINK_ON_WAKE_EN;
2110 if (wolopts & WAKE_PHY)
2111 ocp_data |= LINK_ON_WAKE_EN;
2112 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2113
2114 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2115 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2116 if (wolopts & WAKE_UCAST)
2117 ocp_data |= UWF_EN;
2118 if (wolopts & WAKE_BCAST)
2119 ocp_data |= BWF_EN;
2120 if (wolopts & WAKE_MCAST)
2121 ocp_data |= MWF_EN;
2122 if (wolopts & WAKE_ANY)
2123 ocp_data |= LAN_WAKE_EN;
2124 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2125
2126 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2127
2128 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2129 ocp_data &= ~MAGIC_EN;
2130 if (wolopts & WAKE_MAGIC)
2131 ocp_data |= MAGIC_EN;
2132 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2133
2134 if (wolopts & WAKE_ANY)
2135 device_set_wakeup_enable(&tp->udev->dev, true);
2136 else
2137 device_set_wakeup_enable(&tp->udev->dev, false);
2138}
2139
2140static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2141{
2142 if (enable) {
2143 u32 ocp_data;
2144
2145 __rtl_set_wol(tp, WAKE_ANY);
2146
2147 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2148
2149 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2150 ocp_data |= LINK_OFF_WAKE_EN;
2151 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2152
2153 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2154 } else {
2155 __rtl_set_wol(tp, tp->saved_wolopts);
2156 }
2157}
2158
2159static void rtl_phy_reset(struct r8152 *tp)
2160{
2161 u16 data;
2162 int i;
2163
2164 clear_bit(PHY_RESET, &tp->flags);
2165
2166 data = r8152_mdio_read(tp, MII_BMCR);
2167
2168 /* don't reset again before the previous one complete */
2169 if (data & BMCR_RESET)
2170 return;
2171
2172 data |= BMCR_RESET;
2173 r8152_mdio_write(tp, MII_BMCR, data);
2174
2175 for (i = 0; i < 50; i++) {
2176 msleep(20);
2177 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2178 break;
2179 }
2180}
2181
2182static void rtl_clear_bp(struct r8152 *tp)
2183{
2184 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
2185 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
2186 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
2187 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
2188 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
2189 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
2190 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
2191 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
2192 mdelay(3);
2193 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
2194 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
2195}
2196
2197static void r8153_clear_bp(struct r8152 *tp)
2198{
2199 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
2200 ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0);
2201 rtl_clear_bp(tp);
2202}
2203
2204static void r8153_teredo_off(struct r8152 *tp)
2205{
2206 u32 ocp_data;
2207
2208 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2209 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2210 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2211
2212 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2213 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2214 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2215}
2216
2217static void r8152b_disable_aldps(struct r8152 *tp)
2218{
2219 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2220 msleep(20);
2221}
2222
2223static inline void r8152b_enable_aldps(struct r8152 *tp)
2224{
2225 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2226 LINKENA | DIS_SDSAVE);
2227}
2228
2229static void r8152b_hw_phy_cfg(struct r8152 *tp)
2230{
2231 u16 data;
2232
2233 data = r8152_mdio_read(tp, MII_BMCR);
2234 if (data & BMCR_PDOWN) {
2235 data &= ~BMCR_PDOWN;
2236 r8152_mdio_write(tp, MII_BMCR, data);
2237 }
2238
2239 r8152b_disable_aldps(tp);
2240
2241 rtl_clear_bp(tp);
2242
2243 r8152b_enable_aldps(tp);
2244 set_bit(PHY_RESET, &tp->flags);
2245}
2246
2247static void r8152b_exit_oob(struct r8152 *tp)
2248{
2249 u32 ocp_data;
2250 int i;
2251
2252 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2253 return;
2254
2255 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2256 ocp_data &= ~RCR_ACPT_ALL;
2257 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2258
2259 rxdy_gated_en(tp, true);
2260 r8153_teredo_off(tp);
2261 r8152b_hw_phy_cfg(tp);
2262
2263 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2264 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2265
2266 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2267 ocp_data &= ~NOW_IS_OOB;
2268 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2269
2270 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2271 ocp_data &= ~MCU_BORW_EN;
2272 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2273
2274 for (i = 0; i < 1000; i++) {
2275 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2276 if (ocp_data & LINK_LIST_READY)
2277 break;
2278 mdelay(1);
2279 }
2280
2281 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2282 ocp_data |= RE_INIT_LL;
2283 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2284
2285 for (i = 0; i < 1000; i++) {
2286 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2287 if (ocp_data & LINK_LIST_READY)
2288 break;
2289 mdelay(1);
2290 }
2291
2292 rtl8152_nic_reset(tp);
2293
2294 /* rx share fifo credit full threshold */
2295 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2296
2297 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT);
2298 ocp_data &= STAT_SPEED_MASK;
2299 if (ocp_data == STAT_SPEED_FULL) {
2300 /* rx share fifo credit near full threshold */
2301 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2302 RXFIFO_THR2_FULL);
2303 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2304 RXFIFO_THR3_FULL);
2305 } else {
2306 /* rx share fifo credit near full threshold */
2307 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2308 RXFIFO_THR2_HIGH);
2309 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2310 RXFIFO_THR3_HIGH);
2311 }
2312
2313 /* TX share fifo free credit full threshold */
2314 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2315
2316 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2317 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2318 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2319 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2320
2321 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2322 ocp_data &= ~CPCR_RX_VLAN;
2323 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2324
2325 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2326
2327 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2328 ocp_data |= TCR0_AUTO_FIFO;
2329 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2330}
2331
2332static void r8152b_enter_oob(struct r8152 *tp)
2333{
2334 u32 ocp_data;
2335 int i;
2336
2337 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2338 ocp_data &= ~NOW_IS_OOB;
2339 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2340
2341 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2342 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2343 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2344
2345 rtl8152_disable(tp);
2346
2347 for (i = 0; i < 1000; i++) {
2348 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2349 if (ocp_data & LINK_LIST_READY)
2350 break;
2351 mdelay(1);
2352 }
2353
2354 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2355 ocp_data |= RE_INIT_LL;
2356 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2357
2358 for (i = 0; i < 1000; i++) {
2359 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2360 if (ocp_data & LINK_LIST_READY)
2361 break;
2362 mdelay(1);
2363 }
2364
2365 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2366
2367 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2368 ocp_data |= CPCR_RX_VLAN;
2369 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2370
2371 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2372 ocp_data |= ALDPS_PROXY_MODE;
2373 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2374
2375 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2376 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2377 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2378
2379 rxdy_gated_en(tp, false);
2380
2381 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2382 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2383 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2384}
2385
2386static void r8153_hw_phy_cfg(struct r8152 *tp)
2387{
2388 u32 ocp_data;
2389 u16 data;
2390
2391 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2392 data = r8152_mdio_read(tp, MII_BMCR);
2393 if (data & BMCR_PDOWN) {
2394 data &= ~BMCR_PDOWN;
2395 r8152_mdio_write(tp, MII_BMCR, data);
2396 }
2397
2398 r8153_clear_bp(tp);
2399
2400 if (tp->version == RTL_VER_03) {
2401 data = ocp_reg_read(tp, OCP_EEE_CFG);
2402 data &= ~CTAP_SHORT_EN;
2403 ocp_reg_write(tp, OCP_EEE_CFG, data);
2404 }
2405
2406 data = ocp_reg_read(tp, OCP_POWER_CFG);
2407 data |= EEE_CLKDIV_EN;
2408 ocp_reg_write(tp, OCP_POWER_CFG, data);
2409
2410 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2411 data |= EN_10M_BGOFF;
2412 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2413 data = ocp_reg_read(tp, OCP_POWER_CFG);
2414 data |= EN_10M_PLLOFF;
2415 ocp_reg_write(tp, OCP_POWER_CFG, data);
2416 data = sram_read(tp, SRAM_IMPEDANCE);
2417 data &= ~RX_DRIVING_MASK;
2418 sram_write(tp, SRAM_IMPEDANCE, data);
2419
2420 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2421 ocp_data |= PFM_PWM_SWITCH;
2422 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2423
2424 data = sram_read(tp, SRAM_LPF_CFG);
2425 data |= LPF_AUTO_TUNE;
2426 sram_write(tp, SRAM_LPF_CFG, data);
2427
2428 data = sram_read(tp, SRAM_10M_AMP1);
2429 data |= GDAC_IB_UPALL;
2430 sram_write(tp, SRAM_10M_AMP1, data);
2431 data = sram_read(tp, SRAM_10M_AMP2);
2432 data |= AMP_DN;
2433 sram_write(tp, SRAM_10M_AMP2, data);
2434
2435 set_bit(PHY_RESET, &tp->flags);
2436}
2437
2438static void r8153_u1u2en(struct r8152 *tp, bool enable)
2439{
2440 u8 u1u2[8];
2441
2442 if (enable)
2443 memset(u1u2, 0xff, sizeof(u1u2));
2444 else
2445 memset(u1u2, 0x00, sizeof(u1u2));
2446
2447 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2448}
2449
2450static void r8153_u2p3en(struct r8152 *tp, bool enable)
2451{
2452 u32 ocp_data;
2453
2454 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2455 if (enable)
2456 ocp_data |= U2P3_ENABLE;
2457 else
2458 ocp_data &= ~U2P3_ENABLE;
2459 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2460}
2461
2462static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2463{
2464 u32 ocp_data;
2465
2466 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2467 if (enable)
2468 ocp_data |= PWR_EN | PHASE2_EN;
2469 else
2470 ocp_data &= ~(PWR_EN | PHASE2_EN);
2471 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2472
2473 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2474 ocp_data &= ~PCUT_STATUS;
2475 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2476}
2477
2478static void r8153_first_init(struct r8152 *tp)
2479{
2480 u32 ocp_data;
2481 int i;
2482
2483 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2484 return;
2485
2486 rxdy_gated_en(tp, true);
2487 r8153_teredo_off(tp);
2488
2489 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2490 ocp_data &= ~RCR_ACPT_ALL;
2491 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2492
2493 r8153_hw_phy_cfg(tp);
2494
2495 rtl8152_nic_reset(tp);
2496
2497 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2498 ocp_data &= ~NOW_IS_OOB;
2499 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2500
2501 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2502 ocp_data &= ~MCU_BORW_EN;
2503 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2504
2505 for (i = 0; i < 1000; i++) {
2506 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2507 if (ocp_data & LINK_LIST_READY)
2508 break;
2509 mdelay(1);
2510 }
2511
2512 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2513 ocp_data |= RE_INIT_LL;
2514 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2515
2516 for (i = 0; i < 1000; i++) {
2517 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2518 if (ocp_data & LINK_LIST_READY)
2519 break;
2520 mdelay(1);
2521 }
2522
2523 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2524 ocp_data &= ~CPCR_RX_VLAN;
2525 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2526
2527 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2528
2529 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2530 ocp_data |= TCR0_AUTO_FIFO;
2531 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2532
2533 rtl8152_nic_reset(tp);
2534
2535 /* rx share fifo credit full threshold */
2536 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2537 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2538 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2539 /* TX share fifo free credit full threshold */
2540 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2541
2542 /* rx aggregation */
2543 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2544 ocp_data &= ~RX_AGG_DISABLE;
2545 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2546}
2547
2548static void r8153_enter_oob(struct r8152 *tp)
2549{
2550 u32 ocp_data;
2551 int i;
2552
2553 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2554 ocp_data &= ~NOW_IS_OOB;
2555 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2556
2557 rtl8152_disable(tp);
2558
2559 for (i = 0; i < 1000; i++) {
2560 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2561 if (ocp_data & LINK_LIST_READY)
2562 break;
2563 mdelay(1);
2564 }
2565
2566 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2567 ocp_data |= RE_INIT_LL;
2568 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2569
2570 for (i = 0; i < 1000; i++) {
2571 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2572 if (ocp_data & LINK_LIST_READY)
2573 break;
2574 mdelay(1);
2575 }
2576
2577 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2578
2579 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2580 ocp_data &= ~TEREDO_WAKE_MASK;
2581 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2582
2583 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2584 ocp_data |= CPCR_RX_VLAN;
2585 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2586
2587 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2588 ocp_data |= ALDPS_PROXY_MODE;
2589 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2590
2591 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2592 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2593 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2594
2595 rxdy_gated_en(tp, false);
2596
2597 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2598 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2599 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2600}
2601
2602static void r8153_disable_aldps(struct r8152 *tp)
2603{
2604 u16 data;
2605
2606 data = ocp_reg_read(tp, OCP_POWER_CFG);
2607 data &= ~EN_ALDPS;
2608 ocp_reg_write(tp, OCP_POWER_CFG, data);
2609 msleep(20);
2610}
2611
2612static void r8153_enable_aldps(struct r8152 *tp)
2613{
2614 u16 data;
2615
2616 data = ocp_reg_read(tp, OCP_POWER_CFG);
2617 data |= EN_ALDPS;
2618 ocp_reg_write(tp, OCP_POWER_CFG, data);
2619}
2620
2621static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2622{
2623 u16 bmcr, anar, gbcr;
2624 int ret = 0;
2625
2626 cancel_delayed_work_sync(&tp->schedule);
2627 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2628 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2629 ADVERTISE_100HALF | ADVERTISE_100FULL);
2630 if (tp->mii.supports_gmii) {
2631 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2632 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2633 } else {
2634 gbcr = 0;
2635 }
2636
2637 if (autoneg == AUTONEG_DISABLE) {
2638 if (speed == SPEED_10) {
2639 bmcr = 0;
2640 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2641 } else if (speed == SPEED_100) {
2642 bmcr = BMCR_SPEED100;
2643 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2644 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2645 bmcr = BMCR_SPEED1000;
2646 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2647 } else {
2648 ret = -EINVAL;
2649 goto out;
2650 }
2651
2652 if (duplex == DUPLEX_FULL)
2653 bmcr |= BMCR_FULLDPLX;
2654 } else {
2655 if (speed == SPEED_10) {
2656 if (duplex == DUPLEX_FULL)
2657 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2658 else
2659 anar |= ADVERTISE_10HALF;
2660 } else if (speed == SPEED_100) {
2661 if (duplex == DUPLEX_FULL) {
2662 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2663 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2664 } else {
2665 anar |= ADVERTISE_10HALF;
2666 anar |= ADVERTISE_100HALF;
2667 }
2668 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2669 if (duplex == DUPLEX_FULL) {
2670 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2671 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2672 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2673 } else {
2674 anar |= ADVERTISE_10HALF;
2675 anar |= ADVERTISE_100HALF;
2676 gbcr |= ADVERTISE_1000HALF;
2677 }
2678 } else {
2679 ret = -EINVAL;
2680 goto out;
2681 }
2682
2683 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2684 }
2685
2686 if (test_bit(PHY_RESET, &tp->flags))
2687 bmcr |= BMCR_RESET;
2688
2689 if (tp->mii.supports_gmii)
2690 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2691
2692 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2693 r8152_mdio_write(tp, MII_BMCR, bmcr);
2694
2695 if (test_bit(PHY_RESET, &tp->flags)) {
2696 int i;
2697
2698 clear_bit(PHY_RESET, &tp->flags);
2699 for (i = 0; i < 50; i++) {
2700 msleep(20);
2701 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2702 break;
2703 }
2704 }
2705
2706out:
2707
2708 return ret;
2709}
2710
2711static void rtl8152_down(struct r8152 *tp)
2712{
2713 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2714 rtl_drop_queued_tx(tp);
2715 return;
2716 }
2717
2718 r8152_power_cut_en(tp, false);
2719 r8152b_disable_aldps(tp);
2720 r8152b_enter_oob(tp);
2721 r8152b_enable_aldps(tp);
2722}
2723
2724static void rtl8153_down(struct r8152 *tp)
2725{
2726 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2727 rtl_drop_queued_tx(tp);
2728 return;
2729 }
2730
2731 r8153_u1u2en(tp, false);
2732 r8153_power_cut_en(tp, false);
2733 r8153_disable_aldps(tp);
2734 r8153_enter_oob(tp);
2735 r8153_enable_aldps(tp);
2736}
2737
2738static void set_carrier(struct r8152 *tp)
2739{
2740 struct net_device *netdev = tp->netdev;
2741 u8 speed;
2742
2743 clear_bit(RTL8152_LINK_CHG, &tp->flags);
2744 speed = rtl8152_get_speed(tp);
2745
2746 if (speed & LINK_STATUS) {
2747 if (!(tp->speed & LINK_STATUS)) {
2748 tp->rtl_ops.enable(tp);
2749 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2750 netif_carrier_on(netdev);
2751 }
2752 } else {
2753 if (tp->speed & LINK_STATUS) {
2754 netif_carrier_off(netdev);
2755 tasklet_disable(&tp->tl);
2756 tp->rtl_ops.disable(tp);
2757 tasklet_enable(&tp->tl);
2758 }
2759 }
2760 tp->speed = speed;
2761}
2762
2763static void rtl_work_func_t(struct work_struct *work)
2764{
2765 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2766
2767 if (usb_autopm_get_interface(tp->intf) < 0)
2768 return;
2769
2770 if (!test_bit(WORK_ENABLE, &tp->flags))
2771 goto out1;
2772
2773 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2774 goto out1;
2775
2776 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2777 set_carrier(tp);
2778
2779 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2780 _rtl8152_set_rx_mode(tp->netdev);
2781
2782 if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2783 (tp->speed & LINK_STATUS)) {
2784 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2785 tasklet_schedule(&tp->tl);
2786 }
2787
2788 if (test_bit(PHY_RESET, &tp->flags))
2789 rtl_phy_reset(tp);
2790
2791out1:
2792 usb_autopm_put_interface(tp->intf);
2793}
2794
2795static int rtl8152_open(struct net_device *netdev)
2796{
2797 struct r8152 *tp = netdev_priv(netdev);
2798 int res = 0;
2799
2800 res = alloc_all_mem(tp);
2801 if (res)
2802 goto out;
2803
2804 res = usb_autopm_get_interface(tp->intf);
2805 if (res < 0) {
2806 free_all_mem(tp);
2807 goto out;
2808 }
2809
2810 /* The WORK_ENABLE may be set when autoresume occurs */
2811 if (test_bit(WORK_ENABLE, &tp->flags)) {
2812 clear_bit(WORK_ENABLE, &tp->flags);
2813 usb_kill_urb(tp->intr_urb);
2814 cancel_delayed_work_sync(&tp->schedule);
2815 if (tp->speed & LINK_STATUS)
2816 tp->rtl_ops.disable(tp);
2817 }
2818
2819 tp->rtl_ops.up(tp);
2820
2821 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2822 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2823 DUPLEX_FULL);
2824 tp->speed = 0;
2825 netif_carrier_off(netdev);
2826 netif_start_queue(netdev);
2827 set_bit(WORK_ENABLE, &tp->flags);
2828
2829 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2830 if (res) {
2831 if (res == -ENODEV)
2832 netif_device_detach(tp->netdev);
2833 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2834 res);
2835 free_all_mem(tp);
2836 }
2837
2838 usb_autopm_put_interface(tp->intf);
2839
2840out:
2841 return res;
2842}
2843
2844static int rtl8152_close(struct net_device *netdev)
2845{
2846 struct r8152 *tp = netdev_priv(netdev);
2847 int res = 0;
2848
2849 clear_bit(WORK_ENABLE, &tp->flags);
2850 usb_kill_urb(tp->intr_urb);
2851 cancel_delayed_work_sync(&tp->schedule);
2852 netif_stop_queue(netdev);
2853
2854 res = usb_autopm_get_interface(tp->intf);
2855 if (res < 0) {
2856 rtl_drop_queued_tx(tp);
2857 } else {
2858 /*
2859 * The autosuspend may have been enabled and wouldn't
2860 * be disable when autoresume occurs, because the
2861 * netif_running() would be false.
2862 */
2863 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2864 rtl_runtime_suspend_enable(tp, false);
2865 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
2866 }
2867
2868 tasklet_disable(&tp->tl);
2869 tp->rtl_ops.down(tp);
2870 tasklet_enable(&tp->tl);
2871 usb_autopm_put_interface(tp->intf);
2872 }
2873
2874 free_all_mem(tp);
2875
2876 return res;
2877}
2878
2879static void r8152b_enable_eee(struct r8152 *tp)
2880{
2881 u32 ocp_data;
2882
2883 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2884 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2885 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2886 ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
2887 EEE_10_CAP | EEE_NWAY_EN |
2888 TX_QUIET_EN | RX_QUIET_EN |
2889 SDRISETIME | RG_RXLPI_MSK_HFDUP |
2890 SDFALLTIME);
2891 ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
2892 RG_LDVQUIET_EN | RG_CKRSEL |
2893 RG_EEEPRG_EN);
2894 ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
2895 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
2896 ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
2897 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
2898 ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
2899 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2900}
2901
2902static void r8153_enable_eee(struct r8152 *tp)
2903{
2904 u32 ocp_data;
2905 u16 data;
2906
2907 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2908 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2909 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2910 data = ocp_reg_read(tp, OCP_EEE_CFG);
2911 data |= EEE10_EN;
2912 ocp_reg_write(tp, OCP_EEE_CFG, data);
2913 data = ocp_reg_read(tp, OCP_EEE_CFG2);
2914 data |= MY1000_EEE | MY100_EEE;
2915 ocp_reg_write(tp, OCP_EEE_CFG2, data);
2916}
2917
2918static void r8152b_enable_fc(struct r8152 *tp)
2919{
2920 u16 anar;
2921
2922 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2923 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2924 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2925}
2926
2927static void rtl_tally_reset(struct r8152 *tp)
2928{
2929 u32 ocp_data;
2930
2931 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
2932 ocp_data |= TALLY_RESET;
2933 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
2934}
2935
2936static void r8152b_init(struct r8152 *tp)
2937{
2938 u32 ocp_data;
2939
2940 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2941 return;
2942
2943 if (tp->version == RTL_VER_01) {
2944 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
2945 ocp_data &= ~LED_MODE_MASK;
2946 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
2947 }
2948
2949 r8152_power_cut_en(tp, false);
2950
2951 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2952 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
2953 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2954 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
2955 ocp_data &= ~MCU_CLK_RATIO_MASK;
2956 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
2957 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
2958 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
2959 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
2960 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
2961
2962 r8152b_enable_eee(tp);
2963 r8152b_enable_aldps(tp);
2964 r8152b_enable_fc(tp);
2965 rtl_tally_reset(tp);
2966
2967 /* enable rx aggregation */
2968 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2969 ocp_data &= ~RX_AGG_DISABLE;
2970 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2971}
2972
2973static void r8153_init(struct r8152 *tp)
2974{
2975 u32 ocp_data;
2976 int i;
2977
2978 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2979 return;
2980
2981 r8153_u1u2en(tp, false);
2982
2983 for (i = 0; i < 500; i++) {
2984 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
2985 AUTOLOAD_DONE)
2986 break;
2987 msleep(20);
2988 }
2989
2990 for (i = 0; i < 500; i++) {
2991 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
2992 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
2993 break;
2994 msleep(20);
2995 }
2996
2997 r8153_u2p3en(tp, false);
2998
2999 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3000 ocp_data &= ~TIMER11_EN;
3001 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3002
3003 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3004 ocp_data &= ~LED_MODE_MASK;
3005 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3006
3007 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3008 ocp_data &= ~LPM_TIMER_MASK;
3009 if (tp->udev->speed == USB_SPEED_SUPER)
3010 ocp_data |= LPM_TIMER_500US;
3011 else
3012 ocp_data |= LPM_TIMER_500MS;
3013 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3014
3015 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3016 ocp_data &= ~SEN_VAL_MASK;
3017 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3018 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3019
3020 r8153_power_cut_en(tp, false);
3021 r8153_u1u2en(tp, true);
3022
3023 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3024 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3025 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3026 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3027 U1U2_SPDWN_EN | L1_SPDWN_EN);
3028 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3029 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3030 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3031 EEE_SPDWN_EN);
3032
3033 r8153_enable_eee(tp);
3034 r8153_enable_aldps(tp);
3035 r8152b_enable_fc(tp);
3036 rtl_tally_reset(tp);
3037}
3038
3039static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3040{
3041 struct r8152 *tp = usb_get_intfdata(intf);
3042
3043 if (PMSG_IS_AUTO(message))
3044 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3045 else
3046 netif_device_detach(tp->netdev);
3047
3048 if (netif_running(tp->netdev)) {
3049 clear_bit(WORK_ENABLE, &tp->flags);
3050 usb_kill_urb(tp->intr_urb);
3051 cancel_delayed_work_sync(&tp->schedule);
3052 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3053 rtl_runtime_suspend_enable(tp, true);
3054 } else {
3055 tasklet_disable(&tp->tl);
3056 tp->rtl_ops.down(tp);
3057 tasklet_enable(&tp->tl);
3058 }
3059 }
3060
3061 return 0;
3062}
3063
3064static int rtl8152_resume(struct usb_interface *intf)
3065{
3066 struct r8152 *tp = usb_get_intfdata(intf);
3067
3068 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3069 tp->rtl_ops.init(tp);
3070 netif_device_attach(tp->netdev);
3071 }
3072
3073 if (netif_running(tp->netdev)) {
3074 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3075 rtl_runtime_suspend_enable(tp, false);
3076 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3077 if (tp->speed & LINK_STATUS)
3078 tp->rtl_ops.disable(tp);
3079 } else {
3080 tp->rtl_ops.up(tp);
3081 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3082 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
3083 DUPLEX_FULL);
3084 }
3085 tp->speed = 0;
3086 netif_carrier_off(tp->netdev);
3087 set_bit(WORK_ENABLE, &tp->flags);
3088 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3089 }
3090
3091 return 0;
3092}
3093
3094static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3095{
3096 struct r8152 *tp = netdev_priv(dev);
3097
3098 if (usb_autopm_get_interface(tp->intf) < 0)
3099 return;
3100
3101 wol->supported = WAKE_ANY;
3102 wol->wolopts = __rtl_get_wol(tp);
3103
3104 usb_autopm_put_interface(tp->intf);
3105}
3106
3107static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3108{
3109 struct r8152 *tp = netdev_priv(dev);
3110 int ret;
3111
3112 ret = usb_autopm_get_interface(tp->intf);
3113 if (ret < 0)
3114 goto out_set_wol;
3115
3116 __rtl_set_wol(tp, wol->wolopts);
3117 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3118
3119 usb_autopm_put_interface(tp->intf);
3120
3121out_set_wol:
3122 return ret;
3123}
3124
3125static u32 rtl8152_get_msglevel(struct net_device *dev)
3126{
3127 struct r8152 *tp = netdev_priv(dev);
3128
3129 return tp->msg_enable;
3130}
3131
3132static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3133{
3134 struct r8152 *tp = netdev_priv(dev);
3135
3136 tp->msg_enable = value;
3137}
3138
3139static void rtl8152_get_drvinfo(struct net_device *netdev,
3140 struct ethtool_drvinfo *info)
3141{
3142 struct r8152 *tp = netdev_priv(netdev);
3143
3144 strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
3145 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
3146 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3147}
3148
3149static
3150int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3151{
3152 struct r8152 *tp = netdev_priv(netdev);
3153
3154 if (!tp->mii.mdio_read)
3155 return -EOPNOTSUPP;
3156
3157 return mii_ethtool_gset(&tp->mii, cmd);
3158}
3159
3160static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3161{
3162 struct r8152 *tp = netdev_priv(dev);
3163 int ret;
3164
3165 ret = usb_autopm_get_interface(tp->intf);
3166 if (ret < 0)
3167 goto out;
3168
3169 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3170
3171 usb_autopm_put_interface(tp->intf);
3172
3173out:
3174 return ret;
3175}
3176
3177static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3178 "tx_packets",
3179 "rx_packets",
3180 "tx_errors",
3181 "rx_errors",
3182 "rx_missed",
3183 "align_errors",
3184 "tx_single_collisions",
3185 "tx_multi_collisions",
3186 "rx_unicast",
3187 "rx_broadcast",
3188 "rx_multicast",
3189 "tx_aborted",
3190 "tx_underrun",
3191};
3192
3193static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3194{
3195 switch (sset) {
3196 case ETH_SS_STATS:
3197 return ARRAY_SIZE(rtl8152_gstrings);
3198 default:
3199 return -EOPNOTSUPP;
3200 }
3201}
3202
3203static void rtl8152_get_ethtool_stats(struct net_device *dev,
3204 struct ethtool_stats *stats, u64 *data)
3205{
3206 struct r8152 *tp = netdev_priv(dev);
3207 struct tally_counter tally;
3208
3209 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3210
3211 data[0] = le64_to_cpu(tally.tx_packets);
3212 data[1] = le64_to_cpu(tally.rx_packets);
3213 data[2] = le64_to_cpu(tally.tx_errors);
3214 data[3] = le32_to_cpu(tally.rx_errors);
3215 data[4] = le16_to_cpu(tally.rx_missed);
3216 data[5] = le16_to_cpu(tally.align_errors);
3217 data[6] = le32_to_cpu(tally.tx_one_collision);
3218 data[7] = le32_to_cpu(tally.tx_multi_collision);
3219 data[8] = le64_to_cpu(tally.rx_unicast);
3220 data[9] = le64_to_cpu(tally.rx_broadcast);
3221 data[10] = le32_to_cpu(tally.rx_multicast);
3222 data[11] = le16_to_cpu(tally.tx_aborted);
3223 data[12] = le16_to_cpu(tally.tx_underun);
3224}
3225
3226static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3227{
3228 switch (stringset) {
3229 case ETH_SS_STATS:
3230 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3231 break;
3232 }
3233}
3234
3235static struct ethtool_ops ops = {
3236 .get_drvinfo = rtl8152_get_drvinfo,
3237 .get_settings = rtl8152_get_settings,
3238 .set_settings = rtl8152_set_settings,
3239 .get_link = ethtool_op_get_link,
3240 .get_msglevel = rtl8152_get_msglevel,
3241 .set_msglevel = rtl8152_set_msglevel,
3242 .get_wol = rtl8152_get_wol,
3243 .set_wol = rtl8152_set_wol,
3244 .get_strings = rtl8152_get_strings,
3245 .get_sset_count = rtl8152_get_sset_count,
3246 .get_ethtool_stats = rtl8152_get_ethtool_stats,
3247};
3248
3249static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3250{
3251 struct r8152 *tp = netdev_priv(netdev);
3252 struct mii_ioctl_data *data = if_mii(rq);
3253 int res;
3254
3255 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3256 return -ENODEV;
3257
3258 res = usb_autopm_get_interface(tp->intf);
3259 if (res < 0)
3260 goto out;
3261
3262 switch (cmd) {
3263 case SIOCGMIIPHY:
3264 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3265 break;
3266
3267 case SIOCGMIIREG:
3268 data->val_out = r8152_mdio_read(tp, data->reg_num);
3269 break;
3270
3271 case SIOCSMIIREG:
3272 if (!capable(CAP_NET_ADMIN)) {
3273 res = -EPERM;
3274 break;
3275 }
3276 r8152_mdio_write(tp, data->reg_num, data->val_in);
3277 break;
3278
3279 default:
3280 res = -EOPNOTSUPP;
3281 }
3282
3283 usb_autopm_put_interface(tp->intf);
3284
3285out:
3286 return res;
3287}
3288
3289static const struct net_device_ops rtl8152_netdev_ops = {
3290 .ndo_open = rtl8152_open,
3291 .ndo_stop = rtl8152_close,
3292 .ndo_do_ioctl = rtl8152_ioctl,
3293 .ndo_start_xmit = rtl8152_start_xmit,
3294 .ndo_tx_timeout = rtl8152_tx_timeout,
3295 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3296 .ndo_set_mac_address = rtl8152_set_mac_address,
3297
3298 .ndo_change_mtu = eth_change_mtu,
3299 .ndo_validate_addr = eth_validate_addr,
3300};
3301
3302static void r8152b_get_version(struct r8152 *tp)
3303{
3304 u32 ocp_data;
3305 u16 version;
3306
3307 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3308 version = (u16)(ocp_data & VERSION_MASK);
3309
3310 switch (version) {
3311 case 0x4c00:
3312 tp->version = RTL_VER_01;
3313 break;
3314 case 0x4c10:
3315 tp->version = RTL_VER_02;
3316 break;
3317 case 0x5c00:
3318 tp->version = RTL_VER_03;
3319 tp->mii.supports_gmii = 1;
3320 break;
3321 case 0x5c10:
3322 tp->version = RTL_VER_04;
3323 tp->mii.supports_gmii = 1;
3324 break;
3325 case 0x5c20:
3326 tp->version = RTL_VER_05;
3327 tp->mii.supports_gmii = 1;
3328 break;
3329 default:
3330 netif_info(tp, probe, tp->netdev,
3331 "Unknown version 0x%04x\n", version);
3332 break;
3333 }
3334}
3335
3336static void rtl8152_unload(struct r8152 *tp)
3337{
3338 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3339 return;
3340
3341 if (tp->version != RTL_VER_01)
3342 r8152_power_cut_en(tp, true);
3343}
3344
3345static void rtl8153_unload(struct r8152 *tp)
3346{
3347 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3348 return;
3349
3350 r8153_power_cut_en(tp, true);
3351}
3352
3353static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
3354{
3355 struct rtl_ops *ops = &tp->rtl_ops;
3356 int ret = -ENODEV;
3357
3358 switch (id->idVendor) {
3359 case VENDOR_ID_REALTEK:
3360 switch (id->idProduct) {
3361 case PRODUCT_ID_RTL8152:
3362 ops->init = r8152b_init;
3363 ops->enable = rtl8152_enable;
3364 ops->disable = rtl8152_disable;
3365 ops->up = r8152b_exit_oob;
3366 ops->down = rtl8152_down;
3367 ops->unload = rtl8152_unload;
3368 ret = 0;
3369 break;
3370 case PRODUCT_ID_RTL8153:
3371 ops->init = r8153_init;
3372 ops->enable = rtl8153_enable;
3373 ops->disable = rtl8152_disable;
3374 ops->up = r8153_first_init;
3375 ops->down = rtl8153_down;
3376 ops->unload = rtl8153_unload;
3377 ret = 0;
3378 break;
3379 default:
3380 break;
3381 }
3382 break;
3383
3384 case VENDOR_ID_SAMSUNG:
3385 switch (id->idProduct) {
3386 case PRODUCT_ID_SAMSUNG:
3387 ops->init = r8153_init;
3388 ops->enable = rtl8153_enable;
3389 ops->disable = rtl8152_disable;
3390 ops->up = r8153_first_init;
3391 ops->down = rtl8153_down;
3392 ops->unload = rtl8153_unload;
3393 ret = 0;
3394 break;
3395 default:
3396 break;
3397 }
3398 break;
3399
3400 default:
3401 break;
3402 }
3403
3404 if (ret)
3405 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3406
3407 return ret;
3408}
3409
3410static int rtl8152_probe(struct usb_interface *intf,
3411 const struct usb_device_id *id)
3412{
3413 struct usb_device *udev = interface_to_usbdev(intf);
3414 struct r8152 *tp;
3415 struct net_device *netdev;
3416 int ret;
3417
3418 if (udev->actconfig->desc.bConfigurationValue != 1) {
3419 usb_driver_set_configuration(udev, 1);
3420 return -ENODEV;
3421 }
3422
3423 usb_reset_device(udev);
3424 netdev = alloc_etherdev(sizeof(struct r8152));
3425 if (!netdev) {
3426 dev_err(&intf->dev, "Out of memory\n");
3427 return -ENOMEM;
3428 }
3429
3430 SET_NETDEV_DEV(netdev, &intf->dev);
3431 tp = netdev_priv(netdev);
3432 tp->msg_enable = 0x7FFF;
3433
3434 tp->udev = udev;
3435 tp->netdev = netdev;
3436 tp->intf = intf;
3437
3438 ret = rtl_ops_init(tp, id);
3439 if (ret)
3440 goto out;
3441
3442 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
3443 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3444
3445 netdev->netdev_ops = &rtl8152_netdev_ops;
3446 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
3447
3448 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3449 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
3450 NETIF_F_TSO6;
3451 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3452 NETIF_F_TSO | NETIF_F_FRAGLIST |
3453 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
3454
3455 SET_ETHTOOL_OPS(netdev, &ops);
3456 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
3457
3458 tp->mii.dev = netdev;
3459 tp->mii.mdio_read = read_mii_word;
3460 tp->mii.mdio_write = write_mii_word;
3461 tp->mii.phy_id_mask = 0x3f;
3462 tp->mii.reg_num_mask = 0x1f;
3463 tp->mii.phy_id = R8152_PHY_ID;
3464 tp->mii.supports_gmii = 0;
3465
3466 intf->needs_remote_wakeup = 1;
3467
3468 r8152b_get_version(tp);
3469 tp->rtl_ops.init(tp);
3470 set_ethernet_addr(tp);
3471
3472 usb_set_intfdata(intf, tp);
3473
3474 ret = register_netdev(netdev);
3475 if (ret != 0) {
3476 netif_err(tp, probe, netdev, "couldn't register the device\n");
3477 goto out1;
3478 }
3479
3480 tp->saved_wolopts = __rtl_get_wol(tp);
3481 if (tp->saved_wolopts)
3482 device_set_wakeup_enable(&udev->dev, true);
3483 else
3484 device_set_wakeup_enable(&udev->dev, false);
3485
3486 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
3487
3488 return 0;
3489
3490out1:
3491 usb_set_intfdata(intf, NULL);
3492out:
3493 free_netdev(netdev);
3494 return ret;
3495}
3496
3497static void rtl8152_disconnect(struct usb_interface *intf)
3498{
3499 struct r8152 *tp = usb_get_intfdata(intf);
3500
3501 usb_set_intfdata(intf, NULL);
3502 if (tp) {
3503 set_bit(RTL8152_UNPLUG, &tp->flags);
3504 tasklet_kill(&tp->tl);
3505 unregister_netdev(tp->netdev);
3506 tp->rtl_ops.unload(tp);
3507 free_netdev(tp->netdev);
3508 }
3509}
3510
3511/* table of devices that work with this driver */
3512static struct usb_device_id rtl8152_table[] = {
3513 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
3514 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
3515 {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
3516 {}
3517};
3518
3519MODULE_DEVICE_TABLE(usb, rtl8152_table);
3520
3521static struct usb_driver rtl8152_driver = {
3522 .name = MODULENAME,
3523 .id_table = rtl8152_table,
3524 .probe = rtl8152_probe,
3525 .disconnect = rtl8152_disconnect,
3526 .suspend = rtl8152_suspend,
3527 .resume = rtl8152_resume,
3528 .reset_resume = rtl8152_resume,
3529 .supports_autosuspend = 1,
3530 .disable_hub_initiated_lpm = 1,
3531};
3532
3533module_usb_driver(rtl8152_driver);
3534
3535MODULE_AUTHOR(DRIVER_AUTHOR);
3536MODULE_DESCRIPTION(DRIVER_DESC);
3537MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4 */
5
6#include <linux/signal.h>
7#include <linux/slab.h>
8#include <linux/module.h>
9#include <linux/netdevice.h>
10#include <linux/etherdevice.h>
11#include <linux/mii.h>
12#include <linux/ethtool.h>
13#include <linux/usb.h>
14#include <linux/crc32.h>
15#include <linux/if_vlan.h>
16#include <linux/uaccess.h>
17#include <linux/list.h>
18#include <linux/ip.h>
19#include <linux/ipv6.h>
20#include <net/ip6_checksum.h>
21#include <uapi/linux/mdio.h>
22#include <linux/mdio.h>
23#include <linux/usb/cdc.h>
24#include <linux/suspend.h>
25#include <linux/atomic.h>
26#include <linux/acpi.h>
27#include <linux/firmware.h>
28#include <crypto/hash.h>
29#include <linux/usb/r8152.h>
30
31/* Information for net-next */
32#define NETNEXT_VERSION "12"
33
34/* Information for net */
35#define NET_VERSION "13"
36
37#define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
38#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
39#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
40#define MODULENAME "r8152"
41
42#define R8152_PHY_ID 32
43
44#define PLA_IDR 0xc000
45#define PLA_RCR 0xc010
46#define PLA_RCR1 0xc012
47#define PLA_RMS 0xc016
48#define PLA_RXFIFO_CTRL0 0xc0a0
49#define PLA_RXFIFO_FULL 0xc0a2
50#define PLA_RXFIFO_CTRL1 0xc0a4
51#define PLA_RX_FIFO_FULL 0xc0a6
52#define PLA_RXFIFO_CTRL2 0xc0a8
53#define PLA_RX_FIFO_EMPTY 0xc0aa
54#define PLA_DMY_REG0 0xc0b0
55#define PLA_FMC 0xc0b4
56#define PLA_CFG_WOL 0xc0b6
57#define PLA_TEREDO_CFG 0xc0bc
58#define PLA_TEREDO_WAKE_BASE 0xc0c4
59#define PLA_MAR 0xcd00
60#define PLA_BACKUP 0xd000
61#define PLA_BDC_CR 0xd1a0
62#define PLA_TEREDO_TIMER 0xd2cc
63#define PLA_REALWOW_TIMER 0xd2e8
64#define PLA_UPHY_TIMER 0xd388
65#define PLA_SUSPEND_FLAG 0xd38a
66#define PLA_INDICATE_FALG 0xd38c
67#define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
68#define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
69#define PLA_EXTRA_STATUS 0xd398
70#define PLA_GPHY_CTRL 0xd3ae
71#define PLA_POL_GPIO_CTRL 0xdc6a
72#define PLA_EFUSE_DATA 0xdd00
73#define PLA_EFUSE_CMD 0xdd02
74#define PLA_LEDSEL 0xdd90
75#define PLA_LED_FEATURE 0xdd92
76#define PLA_PHYAR 0xde00
77#define PLA_BOOT_CTRL 0xe004
78#define PLA_LWAKE_CTRL_REG 0xe007
79#define PLA_GPHY_INTR_IMR 0xe022
80#define PLA_EEE_CR 0xe040
81#define PLA_EEE_TXTWSYS 0xe04c
82#define PLA_EEE_TXTWSYS_2P5G 0xe058
83#define PLA_EEEP_CR 0xe080
84#define PLA_MAC_PWR_CTRL 0xe0c0
85#define PLA_MAC_PWR_CTRL2 0xe0ca
86#define PLA_MAC_PWR_CTRL3 0xe0cc
87#define PLA_MAC_PWR_CTRL4 0xe0ce
88#define PLA_WDT6_CTRL 0xe428
89#define PLA_TCR0 0xe610
90#define PLA_TCR1 0xe612
91#define PLA_MTPS 0xe615
92#define PLA_TXFIFO_CTRL 0xe618
93#define PLA_TXFIFO_FULL 0xe61a
94#define PLA_RSTTALLY 0xe800
95#define PLA_CR 0xe813
96#define PLA_CRWECR 0xe81c
97#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
98#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
99#define PLA_CONFIG5 0xe822
100#define PLA_PHY_PWR 0xe84c
101#define PLA_OOB_CTRL 0xe84f
102#define PLA_CPCR 0xe854
103#define PLA_MISC_0 0xe858
104#define PLA_MISC_1 0xe85a
105#define PLA_OCP_GPHY_BASE 0xe86c
106#define PLA_TALLYCNT 0xe890
107#define PLA_SFF_STS_7 0xe8de
108#define PLA_PHYSTATUS 0xe908
109#define PLA_CONFIG6 0xe90a /* CONFIG6 */
110#define PLA_USB_CFG 0xe952
111#define PLA_BP_BA 0xfc26
112#define PLA_BP_0 0xfc28
113#define PLA_BP_1 0xfc2a
114#define PLA_BP_2 0xfc2c
115#define PLA_BP_3 0xfc2e
116#define PLA_BP_4 0xfc30
117#define PLA_BP_5 0xfc32
118#define PLA_BP_6 0xfc34
119#define PLA_BP_7 0xfc36
120#define PLA_BP_EN 0xfc38
121
122#define USB_USB2PHY 0xb41e
123#define USB_SSPHYLINK1 0xb426
124#define USB_SSPHYLINK2 0xb428
125#define USB_L1_CTRL 0xb45e
126#define USB_U2P3_CTRL 0xb460
127#define USB_CSR_DUMMY1 0xb464
128#define USB_CSR_DUMMY2 0xb466
129#define USB_DEV_STAT 0xb808
130#define USB_CONNECT_TIMER 0xcbf8
131#define USB_MSC_TIMER 0xcbfc
132#define USB_BURST_SIZE 0xcfc0
133#define USB_FW_FIX_EN0 0xcfca
134#define USB_FW_FIX_EN1 0xcfcc
135#define USB_LPM_CONFIG 0xcfd8
136#define USB_ECM_OPTION 0xcfee
137#define USB_CSTMR 0xcfef /* RTL8153A */
138#define USB_MISC_2 0xcfff
139#define USB_ECM_OP 0xd26b
140#define USB_GPHY_CTRL 0xd284
141#define USB_SPEED_OPTION 0xd32a
142#define USB_FW_CTRL 0xd334 /* RTL8153B */
143#define USB_FC_TIMER 0xd340
144#define USB_USB_CTRL 0xd406
145#define USB_PHY_CTRL 0xd408
146#define USB_TX_AGG 0xd40a
147#define USB_RX_BUF_TH 0xd40c
148#define USB_USB_TIMER 0xd428
149#define USB_RX_EARLY_TIMEOUT 0xd42c
150#define USB_RX_EARLY_SIZE 0xd42e
151#define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
152#define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
153#define USB_TX_DMA 0xd434
154#define USB_UPT_RXDMA_OWN 0xd437
155#define USB_UPHY3_MDCMDIO 0xd480
156#define USB_TOLERANCE 0xd490
157#define USB_LPM_CTRL 0xd41a
158#define USB_BMU_RESET 0xd4b0
159#define USB_BMU_CONFIG 0xd4b4
160#define USB_U1U2_TIMER 0xd4da
161#define USB_FW_TASK 0xd4e8 /* RTL8153B */
162#define USB_RX_AGGR_NUM 0xd4ee
163#define USB_UPS_CTRL 0xd800
164#define USB_POWER_CUT 0xd80a
165#define USB_MISC_0 0xd81a
166#define USB_MISC_1 0xd81f
167#define USB_AFE_CTRL2 0xd824
168#define USB_UPHY_XTAL 0xd826
169#define USB_UPS_CFG 0xd842
170#define USB_UPS_FLAGS 0xd848
171#define USB_WDT1_CTRL 0xe404
172#define USB_WDT11_CTRL 0xe43c
173#define USB_BP_BA PLA_BP_BA
174#define USB_BP_0 PLA_BP_0
175#define USB_BP_1 PLA_BP_1
176#define USB_BP_2 PLA_BP_2
177#define USB_BP_3 PLA_BP_3
178#define USB_BP_4 PLA_BP_4
179#define USB_BP_5 PLA_BP_5
180#define USB_BP_6 PLA_BP_6
181#define USB_BP_7 PLA_BP_7
182#define USB_BP_EN PLA_BP_EN /* RTL8153A */
183#define USB_BP_8 0xfc38 /* RTL8153B */
184#define USB_BP_9 0xfc3a
185#define USB_BP_10 0xfc3c
186#define USB_BP_11 0xfc3e
187#define USB_BP_12 0xfc40
188#define USB_BP_13 0xfc42
189#define USB_BP_14 0xfc44
190#define USB_BP_15 0xfc46
191#define USB_BP2_EN 0xfc48
192
193/* OCP Registers */
194#define OCP_ALDPS_CONFIG 0x2010
195#define OCP_EEE_CONFIG1 0x2080
196#define OCP_EEE_CONFIG2 0x2092
197#define OCP_EEE_CONFIG3 0x2094
198#define OCP_BASE_MII 0xa400
199#define OCP_EEE_AR 0xa41a
200#define OCP_EEE_DATA 0xa41c
201#define OCP_PHY_STATUS 0xa420
202#define OCP_NCTL_CFG 0xa42c
203#define OCP_POWER_CFG 0xa430
204#define OCP_EEE_CFG 0xa432
205#define OCP_SRAM_ADDR 0xa436
206#define OCP_SRAM_DATA 0xa438
207#define OCP_DOWN_SPEED 0xa442
208#define OCP_EEE_ABLE 0xa5c4
209#define OCP_EEE_ADV 0xa5d0
210#define OCP_EEE_LPABLE 0xa5d2
211#define OCP_10GBT_CTRL 0xa5d4
212#define OCP_10GBT_STAT 0xa5d6
213#define OCP_EEE_ADV2 0xa6d4
214#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
215#define OCP_PHY_PATCH_STAT 0xb800
216#define OCP_PHY_PATCH_CMD 0xb820
217#define OCP_PHY_LOCK 0xb82e
218#define OCP_ADC_IOFFSET 0xbcfc
219#define OCP_ADC_CFG 0xbc06
220#define OCP_SYSCLK_CFG 0xc416
221
222/* SRAM Register */
223#define SRAM_GREEN_CFG 0x8011
224#define SRAM_LPF_CFG 0x8012
225#define SRAM_GPHY_FW_VER 0x801e
226#define SRAM_10M_AMP1 0x8080
227#define SRAM_10M_AMP2 0x8082
228#define SRAM_IMPEDANCE 0x8084
229#define SRAM_PHY_LOCK 0xb82e
230
231/* PLA_RCR */
232#define RCR_AAP 0x00000001
233#define RCR_APM 0x00000002
234#define RCR_AM 0x00000004
235#define RCR_AB 0x00000008
236#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
237#define SLOT_EN BIT(11)
238
239/* PLA_RCR1 */
240#define OUTER_VLAN BIT(7)
241#define INNER_VLAN BIT(6)
242
243/* PLA_RXFIFO_CTRL0 */
244#define RXFIFO_THR1_NORMAL 0x00080002
245#define RXFIFO_THR1_OOB 0x01800003
246
247/* PLA_RXFIFO_FULL */
248#define RXFIFO_FULL_MASK 0xfff
249
250/* PLA_RXFIFO_CTRL1 */
251#define RXFIFO_THR2_FULL 0x00000060
252#define RXFIFO_THR2_HIGH 0x00000038
253#define RXFIFO_THR2_OOB 0x0000004a
254#define RXFIFO_THR2_NORMAL 0x00a0
255
256/* PLA_RXFIFO_CTRL2 */
257#define RXFIFO_THR3_FULL 0x00000078
258#define RXFIFO_THR3_HIGH 0x00000048
259#define RXFIFO_THR3_OOB 0x0000005a
260#define RXFIFO_THR3_NORMAL 0x0110
261
262/* PLA_TXFIFO_CTRL */
263#define TXFIFO_THR_NORMAL 0x00400008
264#define TXFIFO_THR_NORMAL2 0x01000008
265
266/* PLA_DMY_REG0 */
267#define ECM_ALDPS 0x0002
268
269/* PLA_FMC */
270#define FMC_FCR_MCU_EN 0x0001
271
272/* PLA_EEEP_CR */
273#define EEEP_CR_EEEP_TX 0x0002
274
275/* PLA_WDT6_CTRL */
276#define WDT6_SET_MODE 0x0010
277
278/* PLA_TCR0 */
279#define TCR0_TX_EMPTY 0x0800
280#define TCR0_AUTO_FIFO 0x0080
281
282/* PLA_TCR1 */
283#define VERSION_MASK 0x7cf0
284#define IFG_MASK (BIT(3) | BIT(9) | BIT(8))
285#define IFG_144NS BIT(9)
286#define IFG_96NS (BIT(9) | BIT(8))
287
288/* PLA_MTPS */
289#define MTPS_JUMBO (12 * 1024 / 64)
290#define MTPS_DEFAULT (6 * 1024 / 64)
291
292/* PLA_RSTTALLY */
293#define TALLY_RESET 0x0001
294
295/* PLA_CR */
296#define CR_RST 0x10
297#define CR_RE 0x08
298#define CR_TE 0x04
299
300/* PLA_CRWECR */
301#define CRWECR_NORAML 0x00
302#define CRWECR_CONFIG 0xc0
303
304/* PLA_OOB_CTRL */
305#define NOW_IS_OOB 0x80
306#define TXFIFO_EMPTY 0x20
307#define RXFIFO_EMPTY 0x10
308#define LINK_LIST_READY 0x02
309#define DIS_MCU_CLROOB 0x01
310#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
311
312/* PLA_MISC_1 */
313#define RXDY_GATED_EN 0x0008
314
315/* PLA_SFF_STS_7 */
316#define RE_INIT_LL 0x8000
317#define MCU_BORW_EN 0x4000
318
319/* PLA_CPCR */
320#define FLOW_CTRL_EN BIT(0)
321#define CPCR_RX_VLAN 0x0040
322
323/* PLA_CFG_WOL */
324#define MAGIC_EN 0x0001
325
326/* PLA_TEREDO_CFG */
327#define TEREDO_SEL 0x8000
328#define TEREDO_WAKE_MASK 0x7f00
329#define TEREDO_RS_EVENT_MASK 0x00fe
330#define OOB_TEREDO_EN 0x0001
331
332/* PLA_BDC_CR */
333#define ALDPS_PROXY_MODE 0x0001
334
335/* PLA_EFUSE_CMD */
336#define EFUSE_READ_CMD BIT(15)
337#define EFUSE_DATA_BIT16 BIT(7)
338
339/* PLA_CONFIG34 */
340#define LINK_ON_WAKE_EN 0x0010
341#define LINK_OFF_WAKE_EN 0x0008
342
343/* PLA_CONFIG6 */
344#define LANWAKE_CLR_EN BIT(0)
345
346/* PLA_USB_CFG */
347#define EN_XG_LIP BIT(1)
348#define EN_G_LIP BIT(2)
349
350/* PLA_CONFIG5 */
351#define BWF_EN 0x0040
352#define MWF_EN 0x0020
353#define UWF_EN 0x0010
354#define LAN_WAKE_EN 0x0002
355
356/* PLA_LED_FEATURE */
357#define LED_MODE_MASK 0x0700
358
359/* PLA_PHY_PWR */
360#define TX_10M_IDLE_EN 0x0080
361#define PFM_PWM_SWITCH 0x0040
362#define TEST_IO_OFF BIT(4)
363
364/* PLA_MAC_PWR_CTRL */
365#define D3_CLK_GATED_EN 0x00004000
366#define MCU_CLK_RATIO 0x07010f07
367#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
368#define ALDPS_SPDWN_RATIO 0x0f87
369
370/* PLA_MAC_PWR_CTRL2 */
371#define EEE_SPDWN_RATIO 0x8007
372#define MAC_CLK_SPDWN_EN BIT(15)
373#define EEE_SPDWN_RATIO_MASK 0xff
374
375/* PLA_MAC_PWR_CTRL3 */
376#define PLA_MCU_SPDWN_EN BIT(14)
377#define PKT_AVAIL_SPDWN_EN 0x0100
378#define SUSPEND_SPDWN_EN 0x0004
379#define U1U2_SPDWN_EN 0x0002
380#define L1_SPDWN_EN 0x0001
381
382/* PLA_MAC_PWR_CTRL4 */
383#define PWRSAVE_SPDWN_EN 0x1000
384#define RXDV_SPDWN_EN 0x0800
385#define TX10MIDLE_EN 0x0100
386#define IDLE_SPDWN_EN BIT(6)
387#define TP100_SPDWN_EN 0x0020
388#define TP500_SPDWN_EN 0x0010
389#define TP1000_SPDWN_EN 0x0008
390#define EEE_SPDWN_EN 0x0001
391
392/* PLA_GPHY_INTR_IMR */
393#define GPHY_STS_MSK 0x0001
394#define SPEED_DOWN_MSK 0x0002
395#define SPDWN_RXDV_MSK 0x0004
396#define SPDWN_LINKCHG_MSK 0x0008
397
398/* PLA_PHYAR */
399#define PHYAR_FLAG 0x80000000
400
401/* PLA_EEE_CR */
402#define EEE_RX_EN 0x0001
403#define EEE_TX_EN 0x0002
404
405/* PLA_BOOT_CTRL */
406#define AUTOLOAD_DONE 0x0002
407
408/* PLA_LWAKE_CTRL_REG */
409#define LANWAKE_PIN BIT(7)
410
411/* PLA_SUSPEND_FLAG */
412#define LINK_CHG_EVENT BIT(0)
413
414/* PLA_INDICATE_FALG */
415#define UPCOMING_RUNTIME_D3 BIT(0)
416
417/* PLA_MACDBG_PRE and PLA_MACDBG_POST */
418#define DEBUG_OE BIT(0)
419#define DEBUG_LTSSM 0x0082
420
421/* PLA_EXTRA_STATUS */
422#define CUR_LINK_OK BIT(15)
423#define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
424#define LINK_CHANGE_FLAG BIT(8)
425#define POLL_LINK_CHG BIT(0)
426
427/* PLA_GPHY_CTRL */
428#define GPHY_FLASH BIT(1)
429
430/* PLA_POL_GPIO_CTRL */
431#define DACK_DET_EN BIT(15)
432#define POL_GPHY_PATCH BIT(4)
433
434/* USB_USB2PHY */
435#define USB2PHY_SUSPEND 0x0001
436#define USB2PHY_L1 0x0002
437
438/* USB_SSPHYLINK1 */
439#define DELAY_PHY_PWR_CHG BIT(1)
440
441/* USB_SSPHYLINK2 */
442#define pwd_dn_scale_mask 0x3ffe
443#define pwd_dn_scale(x) ((x) << 1)
444
445/* USB_CSR_DUMMY1 */
446#define DYNAMIC_BURST 0x0001
447
448/* USB_CSR_DUMMY2 */
449#define EP4_FULL_FC 0x0001
450
451/* USB_DEV_STAT */
452#define STAT_SPEED_MASK 0x0006
453#define STAT_SPEED_HIGH 0x0000
454#define STAT_SPEED_FULL 0x0002
455
456/* USB_FW_FIX_EN0 */
457#define FW_FIX_SUSPEND BIT(14)
458
459/* USB_FW_FIX_EN1 */
460#define FW_IP_RESET_EN BIT(9)
461
462/* USB_LPM_CONFIG */
463#define LPM_U1U2_EN BIT(0)
464
465/* USB_TX_AGG */
466#define TX_AGG_MAX_THRESHOLD 0x03
467
468/* USB_RX_BUF_TH */
469#define RX_THR_SUPPER 0x0c350180
470#define RX_THR_HIGH 0x7a120180
471#define RX_THR_SLOW 0xffff0180
472#define RX_THR_B 0x00010001
473
474/* USB_TX_DMA */
475#define TEST_MODE_DISABLE 0x00000001
476#define TX_SIZE_ADJUST1 0x00000100
477
478/* USB_BMU_RESET */
479#define BMU_RESET_EP_IN 0x01
480#define BMU_RESET_EP_OUT 0x02
481
482/* USB_BMU_CONFIG */
483#define ACT_ODMA BIT(1)
484
485/* USB_UPT_RXDMA_OWN */
486#define OWN_UPDATE BIT(0)
487#define OWN_CLEAR BIT(1)
488
489/* USB_FW_TASK */
490#define FC_PATCH_TASK BIT(1)
491
492/* USB_RX_AGGR_NUM */
493#define RX_AGGR_NUM_MASK 0x1ff
494
495/* USB_UPS_CTRL */
496#define POWER_CUT 0x0100
497
498/* USB_PM_CTRL_STATUS */
499#define RESUME_INDICATE 0x0001
500
501/* USB_ECM_OPTION */
502#define BYPASS_MAC_RESET BIT(5)
503
504/* USB_CSTMR */
505#define FORCE_SUPER BIT(0)
506
507/* USB_MISC_2 */
508#define UPS_FORCE_PWR_DOWN BIT(0)
509
510/* USB_ECM_OP */
511#define EN_ALL_SPEED BIT(0)
512
513/* USB_GPHY_CTRL */
514#define GPHY_PATCH_DONE BIT(2)
515#define BYPASS_FLASH BIT(5)
516#define BACKUP_RESTRORE BIT(6)
517
518/* USB_SPEED_OPTION */
519#define RG_PWRDN_EN BIT(8)
520#define ALL_SPEED_OFF BIT(9)
521
522/* USB_FW_CTRL */
523#define FLOW_CTRL_PATCH_OPT BIT(1)
524#define AUTO_SPEEDUP BIT(3)
525#define FLOW_CTRL_PATCH_2 BIT(8)
526
527/* USB_FC_TIMER */
528#define CTRL_TIMER_EN BIT(15)
529
530/* USB_USB_CTRL */
531#define CDC_ECM_EN BIT(3)
532#define RX_AGG_DISABLE 0x0010
533#define RX_ZERO_EN 0x0080
534
535/* USB_U2P3_CTRL */
536#define U2P3_ENABLE 0x0001
537#define RX_DETECT8 BIT(3)
538
539/* USB_POWER_CUT */
540#define PWR_EN 0x0001
541#define PHASE2_EN 0x0008
542#define UPS_EN BIT(4)
543#define USP_PREWAKE BIT(5)
544
545/* USB_MISC_0 */
546#define PCUT_STATUS 0x0001
547
548/* USB_RX_EARLY_TIMEOUT */
549#define COALESCE_SUPER 85000U
550#define COALESCE_HIGH 250000U
551#define COALESCE_SLOW 524280U
552
553/* USB_WDT1_CTRL */
554#define WTD1_EN BIT(0)
555
556/* USB_WDT11_CTRL */
557#define TIMER11_EN 0x0001
558
559/* USB_LPM_CTRL */
560/* bit 4 ~ 5: fifo empty boundary */
561#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
562/* bit 2 ~ 3: LMP timer */
563#define LPM_TIMER_MASK 0x0c
564#define LPM_TIMER_500MS 0x04 /* 500 ms */
565#define LPM_TIMER_500US 0x0c /* 500 us */
566#define ROK_EXIT_LPM 0x02
567
568/* USB_AFE_CTRL2 */
569#define SEN_VAL_MASK 0xf800
570#define SEN_VAL_NORMAL 0xa000
571#define SEL_RXIDLE 0x0100
572
573/* USB_UPHY_XTAL */
574#define OOBS_POLLING BIT(8)
575
576/* USB_UPS_CFG */
577#define SAW_CNT_1MS_MASK 0x0fff
578#define MID_REVERSE BIT(5) /* RTL8156A */
579
580/* USB_UPS_FLAGS */
581#define UPS_FLAGS_R_TUNE BIT(0)
582#define UPS_FLAGS_EN_10M_CKDIV BIT(1)
583#define UPS_FLAGS_250M_CKDIV BIT(2)
584#define UPS_FLAGS_EN_ALDPS BIT(3)
585#define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
586#define UPS_FLAGS_SPEED_MASK (0xf << 16)
587#define ups_flags_speed(x) ((x) << 16)
588#define UPS_FLAGS_EN_EEE BIT(20)
589#define UPS_FLAGS_EN_500M_EEE BIT(21)
590#define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
591#define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
592#define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
593#define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
594#define UPS_FLAGS_EN_GREEN BIT(26)
595#define UPS_FLAGS_EN_FLOW_CTR BIT(27)
596
597enum spd_duplex {
598 NWAY_10M_HALF,
599 NWAY_10M_FULL,
600 NWAY_100M_HALF,
601 NWAY_100M_FULL,
602 NWAY_1000M_FULL,
603 FORCE_10M_HALF,
604 FORCE_10M_FULL,
605 FORCE_100M_HALF,
606 FORCE_100M_FULL,
607 FORCE_1000M_FULL,
608 NWAY_2500M_FULL,
609};
610
611/* OCP_ALDPS_CONFIG */
612#define ENPWRSAVE 0x8000
613#define ENPDNPS 0x0200
614#define LINKENA 0x0100
615#define DIS_SDSAVE 0x0010
616
617/* OCP_PHY_STATUS */
618#define PHY_STAT_MASK 0x0007
619#define PHY_STAT_EXT_INIT 2
620#define PHY_STAT_LAN_ON 3
621#define PHY_STAT_PWRDN 5
622
623/* OCP_NCTL_CFG */
624#define PGA_RETURN_EN BIT(1)
625
626/* OCP_POWER_CFG */
627#define EEE_CLKDIV_EN 0x8000
628#define EN_ALDPS 0x0004
629#define EN_10M_PLLOFF 0x0001
630
631/* OCP_EEE_CONFIG1 */
632#define RG_TXLPI_MSK_HFDUP 0x8000
633#define RG_MATCLR_EN 0x4000
634#define EEE_10_CAP 0x2000
635#define EEE_NWAY_EN 0x1000
636#define TX_QUIET_EN 0x0200
637#define RX_QUIET_EN 0x0100
638#define sd_rise_time_mask 0x0070
639#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
640#define RG_RXLPI_MSK_HFDUP 0x0008
641#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
642
643/* OCP_EEE_CONFIG2 */
644#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
645#define RG_DACQUIET_EN 0x0400
646#define RG_LDVQUIET_EN 0x0200
647#define RG_CKRSEL 0x0020
648#define RG_EEEPRG_EN 0x0010
649
650/* OCP_EEE_CONFIG3 */
651#define fast_snr_mask 0xff80
652#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
653#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
654#define MSK_PH 0x0006 /* bit 0 ~ 3 */
655
656/* OCP_EEE_AR */
657/* bit[15:14] function */
658#define FUN_ADDR 0x0000
659#define FUN_DATA 0x4000
660/* bit[4:0] device addr */
661
662/* OCP_EEE_CFG */
663#define CTAP_SHORT_EN 0x0040
664#define EEE10_EN 0x0010
665
666/* OCP_DOWN_SPEED */
667#define EN_EEE_CMODE BIT(14)
668#define EN_EEE_1000 BIT(13)
669#define EN_EEE_100 BIT(12)
670#define EN_10M_CLKDIV BIT(11)
671#define EN_10M_BGOFF 0x0080
672
673/* OCP_10GBT_CTRL */
674#define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
675
676/* OCP_PHY_STATE */
677#define TXDIS_STATE 0x01
678#define ABD_STATE 0x02
679
680/* OCP_PHY_PATCH_STAT */
681#define PATCH_READY BIT(6)
682
683/* OCP_PHY_PATCH_CMD */
684#define PATCH_REQUEST BIT(4)
685
686/* OCP_PHY_LOCK */
687#define PATCH_LOCK BIT(0)
688
689/* OCP_ADC_CFG */
690#define CKADSEL_L 0x0100
691#define ADC_EN 0x0080
692#define EN_EMI_L 0x0040
693
694/* OCP_SYSCLK_CFG */
695#define sysclk_div_expo(x) (min(x, 5) << 8)
696#define clk_div_expo(x) (min(x, 5) << 4)
697
698/* SRAM_GREEN_CFG */
699#define GREEN_ETH_EN BIT(15)
700#define R_TUNE_EN BIT(11)
701
702/* SRAM_LPF_CFG */
703#define LPF_AUTO_TUNE 0x8000
704
705/* SRAM_10M_AMP1 */
706#define GDAC_IB_UPALL 0x0008
707
708/* SRAM_10M_AMP2 */
709#define AMP_DN 0x0200
710
711/* SRAM_IMPEDANCE */
712#define RX_DRIVING_MASK 0x6000
713
714/* SRAM_PHY_LOCK */
715#define PHY_PATCH_LOCK 0x0001
716
717/* MAC PASSTHRU */
718#define AD_MASK 0xfee0
719#define BND_MASK 0x0004
720#define BD_MASK 0x0001
721#define EFUSE 0xcfdb
722#define PASS_THRU_MASK 0x1
723
724#define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
725
726enum rtl_register_content {
727 _2500bps = BIT(10),
728 _1250bps = BIT(9),
729 _500bps = BIT(8),
730 _tx_flow = BIT(6),
731 _rx_flow = BIT(5),
732 _1000bps = 0x10,
733 _100bps = 0x08,
734 _10bps = 0x04,
735 LINK_STATUS = 0x02,
736 FULL_DUP = 0x01,
737};
738
739#define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
740#define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
741
742#define RTL8152_MAX_TX 4
743#define RTL8152_MAX_RX 10
744#define INTBUFSIZE 2
745#define TX_ALIGN 4
746#define RX_ALIGN 8
747
748#define RTL8152_RX_MAX_PENDING 4096
749#define RTL8152_RXFG_HEADSZ 256
750
751#define INTR_LINK 0x0004
752
753#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
754#define RTL8153_RMS RTL8153_MAX_PACKET
755#define RTL8152_TX_TIMEOUT (5 * HZ)
756#define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
757#define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
758#define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
759
760/* rtl8152 flags */
761enum rtl8152_flags {
762 RTL8152_UNPLUG = 0,
763 RTL8152_SET_RX_MODE,
764 WORK_ENABLE,
765 RTL8152_LINK_CHG,
766 SELECTIVE_SUSPEND,
767 PHY_RESET,
768 SCHEDULE_TASKLET,
769 GREEN_ETHERNET,
770 RX_EPROTO,
771};
772
773#define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB 0x721e
774#define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK 0x3054
775#define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
776#define DEVICE_ID_THINKPAD_USB_C_DONGLE 0x720c
777#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
778#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3 0x3062
779
780struct tally_counter {
781 __le64 tx_packets;
782 __le64 rx_packets;
783 __le64 tx_errors;
784 __le32 rx_errors;
785 __le16 rx_missed;
786 __le16 align_errors;
787 __le32 tx_one_collision;
788 __le32 tx_multi_collision;
789 __le64 rx_unicast;
790 __le64 rx_broadcast;
791 __le32 rx_multicast;
792 __le16 tx_aborted;
793 __le16 tx_underrun;
794};
795
796struct rx_desc {
797 __le32 opts1;
798#define RX_LEN_MASK 0x7fff
799
800 __le32 opts2;
801#define RD_UDP_CS BIT(23)
802#define RD_TCP_CS BIT(22)
803#define RD_IPV6_CS BIT(20)
804#define RD_IPV4_CS BIT(19)
805
806 __le32 opts3;
807#define IPF BIT(23) /* IP checksum fail */
808#define UDPF BIT(22) /* UDP checksum fail */
809#define TCPF BIT(21) /* TCP checksum fail */
810#define RX_VLAN_TAG BIT(16)
811
812 __le32 opts4;
813 __le32 opts5;
814 __le32 opts6;
815};
816
817struct tx_desc {
818 __le32 opts1;
819#define TX_FS BIT(31) /* First segment of a packet */
820#define TX_LS BIT(30) /* Final segment of a packet */
821#define GTSENDV4 BIT(28)
822#define GTSENDV6 BIT(27)
823#define GTTCPHO_SHIFT 18
824#define GTTCPHO_MAX 0x7fU
825#define TX_LEN_MAX 0x3ffffU
826
827 __le32 opts2;
828#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
829#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
830#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
831#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
832#define MSS_SHIFT 17
833#define MSS_MAX 0x7ffU
834#define TCPHO_SHIFT 17
835#define TCPHO_MAX 0x7ffU
836#define TX_VLAN_TAG BIT(16)
837};
838
839struct r8152;
840
841struct rx_agg {
842 struct list_head list, info_list;
843 struct urb *urb;
844 struct r8152 *context;
845 struct page *page;
846 void *buffer;
847};
848
849struct tx_agg {
850 struct list_head list;
851 struct urb *urb;
852 struct r8152 *context;
853 void *buffer;
854 void *head;
855 u32 skb_num;
856 u32 skb_len;
857};
858
859struct r8152 {
860 unsigned long flags;
861 struct usb_device *udev;
862 struct napi_struct napi;
863 struct usb_interface *intf;
864 struct net_device *netdev;
865 struct urb *intr_urb;
866 struct tx_agg tx_info[RTL8152_MAX_TX];
867 struct list_head rx_info, rx_used;
868 struct list_head rx_done, tx_free;
869 struct sk_buff_head tx_queue, rx_queue;
870 spinlock_t rx_lock, tx_lock;
871 struct delayed_work schedule, hw_phy_work;
872 struct mii_if_info mii;
873 struct mutex control; /* use for hw setting */
874#ifdef CONFIG_PM_SLEEP
875 struct notifier_block pm_notifier;
876#endif
877 struct tasklet_struct tx_tl;
878
879 struct rtl_ops {
880 void (*init)(struct r8152 *tp);
881 int (*enable)(struct r8152 *tp);
882 void (*disable)(struct r8152 *tp);
883 void (*up)(struct r8152 *tp);
884 void (*down)(struct r8152 *tp);
885 void (*unload)(struct r8152 *tp);
886 int (*eee_get)(struct r8152 *tp, struct ethtool_eee *eee);
887 int (*eee_set)(struct r8152 *tp, struct ethtool_eee *eee);
888 bool (*in_nway)(struct r8152 *tp);
889 void (*hw_phy_cfg)(struct r8152 *tp);
890 void (*autosuspend_en)(struct r8152 *tp, bool enable);
891 void (*change_mtu)(struct r8152 *tp);
892 } rtl_ops;
893
894 struct ups_info {
895 u32 r_tune:1;
896 u32 _10m_ckdiv:1;
897 u32 _250m_ckdiv:1;
898 u32 aldps:1;
899 u32 lite_mode:2;
900 u32 speed_duplex:4;
901 u32 eee:1;
902 u32 eee_lite:1;
903 u32 eee_ckdiv:1;
904 u32 eee_plloff_100:1;
905 u32 eee_plloff_giga:1;
906 u32 eee_cmod_lv:1;
907 u32 green:1;
908 u32 flow_control:1;
909 u32 ctap_short_off:1;
910 } ups_info;
911
912#define RTL_VER_SIZE 32
913
914 struct rtl_fw {
915 const char *fw_name;
916 const struct firmware *fw;
917
918 char version[RTL_VER_SIZE];
919 int (*pre_fw)(struct r8152 *tp);
920 int (*post_fw)(struct r8152 *tp);
921
922 bool retry;
923 } rtl_fw;
924
925 atomic_t rx_count;
926
927 bool eee_en;
928 int intr_interval;
929 u32 saved_wolopts;
930 u32 msg_enable;
931 u32 tx_qlen;
932 u32 coalesce;
933 u32 advertising;
934 u32 rx_buf_sz;
935 u32 rx_copybreak;
936 u32 rx_pending;
937 u32 fc_pause_on, fc_pause_off;
938
939 unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out;
940
941 u32 support_2500full:1;
942 u32 lenovo_macpassthru:1;
943 u32 dell_tb_rx_agg_bug:1;
944 u16 ocp_base;
945 u16 speed;
946 u16 eee_adv;
947 u8 *intr_buff;
948 u8 version;
949 u8 duplex;
950 u8 autoneg;
951};
952
953/**
954 * struct fw_block - block type and total length
955 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA,
956 * RTL_FW_USB and so on.
957 * @length: total length of the current block.
958 */
959struct fw_block {
960 __le32 type;
961 __le32 length;
962} __packed;
963
964/**
965 * struct fw_header - header of the firmware file
966 * @checksum: checksum of sha256 which is calculated from the whole file
967 * except the checksum field of the file. That is, calculate sha256
968 * from the version field to the end of the file.
969 * @version: version of this firmware.
970 * @blocks: the first firmware block of the file
971 */
972struct fw_header {
973 u8 checksum[32];
974 char version[RTL_VER_SIZE];
975 struct fw_block blocks[];
976} __packed;
977
978enum rtl8152_fw_flags {
979 FW_FLAGS_USB = 0,
980 FW_FLAGS_PLA,
981 FW_FLAGS_START,
982 FW_FLAGS_STOP,
983 FW_FLAGS_NC,
984 FW_FLAGS_NC1,
985 FW_FLAGS_NC2,
986 FW_FLAGS_UC2,
987 FW_FLAGS_UC,
988 FW_FLAGS_SPEED_UP,
989 FW_FLAGS_VER,
990};
991
992enum rtl8152_fw_fixup_cmd {
993 FW_FIXUP_AND = 0,
994 FW_FIXUP_OR,
995 FW_FIXUP_NOT,
996 FW_FIXUP_XOR,
997};
998
999struct fw_phy_set {
1000 __le16 addr;
1001 __le16 data;
1002} __packed;
1003
1004struct fw_phy_speed_up {
1005 struct fw_block blk_hdr;
1006 __le16 fw_offset;
1007 __le16 version;
1008 __le16 fw_reg;
1009 __le16 reserved;
1010 char info[];
1011} __packed;
1012
1013struct fw_phy_ver {
1014 struct fw_block blk_hdr;
1015 struct fw_phy_set ver;
1016 __le32 reserved;
1017} __packed;
1018
1019struct fw_phy_fixup {
1020 struct fw_block blk_hdr;
1021 struct fw_phy_set setting;
1022 __le16 bit_cmd;
1023 __le16 reserved;
1024} __packed;
1025
1026struct fw_phy_union {
1027 struct fw_block blk_hdr;
1028 __le16 fw_offset;
1029 __le16 fw_reg;
1030 struct fw_phy_set pre_set[2];
1031 struct fw_phy_set bp[8];
1032 struct fw_phy_set bp_en;
1033 u8 pre_num;
1034 u8 bp_num;
1035 char info[];
1036} __packed;
1037
1038/**
1039 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB.
1040 * The layout of the firmware block is:
1041 * <struct fw_mac> + <info> + <firmware data>.
1042 * @blk_hdr: firmware descriptor (type, length)
1043 * @fw_offset: offset of the firmware binary data. The start address of
1044 * the data would be the address of struct fw_mac + @fw_offset.
1045 * @fw_reg: the register to load the firmware. Depends on chip.
1046 * @bp_ba_addr: the register to write break point base address. Depends on
1047 * chip.
1048 * @bp_ba_value: break point base address. Depends on chip.
1049 * @bp_en_addr: the register to write break point enabled mask. Depends
1050 * on chip.
1051 * @bp_en_value: break point enabled mask. Depends on the firmware.
1052 * @bp_start: the start register of break points. Depends on chip.
1053 * @bp_num: the break point number which needs to be set for this firmware.
1054 * Depends on the firmware.
1055 * @bp: break points. Depends on firmware.
1056 * @reserved: reserved space (unused)
1057 * @fw_ver_reg: the register to store the fw version.
1058 * @fw_ver_data: the firmware version of the current type.
1059 * @info: additional information for debugging, and is followed by the
1060 * binary data of firmware.
1061 */
1062struct fw_mac {
1063 struct fw_block blk_hdr;
1064 __le16 fw_offset;
1065 __le16 fw_reg;
1066 __le16 bp_ba_addr;
1067 __le16 bp_ba_value;
1068 __le16 bp_en_addr;
1069 __le16 bp_en_value;
1070 __le16 bp_start;
1071 __le16 bp_num;
1072 __le16 bp[16]; /* any value determined by firmware */
1073 __le32 reserved;
1074 __le16 fw_ver_reg;
1075 u8 fw_ver_data;
1076 char info[];
1077} __packed;
1078
1079/**
1080 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START.
1081 * This is used to set patch key when loading the firmware of PHY.
1082 * @blk_hdr: firmware descriptor (type, length)
1083 * @key_reg: the register to write the patch key.
1084 * @key_data: patch key.
1085 * @reserved: reserved space (unused)
1086 */
1087struct fw_phy_patch_key {
1088 struct fw_block blk_hdr;
1089 __le16 key_reg;
1090 __le16 key_data;
1091 __le32 reserved;
1092} __packed;
1093
1094/**
1095 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC.
1096 * The layout of the firmware block is:
1097 * <struct fw_phy_nc> + <info> + <firmware data>.
1098 * @blk_hdr: firmware descriptor (type, length)
1099 * @fw_offset: offset of the firmware binary data. The start address of
1100 * the data would be the address of struct fw_phy_nc + @fw_offset.
1101 * @fw_reg: the register to load the firmware. Depends on chip.
1102 * @ba_reg: the register to write the base address. Depends on chip.
1103 * @ba_data: base address. Depends on chip.
1104 * @patch_en_addr: the register of enabling patch mode. Depends on chip.
1105 * @patch_en_value: patch mode enabled mask. Depends on the firmware.
1106 * @mode_reg: the regitster of switching the mode.
1107 * @mode_pre: the mode needing to be set before loading the firmware.
1108 * @mode_post: the mode to be set when finishing to load the firmware.
1109 * @reserved: reserved space (unused)
1110 * @bp_start: the start register of break points. Depends on chip.
1111 * @bp_num: the break point number which needs to be set for this firmware.
1112 * Depends on the firmware.
1113 * @bp: break points. Depends on firmware.
1114 * @info: additional information for debugging, and is followed by the
1115 * binary data of firmware.
1116 */
1117struct fw_phy_nc {
1118 struct fw_block blk_hdr;
1119 __le16 fw_offset;
1120 __le16 fw_reg;
1121 __le16 ba_reg;
1122 __le16 ba_data;
1123 __le16 patch_en_addr;
1124 __le16 patch_en_value;
1125 __le16 mode_reg;
1126 __le16 mode_pre;
1127 __le16 mode_post;
1128 __le16 reserved;
1129 __le16 bp_start;
1130 __le16 bp_num;
1131 __le16 bp[4];
1132 char info[];
1133} __packed;
1134
1135enum rtl_fw_type {
1136 RTL_FW_END = 0,
1137 RTL_FW_PLA,
1138 RTL_FW_USB,
1139 RTL_FW_PHY_START,
1140 RTL_FW_PHY_STOP,
1141 RTL_FW_PHY_NC,
1142 RTL_FW_PHY_FIXUP,
1143 RTL_FW_PHY_UNION_NC,
1144 RTL_FW_PHY_UNION_NC1,
1145 RTL_FW_PHY_UNION_NC2,
1146 RTL_FW_PHY_UNION_UC2,
1147 RTL_FW_PHY_UNION_UC,
1148 RTL_FW_PHY_UNION_MISC,
1149 RTL_FW_PHY_SPEED_UP,
1150 RTL_FW_PHY_VER,
1151};
1152
1153enum rtl_version {
1154 RTL_VER_UNKNOWN = 0,
1155 RTL_VER_01,
1156 RTL_VER_02,
1157 RTL_VER_03,
1158 RTL_VER_04,
1159 RTL_VER_05,
1160 RTL_VER_06,
1161 RTL_VER_07,
1162 RTL_VER_08,
1163 RTL_VER_09,
1164
1165 RTL_TEST_01,
1166 RTL_VER_10,
1167 RTL_VER_11,
1168 RTL_VER_12,
1169 RTL_VER_13,
1170 RTL_VER_14,
1171 RTL_VER_15,
1172
1173 RTL_VER_MAX
1174};
1175
1176enum tx_csum_stat {
1177 TX_CSUM_SUCCESS = 0,
1178 TX_CSUM_TSO,
1179 TX_CSUM_NONE
1180};
1181
1182#define RTL_ADVERTISED_10_HALF BIT(0)
1183#define RTL_ADVERTISED_10_FULL BIT(1)
1184#define RTL_ADVERTISED_100_HALF BIT(2)
1185#define RTL_ADVERTISED_100_FULL BIT(3)
1186#define RTL_ADVERTISED_1000_HALF BIT(4)
1187#define RTL_ADVERTISED_1000_FULL BIT(5)
1188#define RTL_ADVERTISED_2500_FULL BIT(6)
1189
1190/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
1191 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
1192 */
1193static const int multicast_filter_limit = 32;
1194static unsigned int agg_buf_sz = 16384;
1195
1196#define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc))
1197
1198static
1199int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1200{
1201 int ret;
1202 void *tmp;
1203
1204 tmp = kmalloc(size, GFP_KERNEL);
1205 if (!tmp)
1206 return -ENOMEM;
1207
1208 ret = usb_control_msg(tp->udev, tp->pipe_ctrl_in,
1209 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
1210 value, index, tmp, size, 500);
1211 if (ret < 0)
1212 memset(data, 0xff, size);
1213 else
1214 memcpy(data, tmp, size);
1215
1216 kfree(tmp);
1217
1218 return ret;
1219}
1220
1221static
1222int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
1223{
1224 int ret;
1225 void *tmp;
1226
1227 tmp = kmemdup(data, size, GFP_KERNEL);
1228 if (!tmp)
1229 return -ENOMEM;
1230
1231 ret = usb_control_msg(tp->udev, tp->pipe_ctrl_out,
1232 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
1233 value, index, tmp, size, 500);
1234
1235 kfree(tmp);
1236
1237 return ret;
1238}
1239
1240static void rtl_set_unplug(struct r8152 *tp)
1241{
1242 if (tp->udev->state == USB_STATE_NOTATTACHED) {
1243 set_bit(RTL8152_UNPLUG, &tp->flags);
1244 smp_mb__after_atomic();
1245 }
1246}
1247
1248static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
1249 void *data, u16 type)
1250{
1251 u16 limit = 64;
1252 int ret = 0;
1253
1254 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1255 return -ENODEV;
1256
1257 /* both size and indix must be 4 bytes align */
1258 if ((size & 3) || !size || (index & 3) || !data)
1259 return -EPERM;
1260
1261 if ((u32)index + (u32)size > 0xffff)
1262 return -EPERM;
1263
1264 while (size) {
1265 if (size > limit) {
1266 ret = get_registers(tp, index, type, limit, data);
1267 if (ret < 0)
1268 break;
1269
1270 index += limit;
1271 data += limit;
1272 size -= limit;
1273 } else {
1274 ret = get_registers(tp, index, type, size, data);
1275 if (ret < 0)
1276 break;
1277
1278 index += size;
1279 data += size;
1280 size = 0;
1281 break;
1282 }
1283 }
1284
1285 if (ret == -ENODEV)
1286 rtl_set_unplug(tp);
1287
1288 return ret;
1289}
1290
1291static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
1292 u16 size, void *data, u16 type)
1293{
1294 int ret;
1295 u16 byteen_start, byteen_end, byen;
1296 u16 limit = 512;
1297
1298 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1299 return -ENODEV;
1300
1301 /* both size and indix must be 4 bytes align */
1302 if ((size & 3) || !size || (index & 3) || !data)
1303 return -EPERM;
1304
1305 if ((u32)index + (u32)size > 0xffff)
1306 return -EPERM;
1307
1308 byteen_start = byteen & BYTE_EN_START_MASK;
1309 byteen_end = byteen & BYTE_EN_END_MASK;
1310
1311 byen = byteen_start | (byteen_start << 4);
1312 ret = set_registers(tp, index, type | byen, 4, data);
1313 if (ret < 0)
1314 goto error1;
1315
1316 index += 4;
1317 data += 4;
1318 size -= 4;
1319
1320 if (size) {
1321 size -= 4;
1322
1323 while (size) {
1324 if (size > limit) {
1325 ret = set_registers(tp, index,
1326 type | BYTE_EN_DWORD,
1327 limit, data);
1328 if (ret < 0)
1329 goto error1;
1330
1331 index += limit;
1332 data += limit;
1333 size -= limit;
1334 } else {
1335 ret = set_registers(tp, index,
1336 type | BYTE_EN_DWORD,
1337 size, data);
1338 if (ret < 0)
1339 goto error1;
1340
1341 index += size;
1342 data += size;
1343 size = 0;
1344 break;
1345 }
1346 }
1347
1348 byen = byteen_end | (byteen_end >> 4);
1349 ret = set_registers(tp, index, type | byen, 4, data);
1350 if (ret < 0)
1351 goto error1;
1352 }
1353
1354error1:
1355 if (ret == -ENODEV)
1356 rtl_set_unplug(tp);
1357
1358 return ret;
1359}
1360
1361static inline
1362int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
1363{
1364 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
1365}
1366
1367static inline
1368int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1369{
1370 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
1371}
1372
1373static inline
1374int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
1375{
1376 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
1377}
1378
1379static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
1380{
1381 __le32 data;
1382
1383 generic_ocp_read(tp, index, sizeof(data), &data, type);
1384
1385 return __le32_to_cpu(data);
1386}
1387
1388static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
1389{
1390 __le32 tmp = __cpu_to_le32(data);
1391
1392 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
1393}
1394
1395static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
1396{
1397 u32 data;
1398 __le32 tmp;
1399 u16 byen = BYTE_EN_WORD;
1400 u8 shift = index & 2;
1401
1402 index &= ~3;
1403 byen <<= shift;
1404
1405 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
1406
1407 data = __le32_to_cpu(tmp);
1408 data >>= (shift * 8);
1409 data &= 0xffff;
1410
1411 return (u16)data;
1412}
1413
1414static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
1415{
1416 u32 mask = 0xffff;
1417 __le32 tmp;
1418 u16 byen = BYTE_EN_WORD;
1419 u8 shift = index & 2;
1420
1421 data &= mask;
1422
1423 if (index & 2) {
1424 byen <<= shift;
1425 mask <<= (shift * 8);
1426 data <<= (shift * 8);
1427 index &= ~3;
1428 }
1429
1430 tmp = __cpu_to_le32(data);
1431
1432 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1433}
1434
1435static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1436{
1437 u32 data;
1438 __le32 tmp;
1439 u8 shift = index & 3;
1440
1441 index &= ~3;
1442
1443 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1444
1445 data = __le32_to_cpu(tmp);
1446 data >>= (shift * 8);
1447 data &= 0xff;
1448
1449 return (u8)data;
1450}
1451
1452static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1453{
1454 u32 mask = 0xff;
1455 __le32 tmp;
1456 u16 byen = BYTE_EN_BYTE;
1457 u8 shift = index & 3;
1458
1459 data &= mask;
1460
1461 if (index & 3) {
1462 byen <<= shift;
1463 mask <<= (shift * 8);
1464 data <<= (shift * 8);
1465 index &= ~3;
1466 }
1467
1468 tmp = __cpu_to_le32(data);
1469
1470 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1471}
1472
1473static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1474{
1475 u16 ocp_base, ocp_index;
1476
1477 ocp_base = addr & 0xf000;
1478 if (ocp_base != tp->ocp_base) {
1479 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1480 tp->ocp_base = ocp_base;
1481 }
1482
1483 ocp_index = (addr & 0x0fff) | 0xb000;
1484 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1485}
1486
1487static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1488{
1489 u16 ocp_base, ocp_index;
1490
1491 ocp_base = addr & 0xf000;
1492 if (ocp_base != tp->ocp_base) {
1493 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1494 tp->ocp_base = ocp_base;
1495 }
1496
1497 ocp_index = (addr & 0x0fff) | 0xb000;
1498 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1499}
1500
1501static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1502{
1503 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1504}
1505
1506static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1507{
1508 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1509}
1510
1511static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1512{
1513 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1514 ocp_reg_write(tp, OCP_SRAM_DATA, data);
1515}
1516
1517static u16 sram_read(struct r8152 *tp, u16 addr)
1518{
1519 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1520 return ocp_reg_read(tp, OCP_SRAM_DATA);
1521}
1522
1523static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1524{
1525 struct r8152 *tp = netdev_priv(netdev);
1526 int ret;
1527
1528 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1529 return -ENODEV;
1530
1531 if (phy_id != R8152_PHY_ID)
1532 return -EINVAL;
1533
1534 ret = r8152_mdio_read(tp, reg);
1535
1536 return ret;
1537}
1538
1539static
1540void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1541{
1542 struct r8152 *tp = netdev_priv(netdev);
1543
1544 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1545 return;
1546
1547 if (phy_id != R8152_PHY_ID)
1548 return;
1549
1550 r8152_mdio_write(tp, reg, val);
1551}
1552
1553static int
1554r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1555
1556static int
1557rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1558 u32 advertising);
1559
1560static int __rtl8152_set_mac_address(struct net_device *netdev, void *p,
1561 bool in_resume)
1562{
1563 struct r8152 *tp = netdev_priv(netdev);
1564 struct sockaddr *addr = p;
1565 int ret = -EADDRNOTAVAIL;
1566
1567 if (!is_valid_ether_addr(addr->sa_data))
1568 goto out1;
1569
1570 if (!in_resume) {
1571 ret = usb_autopm_get_interface(tp->intf);
1572 if (ret < 0)
1573 goto out1;
1574 }
1575
1576 mutex_lock(&tp->control);
1577
1578 eth_hw_addr_set(netdev, addr->sa_data);
1579
1580 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1581 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1582 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1583
1584 mutex_unlock(&tp->control);
1585
1586 if (!in_resume)
1587 usb_autopm_put_interface(tp->intf);
1588out1:
1589 return ret;
1590}
1591
1592static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1593{
1594 return __rtl8152_set_mac_address(netdev, p, false);
1595}
1596
1597/* Devices containing proper chips can support a persistent
1598 * host system provided MAC address.
1599 * Examples of this are Dell TB15 and Dell WD15 docks
1600 */
1601static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1602{
1603 acpi_status status;
1604 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1605 union acpi_object *obj;
1606 int ret = -EINVAL;
1607 u32 ocp_data;
1608 unsigned char buf[6];
1609 char *mac_obj_name;
1610 acpi_object_type mac_obj_type;
1611 int mac_strlen;
1612
1613 if (tp->lenovo_macpassthru) {
1614 mac_obj_name = "\\MACA";
1615 mac_obj_type = ACPI_TYPE_STRING;
1616 mac_strlen = 0x16;
1617 } else {
1618 /* test for -AD variant of RTL8153 */
1619 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1620 if ((ocp_data & AD_MASK) == 0x1000) {
1621 /* test for MAC address pass-through bit */
1622 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1623 if ((ocp_data & PASS_THRU_MASK) != 1) {
1624 netif_dbg(tp, probe, tp->netdev,
1625 "No efuse for RTL8153-AD MAC pass through\n");
1626 return -ENODEV;
1627 }
1628 } else {
1629 /* test for RTL8153-BND and RTL8153-BD */
1630 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
1631 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) {
1632 netif_dbg(tp, probe, tp->netdev,
1633 "Invalid variant for MAC pass through\n");
1634 return -ENODEV;
1635 }
1636 }
1637
1638 mac_obj_name = "\\_SB.AMAC";
1639 mac_obj_type = ACPI_TYPE_BUFFER;
1640 mac_strlen = 0x17;
1641 }
1642
1643 /* returns _AUXMAC_#AABBCCDDEEFF# */
1644 status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer);
1645 obj = (union acpi_object *)buffer.pointer;
1646 if (!ACPI_SUCCESS(status))
1647 return -ENODEV;
1648 if (obj->type != mac_obj_type || obj->string.length != mac_strlen) {
1649 netif_warn(tp, probe, tp->netdev,
1650 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1651 obj->type, obj->string.length);
1652 goto amacout;
1653 }
1654
1655 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1656 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1657 netif_warn(tp, probe, tp->netdev,
1658 "Invalid header when reading pass-thru MAC addr\n");
1659 goto amacout;
1660 }
1661 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1662 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1663 netif_warn(tp, probe, tp->netdev,
1664 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1665 ret, buf);
1666 ret = -EINVAL;
1667 goto amacout;
1668 }
1669 memcpy(sa->sa_data, buf, 6);
1670 netif_info(tp, probe, tp->netdev,
1671 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1672
1673amacout:
1674 kfree(obj);
1675 return ret;
1676}
1677
1678static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa)
1679{
1680 struct net_device *dev = tp->netdev;
1681 int ret;
1682
1683 sa->sa_family = dev->type;
1684
1685 ret = eth_platform_get_mac_address(&tp->udev->dev, sa->sa_data);
1686 if (ret < 0) {
1687 if (tp->version == RTL_VER_01) {
1688 ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data);
1689 } else {
1690 /* if device doesn't support MAC pass through this will
1691 * be expected to be non-zero
1692 */
1693 ret = vendor_mac_passthru_addr_read(tp, sa);
1694 if (ret < 0)
1695 ret = pla_ocp_read(tp, PLA_BACKUP, 8,
1696 sa->sa_data);
1697 }
1698 }
1699
1700 if (ret < 0) {
1701 netif_err(tp, probe, dev, "Get ether addr fail\n");
1702 } else if (!is_valid_ether_addr(sa->sa_data)) {
1703 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1704 sa->sa_data);
1705 eth_hw_addr_random(dev);
1706 ether_addr_copy(sa->sa_data, dev->dev_addr);
1707 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1708 sa->sa_data);
1709 return 0;
1710 }
1711
1712 return ret;
1713}
1714
1715static int set_ethernet_addr(struct r8152 *tp, bool in_resume)
1716{
1717 struct net_device *dev = tp->netdev;
1718 struct sockaddr sa;
1719 int ret;
1720
1721 ret = determine_ethernet_addr(tp, &sa);
1722 if (ret < 0)
1723 return ret;
1724
1725 if (tp->version == RTL_VER_01)
1726 eth_hw_addr_set(dev, sa.sa_data);
1727 else
1728 ret = __rtl8152_set_mac_address(dev, &sa, in_resume);
1729
1730 return ret;
1731}
1732
1733static void read_bulk_callback(struct urb *urb)
1734{
1735 struct net_device *netdev;
1736 int status = urb->status;
1737 struct rx_agg *agg;
1738 struct r8152 *tp;
1739 unsigned long flags;
1740
1741 agg = urb->context;
1742 if (!agg)
1743 return;
1744
1745 tp = agg->context;
1746 if (!tp)
1747 return;
1748
1749 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1750 return;
1751
1752 if (!test_bit(WORK_ENABLE, &tp->flags))
1753 return;
1754
1755 netdev = tp->netdev;
1756
1757 /* When link down, the driver would cancel all bulks. */
1758 /* This avoid the re-submitting bulk */
1759 if (!netif_carrier_ok(netdev))
1760 return;
1761
1762 usb_mark_last_busy(tp->udev);
1763
1764 switch (status) {
1765 case 0:
1766 if (urb->actual_length < ETH_ZLEN)
1767 break;
1768
1769 spin_lock_irqsave(&tp->rx_lock, flags);
1770 list_add_tail(&agg->list, &tp->rx_done);
1771 spin_unlock_irqrestore(&tp->rx_lock, flags);
1772 napi_schedule(&tp->napi);
1773 return;
1774 case -ESHUTDOWN:
1775 rtl_set_unplug(tp);
1776 netif_device_detach(tp->netdev);
1777 return;
1778 case -EPROTO:
1779 urb->actual_length = 0;
1780 spin_lock_irqsave(&tp->rx_lock, flags);
1781 list_add_tail(&agg->list, &tp->rx_done);
1782 spin_unlock_irqrestore(&tp->rx_lock, flags);
1783 set_bit(RX_EPROTO, &tp->flags);
1784 schedule_delayed_work(&tp->schedule, 1);
1785 return;
1786 case -ENOENT:
1787 return; /* the urb is in unlink state */
1788 case -ETIME:
1789 if (net_ratelimit())
1790 netdev_warn(netdev, "maybe reset is needed?\n");
1791 break;
1792 default:
1793 if (net_ratelimit())
1794 netdev_warn(netdev, "Rx status %d\n", status);
1795 break;
1796 }
1797
1798 r8152_submit_rx(tp, agg, GFP_ATOMIC);
1799}
1800
1801static void write_bulk_callback(struct urb *urb)
1802{
1803 struct net_device_stats *stats;
1804 struct net_device *netdev;
1805 struct tx_agg *agg;
1806 struct r8152 *tp;
1807 unsigned long flags;
1808 int status = urb->status;
1809
1810 agg = urb->context;
1811 if (!agg)
1812 return;
1813
1814 tp = agg->context;
1815 if (!tp)
1816 return;
1817
1818 netdev = tp->netdev;
1819 stats = &netdev->stats;
1820 if (status) {
1821 if (net_ratelimit())
1822 netdev_warn(netdev, "Tx status %d\n", status);
1823 stats->tx_errors += agg->skb_num;
1824 } else {
1825 stats->tx_packets += agg->skb_num;
1826 stats->tx_bytes += agg->skb_len;
1827 }
1828
1829 spin_lock_irqsave(&tp->tx_lock, flags);
1830 list_add_tail(&agg->list, &tp->tx_free);
1831 spin_unlock_irqrestore(&tp->tx_lock, flags);
1832
1833 usb_autopm_put_interface_async(tp->intf);
1834
1835 if (!netif_carrier_ok(netdev))
1836 return;
1837
1838 if (!test_bit(WORK_ENABLE, &tp->flags))
1839 return;
1840
1841 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1842 return;
1843
1844 if (!skb_queue_empty(&tp->tx_queue))
1845 tasklet_schedule(&tp->tx_tl);
1846}
1847
1848static void intr_callback(struct urb *urb)
1849{
1850 struct r8152 *tp;
1851 __le16 *d;
1852 int status = urb->status;
1853 int res;
1854
1855 tp = urb->context;
1856 if (!tp)
1857 return;
1858
1859 if (!test_bit(WORK_ENABLE, &tp->flags))
1860 return;
1861
1862 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1863 return;
1864
1865 switch (status) {
1866 case 0: /* success */
1867 break;
1868 case -ECONNRESET: /* unlink */
1869 case -ESHUTDOWN:
1870 netif_device_detach(tp->netdev);
1871 fallthrough;
1872 case -ENOENT:
1873 case -EPROTO:
1874 netif_info(tp, intr, tp->netdev,
1875 "Stop submitting intr, status %d\n", status);
1876 return;
1877 case -EOVERFLOW:
1878 if (net_ratelimit())
1879 netif_info(tp, intr, tp->netdev,
1880 "intr status -EOVERFLOW\n");
1881 goto resubmit;
1882 /* -EPIPE: should clear the halt */
1883 default:
1884 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1885 goto resubmit;
1886 }
1887
1888 d = urb->transfer_buffer;
1889 if (INTR_LINK & __le16_to_cpu(d[0])) {
1890 if (!netif_carrier_ok(tp->netdev)) {
1891 set_bit(RTL8152_LINK_CHG, &tp->flags);
1892 schedule_delayed_work(&tp->schedule, 0);
1893 }
1894 } else {
1895 if (netif_carrier_ok(tp->netdev)) {
1896 netif_stop_queue(tp->netdev);
1897 set_bit(RTL8152_LINK_CHG, &tp->flags);
1898 schedule_delayed_work(&tp->schedule, 0);
1899 }
1900 }
1901
1902resubmit:
1903 res = usb_submit_urb(urb, GFP_ATOMIC);
1904 if (res == -ENODEV) {
1905 rtl_set_unplug(tp);
1906 netif_device_detach(tp->netdev);
1907 } else if (res) {
1908 netif_err(tp, intr, tp->netdev,
1909 "can't resubmit intr, status %d\n", res);
1910 }
1911}
1912
1913static inline void *rx_agg_align(void *data)
1914{
1915 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1916}
1917
1918static inline void *tx_agg_align(void *data)
1919{
1920 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1921}
1922
1923static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg)
1924{
1925 list_del(&agg->info_list);
1926
1927 usb_free_urb(agg->urb);
1928 put_page(agg->page);
1929 kfree(agg);
1930
1931 atomic_dec(&tp->rx_count);
1932}
1933
1934static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags)
1935{
1936 struct net_device *netdev = tp->netdev;
1937 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1938 unsigned int order = get_order(tp->rx_buf_sz);
1939 struct rx_agg *rx_agg;
1940 unsigned long flags;
1941
1942 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node);
1943 if (!rx_agg)
1944 return NULL;
1945
1946 rx_agg->page = alloc_pages(mflags | __GFP_COMP, order);
1947 if (!rx_agg->page)
1948 goto free_rx;
1949
1950 rx_agg->buffer = page_address(rx_agg->page);
1951
1952 rx_agg->urb = usb_alloc_urb(0, mflags);
1953 if (!rx_agg->urb)
1954 goto free_buf;
1955
1956 rx_agg->context = tp;
1957
1958 INIT_LIST_HEAD(&rx_agg->list);
1959 INIT_LIST_HEAD(&rx_agg->info_list);
1960 spin_lock_irqsave(&tp->rx_lock, flags);
1961 list_add_tail(&rx_agg->info_list, &tp->rx_info);
1962 spin_unlock_irqrestore(&tp->rx_lock, flags);
1963
1964 atomic_inc(&tp->rx_count);
1965
1966 return rx_agg;
1967
1968free_buf:
1969 __free_pages(rx_agg->page, order);
1970free_rx:
1971 kfree(rx_agg);
1972 return NULL;
1973}
1974
1975static void free_all_mem(struct r8152 *tp)
1976{
1977 struct rx_agg *agg, *agg_next;
1978 unsigned long flags;
1979 int i;
1980
1981 spin_lock_irqsave(&tp->rx_lock, flags);
1982
1983 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list)
1984 free_rx_agg(tp, agg);
1985
1986 spin_unlock_irqrestore(&tp->rx_lock, flags);
1987
1988 WARN_ON(atomic_read(&tp->rx_count));
1989
1990 for (i = 0; i < RTL8152_MAX_TX; i++) {
1991 usb_free_urb(tp->tx_info[i].urb);
1992 tp->tx_info[i].urb = NULL;
1993
1994 kfree(tp->tx_info[i].buffer);
1995 tp->tx_info[i].buffer = NULL;
1996 tp->tx_info[i].head = NULL;
1997 }
1998
1999 usb_free_urb(tp->intr_urb);
2000 tp->intr_urb = NULL;
2001
2002 kfree(tp->intr_buff);
2003 tp->intr_buff = NULL;
2004}
2005
2006static int alloc_all_mem(struct r8152 *tp)
2007{
2008 struct net_device *netdev = tp->netdev;
2009 struct usb_interface *intf = tp->intf;
2010 struct usb_host_interface *alt = intf->cur_altsetting;
2011 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
2012 int node, i;
2013
2014 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
2015
2016 spin_lock_init(&tp->rx_lock);
2017 spin_lock_init(&tp->tx_lock);
2018 INIT_LIST_HEAD(&tp->rx_info);
2019 INIT_LIST_HEAD(&tp->tx_free);
2020 INIT_LIST_HEAD(&tp->rx_done);
2021 skb_queue_head_init(&tp->tx_queue);
2022 skb_queue_head_init(&tp->rx_queue);
2023 atomic_set(&tp->rx_count, 0);
2024
2025 for (i = 0; i < RTL8152_MAX_RX; i++) {
2026 if (!alloc_rx_agg(tp, GFP_KERNEL))
2027 goto err1;
2028 }
2029
2030 for (i = 0; i < RTL8152_MAX_TX; i++) {
2031 struct urb *urb;
2032 u8 *buf;
2033
2034 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
2035 if (!buf)
2036 goto err1;
2037
2038 if (buf != tx_agg_align(buf)) {
2039 kfree(buf);
2040 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
2041 node);
2042 if (!buf)
2043 goto err1;
2044 }
2045
2046 urb = usb_alloc_urb(0, GFP_KERNEL);
2047 if (!urb) {
2048 kfree(buf);
2049 goto err1;
2050 }
2051
2052 INIT_LIST_HEAD(&tp->tx_info[i].list);
2053 tp->tx_info[i].context = tp;
2054 tp->tx_info[i].urb = urb;
2055 tp->tx_info[i].buffer = buf;
2056 tp->tx_info[i].head = tx_agg_align(buf);
2057
2058 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
2059 }
2060
2061 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
2062 if (!tp->intr_urb)
2063 goto err1;
2064
2065 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
2066 if (!tp->intr_buff)
2067 goto err1;
2068
2069 tp->intr_interval = (int)ep_intr->desc.bInterval;
2070 usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr,
2071 tp->intr_buff, INTBUFSIZE, intr_callback,
2072 tp, tp->intr_interval);
2073
2074 return 0;
2075
2076err1:
2077 free_all_mem(tp);
2078 return -ENOMEM;
2079}
2080
2081static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
2082{
2083 struct tx_agg *agg = NULL;
2084 unsigned long flags;
2085
2086 if (list_empty(&tp->tx_free))
2087 return NULL;
2088
2089 spin_lock_irqsave(&tp->tx_lock, flags);
2090 if (!list_empty(&tp->tx_free)) {
2091 struct list_head *cursor;
2092
2093 cursor = tp->tx_free.next;
2094 list_del_init(cursor);
2095 agg = list_entry(cursor, struct tx_agg, list);
2096 }
2097 spin_unlock_irqrestore(&tp->tx_lock, flags);
2098
2099 return agg;
2100}
2101
2102/* r8152_csum_workaround()
2103 * The hw limits the value of the transport offset. When the offset is out of
2104 * range, calculate the checksum by sw.
2105 */
2106static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
2107 struct sk_buff_head *list)
2108{
2109 if (skb_shinfo(skb)->gso_size) {
2110 netdev_features_t features = tp->netdev->features;
2111 struct sk_buff *segs, *seg, *next;
2112 struct sk_buff_head seg_list;
2113
2114 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
2115 segs = skb_gso_segment(skb, features);
2116 if (IS_ERR(segs) || !segs)
2117 goto drop;
2118
2119 __skb_queue_head_init(&seg_list);
2120
2121 skb_list_walk_safe(segs, seg, next) {
2122 skb_mark_not_on_list(seg);
2123 __skb_queue_tail(&seg_list, seg);
2124 }
2125
2126 skb_queue_splice(&seg_list, list);
2127 dev_kfree_skb(skb);
2128 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2129 if (skb_checksum_help(skb) < 0)
2130 goto drop;
2131
2132 __skb_queue_head(list, skb);
2133 } else {
2134 struct net_device_stats *stats;
2135
2136drop:
2137 stats = &tp->netdev->stats;
2138 stats->tx_dropped++;
2139 dev_kfree_skb(skb);
2140 }
2141}
2142
2143static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
2144{
2145 if (skb_vlan_tag_present(skb)) {
2146 u32 opts2;
2147
2148 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
2149 desc->opts2 |= cpu_to_le32(opts2);
2150 }
2151}
2152
2153static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
2154{
2155 u32 opts2 = le32_to_cpu(desc->opts2);
2156
2157 if (opts2 & RX_VLAN_TAG)
2158 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
2159 swab16(opts2 & 0xffff));
2160}
2161
2162static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
2163 struct sk_buff *skb, u32 len)
2164{
2165 u32 mss = skb_shinfo(skb)->gso_size;
2166 u32 opts1, opts2 = 0;
2167 int ret = TX_CSUM_SUCCESS;
2168
2169 WARN_ON_ONCE(len > TX_LEN_MAX);
2170
2171 opts1 = len | TX_FS | TX_LS;
2172
2173 if (mss) {
2174 u32 transport_offset = (u32)skb_transport_offset(skb);
2175
2176 if (transport_offset > GTTCPHO_MAX) {
2177 netif_warn(tp, tx_err, tp->netdev,
2178 "Invalid transport offset 0x%x for TSO\n",
2179 transport_offset);
2180 ret = TX_CSUM_TSO;
2181 goto unavailable;
2182 }
2183
2184 switch (vlan_get_protocol(skb)) {
2185 case htons(ETH_P_IP):
2186 opts1 |= GTSENDV4;
2187 break;
2188
2189 case htons(ETH_P_IPV6):
2190 if (skb_cow_head(skb, 0)) {
2191 ret = TX_CSUM_TSO;
2192 goto unavailable;
2193 }
2194 tcp_v6_gso_csum_prep(skb);
2195 opts1 |= GTSENDV6;
2196 break;
2197
2198 default:
2199 WARN_ON_ONCE(1);
2200 break;
2201 }
2202
2203 opts1 |= transport_offset << GTTCPHO_SHIFT;
2204 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
2205 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
2206 u32 transport_offset = (u32)skb_transport_offset(skb);
2207 u8 ip_protocol;
2208
2209 if (transport_offset > TCPHO_MAX) {
2210 netif_warn(tp, tx_err, tp->netdev,
2211 "Invalid transport offset 0x%x\n",
2212 transport_offset);
2213 ret = TX_CSUM_NONE;
2214 goto unavailable;
2215 }
2216
2217 switch (vlan_get_protocol(skb)) {
2218 case htons(ETH_P_IP):
2219 opts2 |= IPV4_CS;
2220 ip_protocol = ip_hdr(skb)->protocol;
2221 break;
2222
2223 case htons(ETH_P_IPV6):
2224 opts2 |= IPV6_CS;
2225 ip_protocol = ipv6_hdr(skb)->nexthdr;
2226 break;
2227
2228 default:
2229 ip_protocol = IPPROTO_RAW;
2230 break;
2231 }
2232
2233 if (ip_protocol == IPPROTO_TCP)
2234 opts2 |= TCP_CS;
2235 else if (ip_protocol == IPPROTO_UDP)
2236 opts2 |= UDP_CS;
2237 else
2238 WARN_ON_ONCE(1);
2239
2240 opts2 |= transport_offset << TCPHO_SHIFT;
2241 }
2242
2243 desc->opts2 = cpu_to_le32(opts2);
2244 desc->opts1 = cpu_to_le32(opts1);
2245
2246unavailable:
2247 return ret;
2248}
2249
2250static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
2251{
2252 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2253 int remain, ret;
2254 u8 *tx_data;
2255
2256 __skb_queue_head_init(&skb_head);
2257 spin_lock(&tx_queue->lock);
2258 skb_queue_splice_init(tx_queue, &skb_head);
2259 spin_unlock(&tx_queue->lock);
2260
2261 tx_data = agg->head;
2262 agg->skb_num = 0;
2263 agg->skb_len = 0;
2264 remain = agg_buf_sz;
2265
2266 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
2267 struct tx_desc *tx_desc;
2268 struct sk_buff *skb;
2269 unsigned int len;
2270
2271 skb = __skb_dequeue(&skb_head);
2272 if (!skb)
2273 break;
2274
2275 len = skb->len + sizeof(*tx_desc);
2276
2277 if (len > remain) {
2278 __skb_queue_head(&skb_head, skb);
2279 break;
2280 }
2281
2282 tx_data = tx_agg_align(tx_data);
2283 tx_desc = (struct tx_desc *)tx_data;
2284
2285 if (r8152_tx_csum(tp, tx_desc, skb, skb->len)) {
2286 r8152_csum_workaround(tp, skb, &skb_head);
2287 continue;
2288 }
2289
2290 rtl_tx_vlan_tag(tx_desc, skb);
2291
2292 tx_data += sizeof(*tx_desc);
2293
2294 len = skb->len;
2295 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
2296 struct net_device_stats *stats = &tp->netdev->stats;
2297
2298 stats->tx_dropped++;
2299 dev_kfree_skb_any(skb);
2300 tx_data -= sizeof(*tx_desc);
2301 continue;
2302 }
2303
2304 tx_data += len;
2305 agg->skb_len += len;
2306 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
2307
2308 dev_kfree_skb_any(skb);
2309
2310 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
2311
2312 if (tp->dell_tb_rx_agg_bug)
2313 break;
2314 }
2315
2316 if (!skb_queue_empty(&skb_head)) {
2317 spin_lock(&tx_queue->lock);
2318 skb_queue_splice(&skb_head, tx_queue);
2319 spin_unlock(&tx_queue->lock);
2320 }
2321
2322 netif_tx_lock(tp->netdev);
2323
2324 if (netif_queue_stopped(tp->netdev) &&
2325 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
2326 netif_wake_queue(tp->netdev);
2327
2328 netif_tx_unlock(tp->netdev);
2329
2330 ret = usb_autopm_get_interface_async(tp->intf);
2331 if (ret < 0)
2332 goto out_tx_fill;
2333
2334 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out,
2335 agg->head, (int)(tx_data - (u8 *)agg->head),
2336 (usb_complete_t)write_bulk_callback, agg);
2337
2338 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
2339 if (ret < 0)
2340 usb_autopm_put_interface_async(tp->intf);
2341
2342out_tx_fill:
2343 return ret;
2344}
2345
2346static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
2347{
2348 u8 checksum = CHECKSUM_NONE;
2349 u32 opts2, opts3;
2350
2351 if (!(tp->netdev->features & NETIF_F_RXCSUM))
2352 goto return_result;
2353
2354 opts2 = le32_to_cpu(rx_desc->opts2);
2355 opts3 = le32_to_cpu(rx_desc->opts3);
2356
2357 if (opts2 & RD_IPV4_CS) {
2358 if (opts3 & IPF)
2359 checksum = CHECKSUM_NONE;
2360 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2361 checksum = CHECKSUM_UNNECESSARY;
2362 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2363 checksum = CHECKSUM_UNNECESSARY;
2364 } else if (opts2 & RD_IPV6_CS) {
2365 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
2366 checksum = CHECKSUM_UNNECESSARY;
2367 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
2368 checksum = CHECKSUM_UNNECESSARY;
2369 }
2370
2371return_result:
2372 return checksum;
2373}
2374
2375static inline bool rx_count_exceed(struct r8152 *tp)
2376{
2377 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX;
2378}
2379
2380static inline int agg_offset(struct rx_agg *agg, void *addr)
2381{
2382 return (int)(addr - agg->buffer);
2383}
2384
2385static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags)
2386{
2387 struct rx_agg *agg, *agg_next, *agg_free = NULL;
2388 unsigned long flags;
2389
2390 spin_lock_irqsave(&tp->rx_lock, flags);
2391
2392 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) {
2393 if (page_count(agg->page) == 1) {
2394 if (!agg_free) {
2395 list_del_init(&agg->list);
2396 agg_free = agg;
2397 continue;
2398 }
2399 if (rx_count_exceed(tp)) {
2400 list_del_init(&agg->list);
2401 free_rx_agg(tp, agg);
2402 }
2403 break;
2404 }
2405 }
2406
2407 spin_unlock_irqrestore(&tp->rx_lock, flags);
2408
2409 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending)
2410 agg_free = alloc_rx_agg(tp, mflags);
2411
2412 return agg_free;
2413}
2414
2415static int rx_bottom(struct r8152 *tp, int budget)
2416{
2417 unsigned long flags;
2418 struct list_head *cursor, *next, rx_queue;
2419 int ret = 0, work_done = 0;
2420 struct napi_struct *napi = &tp->napi;
2421
2422 if (!skb_queue_empty(&tp->rx_queue)) {
2423 while (work_done < budget) {
2424 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
2425 struct net_device *netdev = tp->netdev;
2426 struct net_device_stats *stats = &netdev->stats;
2427 unsigned int pkt_len;
2428
2429 if (!skb)
2430 break;
2431
2432 pkt_len = skb->len;
2433 napi_gro_receive(napi, skb);
2434 work_done++;
2435 stats->rx_packets++;
2436 stats->rx_bytes += pkt_len;
2437 }
2438 }
2439
2440 if (list_empty(&tp->rx_done))
2441 goto out1;
2442
2443 clear_bit(RX_EPROTO, &tp->flags);
2444 INIT_LIST_HEAD(&rx_queue);
2445 spin_lock_irqsave(&tp->rx_lock, flags);
2446 list_splice_init(&tp->rx_done, &rx_queue);
2447 spin_unlock_irqrestore(&tp->rx_lock, flags);
2448
2449 list_for_each_safe(cursor, next, &rx_queue) {
2450 struct rx_desc *rx_desc;
2451 struct rx_agg *agg, *agg_free;
2452 int len_used = 0;
2453 struct urb *urb;
2454 u8 *rx_data;
2455
2456 list_del_init(cursor);
2457
2458 agg = list_entry(cursor, struct rx_agg, list);
2459 urb = agg->urb;
2460 if (urb->status != 0 || urb->actual_length < ETH_ZLEN)
2461 goto submit;
2462
2463 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC);
2464
2465 rx_desc = agg->buffer;
2466 rx_data = agg->buffer;
2467 len_used += sizeof(struct rx_desc);
2468
2469 while (urb->actual_length > len_used) {
2470 struct net_device *netdev = tp->netdev;
2471 struct net_device_stats *stats = &netdev->stats;
2472 unsigned int pkt_len, rx_frag_head_sz;
2473 struct sk_buff *skb;
2474
2475 /* limit the skb numbers for rx_queue */
2476 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
2477 break;
2478
2479 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
2480 if (pkt_len < ETH_ZLEN)
2481 break;
2482
2483 len_used += pkt_len;
2484 if (urb->actual_length < len_used)
2485 break;
2486
2487 pkt_len -= ETH_FCS_LEN;
2488 rx_data += sizeof(struct rx_desc);
2489
2490 if (!agg_free || tp->rx_copybreak > pkt_len)
2491 rx_frag_head_sz = pkt_len;
2492 else
2493 rx_frag_head_sz = tp->rx_copybreak;
2494
2495 skb = napi_alloc_skb(napi, rx_frag_head_sz);
2496 if (!skb) {
2497 stats->rx_dropped++;
2498 goto find_next_rx;
2499 }
2500
2501 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
2502 memcpy(skb->data, rx_data, rx_frag_head_sz);
2503 skb_put(skb, rx_frag_head_sz);
2504 pkt_len -= rx_frag_head_sz;
2505 rx_data += rx_frag_head_sz;
2506 if (pkt_len) {
2507 skb_add_rx_frag(skb, 0, agg->page,
2508 agg_offset(agg, rx_data),
2509 pkt_len,
2510 SKB_DATA_ALIGN(pkt_len));
2511 get_page(agg->page);
2512 }
2513
2514 skb->protocol = eth_type_trans(skb, netdev);
2515 rtl_rx_vlan_tag(rx_desc, skb);
2516 if (work_done < budget) {
2517 work_done++;
2518 stats->rx_packets++;
2519 stats->rx_bytes += skb->len;
2520 napi_gro_receive(napi, skb);
2521 } else {
2522 __skb_queue_tail(&tp->rx_queue, skb);
2523 }
2524
2525find_next_rx:
2526 rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
2527 rx_desc = (struct rx_desc *)rx_data;
2528 len_used = agg_offset(agg, rx_data);
2529 len_used += sizeof(struct rx_desc);
2530 }
2531
2532 WARN_ON(!agg_free && page_count(agg->page) > 1);
2533
2534 if (agg_free) {
2535 spin_lock_irqsave(&tp->rx_lock, flags);
2536 if (page_count(agg->page) == 1) {
2537 list_add(&agg_free->list, &tp->rx_used);
2538 } else {
2539 list_add_tail(&agg->list, &tp->rx_used);
2540 agg = agg_free;
2541 urb = agg->urb;
2542 }
2543 spin_unlock_irqrestore(&tp->rx_lock, flags);
2544 }
2545
2546submit:
2547 if (!ret) {
2548 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
2549 } else {
2550 urb->actual_length = 0;
2551 list_add_tail(&agg->list, next);
2552 }
2553 }
2554
2555 if (!list_empty(&rx_queue)) {
2556 spin_lock_irqsave(&tp->rx_lock, flags);
2557 list_splice_tail(&rx_queue, &tp->rx_done);
2558 spin_unlock_irqrestore(&tp->rx_lock, flags);
2559 }
2560
2561out1:
2562 return work_done;
2563}
2564
2565static void tx_bottom(struct r8152 *tp)
2566{
2567 int res;
2568
2569 do {
2570 struct net_device *netdev = tp->netdev;
2571 struct tx_agg *agg;
2572
2573 if (skb_queue_empty(&tp->tx_queue))
2574 break;
2575
2576 agg = r8152_get_tx_agg(tp);
2577 if (!agg)
2578 break;
2579
2580 res = r8152_tx_agg_fill(tp, agg);
2581 if (!res)
2582 continue;
2583
2584 if (res == -ENODEV) {
2585 rtl_set_unplug(tp);
2586 netif_device_detach(netdev);
2587 } else {
2588 struct net_device_stats *stats = &netdev->stats;
2589 unsigned long flags;
2590
2591 netif_warn(tp, tx_err, netdev,
2592 "failed tx_urb %d\n", res);
2593 stats->tx_dropped += agg->skb_num;
2594
2595 spin_lock_irqsave(&tp->tx_lock, flags);
2596 list_add_tail(&agg->list, &tp->tx_free);
2597 spin_unlock_irqrestore(&tp->tx_lock, flags);
2598 }
2599 } while (res == 0);
2600}
2601
2602static void bottom_half(struct tasklet_struct *t)
2603{
2604 struct r8152 *tp = from_tasklet(tp, t, tx_tl);
2605
2606 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2607 return;
2608
2609 if (!test_bit(WORK_ENABLE, &tp->flags))
2610 return;
2611
2612 /* When link down, the driver would cancel all bulks. */
2613 /* This avoid the re-submitting bulk */
2614 if (!netif_carrier_ok(tp->netdev))
2615 return;
2616
2617 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2618
2619 tx_bottom(tp);
2620}
2621
2622static int r8152_poll(struct napi_struct *napi, int budget)
2623{
2624 struct r8152 *tp = container_of(napi, struct r8152, napi);
2625 int work_done;
2626
2627 work_done = rx_bottom(tp, budget);
2628
2629 if (work_done < budget) {
2630 if (!napi_complete_done(napi, work_done))
2631 goto out;
2632 if (!list_empty(&tp->rx_done))
2633 napi_schedule(napi);
2634 }
2635
2636out:
2637 return work_done;
2638}
2639
2640static
2641int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2642{
2643 int ret;
2644
2645 /* The rx would be stopped, so skip submitting */
2646 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2647 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2648 return 0;
2649
2650 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in,
2651 agg->buffer, tp->rx_buf_sz,
2652 (usb_complete_t)read_bulk_callback, agg);
2653
2654 ret = usb_submit_urb(agg->urb, mem_flags);
2655 if (ret == -ENODEV) {
2656 rtl_set_unplug(tp);
2657 netif_device_detach(tp->netdev);
2658 } else if (ret) {
2659 struct urb *urb = agg->urb;
2660 unsigned long flags;
2661
2662 urb->actual_length = 0;
2663 spin_lock_irqsave(&tp->rx_lock, flags);
2664 list_add_tail(&agg->list, &tp->rx_done);
2665 spin_unlock_irqrestore(&tp->rx_lock, flags);
2666
2667 netif_err(tp, rx_err, tp->netdev,
2668 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2669
2670 napi_schedule(&tp->napi);
2671 }
2672
2673 return ret;
2674}
2675
2676static void rtl_drop_queued_tx(struct r8152 *tp)
2677{
2678 struct net_device_stats *stats = &tp->netdev->stats;
2679 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2680 struct sk_buff *skb;
2681
2682 if (skb_queue_empty(tx_queue))
2683 return;
2684
2685 __skb_queue_head_init(&skb_head);
2686 spin_lock_bh(&tx_queue->lock);
2687 skb_queue_splice_init(tx_queue, &skb_head);
2688 spin_unlock_bh(&tx_queue->lock);
2689
2690 while ((skb = __skb_dequeue(&skb_head))) {
2691 dev_kfree_skb(skb);
2692 stats->tx_dropped++;
2693 }
2694}
2695
2696static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue)
2697{
2698 struct r8152 *tp = netdev_priv(netdev);
2699
2700 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2701
2702 usb_queue_reset_device(tp->intf);
2703}
2704
2705static void rtl8152_set_rx_mode(struct net_device *netdev)
2706{
2707 struct r8152 *tp = netdev_priv(netdev);
2708
2709 if (netif_carrier_ok(netdev)) {
2710 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2711 schedule_delayed_work(&tp->schedule, 0);
2712 }
2713}
2714
2715static void _rtl8152_set_rx_mode(struct net_device *netdev)
2716{
2717 struct r8152 *tp = netdev_priv(netdev);
2718 u32 mc_filter[2]; /* Multicast hash filter */
2719 __le32 tmp[2];
2720 u32 ocp_data;
2721
2722 netif_stop_queue(netdev);
2723 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2724 ocp_data &= ~RCR_ACPT_ALL;
2725 ocp_data |= RCR_AB | RCR_APM;
2726
2727 if (netdev->flags & IFF_PROMISC) {
2728 /* Unconditionally log net taps. */
2729 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2730 ocp_data |= RCR_AM | RCR_AAP;
2731 mc_filter[1] = 0xffffffff;
2732 mc_filter[0] = 0xffffffff;
2733 } else if ((netdev->flags & IFF_MULTICAST &&
2734 netdev_mc_count(netdev) > multicast_filter_limit) ||
2735 (netdev->flags & IFF_ALLMULTI)) {
2736 /* Too many to filter perfectly -- accept all multicasts. */
2737 ocp_data |= RCR_AM;
2738 mc_filter[1] = 0xffffffff;
2739 mc_filter[0] = 0xffffffff;
2740 } else {
2741 mc_filter[1] = 0;
2742 mc_filter[0] = 0;
2743
2744 if (netdev->flags & IFF_MULTICAST) {
2745 struct netdev_hw_addr *ha;
2746
2747 netdev_for_each_mc_addr(ha, netdev) {
2748 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2749
2750 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2751 ocp_data |= RCR_AM;
2752 }
2753 }
2754 }
2755
2756 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2757 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2758
2759 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2760 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2761 netif_wake_queue(netdev);
2762}
2763
2764static netdev_features_t
2765rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2766 netdev_features_t features)
2767{
2768 u32 mss = skb_shinfo(skb)->gso_size;
2769 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2770
2771 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) &&
2772 skb_transport_offset(skb) > max_offset)
2773 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2774 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2775 features &= ~NETIF_F_GSO_MASK;
2776
2777 return features;
2778}
2779
2780static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2781 struct net_device *netdev)
2782{
2783 struct r8152 *tp = netdev_priv(netdev);
2784
2785 skb_tx_timestamp(skb);
2786
2787 skb_queue_tail(&tp->tx_queue, skb);
2788
2789 if (!list_empty(&tp->tx_free)) {
2790 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2791 set_bit(SCHEDULE_TASKLET, &tp->flags);
2792 schedule_delayed_work(&tp->schedule, 0);
2793 } else {
2794 usb_mark_last_busy(tp->udev);
2795 tasklet_schedule(&tp->tx_tl);
2796 }
2797 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2798 netif_stop_queue(netdev);
2799 }
2800
2801 return NETDEV_TX_OK;
2802}
2803
2804static void r8152b_reset_packet_filter(struct r8152 *tp)
2805{
2806 u32 ocp_data;
2807
2808 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2809 ocp_data &= ~FMC_FCR_MCU_EN;
2810 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2811 ocp_data |= FMC_FCR_MCU_EN;
2812 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2813}
2814
2815static void rtl8152_nic_reset(struct r8152 *tp)
2816{
2817 u32 ocp_data;
2818 int i;
2819
2820 switch (tp->version) {
2821 case RTL_TEST_01:
2822 case RTL_VER_10:
2823 case RTL_VER_11:
2824 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2825 ocp_data &= ~CR_TE;
2826 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2827
2828 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2829 ocp_data &= ~BMU_RESET_EP_IN;
2830 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2831
2832 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2833 ocp_data |= CDC_ECM_EN;
2834 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2835
2836 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2837 ocp_data &= ~CR_RE;
2838 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2839
2840 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
2841 ocp_data |= BMU_RESET_EP_IN;
2842 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2843
2844 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2845 ocp_data &= ~CDC_ECM_EN;
2846 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2847 break;
2848
2849 default:
2850 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2851
2852 for (i = 0; i < 1000; i++) {
2853 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2854 break;
2855 usleep_range(100, 400);
2856 }
2857 break;
2858 }
2859}
2860
2861static void set_tx_qlen(struct r8152 *tp)
2862{
2863 tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
2864}
2865
2866static inline u16 rtl8152_get_speed(struct r8152 *tp)
2867{
2868 return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2869}
2870
2871static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
2872{
2873 u32 ocp_data;
2874
2875 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2876 if (enable)
2877 ocp_data |= EEEP_CR_EEEP_TX;
2878 else
2879 ocp_data &= ~EEEP_CR_EEEP_TX;
2880 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2881}
2882
2883static void rtl_set_eee_plus(struct r8152 *tp)
2884{
2885 if (rtl8152_get_speed(tp) & _10bps)
2886 rtl_eee_plus_en(tp, true);
2887 else
2888 rtl_eee_plus_en(tp, false);
2889}
2890
2891static void rxdy_gated_en(struct r8152 *tp, bool enable)
2892{
2893 u32 ocp_data;
2894
2895 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2896 if (enable)
2897 ocp_data |= RXDY_GATED_EN;
2898 else
2899 ocp_data &= ~RXDY_GATED_EN;
2900 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2901}
2902
2903static int rtl_start_rx(struct r8152 *tp)
2904{
2905 struct rx_agg *agg, *agg_next;
2906 struct list_head tmp_list;
2907 unsigned long flags;
2908 int ret = 0, i = 0;
2909
2910 INIT_LIST_HEAD(&tmp_list);
2911
2912 spin_lock_irqsave(&tp->rx_lock, flags);
2913
2914 INIT_LIST_HEAD(&tp->rx_done);
2915 INIT_LIST_HEAD(&tp->rx_used);
2916
2917 list_splice_init(&tp->rx_info, &tmp_list);
2918
2919 spin_unlock_irqrestore(&tp->rx_lock, flags);
2920
2921 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2922 INIT_LIST_HEAD(&agg->list);
2923
2924 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */
2925 if (++i > RTL8152_MAX_RX) {
2926 spin_lock_irqsave(&tp->rx_lock, flags);
2927 list_add_tail(&agg->list, &tp->rx_used);
2928 spin_unlock_irqrestore(&tp->rx_lock, flags);
2929 } else if (unlikely(ret < 0)) {
2930 spin_lock_irqsave(&tp->rx_lock, flags);
2931 list_add_tail(&agg->list, &tp->rx_done);
2932 spin_unlock_irqrestore(&tp->rx_lock, flags);
2933 } else {
2934 ret = r8152_submit_rx(tp, agg, GFP_KERNEL);
2935 }
2936 }
2937
2938 spin_lock_irqsave(&tp->rx_lock, flags);
2939 WARN_ON(!list_empty(&tp->rx_info));
2940 list_splice(&tmp_list, &tp->rx_info);
2941 spin_unlock_irqrestore(&tp->rx_lock, flags);
2942
2943 return ret;
2944}
2945
2946static int rtl_stop_rx(struct r8152 *tp)
2947{
2948 struct rx_agg *agg, *agg_next;
2949 struct list_head tmp_list;
2950 unsigned long flags;
2951
2952 INIT_LIST_HEAD(&tmp_list);
2953
2954 /* The usb_kill_urb() couldn't be used in atomic.
2955 * Therefore, move the list of rx_info to a tmp one.
2956 * Then, list_for_each_entry_safe could be used without
2957 * spin lock.
2958 */
2959
2960 spin_lock_irqsave(&tp->rx_lock, flags);
2961 list_splice_init(&tp->rx_info, &tmp_list);
2962 spin_unlock_irqrestore(&tp->rx_lock, flags);
2963
2964 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) {
2965 /* At least RTL8152_MAX_RX rx_agg have the page_count being
2966 * equal to 1, so the other ones could be freed safely.
2967 */
2968 if (page_count(agg->page) > 1)
2969 free_rx_agg(tp, agg);
2970 else
2971 usb_kill_urb(agg->urb);
2972 }
2973
2974 /* Move back the list of temp to the rx_info */
2975 spin_lock_irqsave(&tp->rx_lock, flags);
2976 WARN_ON(!list_empty(&tp->rx_info));
2977 list_splice(&tmp_list, &tp->rx_info);
2978 spin_unlock_irqrestore(&tp->rx_lock, flags);
2979
2980 while (!skb_queue_empty(&tp->rx_queue))
2981 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2982
2983 return 0;
2984}
2985
2986static void rtl_set_ifg(struct r8152 *tp, u16 speed)
2987{
2988 u32 ocp_data;
2989
2990 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
2991 ocp_data &= ~IFG_MASK;
2992 if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) {
2993 ocp_data |= IFG_144NS;
2994 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
2995
2996 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
2997 ocp_data &= ~TX10MIDLE_EN;
2998 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
2999 } else {
3000 ocp_data |= IFG_96NS;
3001 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data);
3002
3003 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
3004 ocp_data |= TX10MIDLE_EN;
3005 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
3006 }
3007}
3008
3009static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
3010{
3011 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
3012 OWN_UPDATE | OWN_CLEAR);
3013}
3014
3015static int rtl_enable(struct r8152 *tp)
3016{
3017 u32 ocp_data;
3018
3019 r8152b_reset_packet_filter(tp);
3020
3021 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
3022 ocp_data |= CR_RE | CR_TE;
3023 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
3024
3025 switch (tp->version) {
3026 case RTL_VER_08:
3027 case RTL_VER_09:
3028 case RTL_VER_14:
3029 r8153b_rx_agg_chg_indicate(tp);
3030 break;
3031 default:
3032 break;
3033 }
3034
3035 rxdy_gated_en(tp, false);
3036
3037 return 0;
3038}
3039
3040static int rtl8152_enable(struct r8152 *tp)
3041{
3042 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3043 return -ENODEV;
3044
3045 set_tx_qlen(tp);
3046 rtl_set_eee_plus(tp);
3047
3048 return rtl_enable(tp);
3049}
3050
3051static void r8153_set_rx_early_timeout(struct r8152 *tp)
3052{
3053 u32 ocp_data = tp->coalesce / 8;
3054
3055 switch (tp->version) {
3056 case RTL_VER_03:
3057 case RTL_VER_04:
3058 case RTL_VER_05:
3059 case RTL_VER_06:
3060 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3061 ocp_data);
3062 break;
3063
3064 case RTL_VER_08:
3065 case RTL_VER_09:
3066 case RTL_VER_14:
3067 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
3068 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
3069 */
3070 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3071 128 / 8);
3072 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3073 ocp_data);
3074 break;
3075
3076 case RTL_VER_10:
3077 case RTL_VER_11:
3078 case RTL_VER_12:
3079 case RTL_VER_13:
3080 case RTL_VER_15:
3081 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
3082 640 / 8);
3083 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
3084 ocp_data);
3085 r8153b_rx_agg_chg_indicate(tp);
3086 break;
3087
3088 default:
3089 break;
3090 }
3091}
3092
3093static void r8153_set_rx_early_size(struct r8152 *tp)
3094{
3095 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu);
3096
3097 switch (tp->version) {
3098 case RTL_VER_03:
3099 case RTL_VER_04:
3100 case RTL_VER_05:
3101 case RTL_VER_06:
3102 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3103 ocp_data / 4);
3104 break;
3105 case RTL_VER_08:
3106 case RTL_VER_09:
3107 case RTL_VER_14:
3108 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3109 ocp_data / 8);
3110 break;
3111 case RTL_TEST_01:
3112 case RTL_VER_10:
3113 case RTL_VER_11:
3114 case RTL_VER_12:
3115 case RTL_VER_13:
3116 case RTL_VER_15:
3117 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
3118 ocp_data / 8);
3119 r8153b_rx_agg_chg_indicate(tp);
3120 break;
3121 default:
3122 WARN_ON_ONCE(1);
3123 break;
3124 }
3125}
3126
3127static int rtl8153_enable(struct r8152 *tp)
3128{
3129 u32 ocp_data;
3130
3131 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3132 return -ENODEV;
3133
3134 set_tx_qlen(tp);
3135 rtl_set_eee_plus(tp);
3136 r8153_set_rx_early_timeout(tp);
3137 r8153_set_rx_early_size(tp);
3138
3139 rtl_set_ifg(tp, rtl8152_get_speed(tp));
3140
3141 switch (tp->version) {
3142 case RTL_VER_09:
3143 case RTL_VER_14:
3144 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
3145 ocp_data &= ~FC_PATCH_TASK;
3146 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3147 usleep_range(1000, 2000);
3148 ocp_data |= FC_PATCH_TASK;
3149 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
3150 break;
3151 default:
3152 break;
3153 }
3154
3155 return rtl_enable(tp);
3156}
3157
3158static void rtl_disable(struct r8152 *tp)
3159{
3160 u32 ocp_data;
3161 int i;
3162
3163 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3164 rtl_drop_queued_tx(tp);
3165 return;
3166 }
3167
3168 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3169 ocp_data &= ~RCR_ACPT_ALL;
3170 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3171
3172 rtl_drop_queued_tx(tp);
3173
3174 for (i = 0; i < RTL8152_MAX_TX; i++)
3175 usb_kill_urb(tp->tx_info[i].urb);
3176
3177 rxdy_gated_en(tp, true);
3178
3179 for (i = 0; i < 1000; i++) {
3180 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3181 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
3182 break;
3183 usleep_range(1000, 2000);
3184 }
3185
3186 for (i = 0; i < 1000; i++) {
3187 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
3188 break;
3189 usleep_range(1000, 2000);
3190 }
3191
3192 rtl_stop_rx(tp);
3193
3194 rtl8152_nic_reset(tp);
3195}
3196
3197static void r8152_power_cut_en(struct r8152 *tp, bool enable)
3198{
3199 u32 ocp_data;
3200
3201 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
3202 if (enable)
3203 ocp_data |= POWER_CUT;
3204 else
3205 ocp_data &= ~POWER_CUT;
3206 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
3207
3208 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
3209 ocp_data &= ~RESUME_INDICATE;
3210 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
3211}
3212
3213static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
3214{
3215 u32 ocp_data;
3216
3217 switch (tp->version) {
3218 case RTL_VER_01:
3219 case RTL_VER_02:
3220 case RTL_VER_03:
3221 case RTL_VER_04:
3222 case RTL_VER_05:
3223 case RTL_VER_06:
3224 case RTL_VER_07:
3225 case RTL_VER_08:
3226 case RTL_VER_09:
3227 case RTL_VER_14:
3228 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
3229 if (enable)
3230 ocp_data |= CPCR_RX_VLAN;
3231 else
3232 ocp_data &= ~CPCR_RX_VLAN;
3233 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
3234 break;
3235
3236 case RTL_TEST_01:
3237 case RTL_VER_10:
3238 case RTL_VER_11:
3239 case RTL_VER_12:
3240 case RTL_VER_13:
3241 case RTL_VER_15:
3242 default:
3243 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
3244 if (enable)
3245 ocp_data |= OUTER_VLAN | INNER_VLAN;
3246 else
3247 ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
3248 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
3249 break;
3250 }
3251}
3252
3253static int rtl8152_set_features(struct net_device *dev,
3254 netdev_features_t features)
3255{
3256 netdev_features_t changed = features ^ dev->features;
3257 struct r8152 *tp = netdev_priv(dev);
3258 int ret;
3259
3260 ret = usb_autopm_get_interface(tp->intf);
3261 if (ret < 0)
3262 goto out;
3263
3264 mutex_lock(&tp->control);
3265
3266 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
3267 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3268 rtl_rx_vlan_en(tp, true);
3269 else
3270 rtl_rx_vlan_en(tp, false);
3271 }
3272
3273 mutex_unlock(&tp->control);
3274
3275 usb_autopm_put_interface(tp->intf);
3276
3277out:
3278 return ret;
3279}
3280
3281#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
3282
3283static u32 __rtl_get_wol(struct r8152 *tp)
3284{
3285 u32 ocp_data;
3286 u32 wolopts = 0;
3287
3288 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3289 if (ocp_data & LINK_ON_WAKE_EN)
3290 wolopts |= WAKE_PHY;
3291
3292 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3293 if (ocp_data & UWF_EN)
3294 wolopts |= WAKE_UCAST;
3295 if (ocp_data & BWF_EN)
3296 wolopts |= WAKE_BCAST;
3297 if (ocp_data & MWF_EN)
3298 wolopts |= WAKE_MCAST;
3299
3300 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3301 if (ocp_data & MAGIC_EN)
3302 wolopts |= WAKE_MAGIC;
3303
3304 return wolopts;
3305}
3306
3307static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
3308{
3309 u32 ocp_data;
3310
3311 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3312
3313 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3314 ocp_data &= ~LINK_ON_WAKE_EN;
3315 if (wolopts & WAKE_PHY)
3316 ocp_data |= LINK_ON_WAKE_EN;
3317 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3318
3319 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
3320 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
3321 if (wolopts & WAKE_UCAST)
3322 ocp_data |= UWF_EN;
3323 if (wolopts & WAKE_BCAST)
3324 ocp_data |= BWF_EN;
3325 if (wolopts & WAKE_MCAST)
3326 ocp_data |= MWF_EN;
3327 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
3328
3329 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3330
3331 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
3332 ocp_data &= ~MAGIC_EN;
3333 if (wolopts & WAKE_MAGIC)
3334 ocp_data |= MAGIC_EN;
3335 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
3336
3337 if (wolopts & WAKE_ANY)
3338 device_set_wakeup_enable(&tp->udev->dev, true);
3339 else
3340 device_set_wakeup_enable(&tp->udev->dev, false);
3341}
3342
3343static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
3344{
3345 u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3346
3347 /* MAC clock speed down */
3348 if (enable)
3349 ocp_data |= MAC_CLK_SPDWN_EN;
3350 else
3351 ocp_data &= ~MAC_CLK_SPDWN_EN;
3352
3353 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3354}
3355
3356static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
3357{
3358 u32 ocp_data;
3359
3360 /* MAC clock speed down */
3361 if (enable) {
3362 /* aldps_spdwn_ratio, tp10_spdwn_ratio */
3363 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
3364 0x0403);
3365
3366 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3367 ocp_data &= ~EEE_SPDWN_RATIO_MASK;
3368 ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
3369 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3370 } else {
3371 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
3372 ocp_data &= ~MAC_CLK_SPDWN_EN;
3373 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
3374 }
3375}
3376
3377static void r8153_u1u2en(struct r8152 *tp, bool enable)
3378{
3379 u8 u1u2[8];
3380
3381 if (enable)
3382 memset(u1u2, 0xff, sizeof(u1u2));
3383 else
3384 memset(u1u2, 0x00, sizeof(u1u2));
3385
3386 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
3387}
3388
3389static void r8153b_u1u2en(struct r8152 *tp, bool enable)
3390{
3391 u32 ocp_data;
3392
3393 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
3394 if (enable)
3395 ocp_data |= LPM_U1U2_EN;
3396 else
3397 ocp_data &= ~LPM_U1U2_EN;
3398
3399 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
3400}
3401
3402static void r8153_u2p3en(struct r8152 *tp, bool enable)
3403{
3404 u32 ocp_data;
3405
3406 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3407 if (enable)
3408 ocp_data |= U2P3_ENABLE;
3409 else
3410 ocp_data &= ~U2P3_ENABLE;
3411 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
3412}
3413
3414static void r8153b_ups_flags(struct r8152 *tp)
3415{
3416 u32 ups_flags = 0;
3417
3418 if (tp->ups_info.green)
3419 ups_flags |= UPS_FLAGS_EN_GREEN;
3420
3421 if (tp->ups_info.aldps)
3422 ups_flags |= UPS_FLAGS_EN_ALDPS;
3423
3424 if (tp->ups_info.eee)
3425 ups_flags |= UPS_FLAGS_EN_EEE;
3426
3427 if (tp->ups_info.flow_control)
3428 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3429
3430 if (tp->ups_info.eee_ckdiv)
3431 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3432
3433 if (tp->ups_info.eee_cmod_lv)
3434 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
3435
3436 if (tp->ups_info.r_tune)
3437 ups_flags |= UPS_FLAGS_R_TUNE;
3438
3439 if (tp->ups_info._10m_ckdiv)
3440 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3441
3442 if (tp->ups_info.eee_plloff_100)
3443 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3444
3445 if (tp->ups_info.eee_plloff_giga)
3446 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3447
3448 if (tp->ups_info._250m_ckdiv)
3449 ups_flags |= UPS_FLAGS_250M_CKDIV;
3450
3451 if (tp->ups_info.ctap_short_off)
3452 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS;
3453
3454 switch (tp->ups_info.speed_duplex) {
3455 case NWAY_10M_HALF:
3456 ups_flags |= ups_flags_speed(1);
3457 break;
3458 case NWAY_10M_FULL:
3459 ups_flags |= ups_flags_speed(2);
3460 break;
3461 case NWAY_100M_HALF:
3462 ups_flags |= ups_flags_speed(3);
3463 break;
3464 case NWAY_100M_FULL:
3465 ups_flags |= ups_flags_speed(4);
3466 break;
3467 case NWAY_1000M_FULL:
3468 ups_flags |= ups_flags_speed(5);
3469 break;
3470 case FORCE_10M_HALF:
3471 ups_flags |= ups_flags_speed(6);
3472 break;
3473 case FORCE_10M_FULL:
3474 ups_flags |= ups_flags_speed(7);
3475 break;
3476 case FORCE_100M_HALF:
3477 ups_flags |= ups_flags_speed(8);
3478 break;
3479 case FORCE_100M_FULL:
3480 ups_flags |= ups_flags_speed(9);
3481 break;
3482 default:
3483 break;
3484 }
3485
3486 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3487}
3488
3489static void r8156_ups_flags(struct r8152 *tp)
3490{
3491 u32 ups_flags = 0;
3492
3493 if (tp->ups_info.green)
3494 ups_flags |= UPS_FLAGS_EN_GREEN;
3495
3496 if (tp->ups_info.aldps)
3497 ups_flags |= UPS_FLAGS_EN_ALDPS;
3498
3499 if (tp->ups_info.eee)
3500 ups_flags |= UPS_FLAGS_EN_EEE;
3501
3502 if (tp->ups_info.flow_control)
3503 ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
3504
3505 if (tp->ups_info.eee_ckdiv)
3506 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
3507
3508 if (tp->ups_info._10m_ckdiv)
3509 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
3510
3511 if (tp->ups_info.eee_plloff_100)
3512 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
3513
3514 if (tp->ups_info.eee_plloff_giga)
3515 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
3516
3517 if (tp->ups_info._250m_ckdiv)
3518 ups_flags |= UPS_FLAGS_250M_CKDIV;
3519
3520 switch (tp->ups_info.speed_duplex) {
3521 case FORCE_10M_HALF:
3522 ups_flags |= ups_flags_speed(0);
3523 break;
3524 case FORCE_10M_FULL:
3525 ups_flags |= ups_flags_speed(1);
3526 break;
3527 case FORCE_100M_HALF:
3528 ups_flags |= ups_flags_speed(2);
3529 break;
3530 case FORCE_100M_FULL:
3531 ups_flags |= ups_flags_speed(3);
3532 break;
3533 case NWAY_10M_HALF:
3534 ups_flags |= ups_flags_speed(4);
3535 break;
3536 case NWAY_10M_FULL:
3537 ups_flags |= ups_flags_speed(5);
3538 break;
3539 case NWAY_100M_HALF:
3540 ups_flags |= ups_flags_speed(6);
3541 break;
3542 case NWAY_100M_FULL:
3543 ups_flags |= ups_flags_speed(7);
3544 break;
3545 case NWAY_1000M_FULL:
3546 ups_flags |= ups_flags_speed(8);
3547 break;
3548 case NWAY_2500M_FULL:
3549 ups_flags |= ups_flags_speed(9);
3550 break;
3551 default:
3552 break;
3553 }
3554
3555 switch (tp->ups_info.lite_mode) {
3556 case 1:
3557 ups_flags |= 0 << 5;
3558 break;
3559 case 2:
3560 ups_flags |= 2 << 5;
3561 break;
3562 case 0:
3563 default:
3564 ups_flags |= 1 << 5;
3565 break;
3566 }
3567
3568 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
3569}
3570
3571static void rtl_green_en(struct r8152 *tp, bool enable)
3572{
3573 u16 data;
3574
3575 data = sram_read(tp, SRAM_GREEN_CFG);
3576 if (enable)
3577 data |= GREEN_ETH_EN;
3578 else
3579 data &= ~GREEN_ETH_EN;
3580 sram_write(tp, SRAM_GREEN_CFG, data);
3581
3582 tp->ups_info.green = enable;
3583}
3584
3585static void r8153b_green_en(struct r8152 *tp, bool enable)
3586{
3587 if (enable) {
3588 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */
3589 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */
3590 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */
3591 } else {
3592 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */
3593 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */
3594 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */
3595 }
3596
3597 rtl_green_en(tp, true);
3598}
3599
3600static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
3601{
3602 u16 data;
3603 int i;
3604
3605 for (i = 0; i < 500; i++) {
3606 data = ocp_reg_read(tp, OCP_PHY_STATUS);
3607 data &= PHY_STAT_MASK;
3608 if (desired) {
3609 if (data == desired)
3610 break;
3611 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
3612 data == PHY_STAT_EXT_INIT) {
3613 break;
3614 }
3615
3616 msleep(20);
3617 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3618 break;
3619 }
3620
3621 return data;
3622}
3623
3624static void r8153b_ups_en(struct r8152 *tp, bool enable)
3625{
3626 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3627
3628 if (enable) {
3629 r8153b_ups_flags(tp);
3630
3631 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3632 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3633
3634 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3635 ocp_data |= UPS_FORCE_PWR_DOWN;
3636 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3637 } else {
3638 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3639 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3640
3641 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3642 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3643 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3644
3645 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3646 int i;
3647
3648 for (i = 0; i < 500; i++) {
3649 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3650 AUTOLOAD_DONE)
3651 break;
3652 msleep(20);
3653 }
3654
3655 tp->rtl_ops.hw_phy_cfg(tp);
3656
3657 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3658 tp->duplex, tp->advertising);
3659 }
3660 }
3661}
3662
3663static void r8153c_ups_en(struct r8152 *tp, bool enable)
3664{
3665 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3666
3667 if (enable) {
3668 r8153b_ups_flags(tp);
3669
3670 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3671 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3672
3673 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3674 ocp_data |= UPS_FORCE_PWR_DOWN;
3675 ocp_data &= ~BIT(7);
3676 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3677 } else {
3678 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3679 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3680
3681 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3682 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3683 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3684
3685 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3686 int i;
3687
3688 for (i = 0; i < 500; i++) {
3689 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3690 AUTOLOAD_DONE)
3691 break;
3692 msleep(20);
3693 }
3694
3695 tp->rtl_ops.hw_phy_cfg(tp);
3696
3697 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3698 tp->duplex, tp->advertising);
3699 }
3700
3701 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3702
3703 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3704 ocp_data |= BIT(8);
3705 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3706
3707 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3708 }
3709}
3710
3711static void r8156_ups_en(struct r8152 *tp, bool enable)
3712{
3713 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
3714
3715 if (enable) {
3716 r8156_ups_flags(tp);
3717
3718 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
3719 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3720
3721 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3722 ocp_data |= UPS_FORCE_PWR_DOWN;
3723 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3724
3725 switch (tp->version) {
3726 case RTL_VER_13:
3727 case RTL_VER_15:
3728 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
3729 ocp_data &= ~OOBS_POLLING;
3730 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
3731 break;
3732 default:
3733 break;
3734 }
3735 } else {
3736 ocp_data &= ~(UPS_EN | USP_PREWAKE);
3737 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3738
3739 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
3740 ocp_data &= ~UPS_FORCE_PWR_DOWN;
3741 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
3742
3743 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
3744 tp->rtl_ops.hw_phy_cfg(tp);
3745
3746 rtl8152_set_speed(tp, tp->autoneg, tp->speed,
3747 tp->duplex, tp->advertising);
3748 }
3749 }
3750}
3751
3752static void r8153_power_cut_en(struct r8152 *tp, bool enable)
3753{
3754 u32 ocp_data;
3755
3756 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3757 if (enable)
3758 ocp_data |= PWR_EN | PHASE2_EN;
3759 else
3760 ocp_data &= ~(PWR_EN | PHASE2_EN);
3761 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3762
3763 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3764 ocp_data &= ~PCUT_STATUS;
3765 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3766}
3767
3768static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
3769{
3770 u32 ocp_data;
3771
3772 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
3773 if (enable)
3774 ocp_data |= PWR_EN | PHASE2_EN;
3775 else
3776 ocp_data &= ~PWR_EN;
3777 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
3778
3779 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
3780 ocp_data &= ~PCUT_STATUS;
3781 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
3782}
3783
3784static void r8153_queue_wake(struct r8152 *tp, bool enable)
3785{
3786 u32 ocp_data;
3787
3788 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG);
3789 if (enable)
3790 ocp_data |= UPCOMING_RUNTIME_D3;
3791 else
3792 ocp_data &= ~UPCOMING_RUNTIME_D3;
3793 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data);
3794
3795 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG);
3796 ocp_data &= ~LINK_CHG_EVENT;
3797 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data);
3798
3799 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
3800 ocp_data &= ~LINK_CHANGE_FLAG;
3801 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
3802}
3803
3804static bool rtl_can_wakeup(struct r8152 *tp)
3805{
3806 struct usb_device *udev = tp->udev;
3807
3808 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
3809}
3810
3811static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
3812{
3813 if (enable) {
3814 u32 ocp_data;
3815
3816 __rtl_set_wol(tp, WAKE_ANY);
3817
3818 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3819
3820 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3821 ocp_data |= LINK_OFF_WAKE_EN;
3822 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3823
3824 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3825 } else {
3826 u32 ocp_data;
3827
3828 __rtl_set_wol(tp, tp->saved_wolopts);
3829
3830 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
3831
3832 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
3833 ocp_data &= ~LINK_OFF_WAKE_EN;
3834 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
3835
3836 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3837 }
3838}
3839
3840static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
3841{
3842 if (enable) {
3843 r8153_u1u2en(tp, false);
3844 r8153_u2p3en(tp, false);
3845 rtl_runtime_suspend_enable(tp, true);
3846 } else {
3847 rtl_runtime_suspend_enable(tp, false);
3848
3849 switch (tp->version) {
3850 case RTL_VER_03:
3851 case RTL_VER_04:
3852 break;
3853 case RTL_VER_05:
3854 case RTL_VER_06:
3855 default:
3856 r8153_u2p3en(tp, true);
3857 break;
3858 }
3859
3860 r8153_u1u2en(tp, true);
3861 }
3862}
3863
3864static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
3865{
3866 if (enable) {
3867 r8153_queue_wake(tp, true);
3868 r8153b_u1u2en(tp, false);
3869 r8153_u2p3en(tp, false);
3870 rtl_runtime_suspend_enable(tp, true);
3871 r8153b_ups_en(tp, true);
3872 } else {
3873 r8153b_ups_en(tp, false);
3874 r8153_queue_wake(tp, false);
3875 rtl_runtime_suspend_enable(tp, false);
3876 if (tp->udev->speed >= USB_SPEED_SUPER)
3877 r8153b_u1u2en(tp, true);
3878 }
3879}
3880
3881static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
3882{
3883 if (enable) {
3884 r8153_queue_wake(tp, true);
3885 r8153b_u1u2en(tp, false);
3886 r8153_u2p3en(tp, false);
3887 rtl_runtime_suspend_enable(tp, true);
3888 r8153c_ups_en(tp, true);
3889 } else {
3890 r8153c_ups_en(tp, false);
3891 r8153_queue_wake(tp, false);
3892 rtl_runtime_suspend_enable(tp, false);
3893 r8153b_u1u2en(tp, true);
3894 }
3895}
3896
3897static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
3898{
3899 if (enable) {
3900 r8153_queue_wake(tp, true);
3901 r8153b_u1u2en(tp, false);
3902 r8153_u2p3en(tp, false);
3903 rtl_runtime_suspend_enable(tp, true);
3904 } else {
3905 r8153_queue_wake(tp, false);
3906 rtl_runtime_suspend_enable(tp, false);
3907 r8153_u2p3en(tp, true);
3908 if (tp->udev->speed >= USB_SPEED_SUPER)
3909 r8153b_u1u2en(tp, true);
3910 }
3911}
3912
3913static void r8153_teredo_off(struct r8152 *tp)
3914{
3915 u32 ocp_data;
3916
3917 switch (tp->version) {
3918 case RTL_VER_01:
3919 case RTL_VER_02:
3920 case RTL_VER_03:
3921 case RTL_VER_04:
3922 case RTL_VER_05:
3923 case RTL_VER_06:
3924 case RTL_VER_07:
3925 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3926 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
3927 OOB_TEREDO_EN);
3928 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3929 break;
3930
3931 case RTL_VER_08:
3932 case RTL_VER_09:
3933 case RTL_TEST_01:
3934 case RTL_VER_10:
3935 case RTL_VER_11:
3936 case RTL_VER_12:
3937 case RTL_VER_13:
3938 case RTL_VER_14:
3939 case RTL_VER_15:
3940 default:
3941 /* The bit 0 ~ 7 are relative with teredo settings. They are
3942 * W1C (write 1 to clear), so set all 1 to disable it.
3943 */
3944 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
3945 break;
3946 }
3947
3948 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
3949 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
3950 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
3951}
3952
3953static void rtl_reset_bmu(struct r8152 *tp)
3954{
3955 u32 ocp_data;
3956
3957 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
3958 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
3959 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3960 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
3961 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
3962}
3963
3964/* Clear the bp to stop the firmware before loading a new one */
3965static void rtl_clear_bp(struct r8152 *tp, u16 type)
3966{
3967 switch (tp->version) {
3968 case RTL_VER_01:
3969 case RTL_VER_02:
3970 case RTL_VER_07:
3971 break;
3972 case RTL_VER_03:
3973 case RTL_VER_04:
3974 case RTL_VER_05:
3975 case RTL_VER_06:
3976 ocp_write_byte(tp, type, PLA_BP_EN, 0);
3977 break;
3978 case RTL_VER_14:
3979 ocp_write_word(tp, type, USB_BP2_EN, 0);
3980
3981 ocp_write_word(tp, type, USB_BP_8, 0);
3982 ocp_write_word(tp, type, USB_BP_9, 0);
3983 ocp_write_word(tp, type, USB_BP_10, 0);
3984 ocp_write_word(tp, type, USB_BP_11, 0);
3985 ocp_write_word(tp, type, USB_BP_12, 0);
3986 ocp_write_word(tp, type, USB_BP_13, 0);
3987 ocp_write_word(tp, type, USB_BP_14, 0);
3988 ocp_write_word(tp, type, USB_BP_15, 0);
3989 break;
3990 case RTL_VER_08:
3991 case RTL_VER_09:
3992 case RTL_VER_10:
3993 case RTL_VER_11:
3994 case RTL_VER_12:
3995 case RTL_VER_13:
3996 case RTL_VER_15:
3997 default:
3998 if (type == MCU_TYPE_USB) {
3999 ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
4000
4001 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_8, 0);
4002 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_9, 0);
4003 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_10, 0);
4004 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_11, 0);
4005 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_12, 0);
4006 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_13, 0);
4007 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_14, 0);
4008 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_15, 0);
4009 } else {
4010 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
4011 }
4012 break;
4013 }
4014
4015 ocp_write_word(tp, type, PLA_BP_0, 0);
4016 ocp_write_word(tp, type, PLA_BP_1, 0);
4017 ocp_write_word(tp, type, PLA_BP_2, 0);
4018 ocp_write_word(tp, type, PLA_BP_3, 0);
4019 ocp_write_word(tp, type, PLA_BP_4, 0);
4020 ocp_write_word(tp, type, PLA_BP_5, 0);
4021 ocp_write_word(tp, type, PLA_BP_6, 0);
4022 ocp_write_word(tp, type, PLA_BP_7, 0);
4023
4024 /* wait 3 ms to make sure the firmware is stopped */
4025 usleep_range(3000, 6000);
4026 ocp_write_word(tp, type, PLA_BP_BA, 0);
4027}
4028
4029static inline void rtl_reset_ocp_base(struct r8152 *tp)
4030{
4031 tp->ocp_base = -1;
4032}
4033
4034static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait)
4035{
4036 u16 data, check;
4037 int i;
4038
4039 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
4040 if (request) {
4041 data |= PATCH_REQUEST;
4042 check = 0;
4043 } else {
4044 data &= ~PATCH_REQUEST;
4045 check = PATCH_READY;
4046 }
4047 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
4048
4049 for (i = 0; wait && i < 5000; i++) {
4050 u32 ocp_data;
4051
4052 usleep_range(1000, 2000);
4053 ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
4054 if ((ocp_data & PATCH_READY) ^ check)
4055 break;
4056 }
4057
4058 if (request && wait &&
4059 !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
4060 dev_err(&tp->intf->dev, "PHY patch request fail\n");
4061 rtl_phy_patch_request(tp, false, false);
4062 return -ETIME;
4063 } else {
4064 return 0;
4065 }
4066}
4067
4068static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key)
4069{
4070 if (patch_key && key_addr) {
4071 sram_write(tp, key_addr, patch_key);
4072 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK);
4073 } else if (key_addr) {
4074 u16 data;
4075
4076 sram_write(tp, 0x0000, 0x0000);
4077
4078 data = ocp_reg_read(tp, OCP_PHY_LOCK);
4079 data &= ~PATCH_LOCK;
4080 ocp_reg_write(tp, OCP_PHY_LOCK, data);
4081
4082 sram_write(tp, key_addr, 0x0000);
4083 } else {
4084 WARN_ON_ONCE(1);
4085 }
4086}
4087
4088static int
4089rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait)
4090{
4091 if (rtl_phy_patch_request(tp, true, wait))
4092 return -ETIME;
4093
4094 rtl_patch_key_set(tp, key_addr, patch_key);
4095
4096 return 0;
4097}
4098
4099static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait)
4100{
4101 rtl_patch_key_set(tp, key_addr, 0);
4102
4103 rtl_phy_patch_request(tp, false, wait);
4104
4105 return 0;
4106}
4107
4108static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy)
4109{
4110 u16 fw_offset;
4111 u32 length;
4112 bool rc = false;
4113
4114 switch (tp->version) {
4115 case RTL_VER_01:
4116 case RTL_VER_02:
4117 case RTL_VER_03:
4118 case RTL_VER_04:
4119 case RTL_VER_05:
4120 case RTL_VER_06:
4121 case RTL_VER_07:
4122 case RTL_VER_08:
4123 case RTL_VER_09:
4124 case RTL_VER_10:
4125 case RTL_VER_11:
4126 case RTL_VER_12:
4127 case RTL_VER_14:
4128 goto out;
4129 case RTL_VER_13:
4130 case RTL_VER_15:
4131 default:
4132 break;
4133 }
4134
4135 fw_offset = __le16_to_cpu(phy->fw_offset);
4136 length = __le32_to_cpu(phy->blk_hdr.length);
4137 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4138 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4139 goto out;
4140 }
4141
4142 length -= fw_offset;
4143 if (length & 3) {
4144 dev_err(&tp->intf->dev, "invalid block length\n");
4145 goto out;
4146 }
4147
4148 if (__le16_to_cpu(phy->fw_reg) != 0x9A00) {
4149 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4150 goto out;
4151 }
4152
4153 rc = true;
4154out:
4155 return rc;
4156}
4157
4158static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver)
4159{
4160 bool rc = false;
4161
4162 switch (tp->version) {
4163 case RTL_VER_10:
4164 case RTL_VER_11:
4165 case RTL_VER_12:
4166 case RTL_VER_13:
4167 case RTL_VER_15:
4168 break;
4169 default:
4170 goto out;
4171 }
4172
4173 if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) {
4174 dev_err(&tp->intf->dev, "invalid block length\n");
4175 goto out;
4176 }
4177
4178 if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) {
4179 dev_err(&tp->intf->dev, "invalid phy ver addr\n");
4180 goto out;
4181 }
4182
4183 rc = true;
4184out:
4185 return rc;
4186}
4187
4188static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix)
4189{
4190 bool rc = false;
4191
4192 switch (tp->version) {
4193 case RTL_VER_10:
4194 case RTL_VER_11:
4195 case RTL_VER_12:
4196 case RTL_VER_13:
4197 case RTL_VER_15:
4198 break;
4199 default:
4200 goto out;
4201 }
4202
4203 if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) {
4204 dev_err(&tp->intf->dev, "invalid block length\n");
4205 goto out;
4206 }
4207
4208 if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD ||
4209 __le16_to_cpu(fix->setting.data) != BIT(7)) {
4210 dev_err(&tp->intf->dev, "invalid phy fixup\n");
4211 goto out;
4212 }
4213
4214 rc = true;
4215out:
4216 return rc;
4217}
4218
4219static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy)
4220{
4221 u16 fw_offset;
4222 u32 length;
4223 bool rc = false;
4224
4225 switch (tp->version) {
4226 case RTL_VER_10:
4227 case RTL_VER_11:
4228 case RTL_VER_12:
4229 case RTL_VER_13:
4230 case RTL_VER_15:
4231 break;
4232 default:
4233 goto out;
4234 }
4235
4236 fw_offset = __le16_to_cpu(phy->fw_offset);
4237 length = __le32_to_cpu(phy->blk_hdr.length);
4238 if (fw_offset < sizeof(*phy) || length <= fw_offset) {
4239 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4240 goto out;
4241 }
4242
4243 length -= fw_offset;
4244 if (length & 1) {
4245 dev_err(&tp->intf->dev, "invalid block length\n");
4246 goto out;
4247 }
4248
4249 if (phy->pre_num > 2) {
4250 dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num);
4251 goto out;
4252 }
4253
4254 if (phy->bp_num > 8) {
4255 dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num);
4256 goto out;
4257 }
4258
4259 rc = true;
4260out:
4261 return rc;
4262}
4263
4264static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy)
4265{
4266 u32 length;
4267 u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start;
4268 bool rc = false;
4269
4270 switch (tp->version) {
4271 case RTL_VER_04:
4272 case RTL_VER_05:
4273 case RTL_VER_06:
4274 fw_reg = 0xa014;
4275 ba_reg = 0xa012;
4276 patch_en_addr = 0xa01a;
4277 mode_reg = 0xb820;
4278 bp_start = 0xa000;
4279 break;
4280 default:
4281 goto out;
4282 }
4283
4284 fw_offset = __le16_to_cpu(phy->fw_offset);
4285 if (fw_offset < sizeof(*phy)) {
4286 dev_err(&tp->intf->dev, "fw_offset too small\n");
4287 goto out;
4288 }
4289
4290 length = __le32_to_cpu(phy->blk_hdr.length);
4291 if (length < fw_offset) {
4292 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4293 goto out;
4294 }
4295
4296 length -= __le16_to_cpu(phy->fw_offset);
4297 if (!length || (length & 1)) {
4298 dev_err(&tp->intf->dev, "invalid block length\n");
4299 goto out;
4300 }
4301
4302 if (__le16_to_cpu(phy->fw_reg) != fw_reg) {
4303 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4304 goto out;
4305 }
4306
4307 if (__le16_to_cpu(phy->ba_reg) != ba_reg) {
4308 dev_err(&tp->intf->dev, "invalid base address register\n");
4309 goto out;
4310 }
4311
4312 if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) {
4313 dev_err(&tp->intf->dev,
4314 "invalid patch mode enabled register\n");
4315 goto out;
4316 }
4317
4318 if (__le16_to_cpu(phy->mode_reg) != mode_reg) {
4319 dev_err(&tp->intf->dev,
4320 "invalid register to switch the mode\n");
4321 goto out;
4322 }
4323
4324 if (__le16_to_cpu(phy->bp_start) != bp_start) {
4325 dev_err(&tp->intf->dev,
4326 "invalid start register of break point\n");
4327 goto out;
4328 }
4329
4330 if (__le16_to_cpu(phy->bp_num) > 4) {
4331 dev_err(&tp->intf->dev, "invalid break point number\n");
4332 goto out;
4333 }
4334
4335 rc = true;
4336out:
4337 return rc;
4338}
4339
4340static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac)
4341{
4342 u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset;
4343 bool rc = false;
4344 u32 length, type;
4345 int i, max_bp;
4346
4347 type = __le32_to_cpu(mac->blk_hdr.type);
4348 if (type == RTL_FW_PLA) {
4349 switch (tp->version) {
4350 case RTL_VER_01:
4351 case RTL_VER_02:
4352 case RTL_VER_07:
4353 fw_reg = 0xf800;
4354 bp_ba_addr = PLA_BP_BA;
4355 bp_en_addr = 0;
4356 bp_start = PLA_BP_0;
4357 max_bp = 8;
4358 break;
4359 case RTL_VER_03:
4360 case RTL_VER_04:
4361 case RTL_VER_05:
4362 case RTL_VER_06:
4363 case RTL_VER_08:
4364 case RTL_VER_09:
4365 case RTL_VER_11:
4366 case RTL_VER_12:
4367 case RTL_VER_13:
4368 case RTL_VER_15:
4369 fw_reg = 0xf800;
4370 bp_ba_addr = PLA_BP_BA;
4371 bp_en_addr = PLA_BP_EN;
4372 bp_start = PLA_BP_0;
4373 max_bp = 8;
4374 break;
4375 case RTL_VER_14:
4376 fw_reg = 0xf800;
4377 bp_ba_addr = PLA_BP_BA;
4378 bp_en_addr = USB_BP2_EN;
4379 bp_start = PLA_BP_0;
4380 max_bp = 16;
4381 break;
4382 default:
4383 goto out;
4384 }
4385 } else if (type == RTL_FW_USB) {
4386 switch (tp->version) {
4387 case RTL_VER_03:
4388 case RTL_VER_04:
4389 case RTL_VER_05:
4390 case RTL_VER_06:
4391 fw_reg = 0xf800;
4392 bp_ba_addr = USB_BP_BA;
4393 bp_en_addr = USB_BP_EN;
4394 bp_start = USB_BP_0;
4395 max_bp = 8;
4396 break;
4397 case RTL_VER_08:
4398 case RTL_VER_09:
4399 case RTL_VER_11:
4400 case RTL_VER_12:
4401 case RTL_VER_13:
4402 case RTL_VER_14:
4403 case RTL_VER_15:
4404 fw_reg = 0xe600;
4405 bp_ba_addr = USB_BP_BA;
4406 bp_en_addr = USB_BP2_EN;
4407 bp_start = USB_BP_0;
4408 max_bp = 16;
4409 break;
4410 case RTL_VER_01:
4411 case RTL_VER_02:
4412 case RTL_VER_07:
4413 default:
4414 goto out;
4415 }
4416 } else {
4417 goto out;
4418 }
4419
4420 fw_offset = __le16_to_cpu(mac->fw_offset);
4421 if (fw_offset < sizeof(*mac)) {
4422 dev_err(&tp->intf->dev, "fw_offset too small\n");
4423 goto out;
4424 }
4425
4426 length = __le32_to_cpu(mac->blk_hdr.length);
4427 if (length < fw_offset) {
4428 dev_err(&tp->intf->dev, "invalid fw_offset\n");
4429 goto out;
4430 }
4431
4432 length -= fw_offset;
4433 if (length < 4 || (length & 3)) {
4434 dev_err(&tp->intf->dev, "invalid block length\n");
4435 goto out;
4436 }
4437
4438 if (__le16_to_cpu(mac->fw_reg) != fw_reg) {
4439 dev_err(&tp->intf->dev, "invalid register to load firmware\n");
4440 goto out;
4441 }
4442
4443 if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) {
4444 dev_err(&tp->intf->dev, "invalid base address register\n");
4445 goto out;
4446 }
4447
4448 if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) {
4449 dev_err(&tp->intf->dev, "invalid enabled mask register\n");
4450 goto out;
4451 }
4452
4453 if (__le16_to_cpu(mac->bp_start) != bp_start) {
4454 dev_err(&tp->intf->dev,
4455 "invalid start register of break point\n");
4456 goto out;
4457 }
4458
4459 if (__le16_to_cpu(mac->bp_num) > max_bp) {
4460 dev_err(&tp->intf->dev, "invalid break point number\n");
4461 goto out;
4462 }
4463
4464 for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) {
4465 if (mac->bp[i]) {
4466 dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i);
4467 goto out;
4468 }
4469 }
4470
4471 rc = true;
4472out:
4473 return rc;
4474}
4475
4476/* Verify the checksum for the firmware file. It is calculated from the version
4477 * field to the end of the file. Compare the result with the checksum field to
4478 * make sure the file is correct.
4479 */
4480static long rtl8152_fw_verify_checksum(struct r8152 *tp,
4481 struct fw_header *fw_hdr, size_t size)
4482{
4483 unsigned char checksum[sizeof(fw_hdr->checksum)];
4484 struct crypto_shash *alg;
4485 struct shash_desc *sdesc;
4486 size_t len;
4487 long rc;
4488
4489 alg = crypto_alloc_shash("sha256", 0, 0);
4490 if (IS_ERR(alg)) {
4491 rc = PTR_ERR(alg);
4492 goto out;
4493 }
4494
4495 if (crypto_shash_digestsize(alg) != sizeof(fw_hdr->checksum)) {
4496 rc = -EFAULT;
4497 dev_err(&tp->intf->dev, "digestsize incorrect (%u)\n",
4498 crypto_shash_digestsize(alg));
4499 goto free_shash;
4500 }
4501
4502 len = sizeof(*sdesc) + crypto_shash_descsize(alg);
4503 sdesc = kmalloc(len, GFP_KERNEL);
4504 if (!sdesc) {
4505 rc = -ENOMEM;
4506 goto free_shash;
4507 }
4508 sdesc->tfm = alg;
4509
4510 len = size - sizeof(fw_hdr->checksum);
4511 rc = crypto_shash_digest(sdesc, fw_hdr->version, len, checksum);
4512 kfree(sdesc);
4513 if (rc)
4514 goto free_shash;
4515
4516 if (memcmp(fw_hdr->checksum, checksum, sizeof(fw_hdr->checksum))) {
4517 dev_err(&tp->intf->dev, "checksum fail\n");
4518 rc = -EFAULT;
4519 }
4520
4521free_shash:
4522 crypto_free_shash(alg);
4523out:
4524 return rc;
4525}
4526
4527static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw)
4528{
4529 const struct firmware *fw = rtl_fw->fw;
4530 struct fw_header *fw_hdr = (struct fw_header *)fw->data;
4531 unsigned long fw_flags = 0;
4532 long ret = -EFAULT;
4533 int i;
4534
4535 if (fw->size < sizeof(*fw_hdr)) {
4536 dev_err(&tp->intf->dev, "file too small\n");
4537 goto fail;
4538 }
4539
4540 ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size);
4541 if (ret)
4542 goto fail;
4543
4544 ret = -EFAULT;
4545
4546 for (i = sizeof(*fw_hdr); i < fw->size;) {
4547 struct fw_block *block = (struct fw_block *)&fw->data[i];
4548 u32 type;
4549
4550 if ((i + sizeof(*block)) > fw->size)
4551 goto fail;
4552
4553 type = __le32_to_cpu(block->type);
4554 switch (type) {
4555 case RTL_FW_END:
4556 if (__le32_to_cpu(block->length) != sizeof(*block))
4557 goto fail;
4558 goto fw_end;
4559 case RTL_FW_PLA:
4560 if (test_bit(FW_FLAGS_PLA, &fw_flags)) {
4561 dev_err(&tp->intf->dev,
4562 "multiple PLA firmware encountered");
4563 goto fail;
4564 }
4565
4566 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4567 dev_err(&tp->intf->dev,
4568 "check PLA firmware failed\n");
4569 goto fail;
4570 }
4571 __set_bit(FW_FLAGS_PLA, &fw_flags);
4572 break;
4573 case RTL_FW_USB:
4574 if (test_bit(FW_FLAGS_USB, &fw_flags)) {
4575 dev_err(&tp->intf->dev,
4576 "multiple USB firmware encountered");
4577 goto fail;
4578 }
4579
4580 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) {
4581 dev_err(&tp->intf->dev,
4582 "check USB firmware failed\n");
4583 goto fail;
4584 }
4585 __set_bit(FW_FLAGS_USB, &fw_flags);
4586 break;
4587 case RTL_FW_PHY_START:
4588 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4589 test_bit(FW_FLAGS_NC, &fw_flags) ||
4590 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4591 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4592 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4593 test_bit(FW_FLAGS_UC, &fw_flags) ||
4594 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4595 dev_err(&tp->intf->dev,
4596 "check PHY_START fail\n");
4597 goto fail;
4598 }
4599
4600 if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) {
4601 dev_err(&tp->intf->dev,
4602 "Invalid length for PHY_START\n");
4603 goto fail;
4604 }
4605 __set_bit(FW_FLAGS_START, &fw_flags);
4606 break;
4607 case RTL_FW_PHY_STOP:
4608 if (test_bit(FW_FLAGS_STOP, &fw_flags) ||
4609 !test_bit(FW_FLAGS_START, &fw_flags)) {
4610 dev_err(&tp->intf->dev,
4611 "Check PHY_STOP fail\n");
4612 goto fail;
4613 }
4614
4615 if (__le32_to_cpu(block->length) != sizeof(*block)) {
4616 dev_err(&tp->intf->dev,
4617 "Invalid length for PHY_STOP\n");
4618 goto fail;
4619 }
4620 __set_bit(FW_FLAGS_STOP, &fw_flags);
4621 break;
4622 case RTL_FW_PHY_NC:
4623 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4624 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4625 dev_err(&tp->intf->dev,
4626 "check PHY_NC fail\n");
4627 goto fail;
4628 }
4629
4630 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4631 dev_err(&tp->intf->dev,
4632 "multiple PHY NC encountered\n");
4633 goto fail;
4634 }
4635
4636 if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) {
4637 dev_err(&tp->intf->dev,
4638 "check PHY NC firmware failed\n");
4639 goto fail;
4640 }
4641 __set_bit(FW_FLAGS_NC, &fw_flags);
4642 break;
4643 case RTL_FW_PHY_UNION_NC:
4644 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4645 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4646 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4647 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4648 test_bit(FW_FLAGS_UC, &fw_flags) ||
4649 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4650 dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n");
4651 goto fail;
4652 }
4653
4654 if (test_bit(FW_FLAGS_NC, &fw_flags)) {
4655 dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n");
4656 goto fail;
4657 }
4658
4659 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4660 dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n");
4661 goto fail;
4662 }
4663 __set_bit(FW_FLAGS_NC, &fw_flags);
4664 break;
4665 case RTL_FW_PHY_UNION_NC1:
4666 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4667 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4668 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4669 test_bit(FW_FLAGS_UC, &fw_flags) ||
4670 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4671 dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n");
4672 goto fail;
4673 }
4674
4675 if (test_bit(FW_FLAGS_NC1, &fw_flags)) {
4676 dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n");
4677 goto fail;
4678 }
4679
4680 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4681 dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n");
4682 goto fail;
4683 }
4684 __set_bit(FW_FLAGS_NC1, &fw_flags);
4685 break;
4686 case RTL_FW_PHY_UNION_NC2:
4687 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4688 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4689 test_bit(FW_FLAGS_UC, &fw_flags) ||
4690 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4691 dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n");
4692 goto fail;
4693 }
4694
4695 if (test_bit(FW_FLAGS_NC2, &fw_flags)) {
4696 dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n");
4697 goto fail;
4698 }
4699
4700 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4701 dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n");
4702 goto fail;
4703 }
4704 __set_bit(FW_FLAGS_NC2, &fw_flags);
4705 break;
4706 case RTL_FW_PHY_UNION_UC2:
4707 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4708 test_bit(FW_FLAGS_UC, &fw_flags) ||
4709 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4710 dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n");
4711 goto fail;
4712 }
4713
4714 if (test_bit(FW_FLAGS_UC2, &fw_flags)) {
4715 dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n");
4716 goto fail;
4717 }
4718
4719 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4720 dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n");
4721 goto fail;
4722 }
4723 __set_bit(FW_FLAGS_UC2, &fw_flags);
4724 break;
4725 case RTL_FW_PHY_UNION_UC:
4726 if (!test_bit(FW_FLAGS_START, &fw_flags) ||
4727 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4728 dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n");
4729 goto fail;
4730 }
4731
4732 if (test_bit(FW_FLAGS_UC, &fw_flags)) {
4733 dev_err(&tp->intf->dev, "multiple PHY UC encountered\n");
4734 goto fail;
4735 }
4736
4737 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4738 dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n");
4739 goto fail;
4740 }
4741 __set_bit(FW_FLAGS_UC, &fw_flags);
4742 break;
4743 case RTL_FW_PHY_UNION_MISC:
4744 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) {
4745 dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n");
4746 goto fail;
4747 }
4748 break;
4749 case RTL_FW_PHY_FIXUP:
4750 if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) {
4751 dev_err(&tp->intf->dev, "check PHY fixup failed\n");
4752 goto fail;
4753 }
4754 break;
4755 case RTL_FW_PHY_SPEED_UP:
4756 if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) {
4757 dev_err(&tp->intf->dev, "multiple PHY firmware encountered");
4758 goto fail;
4759 }
4760
4761 if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) {
4762 dev_err(&tp->intf->dev, "check PHY speed up failed\n");
4763 goto fail;
4764 }
4765 __set_bit(FW_FLAGS_SPEED_UP, &fw_flags);
4766 break;
4767 case RTL_FW_PHY_VER:
4768 if (test_bit(FW_FLAGS_START, &fw_flags) ||
4769 test_bit(FW_FLAGS_NC, &fw_flags) ||
4770 test_bit(FW_FLAGS_NC1, &fw_flags) ||
4771 test_bit(FW_FLAGS_NC2, &fw_flags) ||
4772 test_bit(FW_FLAGS_UC2, &fw_flags) ||
4773 test_bit(FW_FLAGS_UC, &fw_flags) ||
4774 test_bit(FW_FLAGS_STOP, &fw_flags)) {
4775 dev_err(&tp->intf->dev, "Invalid order to set PHY version\n");
4776 goto fail;
4777 }
4778
4779 if (test_bit(FW_FLAGS_VER, &fw_flags)) {
4780 dev_err(&tp->intf->dev, "multiple PHY version encountered");
4781 goto fail;
4782 }
4783
4784 if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) {
4785 dev_err(&tp->intf->dev, "check PHY version failed\n");
4786 goto fail;
4787 }
4788 __set_bit(FW_FLAGS_VER, &fw_flags);
4789 break;
4790 default:
4791 dev_warn(&tp->intf->dev, "Unknown type %u is found\n",
4792 type);
4793 break;
4794 }
4795
4796 /* next block */
4797 i += ALIGN(__le32_to_cpu(block->length), 8);
4798 }
4799
4800fw_end:
4801 if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) {
4802 dev_err(&tp->intf->dev, "without PHY_STOP\n");
4803 goto fail;
4804 }
4805
4806 return 0;
4807fail:
4808 return ret;
4809}
4810
4811static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait)
4812{
4813 u32 len;
4814 u8 *data;
4815
4816 rtl_reset_ocp_base(tp);
4817
4818 if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) {
4819 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4820 return;
4821 }
4822
4823 len = __le32_to_cpu(phy->blk_hdr.length);
4824 len -= __le16_to_cpu(phy->fw_offset);
4825 data = (u8 *)phy + __le16_to_cpu(phy->fw_offset);
4826
4827 if (rtl_phy_patch_request(tp, true, wait))
4828 return;
4829
4830 while (len) {
4831 u32 ocp_data, size;
4832 int i;
4833
4834 if (len < 2048)
4835 size = len;
4836 else
4837 size = 2048;
4838
4839 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL);
4840 ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE;
4841 ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data);
4842
4843 generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB);
4844
4845 data += size;
4846 len -= size;
4847
4848 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL);
4849 ocp_data |= POL_GPHY_PATCH;
4850 ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data);
4851
4852 for (i = 0; i < 1000; i++) {
4853 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH))
4854 break;
4855 }
4856
4857 if (i == 1000) {
4858 dev_err(&tp->intf->dev, "ram code speedup mode timeout\n");
4859 break;
4860 }
4861 }
4862
4863 rtl_reset_ocp_base(tp);
4864
4865 rtl_phy_patch_request(tp, false, wait);
4866
4867 if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version))
4868 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4869 else
4870 dev_err(&tp->intf->dev, "ram code speedup mode fail\n");
4871}
4872
4873static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver)
4874{
4875 u16 ver_addr, ver;
4876
4877 ver_addr = __le16_to_cpu(phy_ver->ver.addr);
4878 ver = __le16_to_cpu(phy_ver->ver.data);
4879
4880 rtl_reset_ocp_base(tp);
4881
4882 if (sram_read(tp, ver_addr) >= ver) {
4883 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n");
4884 return 0;
4885 }
4886
4887 sram_write(tp, ver_addr, ver);
4888
4889 dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver);
4890
4891 return ver;
4892}
4893
4894static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix)
4895{
4896 u16 addr, data;
4897
4898 rtl_reset_ocp_base(tp);
4899
4900 addr = __le16_to_cpu(fix->setting.addr);
4901 data = ocp_reg_read(tp, addr);
4902
4903 switch (__le16_to_cpu(fix->bit_cmd)) {
4904 case FW_FIXUP_AND:
4905 data &= __le16_to_cpu(fix->setting.data);
4906 break;
4907 case FW_FIXUP_OR:
4908 data |= __le16_to_cpu(fix->setting.data);
4909 break;
4910 case FW_FIXUP_NOT:
4911 data &= ~__le16_to_cpu(fix->setting.data);
4912 break;
4913 case FW_FIXUP_XOR:
4914 data ^= __le16_to_cpu(fix->setting.data);
4915 break;
4916 default:
4917 return;
4918 }
4919
4920 ocp_reg_write(tp, addr, data);
4921
4922 dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data);
4923}
4924
4925static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy)
4926{
4927 __le16 *data;
4928 u32 length;
4929 int i, num;
4930
4931 rtl_reset_ocp_base(tp);
4932
4933 num = phy->pre_num;
4934 for (i = 0; i < num; i++)
4935 sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr),
4936 __le16_to_cpu(phy->pre_set[i].data));
4937
4938 length = __le32_to_cpu(phy->blk_hdr.length);
4939 length -= __le16_to_cpu(phy->fw_offset);
4940 num = length / 2;
4941 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
4942
4943 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
4944 for (i = 0; i < num; i++)
4945 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
4946
4947 num = phy->bp_num;
4948 for (i = 0; i < num; i++)
4949 sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data));
4950
4951 if (phy->bp_num && phy->bp_en.addr)
4952 sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data));
4953
4954 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4955}
4956
4957static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy)
4958{
4959 u16 mode_reg, bp_index;
4960 u32 length, i, num;
4961 __le16 *data;
4962
4963 rtl_reset_ocp_base(tp);
4964
4965 mode_reg = __le16_to_cpu(phy->mode_reg);
4966 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre));
4967 sram_write(tp, __le16_to_cpu(phy->ba_reg),
4968 __le16_to_cpu(phy->ba_data));
4969
4970 length = __le32_to_cpu(phy->blk_hdr.length);
4971 length -= __le16_to_cpu(phy->fw_offset);
4972 num = length / 2;
4973 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset));
4974
4975 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg));
4976 for (i = 0; i < num; i++)
4977 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i]));
4978
4979 sram_write(tp, __le16_to_cpu(phy->patch_en_addr),
4980 __le16_to_cpu(phy->patch_en_value));
4981
4982 bp_index = __le16_to_cpu(phy->bp_start);
4983 num = __le16_to_cpu(phy->bp_num);
4984 for (i = 0; i < num; i++) {
4985 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i]));
4986 bp_index += 2;
4987 }
4988
4989 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post));
4990
4991 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info);
4992}
4993
4994static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
4995{
4996 u16 bp_en_addr, bp_index, type, bp_num, fw_ver_reg;
4997 u32 length;
4998 u8 *data;
4999 int i;
5000
5001 switch (__le32_to_cpu(mac->blk_hdr.type)) {
5002 case RTL_FW_PLA:
5003 type = MCU_TYPE_PLA;
5004 break;
5005 case RTL_FW_USB:
5006 type = MCU_TYPE_USB;
5007 break;
5008 default:
5009 return;
5010 }
5011
5012 fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg);
5013 if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) {
5014 dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB");
5015 return;
5016 }
5017
5018 rtl_clear_bp(tp, type);
5019
5020 /* Enable backup/restore of MACDBG. This is required after clearing PLA
5021 * break points and before applying the PLA firmware.
5022 */
5023 if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA &&
5024 !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) {
5025 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM);
5026 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM);
5027 }
5028
5029 length = __le32_to_cpu(mac->blk_hdr.length);
5030 length -= __le16_to_cpu(mac->fw_offset);
5031
5032 data = (u8 *)mac;
5033 data += __le16_to_cpu(mac->fw_offset);
5034
5035 generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, data,
5036 type);
5037
5038 ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
5039 __le16_to_cpu(mac->bp_ba_value));
5040
5041 bp_index = __le16_to_cpu(mac->bp_start);
5042 bp_num = __le16_to_cpu(mac->bp_num);
5043 for (i = 0; i < bp_num; i++) {
5044 ocp_write_word(tp, type, bp_index, __le16_to_cpu(mac->bp[i]));
5045 bp_index += 2;
5046 }
5047
5048 bp_en_addr = __le16_to_cpu(mac->bp_en_addr);
5049 if (bp_en_addr)
5050 ocp_write_word(tp, type, bp_en_addr,
5051 __le16_to_cpu(mac->bp_en_value));
5052
5053 if (fw_ver_reg)
5054 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg,
5055 mac->fw_ver_data);
5056
5057 dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info);
5058}
5059
5060static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut)
5061{
5062 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5063 const struct firmware *fw;
5064 struct fw_header *fw_hdr;
5065 struct fw_phy_patch_key *key;
5066 u16 key_addr = 0;
5067 int i, patch_phy = 1;
5068
5069 if (IS_ERR_OR_NULL(rtl_fw->fw))
5070 return;
5071
5072 fw = rtl_fw->fw;
5073 fw_hdr = (struct fw_header *)fw->data;
5074
5075 if (rtl_fw->pre_fw)
5076 rtl_fw->pre_fw(tp);
5077
5078 for (i = offsetof(struct fw_header, blocks); i < fw->size;) {
5079 struct fw_block *block = (struct fw_block *)&fw->data[i];
5080
5081 switch (__le32_to_cpu(block->type)) {
5082 case RTL_FW_END:
5083 goto post_fw;
5084 case RTL_FW_PLA:
5085 case RTL_FW_USB:
5086 rtl8152_fw_mac_apply(tp, (struct fw_mac *)block);
5087 break;
5088 case RTL_FW_PHY_START:
5089 if (!patch_phy)
5090 break;
5091 key = (struct fw_phy_patch_key *)block;
5092 key_addr = __le16_to_cpu(key->key_reg);
5093 rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut);
5094 break;
5095 case RTL_FW_PHY_STOP:
5096 if (!patch_phy)
5097 break;
5098 WARN_ON(!key_addr);
5099 rtl_post_ram_code(tp, key_addr, !power_cut);
5100 break;
5101 case RTL_FW_PHY_NC:
5102 rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block);
5103 break;
5104 case RTL_FW_PHY_VER:
5105 patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block);
5106 break;
5107 case RTL_FW_PHY_UNION_NC:
5108 case RTL_FW_PHY_UNION_NC1:
5109 case RTL_FW_PHY_UNION_NC2:
5110 case RTL_FW_PHY_UNION_UC2:
5111 case RTL_FW_PHY_UNION_UC:
5112 case RTL_FW_PHY_UNION_MISC:
5113 if (patch_phy)
5114 rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block);
5115 break;
5116 case RTL_FW_PHY_FIXUP:
5117 if (patch_phy)
5118 rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block);
5119 break;
5120 case RTL_FW_PHY_SPEED_UP:
5121 rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut);
5122 break;
5123 default:
5124 break;
5125 }
5126
5127 i += ALIGN(__le32_to_cpu(block->length), 8);
5128 }
5129
5130post_fw:
5131 if (rtl_fw->post_fw)
5132 rtl_fw->post_fw(tp);
5133
5134 rtl_reset_ocp_base(tp);
5135 strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE);
5136 dev_info(&tp->intf->dev, "load %s successfully\n", rtl_fw->version);
5137}
5138
5139static void rtl8152_release_firmware(struct r8152 *tp)
5140{
5141 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5142
5143 if (!IS_ERR_OR_NULL(rtl_fw->fw)) {
5144 release_firmware(rtl_fw->fw);
5145 rtl_fw->fw = NULL;
5146 }
5147}
5148
5149static int rtl8152_request_firmware(struct r8152 *tp)
5150{
5151 struct rtl_fw *rtl_fw = &tp->rtl_fw;
5152 long rc;
5153
5154 if (rtl_fw->fw || !rtl_fw->fw_name) {
5155 dev_info(&tp->intf->dev, "skip request firmware\n");
5156 rc = 0;
5157 goto result;
5158 }
5159
5160 rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev);
5161 if (rc < 0)
5162 goto result;
5163
5164 rc = rtl8152_check_firmware(tp, rtl_fw);
5165 if (rc < 0)
5166 release_firmware(rtl_fw->fw);
5167
5168result:
5169 if (rc) {
5170 rtl_fw->fw = ERR_PTR(rc);
5171
5172 dev_warn(&tp->intf->dev,
5173 "unable to load firmware patch %s (%ld)\n",
5174 rtl_fw->fw_name, rc);
5175 }
5176
5177 return rc;
5178}
5179
5180static void r8152_aldps_en(struct r8152 *tp, bool enable)
5181{
5182 if (enable) {
5183 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
5184 LINKENA | DIS_SDSAVE);
5185 } else {
5186 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
5187 DIS_SDSAVE);
5188 msleep(20);
5189 }
5190}
5191
5192static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
5193{
5194 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
5195 ocp_reg_write(tp, OCP_EEE_DATA, reg);
5196 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
5197}
5198
5199static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
5200{
5201 u16 data;
5202
5203 r8152_mmd_indirect(tp, dev, reg);
5204 data = ocp_reg_read(tp, OCP_EEE_DATA);
5205 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5206
5207 return data;
5208}
5209
5210static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
5211{
5212 r8152_mmd_indirect(tp, dev, reg);
5213 ocp_reg_write(tp, OCP_EEE_DATA, data);
5214 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
5215}
5216
5217static void r8152_eee_en(struct r8152 *tp, bool enable)
5218{
5219 u16 config1, config2, config3;
5220 u32 ocp_data;
5221
5222 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5223 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
5224 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
5225 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
5226
5227 if (enable) {
5228 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5229 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
5230 config1 |= sd_rise_time(1);
5231 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
5232 config3 |= fast_snr(42);
5233 } else {
5234 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5235 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
5236 RX_QUIET_EN);
5237 config1 |= sd_rise_time(7);
5238 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
5239 config3 |= fast_snr(511);
5240 }
5241
5242 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5243 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
5244 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
5245 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
5246}
5247
5248static void r8153_eee_en(struct r8152 *tp, bool enable)
5249{
5250 u32 ocp_data;
5251 u16 config;
5252
5253 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
5254 config = ocp_reg_read(tp, OCP_EEE_CFG);
5255
5256 if (enable) {
5257 ocp_data |= EEE_RX_EN | EEE_TX_EN;
5258 config |= EEE10_EN;
5259 } else {
5260 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
5261 config &= ~EEE10_EN;
5262 }
5263
5264 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
5265 ocp_reg_write(tp, OCP_EEE_CFG, config);
5266
5267 tp->ups_info.eee = enable;
5268}
5269
5270static void r8156_eee_en(struct r8152 *tp, bool enable)
5271{
5272 u16 config;
5273
5274 r8153_eee_en(tp, enable);
5275
5276 config = ocp_reg_read(tp, OCP_EEE_ADV2);
5277
5278 if (enable)
5279 config |= MDIO_EEE_2_5GT;
5280 else
5281 config &= ~MDIO_EEE_2_5GT;
5282
5283 ocp_reg_write(tp, OCP_EEE_ADV2, config);
5284}
5285
5286static void rtl_eee_enable(struct r8152 *tp, bool enable)
5287{
5288 switch (tp->version) {
5289 case RTL_VER_01:
5290 case RTL_VER_02:
5291 case RTL_VER_07:
5292 if (enable) {
5293 r8152_eee_en(tp, true);
5294 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
5295 tp->eee_adv);
5296 } else {
5297 r8152_eee_en(tp, false);
5298 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
5299 }
5300 break;
5301 case RTL_VER_03:
5302 case RTL_VER_04:
5303 case RTL_VER_05:
5304 case RTL_VER_06:
5305 case RTL_VER_08:
5306 case RTL_VER_09:
5307 case RTL_VER_14:
5308 if (enable) {
5309 r8153_eee_en(tp, true);
5310 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5311 } else {
5312 r8153_eee_en(tp, false);
5313 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5314 }
5315 break;
5316 case RTL_VER_10:
5317 case RTL_VER_11:
5318 case RTL_VER_12:
5319 case RTL_VER_13:
5320 case RTL_VER_15:
5321 if (enable) {
5322 r8156_eee_en(tp, true);
5323 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
5324 } else {
5325 r8156_eee_en(tp, false);
5326 ocp_reg_write(tp, OCP_EEE_ADV, 0);
5327 }
5328 break;
5329 default:
5330 break;
5331 }
5332}
5333
5334static void r8152b_enable_fc(struct r8152 *tp)
5335{
5336 u16 anar;
5337
5338 anar = r8152_mdio_read(tp, MII_ADVERTISE);
5339 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
5340 r8152_mdio_write(tp, MII_ADVERTISE, anar);
5341
5342 tp->ups_info.flow_control = true;
5343}
5344
5345static void rtl8152_disable(struct r8152 *tp)
5346{
5347 r8152_aldps_en(tp, false);
5348 rtl_disable(tp);
5349 r8152_aldps_en(tp, true);
5350}
5351
5352static void r8152b_hw_phy_cfg(struct r8152 *tp)
5353{
5354 rtl8152_apply_firmware(tp, false);
5355 rtl_eee_enable(tp, tp->eee_en);
5356 r8152_aldps_en(tp, true);
5357 r8152b_enable_fc(tp);
5358
5359 set_bit(PHY_RESET, &tp->flags);
5360}
5361
5362static void wait_oob_link_list_ready(struct r8152 *tp)
5363{
5364 u32 ocp_data;
5365 int i;
5366
5367 for (i = 0; i < 1000; i++) {
5368 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5369 if (ocp_data & LINK_LIST_READY)
5370 break;
5371 usleep_range(1000, 2000);
5372 }
5373}
5374
5375static void r8156b_wait_loading_flash(struct r8152 *tp)
5376{
5377 if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
5378 !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
5379 int i;
5380
5381 for (i = 0; i < 100; i++) {
5382 if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
5383 break;
5384 usleep_range(1000, 2000);
5385 }
5386 }
5387}
5388
5389static void r8152b_exit_oob(struct r8152 *tp)
5390{
5391 u32 ocp_data;
5392
5393 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5394 ocp_data &= ~RCR_ACPT_ALL;
5395 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5396
5397 rxdy_gated_en(tp, true);
5398 r8153_teredo_off(tp);
5399 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
5400 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
5401
5402 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5403 ocp_data &= ~NOW_IS_OOB;
5404 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5405
5406 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5407 ocp_data &= ~MCU_BORW_EN;
5408 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5409
5410 wait_oob_link_list_ready(tp);
5411
5412 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5413 ocp_data |= RE_INIT_LL;
5414 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5415
5416 wait_oob_link_list_ready(tp);
5417
5418 rtl8152_nic_reset(tp);
5419
5420 /* rx share fifo credit full threshold */
5421 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5422
5423 if (tp->udev->speed == USB_SPEED_FULL ||
5424 tp->udev->speed == USB_SPEED_LOW) {
5425 /* rx share fifo credit near full threshold */
5426 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5427 RXFIFO_THR2_FULL);
5428 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5429 RXFIFO_THR3_FULL);
5430 } else {
5431 /* rx share fifo credit near full threshold */
5432 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
5433 RXFIFO_THR2_HIGH);
5434 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
5435 RXFIFO_THR3_HIGH);
5436 }
5437
5438 /* TX share fifo free credit full threshold */
5439 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5440
5441 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
5442 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
5443 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
5444 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
5445
5446 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5447
5448 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5449
5450 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5451 ocp_data |= TCR0_AUTO_FIFO;
5452 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5453}
5454
5455static void r8152b_enter_oob(struct r8152 *tp)
5456{
5457 u32 ocp_data;
5458
5459 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5460 ocp_data &= ~NOW_IS_OOB;
5461 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5462
5463 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5464 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
5465 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
5466
5467 rtl_disable(tp);
5468
5469 wait_oob_link_list_ready(tp);
5470
5471 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5472 ocp_data |= RE_INIT_LL;
5473 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5474
5475 wait_oob_link_list_ready(tp);
5476
5477 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
5478
5479 rtl_rx_vlan_en(tp, true);
5480
5481 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5482 ocp_data |= ALDPS_PROXY_MODE;
5483 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5484
5485 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5486 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5487 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5488
5489 rxdy_gated_en(tp, false);
5490
5491 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5492 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5493 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5494}
5495
5496static int r8153_pre_firmware_1(struct r8152 *tp)
5497{
5498 int i;
5499
5500 /* Wait till the WTD timer is ready. It would take at most 104 ms. */
5501 for (i = 0; i < 104; i++) {
5502 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL);
5503
5504 if (!(ocp_data & WTD1_EN))
5505 break;
5506 usleep_range(1000, 2000);
5507 }
5508
5509 return 0;
5510}
5511
5512static int r8153_post_firmware_1(struct r8152 *tp)
5513{
5514 /* set USB_BP_4 to support USB_SPEED_SUPER only */
5515 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER)
5516 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY);
5517
5518 /* reset UPHY timer to 36 ms */
5519 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5520
5521 return 0;
5522}
5523
5524static int r8153_pre_firmware_2(struct r8152 *tp)
5525{
5526 u32 ocp_data;
5527
5528 r8153_pre_firmware_1(tp);
5529
5530 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5531 ocp_data &= ~FW_FIX_SUSPEND;
5532 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5533
5534 return 0;
5535}
5536
5537static int r8153_post_firmware_2(struct r8152 *tp)
5538{
5539 u32 ocp_data;
5540
5541 /* enable bp0 if support USB_SPEED_SUPER only */
5542 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) {
5543 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5544 ocp_data |= BIT(0);
5545 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5546 }
5547
5548 /* reset UPHY timer to 36 ms */
5549 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16);
5550
5551 /* enable U3P3 check, set the counter to 4 */
5552 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4);
5553
5554 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0);
5555 ocp_data |= FW_FIX_SUSPEND;
5556 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data);
5557
5558 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5559 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5560 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5561
5562 return 0;
5563}
5564
5565static int r8153_post_firmware_3(struct r8152 *tp)
5566{
5567 u32 ocp_data;
5568
5569 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
5570 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
5571 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
5572
5573 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5574 ocp_data |= FW_IP_RESET_EN;
5575 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5576
5577 return 0;
5578}
5579
5580static int r8153b_pre_firmware_1(struct r8152 *tp)
5581{
5582 /* enable fc timer and set timer to 1 second. */
5583 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
5584 CTRL_TIMER_EN | (1000 / 8));
5585
5586 return 0;
5587}
5588
5589static int r8153b_post_firmware_1(struct r8152 *tp)
5590{
5591 u32 ocp_data;
5592
5593 /* enable bp0 for RTL8153-BND */
5594 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1);
5595 if (ocp_data & BND_MASK) {
5596 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN);
5597 ocp_data |= BIT(0);
5598 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data);
5599 }
5600
5601 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5602 ocp_data |= FLOW_CTRL_PATCH_OPT;
5603 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5604
5605 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5606 ocp_data |= FC_PATCH_TASK;
5607 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5608
5609 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5610 ocp_data |= FW_IP_RESET_EN;
5611 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5612
5613 return 0;
5614}
5615
5616static int r8153c_post_firmware_1(struct r8152 *tp)
5617{
5618 u32 ocp_data;
5619
5620 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
5621 ocp_data |= FLOW_CTRL_PATCH_2;
5622 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
5623
5624 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
5625 ocp_data |= FC_PATCH_TASK;
5626 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
5627
5628 return 0;
5629}
5630
5631static int r8156a_post_firmware_1(struct r8152 *tp)
5632{
5633 u32 ocp_data;
5634
5635 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1);
5636 ocp_data |= FW_IP_RESET_EN;
5637 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data);
5638
5639 /* Modify U3PHY parameter for compatibility issue */
5640 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e);
5641 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9);
5642
5643 return 0;
5644}
5645
5646static void r8153_aldps_en(struct r8152 *tp, bool enable)
5647{
5648 u16 data;
5649
5650 data = ocp_reg_read(tp, OCP_POWER_CFG);
5651 if (enable) {
5652 data |= EN_ALDPS;
5653 ocp_reg_write(tp, OCP_POWER_CFG, data);
5654 } else {
5655 int i;
5656
5657 data &= ~EN_ALDPS;
5658 ocp_reg_write(tp, OCP_POWER_CFG, data);
5659 for (i = 0; i < 20; i++) {
5660 usleep_range(1000, 2000);
5661 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
5662 break;
5663 }
5664 }
5665
5666 tp->ups_info.aldps = enable;
5667}
5668
5669static void r8153_hw_phy_cfg(struct r8152 *tp)
5670{
5671 u32 ocp_data;
5672 u16 data;
5673
5674 /* disable ALDPS before updating the PHY parameters */
5675 r8153_aldps_en(tp, false);
5676
5677 /* disable EEE before updating the PHY parameters */
5678 rtl_eee_enable(tp, false);
5679
5680 rtl8152_apply_firmware(tp, false);
5681
5682 if (tp->version == RTL_VER_03) {
5683 data = ocp_reg_read(tp, OCP_EEE_CFG);
5684 data &= ~CTAP_SHORT_EN;
5685 ocp_reg_write(tp, OCP_EEE_CFG, data);
5686 }
5687
5688 data = ocp_reg_read(tp, OCP_POWER_CFG);
5689 data |= EEE_CLKDIV_EN;
5690 ocp_reg_write(tp, OCP_POWER_CFG, data);
5691
5692 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5693 data |= EN_10M_BGOFF;
5694 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5695 data = ocp_reg_read(tp, OCP_POWER_CFG);
5696 data |= EN_10M_PLLOFF;
5697 ocp_reg_write(tp, OCP_POWER_CFG, data);
5698 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
5699
5700 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5701 ocp_data |= PFM_PWM_SWITCH;
5702 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5703
5704 /* Enable LPF corner auto tune */
5705 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
5706
5707 /* Adjust 10M Amplitude */
5708 sram_write(tp, SRAM_10M_AMP1, 0x00af);
5709 sram_write(tp, SRAM_10M_AMP2, 0x0208);
5710
5711 if (tp->eee_en)
5712 rtl_eee_enable(tp, true);
5713
5714 r8153_aldps_en(tp, true);
5715 r8152b_enable_fc(tp);
5716
5717 switch (tp->version) {
5718 case RTL_VER_03:
5719 case RTL_VER_04:
5720 break;
5721 case RTL_VER_05:
5722 case RTL_VER_06:
5723 default:
5724 r8153_u2p3en(tp, true);
5725 break;
5726 }
5727
5728 set_bit(PHY_RESET, &tp->flags);
5729}
5730
5731static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
5732{
5733 u32 ocp_data;
5734
5735 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
5736 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
5737 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */
5738 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
5739
5740 return ocp_data;
5741}
5742
5743static void r8153b_hw_phy_cfg(struct r8152 *tp)
5744{
5745 u32 ocp_data;
5746 u16 data;
5747
5748 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
5749 if (ocp_data & PCUT_STATUS) {
5750 ocp_data &= ~PCUT_STATUS;
5751 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
5752 }
5753
5754 /* disable ALDPS before updating the PHY parameters */
5755 r8153_aldps_en(tp, false);
5756
5757 /* disable EEE before updating the PHY parameters */
5758 rtl_eee_enable(tp, false);
5759
5760 /* U1/U2/L1 idle timer. 500 us */
5761 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
5762
5763 data = r8153_phy_status(tp, 0);
5764
5765 switch (data) {
5766 case PHY_STAT_PWRDN:
5767 case PHY_STAT_EXT_INIT:
5768 rtl8152_apply_firmware(tp, true);
5769
5770 data = r8152_mdio_read(tp, MII_BMCR);
5771 data &= ~BMCR_PDOWN;
5772 r8152_mdio_write(tp, MII_BMCR, data);
5773 break;
5774 case PHY_STAT_LAN_ON:
5775 default:
5776 rtl8152_apply_firmware(tp, false);
5777 break;
5778 }
5779
5780 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
5781
5782 data = sram_read(tp, SRAM_GREEN_CFG);
5783 data |= R_TUNE_EN;
5784 sram_write(tp, SRAM_GREEN_CFG, data);
5785 data = ocp_reg_read(tp, OCP_NCTL_CFG);
5786 data |= PGA_RETURN_EN;
5787 ocp_reg_write(tp, OCP_NCTL_CFG, data);
5788
5789 /* ADC Bias Calibration:
5790 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
5791 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
5792 * ADC ioffset.
5793 */
5794 ocp_data = r8152_efuse_read(tp, 0x7d);
5795 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
5796 if (data != 0xffff)
5797 ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
5798
5799 /* ups mode tx-link-pulse timing adjustment:
5800 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
5801 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
5802 */
5803 ocp_data = ocp_reg_read(tp, 0xc426);
5804 ocp_data &= 0x3fff;
5805 if (ocp_data) {
5806 u32 swr_cnt_1ms_ini;
5807
5808 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
5809 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
5810 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
5811 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
5812 }
5813
5814 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
5815 ocp_data |= PFM_PWM_SWITCH;
5816 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
5817
5818 /* Advnace EEE */
5819 if (!rtl_phy_patch_request(tp, true, true)) {
5820 data = ocp_reg_read(tp, OCP_POWER_CFG);
5821 data |= EEE_CLKDIV_EN;
5822 ocp_reg_write(tp, OCP_POWER_CFG, data);
5823 tp->ups_info.eee_ckdiv = true;
5824
5825 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
5826 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
5827 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
5828 tp->ups_info.eee_cmod_lv = true;
5829 tp->ups_info._10m_ckdiv = true;
5830 tp->ups_info.eee_plloff_giga = true;
5831
5832 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
5833 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
5834 tp->ups_info._250m_ckdiv = true;
5835
5836 rtl_phy_patch_request(tp, false, true);
5837 }
5838
5839 if (tp->eee_en)
5840 rtl_eee_enable(tp, true);
5841
5842 r8153_aldps_en(tp, true);
5843 r8152b_enable_fc(tp);
5844
5845 set_bit(PHY_RESET, &tp->flags);
5846}
5847
5848static void r8153c_hw_phy_cfg(struct r8152 *tp)
5849{
5850 r8153b_hw_phy_cfg(tp);
5851
5852 tp->ups_info.r_tune = true;
5853}
5854
5855static void rtl8153_change_mtu(struct r8152 *tp)
5856{
5857 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
5858 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
5859}
5860
5861static void r8153_first_init(struct r8152 *tp)
5862{
5863 u32 ocp_data;
5864
5865 rxdy_gated_en(tp, true);
5866 r8153_teredo_off(tp);
5867
5868 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5869 ocp_data &= ~RCR_ACPT_ALL;
5870 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5871
5872 rtl8152_nic_reset(tp);
5873 rtl_reset_bmu(tp);
5874
5875 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5876 ocp_data &= ~NOW_IS_OOB;
5877 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5878
5879 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5880 ocp_data &= ~MCU_BORW_EN;
5881 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5882
5883 wait_oob_link_list_ready(tp);
5884
5885 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5886 ocp_data |= RE_INIT_LL;
5887 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5888
5889 wait_oob_link_list_ready(tp);
5890
5891 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
5892
5893 rtl8153_change_mtu(tp);
5894
5895 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
5896 ocp_data |= TCR0_AUTO_FIFO;
5897 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
5898
5899 rtl8152_nic_reset(tp);
5900
5901 /* rx share fifo credit full threshold */
5902 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
5903 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
5904 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
5905 /* TX share fifo free credit full threshold */
5906 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
5907}
5908
5909static void r8153_enter_oob(struct r8152 *tp)
5910{
5911 u32 ocp_data;
5912
5913 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5914 ocp_data &= ~NOW_IS_OOB;
5915 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5916
5917 /* RX FIFO settings for OOB */
5918 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
5919 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
5920 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
5921
5922 rtl_disable(tp);
5923 rtl_reset_bmu(tp);
5924
5925 wait_oob_link_list_ready(tp);
5926
5927 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5928 ocp_data |= RE_INIT_LL;
5929 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5930
5931 wait_oob_link_list_ready(tp);
5932
5933 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);
5934 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
5935
5936 switch (tp->version) {
5937 case RTL_VER_03:
5938 case RTL_VER_04:
5939 case RTL_VER_05:
5940 case RTL_VER_06:
5941 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
5942 ocp_data &= ~TEREDO_WAKE_MASK;
5943 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
5944 break;
5945
5946 case RTL_VER_08:
5947 case RTL_VER_09:
5948 case RTL_VER_14:
5949 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
5950 * type. Set it to zero. bits[7:0] are the W1C bits about
5951 * the events. Set them to all 1 to clear them.
5952 */
5953 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
5954 break;
5955
5956 default:
5957 break;
5958 }
5959
5960 rtl_rx_vlan_en(tp, true);
5961
5962 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
5963 ocp_data |= ALDPS_PROXY_MODE;
5964 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
5965
5966 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
5967 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
5968 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
5969
5970 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
5971 ocp_data |= MCU_BORW_EN;
5972 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
5973
5974 rxdy_gated_en(tp, false);
5975
5976 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
5977 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
5978 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
5979}
5980
5981static void rtl8153_disable(struct r8152 *tp)
5982{
5983 r8153_aldps_en(tp, false);
5984 rtl_disable(tp);
5985 rtl_reset_bmu(tp);
5986 r8153_aldps_en(tp, true);
5987}
5988
5989static int rtl8156_enable(struct r8152 *tp)
5990{
5991 u32 ocp_data;
5992 u16 speed;
5993
5994 if (test_bit(RTL8152_UNPLUG, &tp->flags))
5995 return -ENODEV;
5996
5997 set_tx_qlen(tp);
5998 rtl_set_eee_plus(tp);
5999 r8153_set_rx_early_timeout(tp);
6000 r8153_set_rx_early_size(tp);
6001
6002 speed = rtl8152_get_speed(tp);
6003 rtl_set_ifg(tp, speed);
6004
6005 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6006 if (speed & _2500bps)
6007 ocp_data &= ~IDLE_SPDWN_EN;
6008 else
6009 ocp_data |= IDLE_SPDWN_EN;
6010 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
6011
6012 if (speed & _1000bps)
6013 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);
6014 else if (speed & _500bps)
6015 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);
6016
6017 if (tp->udev->speed == USB_SPEED_HIGH) {
6018 /* USB 0xb45e[3:0] l1_nyet_hird */
6019 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6020 ocp_data &= ~0xf;
6021 if (is_flow_control(speed))
6022 ocp_data |= 0xf;
6023 else
6024 ocp_data |= 0x1;
6025 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6026 }
6027
6028 return rtl_enable(tp);
6029}
6030
6031static int rtl8156b_enable(struct r8152 *tp)
6032{
6033 u32 ocp_data;
6034 u16 speed;
6035
6036 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6037 return -ENODEV;
6038
6039 set_tx_qlen(tp);
6040 rtl_set_eee_plus(tp);
6041
6042 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
6043 ocp_data &= ~RX_AGGR_NUM_MASK;
6044 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);
6045
6046 r8153_set_rx_early_timeout(tp);
6047 r8153_set_rx_early_size(tp);
6048
6049 speed = rtl8152_get_speed(tp);
6050 rtl_set_ifg(tp, speed);
6051
6052 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
6053 if (speed & _2500bps)
6054 ocp_data &= ~IDLE_SPDWN_EN;
6055 else
6056 ocp_data |= IDLE_SPDWN_EN;
6057 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
6058
6059 if (tp->udev->speed == USB_SPEED_HIGH) {
6060 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
6061 ocp_data &= ~0xf;
6062 if (is_flow_control(speed))
6063 ocp_data |= 0xf;
6064 else
6065 ocp_data |= 0x1;
6066 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
6067 }
6068
6069 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
6070 ocp_data &= ~FC_PATCH_TASK;
6071 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6072 usleep_range(1000, 2000);
6073 ocp_data |= FC_PATCH_TASK;
6074 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
6075
6076 return rtl_enable(tp);
6077}
6078
6079static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
6080 u32 advertising)
6081{
6082 u16 bmcr;
6083 int ret = 0;
6084
6085 if (autoneg == AUTONEG_DISABLE) {
6086 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL)
6087 return -EINVAL;
6088
6089 switch (speed) {
6090 case SPEED_10:
6091 bmcr = BMCR_SPEED10;
6092 if (duplex == DUPLEX_FULL) {
6093 bmcr |= BMCR_FULLDPLX;
6094 tp->ups_info.speed_duplex = FORCE_10M_FULL;
6095 } else {
6096 tp->ups_info.speed_duplex = FORCE_10M_HALF;
6097 }
6098 break;
6099 case SPEED_100:
6100 bmcr = BMCR_SPEED100;
6101 if (duplex == DUPLEX_FULL) {
6102 bmcr |= BMCR_FULLDPLX;
6103 tp->ups_info.speed_duplex = FORCE_100M_FULL;
6104 } else {
6105 tp->ups_info.speed_duplex = FORCE_100M_HALF;
6106 }
6107 break;
6108 case SPEED_1000:
6109 if (tp->mii.supports_gmii) {
6110 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX;
6111 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6112 break;
6113 }
6114 fallthrough;
6115 default:
6116 ret = -EINVAL;
6117 goto out;
6118 }
6119
6120 if (duplex == DUPLEX_FULL)
6121 tp->mii.full_duplex = 1;
6122 else
6123 tp->mii.full_duplex = 0;
6124
6125 tp->mii.force_media = 1;
6126 } else {
6127 u16 orig, new1;
6128 u32 support;
6129
6130 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
6131 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
6132
6133 if (tp->mii.supports_gmii) {
6134 support |= RTL_ADVERTISED_1000_FULL;
6135
6136 if (tp->support_2500full)
6137 support |= RTL_ADVERTISED_2500_FULL;
6138 }
6139
6140 if (!(advertising & support))
6141 return -EINVAL;
6142
6143 orig = r8152_mdio_read(tp, MII_ADVERTISE);
6144 new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
6145 ADVERTISE_100HALF | ADVERTISE_100FULL);
6146 if (advertising & RTL_ADVERTISED_10_HALF) {
6147 new1 |= ADVERTISE_10HALF;
6148 tp->ups_info.speed_duplex = NWAY_10M_HALF;
6149 }
6150 if (advertising & RTL_ADVERTISED_10_FULL) {
6151 new1 |= ADVERTISE_10FULL;
6152 tp->ups_info.speed_duplex = NWAY_10M_FULL;
6153 }
6154
6155 if (advertising & RTL_ADVERTISED_100_HALF) {
6156 new1 |= ADVERTISE_100HALF;
6157 tp->ups_info.speed_duplex = NWAY_100M_HALF;
6158 }
6159 if (advertising & RTL_ADVERTISED_100_FULL) {
6160 new1 |= ADVERTISE_100FULL;
6161 tp->ups_info.speed_duplex = NWAY_100M_FULL;
6162 }
6163
6164 if (orig != new1) {
6165 r8152_mdio_write(tp, MII_ADVERTISE, new1);
6166 tp->mii.advertising = new1;
6167 }
6168
6169 if (tp->mii.supports_gmii) {
6170 orig = r8152_mdio_read(tp, MII_CTRL1000);
6171 new1 = orig & ~(ADVERTISE_1000FULL |
6172 ADVERTISE_1000HALF);
6173
6174 if (advertising & RTL_ADVERTISED_1000_FULL) {
6175 new1 |= ADVERTISE_1000FULL;
6176 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
6177 }
6178
6179 if (orig != new1)
6180 r8152_mdio_write(tp, MII_CTRL1000, new1);
6181 }
6182
6183 if (tp->support_2500full) {
6184 orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
6185 new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
6186
6187 if (advertising & RTL_ADVERTISED_2500_FULL) {
6188 new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
6189 tp->ups_info.speed_duplex = NWAY_2500M_FULL;
6190 }
6191
6192 if (orig != new1)
6193 ocp_reg_write(tp, OCP_10GBT_CTRL, new1);
6194 }
6195
6196 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
6197
6198 tp->mii.force_media = 0;
6199 }
6200
6201 if (test_and_clear_bit(PHY_RESET, &tp->flags))
6202 bmcr |= BMCR_RESET;
6203
6204 r8152_mdio_write(tp, MII_BMCR, bmcr);
6205
6206 if (bmcr & BMCR_RESET) {
6207 int i;
6208
6209 for (i = 0; i < 50; i++) {
6210 msleep(20);
6211 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
6212 break;
6213 }
6214 }
6215
6216out:
6217 return ret;
6218}
6219
6220static void rtl8152_up(struct r8152 *tp)
6221{
6222 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6223 return;
6224
6225 r8152_aldps_en(tp, false);
6226 r8152b_exit_oob(tp);
6227 r8152_aldps_en(tp, true);
6228}
6229
6230static void rtl8152_down(struct r8152 *tp)
6231{
6232 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6233 rtl_drop_queued_tx(tp);
6234 return;
6235 }
6236
6237 r8152_power_cut_en(tp, false);
6238 r8152_aldps_en(tp, false);
6239 r8152b_enter_oob(tp);
6240 r8152_aldps_en(tp, true);
6241}
6242
6243static void rtl8153_up(struct r8152 *tp)
6244{
6245 u32 ocp_data;
6246
6247 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6248 return;
6249
6250 r8153_u1u2en(tp, false);
6251 r8153_u2p3en(tp, false);
6252 r8153_aldps_en(tp, false);
6253 r8153_first_init(tp);
6254
6255 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6256 ocp_data |= LANWAKE_CLR_EN;
6257 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6258
6259 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
6260 ocp_data &= ~LANWAKE_PIN;
6261 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
6262
6263 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1);
6264 ocp_data &= ~DELAY_PHY_PWR_CHG;
6265 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data);
6266
6267 r8153_aldps_en(tp, true);
6268
6269 switch (tp->version) {
6270 case RTL_VER_03:
6271 case RTL_VER_04:
6272 break;
6273 case RTL_VER_05:
6274 case RTL_VER_06:
6275 default:
6276 r8153_u2p3en(tp, true);
6277 break;
6278 }
6279
6280 r8153_u1u2en(tp, true);
6281}
6282
6283static void rtl8153_down(struct r8152 *tp)
6284{
6285 u32 ocp_data;
6286
6287 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6288 rtl_drop_queued_tx(tp);
6289 return;
6290 }
6291
6292 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
6293 ocp_data &= ~LANWAKE_CLR_EN;
6294 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
6295
6296 r8153_u1u2en(tp, false);
6297 r8153_u2p3en(tp, false);
6298 r8153_power_cut_en(tp, false);
6299 r8153_aldps_en(tp, false);
6300 r8153_enter_oob(tp);
6301 r8153_aldps_en(tp, true);
6302}
6303
6304static void rtl8153b_up(struct r8152 *tp)
6305{
6306 u32 ocp_data;
6307
6308 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6309 return;
6310
6311 r8153b_u1u2en(tp, false);
6312 r8153_u2p3en(tp, false);
6313 r8153_aldps_en(tp, false);
6314
6315 r8153_first_init(tp);
6316 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6317
6318 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6319 ocp_data &= ~PLA_MCU_SPDWN_EN;
6320 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6321
6322 r8153_aldps_en(tp, true);
6323
6324 if (tp->udev->speed >= USB_SPEED_SUPER)
6325 r8153b_u1u2en(tp, true);
6326}
6327
6328static void rtl8153b_down(struct r8152 *tp)
6329{
6330 u32 ocp_data;
6331
6332 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6333 rtl_drop_queued_tx(tp);
6334 return;
6335 }
6336
6337 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6338 ocp_data |= PLA_MCU_SPDWN_EN;
6339 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6340
6341 r8153b_u1u2en(tp, false);
6342 r8153_u2p3en(tp, false);
6343 r8153b_power_cut_en(tp, false);
6344 r8153_aldps_en(tp, false);
6345 r8153_enter_oob(tp);
6346 r8153_aldps_en(tp, true);
6347}
6348
6349static void rtl8153c_change_mtu(struct r8152 *tp)
6350{
6351 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
6352 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);
6353
6354 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6355
6356 /* Adjust the tx fifo free credit full threshold, otherwise
6357 * the fifo would be too small to send a jumbo frame packet.
6358 */
6359 if (tp->netdev->mtu < 8000)
6360 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);
6361 else
6362 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);
6363}
6364
6365static void rtl8153c_up(struct r8152 *tp)
6366{
6367 u32 ocp_data;
6368
6369 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6370 return;
6371
6372 r8153b_u1u2en(tp, false);
6373 r8153_u2p3en(tp, false);
6374 r8153_aldps_en(tp, false);
6375
6376 rxdy_gated_en(tp, true);
6377 r8153_teredo_off(tp);
6378
6379 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6380 ocp_data &= ~RCR_ACPT_ALL;
6381 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6382
6383 rtl8152_nic_reset(tp);
6384 rtl_reset_bmu(tp);
6385
6386 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6387 ocp_data &= ~NOW_IS_OOB;
6388 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6389
6390 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6391 ocp_data &= ~MCU_BORW_EN;
6392 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6393
6394 wait_oob_link_list_ready(tp);
6395
6396 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6397 ocp_data |= RE_INIT_LL;
6398 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6399
6400 wait_oob_link_list_ready(tp);
6401
6402 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6403
6404 rtl8153c_change_mtu(tp);
6405
6406 rtl8152_nic_reset(tp);
6407
6408 /* rx share fifo credit full threshold */
6409 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);
6410 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);
6411 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
6412 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
6413
6414 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
6415
6416 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
6417
6418 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
6419 ocp_data |= BIT(8);
6420 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
6421
6422 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
6423
6424 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6425 ocp_data &= ~PLA_MCU_SPDWN_EN;
6426 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6427
6428 r8153_aldps_en(tp, true);
6429 r8153b_u1u2en(tp, true);
6430}
6431
6432static inline u32 fc_pause_on_auto(struct r8152 *tp)
6433{
6434 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
6435}
6436
6437static inline u32 fc_pause_off_auto(struct r8152 *tp)
6438{
6439 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
6440}
6441
6442static void r8156_fc_parameter(struct r8152 *tp)
6443{
6444 u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
6445 u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
6446
6447 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);
6448 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);
6449}
6450
6451static void rtl8156_change_mtu(struct r8152 *tp)
6452{
6453 u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
6454
6455 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);
6456 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
6457 r8156_fc_parameter(tp);
6458
6459 /* TX share fifo free credit full threshold */
6460 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
6461 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
6462 ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
6463}
6464
6465static void rtl8156_up(struct r8152 *tp)
6466{
6467 u32 ocp_data;
6468
6469 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6470 return;
6471
6472 r8153b_u1u2en(tp, false);
6473 r8153_u2p3en(tp, false);
6474 r8153_aldps_en(tp, false);
6475
6476 rxdy_gated_en(tp, true);
6477 r8153_teredo_off(tp);
6478
6479 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6480 ocp_data &= ~RCR_ACPT_ALL;
6481 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6482
6483 rtl8152_nic_reset(tp);
6484 rtl_reset_bmu(tp);
6485
6486 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6487 ocp_data &= ~NOW_IS_OOB;
6488 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6489
6490 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6491 ocp_data &= ~MCU_BORW_EN;
6492 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6493
6494 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
6495
6496 rtl8156_change_mtu(tp);
6497
6498 switch (tp->version) {
6499 case RTL_TEST_01:
6500 case RTL_VER_10:
6501 case RTL_VER_11:
6502 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
6503 ocp_data |= ACT_ODMA;
6504 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
6505 break;
6506 default:
6507 break;
6508 }
6509
6510 /* share FIFO settings */
6511 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
6512 ocp_data &= ~RXFIFO_FULL_MASK;
6513 ocp_data |= 0x08;
6514 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);
6515
6516 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6517 ocp_data &= ~PLA_MCU_SPDWN_EN;
6518 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6519
6520 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
6521 ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
6522 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);
6523
6524 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);
6525
6526 if (tp->saved_wolopts != __rtl_get_wol(tp)) {
6527 netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
6528 __rtl_set_wol(tp, tp->saved_wolopts);
6529 }
6530
6531 r8153_aldps_en(tp, true);
6532 r8153_u2p3en(tp, true);
6533
6534 if (tp->udev->speed >= USB_SPEED_SUPER)
6535 r8153b_u1u2en(tp, true);
6536}
6537
6538static void rtl8156_down(struct r8152 *tp)
6539{
6540 u32 ocp_data;
6541
6542 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
6543 rtl_drop_queued_tx(tp);
6544 return;
6545 }
6546
6547 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
6548 ocp_data |= PLA_MCU_SPDWN_EN;
6549 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
6550
6551 r8153b_u1u2en(tp, false);
6552 r8153_u2p3en(tp, false);
6553 r8153b_power_cut_en(tp, false);
6554 r8153_aldps_en(tp, false);
6555
6556 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6557 ocp_data &= ~NOW_IS_OOB;
6558 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6559
6560 /* RX FIFO settings for OOB */
6561 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 64 / 16);
6562 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 1024 / 16);
6563 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 4096 / 16);
6564
6565 rtl_disable(tp);
6566 rtl_reset_bmu(tp);
6567
6568 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522);
6569 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT);
6570
6571 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
6572 * type. Set it to zero. bits[7:0] are the W1C bits about
6573 * the events. Set them to all 1 to clear them.
6574 */
6575 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
6576
6577 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
6578 ocp_data |= NOW_IS_OOB;
6579 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
6580
6581 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
6582 ocp_data |= MCU_BORW_EN;
6583 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
6584
6585 rtl_rx_vlan_en(tp, true);
6586 rxdy_gated_en(tp, false);
6587
6588 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
6589 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
6590 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
6591
6592 r8153_aldps_en(tp, true);
6593}
6594
6595static bool rtl8152_in_nway(struct r8152 *tp)
6596{
6597 u16 nway_state;
6598
6599 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
6600 tp->ocp_base = 0x2000;
6601 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
6602 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
6603
6604 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
6605 if (nway_state & 0xc000)
6606 return false;
6607 else
6608 return true;
6609}
6610
6611static bool rtl8153_in_nway(struct r8152 *tp)
6612{
6613 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
6614
6615 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
6616 return false;
6617 else
6618 return true;
6619}
6620
6621static void r8156_mdio_force_mode(struct r8152 *tp)
6622{
6623 u16 data;
6624
6625 /* Select force mode through 0xa5b4 bit 15
6626 * 0: MDIO force mode
6627 * 1: MMD force mode
6628 */
6629 data = ocp_reg_read(tp, 0xa5b4);
6630 if (data & BIT(15)) {
6631 data &= ~BIT(15);
6632 ocp_reg_write(tp, 0xa5b4, data);
6633 }
6634}
6635
6636static void set_carrier(struct r8152 *tp)
6637{
6638 struct net_device *netdev = tp->netdev;
6639 struct napi_struct *napi = &tp->napi;
6640 u16 speed;
6641
6642 speed = rtl8152_get_speed(tp);
6643
6644 if (speed & LINK_STATUS) {
6645 if (!netif_carrier_ok(netdev)) {
6646 tp->rtl_ops.enable(tp);
6647 netif_stop_queue(netdev);
6648 napi_disable(napi);
6649 netif_carrier_on(netdev);
6650 rtl_start_rx(tp);
6651 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
6652 _rtl8152_set_rx_mode(netdev);
6653 napi_enable(napi);
6654 netif_wake_queue(netdev);
6655 netif_info(tp, link, netdev, "carrier on\n");
6656 } else if (netif_queue_stopped(netdev) &&
6657 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
6658 netif_wake_queue(netdev);
6659 }
6660 } else {
6661 if (netif_carrier_ok(netdev)) {
6662 netif_carrier_off(netdev);
6663 tasklet_disable(&tp->tx_tl);
6664 napi_disable(napi);
6665 tp->rtl_ops.disable(tp);
6666 napi_enable(napi);
6667 tasklet_enable(&tp->tx_tl);
6668 netif_info(tp, link, netdev, "carrier off\n");
6669 }
6670 }
6671}
6672
6673static void rtl_work_func_t(struct work_struct *work)
6674{
6675 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
6676
6677 /* If the device is unplugged or !netif_running(), the workqueue
6678 * doesn't need to wake the device, and could return directly.
6679 */
6680 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
6681 return;
6682
6683 if (usb_autopm_get_interface(tp->intf) < 0)
6684 return;
6685
6686 if (!test_bit(WORK_ENABLE, &tp->flags))
6687 goto out1;
6688
6689 if (!mutex_trylock(&tp->control)) {
6690 schedule_delayed_work(&tp->schedule, 0);
6691 goto out1;
6692 }
6693
6694 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
6695 set_carrier(tp);
6696
6697 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
6698 _rtl8152_set_rx_mode(tp->netdev);
6699
6700 /* don't schedule tasket before linking */
6701 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) &&
6702 netif_carrier_ok(tp->netdev))
6703 tasklet_schedule(&tp->tx_tl);
6704
6705 if (test_and_clear_bit(RX_EPROTO, &tp->flags) &&
6706 !list_empty(&tp->rx_done))
6707 napi_schedule(&tp->napi);
6708
6709 mutex_unlock(&tp->control);
6710
6711out1:
6712 usb_autopm_put_interface(tp->intf);
6713}
6714
6715static void rtl_hw_phy_work_func_t(struct work_struct *work)
6716{
6717 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
6718
6719 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6720 return;
6721
6722 if (usb_autopm_get_interface(tp->intf) < 0)
6723 return;
6724
6725 mutex_lock(&tp->control);
6726
6727 if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) {
6728 tp->rtl_fw.retry = false;
6729 tp->rtl_fw.fw = NULL;
6730
6731 /* Delay execution in case request_firmware() is not ready yet.
6732 */
6733 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10);
6734 goto ignore_once;
6735 }
6736
6737 tp->rtl_ops.hw_phy_cfg(tp);
6738
6739 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex,
6740 tp->advertising);
6741
6742ignore_once:
6743 mutex_unlock(&tp->control);
6744
6745 usb_autopm_put_interface(tp->intf);
6746}
6747
6748#ifdef CONFIG_PM_SLEEP
6749static int rtl_notifier(struct notifier_block *nb, unsigned long action,
6750 void *data)
6751{
6752 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
6753
6754 switch (action) {
6755 case PM_HIBERNATION_PREPARE:
6756 case PM_SUSPEND_PREPARE:
6757 usb_autopm_get_interface(tp->intf);
6758 break;
6759
6760 case PM_POST_HIBERNATION:
6761 case PM_POST_SUSPEND:
6762 usb_autopm_put_interface(tp->intf);
6763 break;
6764
6765 case PM_POST_RESTORE:
6766 case PM_RESTORE_PREPARE:
6767 default:
6768 break;
6769 }
6770
6771 return NOTIFY_DONE;
6772}
6773#endif
6774
6775static int rtl8152_open(struct net_device *netdev)
6776{
6777 struct r8152 *tp = netdev_priv(netdev);
6778 int res = 0;
6779
6780 if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) {
6781 cancel_delayed_work_sync(&tp->hw_phy_work);
6782 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work);
6783 }
6784
6785 res = alloc_all_mem(tp);
6786 if (res)
6787 goto out;
6788
6789 res = usb_autopm_get_interface(tp->intf);
6790 if (res < 0)
6791 goto out_free;
6792
6793 mutex_lock(&tp->control);
6794
6795 tp->rtl_ops.up(tp);
6796
6797 netif_carrier_off(netdev);
6798 netif_start_queue(netdev);
6799 set_bit(WORK_ENABLE, &tp->flags);
6800
6801 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
6802 if (res) {
6803 if (res == -ENODEV)
6804 netif_device_detach(tp->netdev);
6805 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
6806 res);
6807 goto out_unlock;
6808 }
6809 napi_enable(&tp->napi);
6810 tasklet_enable(&tp->tx_tl);
6811
6812 mutex_unlock(&tp->control);
6813
6814 usb_autopm_put_interface(tp->intf);
6815#ifdef CONFIG_PM_SLEEP
6816 tp->pm_notifier.notifier_call = rtl_notifier;
6817 register_pm_notifier(&tp->pm_notifier);
6818#endif
6819 return 0;
6820
6821out_unlock:
6822 mutex_unlock(&tp->control);
6823 usb_autopm_put_interface(tp->intf);
6824out_free:
6825 free_all_mem(tp);
6826out:
6827 return res;
6828}
6829
6830static int rtl8152_close(struct net_device *netdev)
6831{
6832 struct r8152 *tp = netdev_priv(netdev);
6833 int res = 0;
6834
6835#ifdef CONFIG_PM_SLEEP
6836 unregister_pm_notifier(&tp->pm_notifier);
6837#endif
6838 tasklet_disable(&tp->tx_tl);
6839 clear_bit(WORK_ENABLE, &tp->flags);
6840 usb_kill_urb(tp->intr_urb);
6841 cancel_delayed_work_sync(&tp->schedule);
6842 napi_disable(&tp->napi);
6843 netif_stop_queue(netdev);
6844
6845 res = usb_autopm_get_interface(tp->intf);
6846 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
6847 rtl_drop_queued_tx(tp);
6848 rtl_stop_rx(tp);
6849 } else {
6850 mutex_lock(&tp->control);
6851
6852 tp->rtl_ops.down(tp);
6853
6854 mutex_unlock(&tp->control);
6855 }
6856
6857 if (!res)
6858 usb_autopm_put_interface(tp->intf);
6859
6860 free_all_mem(tp);
6861
6862 return res;
6863}
6864
6865static void rtl_tally_reset(struct r8152 *tp)
6866{
6867 u32 ocp_data;
6868
6869 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
6870 ocp_data |= TALLY_RESET;
6871 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
6872}
6873
6874static void r8152b_init(struct r8152 *tp)
6875{
6876 u32 ocp_data;
6877 u16 data;
6878
6879 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6880 return;
6881
6882 data = r8152_mdio_read(tp, MII_BMCR);
6883 if (data & BMCR_PDOWN) {
6884 data &= ~BMCR_PDOWN;
6885 r8152_mdio_write(tp, MII_BMCR, data);
6886 }
6887
6888 r8152_aldps_en(tp, false);
6889
6890 if (tp->version == RTL_VER_01) {
6891 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
6892 ocp_data &= ~LED_MODE_MASK;
6893 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
6894 }
6895
6896 r8152_power_cut_en(tp, false);
6897
6898 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
6899 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
6900 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
6901 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
6902 ocp_data &= ~MCU_CLK_RATIO_MASK;
6903 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
6904 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
6905 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
6906 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
6907 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
6908
6909 rtl_tally_reset(tp);
6910
6911 /* enable rx aggregation */
6912 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
6913 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
6914 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
6915}
6916
6917static void r8153_init(struct r8152 *tp)
6918{
6919 u32 ocp_data;
6920 u16 data;
6921 int i;
6922
6923 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6924 return;
6925
6926 r8153_u1u2en(tp, false);
6927
6928 for (i = 0; i < 500; i++) {
6929 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
6930 AUTOLOAD_DONE)
6931 break;
6932
6933 msleep(20);
6934 if (test_bit(RTL8152_UNPLUG, &tp->flags))
6935 break;
6936 }
6937
6938 data = r8153_phy_status(tp, 0);
6939
6940 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
6941 tp->version == RTL_VER_05)
6942 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
6943
6944 data = r8152_mdio_read(tp, MII_BMCR);
6945 if (data & BMCR_PDOWN) {
6946 data &= ~BMCR_PDOWN;
6947 r8152_mdio_write(tp, MII_BMCR, data);
6948 }
6949
6950 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
6951
6952 r8153_u2p3en(tp, false);
6953
6954 if (tp->version == RTL_VER_04) {
6955 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
6956 ocp_data &= ~pwd_dn_scale_mask;
6957 ocp_data |= pwd_dn_scale(96);
6958 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
6959
6960 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
6961 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
6962 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
6963 } else if (tp->version == RTL_VER_05) {
6964 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
6965 ocp_data &= ~ECM_ALDPS;
6966 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
6967
6968 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6969 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6970 ocp_data &= ~DYNAMIC_BURST;
6971 else
6972 ocp_data |= DYNAMIC_BURST;
6973 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
6974 } else if (tp->version == RTL_VER_06) {
6975 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
6976 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
6977 ocp_data &= ~DYNAMIC_BURST;
6978 else
6979 ocp_data |= DYNAMIC_BURST;
6980 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
6981
6982 r8153_queue_wake(tp, false);
6983
6984 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
6985 if (rtl8152_get_speed(tp) & LINK_STATUS)
6986 ocp_data |= CUR_LINK_OK;
6987 else
6988 ocp_data &= ~CUR_LINK_OK;
6989 ocp_data |= POLL_LINK_CHG;
6990 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
6991 }
6992
6993 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
6994 ocp_data |= EP4_FULL_FC;
6995 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
6996
6997 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
6998 ocp_data &= ~TIMER11_EN;
6999 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
7000
7001 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
7002 ocp_data &= ~LED_MODE_MASK;
7003 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
7004
7005 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
7006 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
7007 ocp_data |= LPM_TIMER_500MS;
7008 else
7009 ocp_data |= LPM_TIMER_500US;
7010 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
7011
7012 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
7013 ocp_data &= ~SEN_VAL_MASK;
7014 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
7015 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
7016
7017 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
7018
7019 r8153_power_cut_en(tp, false);
7020 rtl_runtime_suspend_enable(tp, false);
7021 r8153_mac_clk_speed_down(tp, false);
7022 r8153_u1u2en(tp, true);
7023 usb_enable_lpm(tp->udev);
7024
7025 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6);
7026 ocp_data |= LANWAKE_CLR_EN;
7027 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data);
7028
7029 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG);
7030 ocp_data &= ~LANWAKE_PIN;
7031 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data);
7032
7033 /* rx aggregation */
7034 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7035 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7036 if (tp->dell_tb_rx_agg_bug)
7037 ocp_data |= RX_AGG_DISABLE;
7038
7039 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7040
7041 rtl_tally_reset(tp);
7042
7043 switch (tp->udev->speed) {
7044 case USB_SPEED_SUPER:
7045 case USB_SPEED_SUPER_PLUS:
7046 tp->coalesce = COALESCE_SUPER;
7047 break;
7048 case USB_SPEED_HIGH:
7049 tp->coalesce = COALESCE_HIGH;
7050 break;
7051 default:
7052 tp->coalesce = COALESCE_SLOW;
7053 break;
7054 }
7055}
7056
7057static void r8153b_init(struct r8152 *tp)
7058{
7059 u32 ocp_data;
7060 u16 data;
7061 int i;
7062
7063 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7064 return;
7065
7066 r8153b_u1u2en(tp, false);
7067
7068 for (i = 0; i < 500; i++) {
7069 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7070 AUTOLOAD_DONE)
7071 break;
7072
7073 msleep(20);
7074 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7075 break;
7076 }
7077
7078 data = r8153_phy_status(tp, 0);
7079
7080 data = r8152_mdio_read(tp, MII_BMCR);
7081 if (data & BMCR_PDOWN) {
7082 data &= ~BMCR_PDOWN;
7083 r8152_mdio_write(tp, MII_BMCR, data);
7084 }
7085
7086 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7087
7088 r8153_u2p3en(tp, false);
7089
7090 /* MSC timer = 0xfff * 8ms = 32760 ms */
7091 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7092
7093 r8153b_power_cut_en(tp, false);
7094 r8153b_ups_en(tp, false);
7095 r8153_queue_wake(tp, false);
7096 rtl_runtime_suspend_enable(tp, false);
7097
7098 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7099 if (rtl8152_get_speed(tp) & LINK_STATUS)
7100 ocp_data |= CUR_LINK_OK;
7101 else
7102 ocp_data &= ~CUR_LINK_OK;
7103 ocp_data |= POLL_LINK_CHG;
7104 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7105
7106 if (tp->udev->speed >= USB_SPEED_SUPER)
7107 r8153b_u1u2en(tp, true);
7108
7109 usb_enable_lpm(tp->udev);
7110
7111 /* MAC clock speed down */
7112 r8153_mac_clk_speed_down(tp, true);
7113
7114 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
7115 ocp_data &= ~PLA_MCU_SPDWN_EN;
7116 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
7117
7118 if (tp->version == RTL_VER_09) {
7119 /* Disable Test IO for 32QFN */
7120 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) {
7121 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7122 ocp_data |= TEST_IO_OFF;
7123 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7124 }
7125 }
7126
7127 set_bit(GREEN_ETHERNET, &tp->flags);
7128
7129 /* rx aggregation */
7130 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7131 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7132 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7133
7134 rtl_tally_reset(tp);
7135
7136 tp->coalesce = 15000; /* 15 us */
7137}
7138
7139static void r8153c_init(struct r8152 *tp)
7140{
7141 u32 ocp_data;
7142 u16 data;
7143 int i;
7144
7145 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7146 return;
7147
7148 r8153b_u1u2en(tp, false);
7149
7150 /* Disable spi_en */
7151 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
7152 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
7153 ocp_data &= ~BIT(3);
7154 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
7155 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);
7156 ocp_data |= BIT(1);
7157 ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);
7158
7159 for (i = 0; i < 500; i++) {
7160 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
7161 AUTOLOAD_DONE)
7162 break;
7163
7164 msleep(20);
7165 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7166 return;
7167 }
7168
7169 data = r8153_phy_status(tp, 0);
7170
7171 data = r8152_mdio_read(tp, MII_BMCR);
7172 if (data & BMCR_PDOWN) {
7173 data &= ~BMCR_PDOWN;
7174 r8152_mdio_write(tp, MII_BMCR, data);
7175 }
7176
7177 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7178
7179 r8153_u2p3en(tp, false);
7180
7181 /* MSC timer = 0xfff * 8ms = 32760 ms */
7182 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
7183
7184 r8153b_power_cut_en(tp, false);
7185 r8153c_ups_en(tp, false);
7186 r8153_queue_wake(tp, false);
7187 rtl_runtime_suspend_enable(tp, false);
7188
7189 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
7190 if (rtl8152_get_speed(tp) & LINK_STATUS)
7191 ocp_data |= CUR_LINK_OK;
7192 else
7193 ocp_data &= ~CUR_LINK_OK;
7194
7195 ocp_data |= POLL_LINK_CHG;
7196 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
7197
7198 r8153b_u1u2en(tp, true);
7199
7200 usb_enable_lpm(tp->udev);
7201
7202 /* MAC clock speed down */
7203 r8153_mac_clk_speed_down(tp, true);
7204
7205 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
7206 ocp_data &= ~BIT(7);
7207 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
7208
7209 set_bit(GREEN_ETHERNET, &tp->flags);
7210
7211 /* rx aggregation */
7212 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
7213 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
7214 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
7215
7216 rtl_tally_reset(tp);
7217
7218 tp->coalesce = 15000; /* 15 us */
7219}
7220
7221static void r8156_hw_phy_cfg(struct r8152 *tp)
7222{
7223 u32 ocp_data;
7224 u16 data;
7225
7226 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7227 if (ocp_data & PCUT_STATUS) {
7228 ocp_data &= ~PCUT_STATUS;
7229 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7230 }
7231
7232 data = r8153_phy_status(tp, 0);
7233 switch (data) {
7234 case PHY_STAT_EXT_INIT:
7235 rtl8152_apply_firmware(tp, true);
7236
7237 data = ocp_reg_read(tp, 0xa468);
7238 data &= ~(BIT(3) | BIT(1));
7239 ocp_reg_write(tp, 0xa468, data);
7240 break;
7241 case PHY_STAT_LAN_ON:
7242 case PHY_STAT_PWRDN:
7243 default:
7244 rtl8152_apply_firmware(tp, false);
7245 break;
7246 }
7247
7248 /* disable ALDPS before updating the PHY parameters */
7249 r8153_aldps_en(tp, false);
7250
7251 /* disable EEE before updating the PHY parameters */
7252 rtl_eee_enable(tp, false);
7253
7254 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7255 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7256
7257 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7258 ocp_data |= PFM_PWM_SWITCH;
7259 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7260
7261 switch (tp->version) {
7262 case RTL_VER_10:
7263 data = ocp_reg_read(tp, 0xad40);
7264 data &= ~0x3ff;
7265 data |= BIT(7) | BIT(2);
7266 ocp_reg_write(tp, 0xad40, data);
7267
7268 data = ocp_reg_read(tp, 0xad4e);
7269 data |= BIT(4);
7270 ocp_reg_write(tp, 0xad4e, data);
7271 data = ocp_reg_read(tp, 0xad16);
7272 data &= ~0x3ff;
7273 data |= 0x6;
7274 ocp_reg_write(tp, 0xad16, data);
7275 data = ocp_reg_read(tp, 0xad32);
7276 data &= ~0x3f;
7277 data |= 6;
7278 ocp_reg_write(tp, 0xad32, data);
7279 data = ocp_reg_read(tp, 0xac08);
7280 data &= ~(BIT(12) | BIT(8));
7281 ocp_reg_write(tp, 0xac08, data);
7282 data = ocp_reg_read(tp, 0xac8a);
7283 data |= BIT(12) | BIT(13) | BIT(14);
7284 data &= ~BIT(15);
7285 ocp_reg_write(tp, 0xac8a, data);
7286 data = ocp_reg_read(tp, 0xad18);
7287 data |= BIT(10);
7288 ocp_reg_write(tp, 0xad18, data);
7289 data = ocp_reg_read(tp, 0xad1a);
7290 data |= 0x3ff;
7291 ocp_reg_write(tp, 0xad1a, data);
7292 data = ocp_reg_read(tp, 0xad1c);
7293 data |= 0x3ff;
7294 ocp_reg_write(tp, 0xad1c, data);
7295
7296 data = sram_read(tp, 0x80ea);
7297 data &= ~0xff00;
7298 data |= 0xc400;
7299 sram_write(tp, 0x80ea, data);
7300 data = sram_read(tp, 0x80eb);
7301 data &= ~0x0700;
7302 data |= 0x0300;
7303 sram_write(tp, 0x80eb, data);
7304 data = sram_read(tp, 0x80f8);
7305 data &= ~0xff00;
7306 data |= 0x1c00;
7307 sram_write(tp, 0x80f8, data);
7308 data = sram_read(tp, 0x80f1);
7309 data &= ~0xff00;
7310 data |= 0x3000;
7311 sram_write(tp, 0x80f1, data);
7312
7313 data = sram_read(tp, 0x80fe);
7314 data &= ~0xff00;
7315 data |= 0xa500;
7316 sram_write(tp, 0x80fe, data);
7317 data = sram_read(tp, 0x8102);
7318 data &= ~0xff00;
7319 data |= 0x5000;
7320 sram_write(tp, 0x8102, data);
7321 data = sram_read(tp, 0x8015);
7322 data &= ~0xff00;
7323 data |= 0x3300;
7324 sram_write(tp, 0x8015, data);
7325 data = sram_read(tp, 0x8100);
7326 data &= ~0xff00;
7327 data |= 0x7000;
7328 sram_write(tp, 0x8100, data);
7329 data = sram_read(tp, 0x8014);
7330 data &= ~0xff00;
7331 data |= 0xf000;
7332 sram_write(tp, 0x8014, data);
7333 data = sram_read(tp, 0x8016);
7334 data &= ~0xff00;
7335 data |= 0x6500;
7336 sram_write(tp, 0x8016, data);
7337 data = sram_read(tp, 0x80dc);
7338 data &= ~0xff00;
7339 data |= 0xed00;
7340 sram_write(tp, 0x80dc, data);
7341 data = sram_read(tp, 0x80df);
7342 data |= BIT(8);
7343 sram_write(tp, 0x80df, data);
7344 data = sram_read(tp, 0x80e1);
7345 data &= ~BIT(8);
7346 sram_write(tp, 0x80e1, data);
7347
7348 data = ocp_reg_read(tp, 0xbf06);
7349 data &= ~0x003f;
7350 data |= 0x0038;
7351 ocp_reg_write(tp, 0xbf06, data);
7352
7353 sram_write(tp, 0x819f, 0xddb6);
7354
7355 ocp_reg_write(tp, 0xbc34, 0x5555);
7356 data = ocp_reg_read(tp, 0xbf0a);
7357 data &= ~0x0e00;
7358 data |= 0x0a00;
7359 ocp_reg_write(tp, 0xbf0a, data);
7360
7361 data = ocp_reg_read(tp, 0xbd2c);
7362 data &= ~BIT(13);
7363 ocp_reg_write(tp, 0xbd2c, data);
7364 break;
7365 case RTL_VER_11:
7366 data = ocp_reg_read(tp, 0xad16);
7367 data |= 0x3ff;
7368 ocp_reg_write(tp, 0xad16, data);
7369 data = ocp_reg_read(tp, 0xad32);
7370 data &= ~0x3f;
7371 data |= 6;
7372 ocp_reg_write(tp, 0xad32, data);
7373 data = ocp_reg_read(tp, 0xac08);
7374 data &= ~(BIT(12) | BIT(8));
7375 ocp_reg_write(tp, 0xac08, data);
7376 data = ocp_reg_read(tp, 0xacc0);
7377 data &= ~0x3;
7378 data |= BIT(1);
7379 ocp_reg_write(tp, 0xacc0, data);
7380 data = ocp_reg_read(tp, 0xad40);
7381 data &= ~0xe7;
7382 data |= BIT(6) | BIT(2);
7383 ocp_reg_write(tp, 0xad40, data);
7384 data = ocp_reg_read(tp, 0xac14);
7385 data &= ~BIT(7);
7386 ocp_reg_write(tp, 0xac14, data);
7387 data = ocp_reg_read(tp, 0xac80);
7388 data &= ~(BIT(8) | BIT(9));
7389 ocp_reg_write(tp, 0xac80, data);
7390 data = ocp_reg_read(tp, 0xac5e);
7391 data &= ~0x7;
7392 data |= BIT(1);
7393 ocp_reg_write(tp, 0xac5e, data);
7394 ocp_reg_write(tp, 0xad4c, 0x00a8);
7395 ocp_reg_write(tp, 0xac5c, 0x01ff);
7396 data = ocp_reg_read(tp, 0xac8a);
7397 data &= ~0xf0;
7398 data |= BIT(4) | BIT(5);
7399 ocp_reg_write(tp, 0xac8a, data);
7400 ocp_reg_write(tp, 0xb87c, 0x8157);
7401 data = ocp_reg_read(tp, 0xb87e);
7402 data &= ~0xff00;
7403 data |= 0x0500;
7404 ocp_reg_write(tp, 0xb87e, data);
7405 ocp_reg_write(tp, 0xb87c, 0x8159);
7406 data = ocp_reg_read(tp, 0xb87e);
7407 data &= ~0xff00;
7408 data |= 0x0700;
7409 ocp_reg_write(tp, 0xb87e, data);
7410
7411 /* AAGC */
7412 ocp_reg_write(tp, 0xb87c, 0x80a2);
7413 ocp_reg_write(tp, 0xb87e, 0x0153);
7414 ocp_reg_write(tp, 0xb87c, 0x809c);
7415 ocp_reg_write(tp, 0xb87e, 0x0153);
7416
7417 /* EEE parameter */
7418 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
7419
7420 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7421 ocp_data |= EN_XG_LIP | EN_G_LIP;
7422 ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7423
7424 sram_write(tp, 0x8257, 0x020f); /* XG PLL */
7425 sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */
7426
7427 if (rtl_phy_patch_request(tp, true, true))
7428 return;
7429
7430 /* Advance EEE */
7431 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7432 ocp_data |= EEE_SPDWN_EN;
7433 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7434
7435 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7436 data &= ~(EN_EEE_100 | EN_EEE_1000);
7437 data |= EN_10M_CLKDIV;
7438 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7439 tp->ups_info._10m_ckdiv = true;
7440 tp->ups_info.eee_plloff_100 = false;
7441 tp->ups_info.eee_plloff_giga = false;
7442
7443 data = ocp_reg_read(tp, OCP_POWER_CFG);
7444 data &= ~EEE_CLKDIV_EN;
7445 ocp_reg_write(tp, OCP_POWER_CFG, data);
7446 tp->ups_info.eee_ckdiv = false;
7447
7448 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
7449 ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
7450 tp->ups_info._250m_ckdiv = false;
7451
7452 rtl_phy_patch_request(tp, false, true);
7453
7454 /* enable ADC Ibias Cal */
7455 data = ocp_reg_read(tp, 0xd068);
7456 data |= BIT(13);
7457 ocp_reg_write(tp, 0xd068, data);
7458
7459 /* enable Thermal Sensor */
7460 data = sram_read(tp, 0x81a2);
7461 data &= ~BIT(8);
7462 sram_write(tp, 0x81a2, data);
7463 data = ocp_reg_read(tp, 0xb54c);
7464 data &= ~0xff00;
7465 data |= 0xdb00;
7466 ocp_reg_write(tp, 0xb54c, data);
7467
7468 /* Nway 2.5G Lite */
7469 data = ocp_reg_read(tp, 0xa454);
7470 data &= ~BIT(0);
7471 ocp_reg_write(tp, 0xa454, data);
7472
7473 /* CS DSP solution */
7474 data = ocp_reg_read(tp, OCP_10GBT_CTRL);
7475 data |= RTL_ADV2_5G_F_R;
7476 ocp_reg_write(tp, OCP_10GBT_CTRL, data);
7477 data = ocp_reg_read(tp, 0xad4e);
7478 data &= ~BIT(4);
7479 ocp_reg_write(tp, 0xad4e, data);
7480 data = ocp_reg_read(tp, 0xa86a);
7481 data &= ~BIT(0);
7482 ocp_reg_write(tp, 0xa86a, data);
7483
7484 /* MDI SWAP */
7485 if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
7486 (ocp_reg_read(tp, 0xd068) & BIT(1))) {
7487 u16 swap_a, swap_b;
7488
7489 data = ocp_reg_read(tp, 0xd068);
7490 data &= ~0x1f;
7491 data |= 0x1; /* p0 */
7492 ocp_reg_write(tp, 0xd068, data);
7493 swap_a = ocp_reg_read(tp, 0xd06a);
7494 data &= ~0x18;
7495 data |= 0x18; /* p3 */
7496 ocp_reg_write(tp, 0xd068, data);
7497 swap_b = ocp_reg_read(tp, 0xd06a);
7498 data &= ~0x18; /* p0 */
7499 ocp_reg_write(tp, 0xd068, data);
7500 ocp_reg_write(tp, 0xd06a,
7501 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7502 data |= 0x18; /* p3 */
7503 ocp_reg_write(tp, 0xd068, data);
7504 ocp_reg_write(tp, 0xd06a,
7505 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7506 data &= ~0x18;
7507 data |= 0x08; /* p1 */
7508 ocp_reg_write(tp, 0xd068, data);
7509 swap_a = ocp_reg_read(tp, 0xd06a);
7510 data &= ~0x18;
7511 data |= 0x10; /* p2 */
7512 ocp_reg_write(tp, 0xd068, data);
7513 swap_b = ocp_reg_read(tp, 0xd06a);
7514 data &= ~0x18;
7515 data |= 0x08; /* p1 */
7516 ocp_reg_write(tp, 0xd068, data);
7517 ocp_reg_write(tp, 0xd06a,
7518 (swap_a & ~0x7ff) | (swap_b & 0x7ff));
7519 data &= ~0x18;
7520 data |= 0x10; /* p2 */
7521 ocp_reg_write(tp, 0xd068, data);
7522 ocp_reg_write(tp, 0xd06a,
7523 (swap_b & ~0x7ff) | (swap_a & 0x7ff));
7524 swap_a = ocp_reg_read(tp, 0xbd5a);
7525 swap_b = ocp_reg_read(tp, 0xbd5c);
7526 ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |
7527 ((swap_b & 0x1f) << 8) |
7528 ((swap_b >> 8) & 0x1f));
7529 ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |
7530 ((swap_a & 0x1f) << 8) |
7531 ((swap_a >> 8) & 0x1f));
7532 swap_a = ocp_reg_read(tp, 0xbc18);
7533 swap_b = ocp_reg_read(tp, 0xbc1a);
7534 ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |
7535 ((swap_b & 0x1f) << 8) |
7536 ((swap_b >> 8) & 0x1f));
7537 ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |
7538 ((swap_a & 0x1f) << 8) |
7539 ((swap_a >> 8) & 0x1f));
7540 }
7541 break;
7542 default:
7543 break;
7544 }
7545
7546 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7547
7548 data = ocp_reg_read(tp, 0xa428);
7549 data &= ~BIT(9);
7550 ocp_reg_write(tp, 0xa428, data);
7551 data = ocp_reg_read(tp, 0xa5ea);
7552 data &= ~BIT(0);
7553 ocp_reg_write(tp, 0xa5ea, data);
7554 tp->ups_info.lite_mode = 0;
7555
7556 if (tp->eee_en)
7557 rtl_eee_enable(tp, true);
7558
7559 r8153_aldps_en(tp, true);
7560 r8152b_enable_fc(tp);
7561 r8153_u2p3en(tp, true);
7562
7563 set_bit(PHY_RESET, &tp->flags);
7564}
7565
7566static void r8156b_hw_phy_cfg(struct r8152 *tp)
7567{
7568 u32 ocp_data;
7569 u16 data;
7570
7571 switch (tp->version) {
7572 case RTL_VER_12:
7573 ocp_reg_write(tp, 0xbf86, 0x9000);
7574 data = ocp_reg_read(tp, 0xc402);
7575 data |= BIT(10);
7576 ocp_reg_write(tp, 0xc402, data);
7577 data &= ~BIT(10);
7578 ocp_reg_write(tp, 0xc402, data);
7579 ocp_reg_write(tp, 0xbd86, 0x1010);
7580 ocp_reg_write(tp, 0xbd88, 0x1010);
7581 data = ocp_reg_read(tp, 0xbd4e);
7582 data &= ~(BIT(10) | BIT(11));
7583 data |= BIT(11);
7584 ocp_reg_write(tp, 0xbd4e, data);
7585 data = ocp_reg_read(tp, 0xbf46);
7586 data &= ~0xf00;
7587 data |= 0x700;
7588 ocp_reg_write(tp, 0xbf46, data);
7589 break;
7590 case RTL_VER_13:
7591 case RTL_VER_15:
7592 r8156b_wait_loading_flash(tp);
7593 break;
7594 default:
7595 break;
7596 }
7597
7598 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
7599 if (ocp_data & PCUT_STATUS) {
7600 ocp_data &= ~PCUT_STATUS;
7601 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
7602 }
7603
7604 data = r8153_phy_status(tp, 0);
7605 switch (data) {
7606 case PHY_STAT_EXT_INIT:
7607 rtl8152_apply_firmware(tp, true);
7608
7609 data = ocp_reg_read(tp, 0xa466);
7610 data &= ~BIT(0);
7611 ocp_reg_write(tp, 0xa466, data);
7612
7613 data = ocp_reg_read(tp, 0xa468);
7614 data &= ~(BIT(3) | BIT(1));
7615 ocp_reg_write(tp, 0xa468, data);
7616 break;
7617 case PHY_STAT_LAN_ON:
7618 case PHY_STAT_PWRDN:
7619 default:
7620 rtl8152_apply_firmware(tp, false);
7621 break;
7622 }
7623
7624 data = r8152_mdio_read(tp, MII_BMCR);
7625 if (data & BMCR_PDOWN) {
7626 data &= ~BMCR_PDOWN;
7627 r8152_mdio_write(tp, MII_BMCR, data);
7628 }
7629
7630 /* disable ALDPS before updating the PHY parameters */
7631 r8153_aldps_en(tp, false);
7632
7633 /* disable EEE before updating the PHY parameters */
7634 rtl_eee_enable(tp, false);
7635
7636 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
7637 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
7638
7639 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
7640 ocp_data |= PFM_PWM_SWITCH;
7641 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
7642
7643 switch (tp->version) {
7644 case RTL_VER_12:
7645 data = ocp_reg_read(tp, 0xbc08);
7646 data |= BIT(3) | BIT(2);
7647 ocp_reg_write(tp, 0xbc08, data);
7648
7649 data = sram_read(tp, 0x8fff);
7650 data &= ~0xff00;
7651 data |= 0x0400;
7652 sram_write(tp, 0x8fff, data);
7653
7654 data = ocp_reg_read(tp, 0xacda);
7655 data |= 0xff00;
7656 ocp_reg_write(tp, 0xacda, data);
7657 data = ocp_reg_read(tp, 0xacde);
7658 data |= 0xf000;
7659 ocp_reg_write(tp, 0xacde, data);
7660 ocp_reg_write(tp, 0xac8c, 0x0ffc);
7661 ocp_reg_write(tp, 0xac46, 0xb7b4);
7662 ocp_reg_write(tp, 0xac50, 0x0fbc);
7663 ocp_reg_write(tp, 0xac3c, 0x9240);
7664 ocp_reg_write(tp, 0xac4e, 0x0db4);
7665 ocp_reg_write(tp, 0xacc6, 0x0707);
7666 ocp_reg_write(tp, 0xacc8, 0xa0d3);
7667 ocp_reg_write(tp, 0xad08, 0x0007);
7668
7669 ocp_reg_write(tp, 0xb87c, 0x8560);
7670 ocp_reg_write(tp, 0xb87e, 0x19cc);
7671 ocp_reg_write(tp, 0xb87c, 0x8562);
7672 ocp_reg_write(tp, 0xb87e, 0x19cc);
7673 ocp_reg_write(tp, 0xb87c, 0x8564);
7674 ocp_reg_write(tp, 0xb87e, 0x19cc);
7675 ocp_reg_write(tp, 0xb87c, 0x8566);
7676 ocp_reg_write(tp, 0xb87e, 0x147d);
7677 ocp_reg_write(tp, 0xb87c, 0x8568);
7678 ocp_reg_write(tp, 0xb87e, 0x147d);
7679 ocp_reg_write(tp, 0xb87c, 0x856a);
7680 ocp_reg_write(tp, 0xb87e, 0x147d);
7681 ocp_reg_write(tp, 0xb87c, 0x8ffe);
7682 ocp_reg_write(tp, 0xb87e, 0x0907);
7683 ocp_reg_write(tp, 0xb87c, 0x80d6);
7684 ocp_reg_write(tp, 0xb87e, 0x2801);
7685 ocp_reg_write(tp, 0xb87c, 0x80f2);
7686 ocp_reg_write(tp, 0xb87e, 0x2801);
7687 ocp_reg_write(tp, 0xb87c, 0x80f4);
7688 ocp_reg_write(tp, 0xb87e, 0x6077);
7689 ocp_reg_write(tp, 0xb506, 0x01e7);
7690
7691 ocp_reg_write(tp, 0xb87c, 0x8013);
7692 ocp_reg_write(tp, 0xb87e, 0x0700);
7693 ocp_reg_write(tp, 0xb87c, 0x8fb9);
7694 ocp_reg_write(tp, 0xb87e, 0x2801);
7695 ocp_reg_write(tp, 0xb87c, 0x8fba);
7696 ocp_reg_write(tp, 0xb87e, 0x0100);
7697 ocp_reg_write(tp, 0xb87c, 0x8fbc);
7698 ocp_reg_write(tp, 0xb87e, 0x1900);
7699 ocp_reg_write(tp, 0xb87c, 0x8fbe);
7700 ocp_reg_write(tp, 0xb87e, 0xe100);
7701 ocp_reg_write(tp, 0xb87c, 0x8fc0);
7702 ocp_reg_write(tp, 0xb87e, 0x0800);
7703 ocp_reg_write(tp, 0xb87c, 0x8fc2);
7704 ocp_reg_write(tp, 0xb87e, 0xe500);
7705 ocp_reg_write(tp, 0xb87c, 0x8fc4);
7706 ocp_reg_write(tp, 0xb87e, 0x0f00);
7707 ocp_reg_write(tp, 0xb87c, 0x8fc6);
7708 ocp_reg_write(tp, 0xb87e, 0xf100);
7709 ocp_reg_write(tp, 0xb87c, 0x8fc8);
7710 ocp_reg_write(tp, 0xb87e, 0x0400);
7711 ocp_reg_write(tp, 0xb87c, 0x8fca);
7712 ocp_reg_write(tp, 0xb87e, 0xf300);
7713 ocp_reg_write(tp, 0xb87c, 0x8fcc);
7714 ocp_reg_write(tp, 0xb87e, 0xfd00);
7715 ocp_reg_write(tp, 0xb87c, 0x8fce);
7716 ocp_reg_write(tp, 0xb87e, 0xff00);
7717 ocp_reg_write(tp, 0xb87c, 0x8fd0);
7718 ocp_reg_write(tp, 0xb87e, 0xfb00);
7719 ocp_reg_write(tp, 0xb87c, 0x8fd2);
7720 ocp_reg_write(tp, 0xb87e, 0x0100);
7721 ocp_reg_write(tp, 0xb87c, 0x8fd4);
7722 ocp_reg_write(tp, 0xb87e, 0xf400);
7723 ocp_reg_write(tp, 0xb87c, 0x8fd6);
7724 ocp_reg_write(tp, 0xb87e, 0xff00);
7725 ocp_reg_write(tp, 0xb87c, 0x8fd8);
7726 ocp_reg_write(tp, 0xb87e, 0xf600);
7727
7728 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
7729 ocp_data |= EN_XG_LIP | EN_G_LIP;
7730 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
7731 ocp_reg_write(tp, 0xb87c, 0x813d);
7732 ocp_reg_write(tp, 0xb87e, 0x390e);
7733 ocp_reg_write(tp, 0xb87c, 0x814f);
7734 ocp_reg_write(tp, 0xb87e, 0x790e);
7735 ocp_reg_write(tp, 0xb87c, 0x80b0);
7736 ocp_reg_write(tp, 0xb87e, 0x0f31);
7737 data = ocp_reg_read(tp, 0xbf4c);
7738 data |= BIT(1);
7739 ocp_reg_write(tp, 0xbf4c, data);
7740 data = ocp_reg_read(tp, 0xbcca);
7741 data |= BIT(9) | BIT(8);
7742 ocp_reg_write(tp, 0xbcca, data);
7743 ocp_reg_write(tp, 0xb87c, 0x8141);
7744 ocp_reg_write(tp, 0xb87e, 0x320e);
7745 ocp_reg_write(tp, 0xb87c, 0x8153);
7746 ocp_reg_write(tp, 0xb87e, 0x720e);
7747 ocp_reg_write(tp, 0xb87c, 0x8529);
7748 ocp_reg_write(tp, 0xb87e, 0x050e);
7749 data = ocp_reg_read(tp, OCP_EEE_CFG);
7750 data &= ~CTAP_SHORT_EN;
7751 ocp_reg_write(tp, OCP_EEE_CFG, data);
7752
7753 sram_write(tp, 0x816c, 0xc4a0);
7754 sram_write(tp, 0x8170, 0xc4a0);
7755 sram_write(tp, 0x8174, 0x04a0);
7756 sram_write(tp, 0x8178, 0x04a0);
7757 sram_write(tp, 0x817c, 0x0719);
7758 sram_write(tp, 0x8ff4, 0x0400);
7759 sram_write(tp, 0x8ff1, 0x0404);
7760
7761 ocp_reg_write(tp, 0xbf4a, 0x001b);
7762 ocp_reg_write(tp, 0xb87c, 0x8033);
7763 ocp_reg_write(tp, 0xb87e, 0x7c13);
7764 ocp_reg_write(tp, 0xb87c, 0x8037);
7765 ocp_reg_write(tp, 0xb87e, 0x7c13);
7766 ocp_reg_write(tp, 0xb87c, 0x803b);
7767 ocp_reg_write(tp, 0xb87e, 0xfc32);
7768 ocp_reg_write(tp, 0xb87c, 0x803f);
7769 ocp_reg_write(tp, 0xb87e, 0x7c13);
7770 ocp_reg_write(tp, 0xb87c, 0x8043);
7771 ocp_reg_write(tp, 0xb87e, 0x7c13);
7772 ocp_reg_write(tp, 0xb87c, 0x8047);
7773 ocp_reg_write(tp, 0xb87e, 0x7c13);
7774
7775 ocp_reg_write(tp, 0xb87c, 0x8145);
7776 ocp_reg_write(tp, 0xb87e, 0x370e);
7777 ocp_reg_write(tp, 0xb87c, 0x8157);
7778 ocp_reg_write(tp, 0xb87e, 0x770e);
7779 ocp_reg_write(tp, 0xb87c, 0x8169);
7780 ocp_reg_write(tp, 0xb87e, 0x0d0a);
7781 ocp_reg_write(tp, 0xb87c, 0x817b);
7782 ocp_reg_write(tp, 0xb87e, 0x1d0a);
7783
7784 data = sram_read(tp, 0x8217);
7785 data &= ~0xff00;
7786 data |= 0x5000;
7787 sram_write(tp, 0x8217, data);
7788 data = sram_read(tp, 0x821a);
7789 data &= ~0xff00;
7790 data |= 0x5000;
7791 sram_write(tp, 0x821a, data);
7792 sram_write(tp, 0x80da, 0x0403);
7793 data = sram_read(tp, 0x80dc);
7794 data &= ~0xff00;
7795 data |= 0x1000;
7796 sram_write(tp, 0x80dc, data);
7797 sram_write(tp, 0x80b3, 0x0384);
7798 sram_write(tp, 0x80b7, 0x2007);
7799 data = sram_read(tp, 0x80ba);
7800 data &= ~0xff00;
7801 data |= 0x6c00;
7802 sram_write(tp, 0x80ba, data);
7803 sram_write(tp, 0x80b5, 0xf009);
7804 data = sram_read(tp, 0x80bd);
7805 data &= ~0xff00;
7806 data |= 0x9f00;
7807 sram_write(tp, 0x80bd, data);
7808 sram_write(tp, 0x80c7, 0xf083);
7809 sram_write(tp, 0x80dd, 0x03f0);
7810 data = sram_read(tp, 0x80df);
7811 data &= ~0xff00;
7812 data |= 0x1000;
7813 sram_write(tp, 0x80df, data);
7814 sram_write(tp, 0x80cb, 0x2007);
7815 data = sram_read(tp, 0x80ce);
7816 data &= ~0xff00;
7817 data |= 0x6c00;
7818 sram_write(tp, 0x80ce, data);
7819 sram_write(tp, 0x80c9, 0x8009);
7820 data = sram_read(tp, 0x80d1);
7821 data &= ~0xff00;
7822 data |= 0x8000;
7823 sram_write(tp, 0x80d1, data);
7824 sram_write(tp, 0x80a3, 0x200a);
7825 sram_write(tp, 0x80a5, 0xf0ad);
7826 sram_write(tp, 0x809f, 0x6073);
7827 sram_write(tp, 0x80a1, 0x000b);
7828 data = sram_read(tp, 0x80a9);
7829 data &= ~0xff00;
7830 data |= 0xc000;
7831 sram_write(tp, 0x80a9, data);
7832
7833 if (rtl_phy_patch_request(tp, true, true))
7834 return;
7835
7836 data = ocp_reg_read(tp, 0xb896);
7837 data &= ~BIT(0);
7838 ocp_reg_write(tp, 0xb896, data);
7839 data = ocp_reg_read(tp, 0xb892);
7840 data &= ~0xff00;
7841 ocp_reg_write(tp, 0xb892, data);
7842 ocp_reg_write(tp, 0xb88e, 0xc23e);
7843 ocp_reg_write(tp, 0xb890, 0x0000);
7844 ocp_reg_write(tp, 0xb88e, 0xc240);
7845 ocp_reg_write(tp, 0xb890, 0x0103);
7846 ocp_reg_write(tp, 0xb88e, 0xc242);
7847 ocp_reg_write(tp, 0xb890, 0x0507);
7848 ocp_reg_write(tp, 0xb88e, 0xc244);
7849 ocp_reg_write(tp, 0xb890, 0x090b);
7850 ocp_reg_write(tp, 0xb88e, 0xc246);
7851 ocp_reg_write(tp, 0xb890, 0x0c0e);
7852 ocp_reg_write(tp, 0xb88e, 0xc248);
7853 ocp_reg_write(tp, 0xb890, 0x1012);
7854 ocp_reg_write(tp, 0xb88e, 0xc24a);
7855 ocp_reg_write(tp, 0xb890, 0x1416);
7856 data = ocp_reg_read(tp, 0xb896);
7857 data |= BIT(0);
7858 ocp_reg_write(tp, 0xb896, data);
7859
7860 rtl_phy_patch_request(tp, false, true);
7861
7862 data = ocp_reg_read(tp, 0xa86a);
7863 data |= BIT(0);
7864 ocp_reg_write(tp, 0xa86a, data);
7865 data = ocp_reg_read(tp, 0xa6f0);
7866 data |= BIT(0);
7867 ocp_reg_write(tp, 0xa6f0, data);
7868
7869 ocp_reg_write(tp, 0xbfa0, 0xd70d);
7870 ocp_reg_write(tp, 0xbfa2, 0x4100);
7871 ocp_reg_write(tp, 0xbfa4, 0xe868);
7872 ocp_reg_write(tp, 0xbfa6, 0xdc59);
7873 ocp_reg_write(tp, 0xb54c, 0x3c18);
7874 data = ocp_reg_read(tp, 0xbfa4);
7875 data &= ~BIT(5);
7876 ocp_reg_write(tp, 0xbfa4, data);
7877 data = sram_read(tp, 0x817d);
7878 data |= BIT(12);
7879 sram_write(tp, 0x817d, data);
7880 break;
7881 case RTL_VER_13:
7882 /* 2.5G INRX */
7883 data = ocp_reg_read(tp, 0xac46);
7884 data &= ~0x00f0;
7885 data |= 0x0090;
7886 ocp_reg_write(tp, 0xac46, data);
7887 data = ocp_reg_read(tp, 0xad30);
7888 data &= ~0x0003;
7889 data |= 0x0001;
7890 ocp_reg_write(tp, 0xad30, data);
7891 fallthrough;
7892 case RTL_VER_15:
7893 /* EEE parameter */
7894 ocp_reg_write(tp, 0xb87c, 0x80f5);
7895 ocp_reg_write(tp, 0xb87e, 0x760e);
7896 ocp_reg_write(tp, 0xb87c, 0x8107);
7897 ocp_reg_write(tp, 0xb87e, 0x360e);
7898 ocp_reg_write(tp, 0xb87c, 0x8551);
7899 data = ocp_reg_read(tp, 0xb87e);
7900 data &= ~0xff00;
7901 data |= 0x0800;
7902 ocp_reg_write(tp, 0xb87e, data);
7903
7904 /* ADC_PGA parameter */
7905 data = ocp_reg_read(tp, 0xbf00);
7906 data &= ~0xe000;
7907 data |= 0xa000;
7908 ocp_reg_write(tp, 0xbf00, data);
7909 data = ocp_reg_read(tp, 0xbf46);
7910 data &= ~0x0f00;
7911 data |= 0x0300;
7912 ocp_reg_write(tp, 0xbf46, data);
7913
7914 /* Green Table-PGA, 1G full viterbi */
7915 sram_write(tp, 0x8044, 0x2417);
7916 sram_write(tp, 0x804a, 0x2417);
7917 sram_write(tp, 0x8050, 0x2417);
7918 sram_write(tp, 0x8056, 0x2417);
7919 sram_write(tp, 0x805c, 0x2417);
7920 sram_write(tp, 0x8062, 0x2417);
7921 sram_write(tp, 0x8068, 0x2417);
7922 sram_write(tp, 0x806e, 0x2417);
7923 sram_write(tp, 0x8074, 0x2417);
7924 sram_write(tp, 0x807a, 0x2417);
7925
7926 /* XG PLL */
7927 data = ocp_reg_read(tp, 0xbf84);
7928 data &= ~0xe000;
7929 data |= 0xa000;
7930 ocp_reg_write(tp, 0xbf84, data);
7931 break;
7932 default:
7933 break;
7934 }
7935
7936 if (rtl_phy_patch_request(tp, true, true))
7937 return;
7938
7939 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
7940 ocp_data |= EEE_SPDWN_EN;
7941 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
7942
7943 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
7944 data &= ~(EN_EEE_100 | EN_EEE_1000);
7945 data |= EN_10M_CLKDIV;
7946 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
7947 tp->ups_info._10m_ckdiv = true;
7948 tp->ups_info.eee_plloff_100 = false;
7949 tp->ups_info.eee_plloff_giga = false;
7950
7951 data = ocp_reg_read(tp, OCP_POWER_CFG);
7952 data &= ~EEE_CLKDIV_EN;
7953 ocp_reg_write(tp, OCP_POWER_CFG, data);
7954 tp->ups_info.eee_ckdiv = false;
7955
7956 rtl_phy_patch_request(tp, false, true);
7957
7958 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
7959
7960 data = ocp_reg_read(tp, 0xa428);
7961 data &= ~BIT(9);
7962 ocp_reg_write(tp, 0xa428, data);
7963 data = ocp_reg_read(tp, 0xa5ea);
7964 data &= ~BIT(0);
7965 ocp_reg_write(tp, 0xa5ea, data);
7966 tp->ups_info.lite_mode = 0;
7967
7968 if (tp->eee_en)
7969 rtl_eee_enable(tp, true);
7970
7971 r8153_aldps_en(tp, true);
7972 r8152b_enable_fc(tp);
7973 r8153_u2p3en(tp, true);
7974
7975 set_bit(PHY_RESET, &tp->flags);
7976}
7977
7978static void r8156_init(struct r8152 *tp)
7979{
7980 u32 ocp_data;
7981 u16 data;
7982 int i;
7983
7984 if (test_bit(RTL8152_UNPLUG, &tp->flags))
7985 return;
7986
7987 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
7988 ocp_data &= ~EN_ALL_SPEED;
7989 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
7990
7991 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
7992
7993 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
7994 ocp_data |= BYPASS_MAC_RESET;
7995 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
7996
7997 r8153b_u1u2en(tp, false);
7998
7999 for (i = 0; i < 500; i++) {
8000 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8001 AUTOLOAD_DONE)
8002 break;
8003
8004 msleep(20);
8005 if (test_bit(RTL8152_UNPLUG, &tp->flags))
8006 return;
8007 }
8008
8009 data = r8153_phy_status(tp, 0);
8010 if (data == PHY_STAT_EXT_INIT) {
8011 data = ocp_reg_read(tp, 0xa468);
8012 data &= ~(BIT(3) | BIT(1));
8013 ocp_reg_write(tp, 0xa468, data);
8014 }
8015
8016 data = r8152_mdio_read(tp, MII_BMCR);
8017 if (data & BMCR_PDOWN) {
8018 data &= ~BMCR_PDOWN;
8019 r8152_mdio_write(tp, MII_BMCR, data);
8020 }
8021
8022 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8023 WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
8024
8025 r8153_u2p3en(tp, false);
8026
8027 /* MSC timer = 0xfff * 8ms = 32760 ms */
8028 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8029
8030 /* U1/U2/L1 idle timer. 500 us */
8031 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8032
8033 r8153b_power_cut_en(tp, false);
8034 r8156_ups_en(tp, false);
8035 r8153_queue_wake(tp, false);
8036 rtl_runtime_suspend_enable(tp, false);
8037
8038 if (tp->udev->speed >= USB_SPEED_SUPER)
8039 r8153b_u1u2en(tp, true);
8040
8041 usb_enable_lpm(tp->udev);
8042
8043 r8156_mac_clk_spd(tp, true);
8044
8045 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8046 ocp_data &= ~PLA_MCU_SPDWN_EN;
8047 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8048
8049 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8050 if (rtl8152_get_speed(tp) & LINK_STATUS)
8051 ocp_data |= CUR_LINK_OK;
8052 else
8053 ocp_data &= ~CUR_LINK_OK;
8054 ocp_data |= POLL_LINK_CHG;
8055 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8056
8057 set_bit(GREEN_ETHERNET, &tp->flags);
8058
8059 /* rx aggregation */
8060 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8061 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8062 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8063
8064 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
8065 ocp_data |= ACT_ODMA;
8066 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
8067
8068 r8156_mdio_force_mode(tp);
8069 rtl_tally_reset(tp);
8070
8071 tp->coalesce = 15000; /* 15 us */
8072}
8073
8074static void r8156b_init(struct r8152 *tp)
8075{
8076 u32 ocp_data;
8077 u16 data;
8078 int i;
8079
8080 if (test_bit(RTL8152_UNPLUG, &tp->flags))
8081 return;
8082
8083 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
8084 ocp_data &= ~EN_ALL_SPEED;
8085 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
8086
8087 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
8088
8089 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
8090 ocp_data |= BYPASS_MAC_RESET;
8091 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
8092
8093 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
8094 ocp_data |= RX_DETECT8;
8095 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
8096
8097 r8153b_u1u2en(tp, false);
8098
8099 switch (tp->version) {
8100 case RTL_VER_13:
8101 case RTL_VER_15:
8102 r8156b_wait_loading_flash(tp);
8103 break;
8104 default:
8105 break;
8106 }
8107
8108 for (i = 0; i < 500; i++) {
8109 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
8110 AUTOLOAD_DONE)
8111 break;
8112
8113 msleep(20);
8114 if (test_bit(RTL8152_UNPLUG, &tp->flags))
8115 return;
8116 }
8117
8118 data = r8153_phy_status(tp, 0);
8119 if (data == PHY_STAT_EXT_INIT) {
8120 data = ocp_reg_read(tp, 0xa468);
8121 data &= ~(BIT(3) | BIT(1));
8122 ocp_reg_write(tp, 0xa468, data);
8123
8124 data = ocp_reg_read(tp, 0xa466);
8125 data &= ~BIT(0);
8126 ocp_reg_write(tp, 0xa466, data);
8127 }
8128
8129 data = r8152_mdio_read(tp, MII_BMCR);
8130 if (data & BMCR_PDOWN) {
8131 data &= ~BMCR_PDOWN;
8132 r8152_mdio_write(tp, MII_BMCR, data);
8133 }
8134
8135 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
8136
8137 r8153_u2p3en(tp, false);
8138
8139 /* MSC timer = 0xfff * 8ms = 32760 ms */
8140 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
8141
8142 /* U1/U2/L1 idle timer. 500 us */
8143 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
8144
8145 r8153b_power_cut_en(tp, false);
8146 r8156_ups_en(tp, false);
8147 r8153_queue_wake(tp, false);
8148 rtl_runtime_suspend_enable(tp, false);
8149
8150 if (tp->udev->speed >= USB_SPEED_SUPER)
8151 r8153b_u1u2en(tp, true);
8152
8153 usb_enable_lpm(tp->udev);
8154
8155 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
8156 ocp_data &= ~SLOT_EN;
8157 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8158
8159 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
8160 ocp_data |= FLOW_CTRL_EN;
8161 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
8162
8163 /* enable fc timer and set timer to 600 ms. */
8164 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
8165 CTRL_TIMER_EN | (600 / 8));
8166
8167 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
8168 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
8169 ocp_data |= FLOW_CTRL_PATCH_2;
8170 ocp_data &= ~AUTO_SPEEDUP;
8171 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
8172
8173 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
8174 ocp_data |= FC_PATCH_TASK;
8175 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
8176
8177 r8156_mac_clk_spd(tp, true);
8178
8179 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
8180 ocp_data &= ~PLA_MCU_SPDWN_EN;
8181 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
8182
8183 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
8184 if (rtl8152_get_speed(tp) & LINK_STATUS)
8185 ocp_data |= CUR_LINK_OK;
8186 else
8187 ocp_data &= ~CUR_LINK_OK;
8188 ocp_data |= POLL_LINK_CHG;
8189 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
8190
8191 set_bit(GREEN_ETHERNET, &tp->flags);
8192
8193 /* rx aggregation */
8194 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
8195 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
8196 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
8197
8198 r8156_mdio_force_mode(tp);
8199 rtl_tally_reset(tp);
8200
8201 tp->coalesce = 15000; /* 15 us */
8202}
8203
8204static bool rtl_check_vendor_ok(struct usb_interface *intf)
8205{
8206 struct usb_host_interface *alt = intf->cur_altsetting;
8207 struct usb_endpoint_descriptor *in, *out, *intr;
8208
8209 if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) {
8210 dev_err(&intf->dev, "Expected endpoints are not found\n");
8211 return false;
8212 }
8213
8214 /* Check Rx endpoint address */
8215 if (usb_endpoint_num(in) != 1) {
8216 dev_err(&intf->dev, "Invalid Rx endpoint address\n");
8217 return false;
8218 }
8219
8220 /* Check Tx endpoint address */
8221 if (usb_endpoint_num(out) != 2) {
8222 dev_err(&intf->dev, "Invalid Tx endpoint address\n");
8223 return false;
8224 }
8225
8226 /* Check interrupt endpoint address */
8227 if (usb_endpoint_num(intr) != 3) {
8228 dev_err(&intf->dev, "Invalid interrupt endpoint address\n");
8229 return false;
8230 }
8231
8232 return true;
8233}
8234
8235static bool rtl_vendor_mode(struct usb_interface *intf)
8236{
8237 struct usb_host_interface *alt = intf->cur_altsetting;
8238 struct usb_device *udev;
8239 struct usb_host_config *c;
8240 int i, num_configs;
8241
8242 if (alt->desc.bInterfaceClass == USB_CLASS_VENDOR_SPEC)
8243 return rtl_check_vendor_ok(intf);
8244
8245 /* The vendor mode is not always config #1, so to find it out. */
8246 udev = interface_to_usbdev(intf);
8247 c = udev->config;
8248 num_configs = udev->descriptor.bNumConfigurations;
8249 if (num_configs < 2)
8250 return false;
8251
8252 for (i = 0; i < num_configs; (i++, c++)) {
8253 struct usb_interface_descriptor *desc = NULL;
8254
8255 if (c->desc.bNumInterfaces > 0)
8256 desc = &c->intf_cache[0]->altsetting->desc;
8257 else
8258 continue;
8259
8260 if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) {
8261 usb_driver_set_configuration(udev, c->desc.bConfigurationValue);
8262 break;
8263 }
8264 }
8265
8266 if (i == num_configs)
8267 dev_err(&intf->dev, "Unexpected Device\n");
8268
8269 return false;
8270}
8271
8272static int rtl8152_pre_reset(struct usb_interface *intf)
8273{
8274 struct r8152 *tp = usb_get_intfdata(intf);
8275 struct net_device *netdev;
8276
8277 if (!tp)
8278 return 0;
8279
8280 netdev = tp->netdev;
8281 if (!netif_running(netdev))
8282 return 0;
8283
8284 netif_stop_queue(netdev);
8285 tasklet_disable(&tp->tx_tl);
8286 clear_bit(WORK_ENABLE, &tp->flags);
8287 usb_kill_urb(tp->intr_urb);
8288 cancel_delayed_work_sync(&tp->schedule);
8289 napi_disable(&tp->napi);
8290 if (netif_carrier_ok(netdev)) {
8291 mutex_lock(&tp->control);
8292 tp->rtl_ops.disable(tp);
8293 mutex_unlock(&tp->control);
8294 }
8295
8296 return 0;
8297}
8298
8299static int rtl8152_post_reset(struct usb_interface *intf)
8300{
8301 struct r8152 *tp = usb_get_intfdata(intf);
8302 struct net_device *netdev;
8303 struct sockaddr sa;
8304
8305 if (!tp)
8306 return 0;
8307
8308 /* reset the MAC address in case of policy change */
8309 if (determine_ethernet_addr(tp, &sa) >= 0) {
8310 rtnl_lock();
8311 dev_set_mac_address (tp->netdev, &sa, NULL);
8312 rtnl_unlock();
8313 }
8314
8315 netdev = tp->netdev;
8316 if (!netif_running(netdev))
8317 return 0;
8318
8319 set_bit(WORK_ENABLE, &tp->flags);
8320 if (netif_carrier_ok(netdev)) {
8321 mutex_lock(&tp->control);
8322 tp->rtl_ops.enable(tp);
8323 rtl_start_rx(tp);
8324 _rtl8152_set_rx_mode(netdev);
8325 mutex_unlock(&tp->control);
8326 }
8327
8328 napi_enable(&tp->napi);
8329 tasklet_enable(&tp->tx_tl);
8330 netif_wake_queue(netdev);
8331 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
8332
8333 if (!list_empty(&tp->rx_done))
8334 napi_schedule(&tp->napi);
8335
8336 return 0;
8337}
8338
8339static bool delay_autosuspend(struct r8152 *tp)
8340{
8341 bool sw_linking = !!netif_carrier_ok(tp->netdev);
8342 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
8343
8344 /* This means a linking change occurs and the driver doesn't detect it,
8345 * yet. If the driver has disabled tx/rx and hw is linking on, the
8346 * device wouldn't wake up by receiving any packet.
8347 */
8348 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
8349 return true;
8350
8351 /* If the linking down is occurred by nway, the device may miss the
8352 * linking change event. And it wouldn't wake when linking on.
8353 */
8354 if (!sw_linking && tp->rtl_ops.in_nway(tp))
8355 return true;
8356 else if (!skb_queue_empty(&tp->tx_queue))
8357 return true;
8358 else
8359 return false;
8360}
8361
8362static int rtl8152_runtime_resume(struct r8152 *tp)
8363{
8364 struct net_device *netdev = tp->netdev;
8365
8366 if (netif_running(netdev) && netdev->flags & IFF_UP) {
8367 struct napi_struct *napi = &tp->napi;
8368
8369 tp->rtl_ops.autosuspend_en(tp, false);
8370 napi_disable(napi);
8371 set_bit(WORK_ENABLE, &tp->flags);
8372
8373 if (netif_carrier_ok(netdev)) {
8374 if (rtl8152_get_speed(tp) & LINK_STATUS) {
8375 rtl_start_rx(tp);
8376 } else {
8377 netif_carrier_off(netdev);
8378 tp->rtl_ops.disable(tp);
8379 netif_info(tp, link, netdev, "linking down\n");
8380 }
8381 }
8382
8383 napi_enable(napi);
8384 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8385 smp_mb__after_atomic();
8386
8387 if (!list_empty(&tp->rx_done))
8388 napi_schedule(&tp->napi);
8389
8390 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8391 } else {
8392 if (netdev->flags & IFF_UP)
8393 tp->rtl_ops.autosuspend_en(tp, false);
8394
8395 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8396 }
8397
8398 return 0;
8399}
8400
8401static int rtl8152_system_resume(struct r8152 *tp)
8402{
8403 struct net_device *netdev = tp->netdev;
8404
8405 netif_device_attach(netdev);
8406
8407 if (netif_running(netdev) && (netdev->flags & IFF_UP)) {
8408 tp->rtl_ops.up(tp);
8409 netif_carrier_off(netdev);
8410 set_bit(WORK_ENABLE, &tp->flags);
8411 usb_submit_urb(tp->intr_urb, GFP_NOIO);
8412 }
8413
8414 return 0;
8415}
8416
8417static int rtl8152_runtime_suspend(struct r8152 *tp)
8418{
8419 struct net_device *netdev = tp->netdev;
8420 int ret = 0;
8421
8422 if (!tp->rtl_ops.autosuspend_en)
8423 return -EBUSY;
8424
8425 set_bit(SELECTIVE_SUSPEND, &tp->flags);
8426 smp_mb__after_atomic();
8427
8428 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8429 u32 rcr = 0;
8430
8431 if (netif_carrier_ok(netdev)) {
8432 u32 ocp_data;
8433
8434 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
8435 ocp_data = rcr & ~RCR_ACPT_ALL;
8436 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
8437 rxdy_gated_en(tp, true);
8438 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
8439 PLA_OOB_CTRL);
8440 if (!(ocp_data & RXFIFO_EMPTY)) {
8441 rxdy_gated_en(tp, false);
8442 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8443 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8444 smp_mb__after_atomic();
8445 ret = -EBUSY;
8446 goto out1;
8447 }
8448 }
8449
8450 clear_bit(WORK_ENABLE, &tp->flags);
8451 usb_kill_urb(tp->intr_urb);
8452
8453 tp->rtl_ops.autosuspend_en(tp, true);
8454
8455 if (netif_carrier_ok(netdev)) {
8456 struct napi_struct *napi = &tp->napi;
8457
8458 napi_disable(napi);
8459 rtl_stop_rx(tp);
8460 rxdy_gated_en(tp, false);
8461 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
8462 napi_enable(napi);
8463 }
8464
8465 if (delay_autosuspend(tp)) {
8466 rtl8152_runtime_resume(tp);
8467 ret = -EBUSY;
8468 }
8469 }
8470
8471out1:
8472 return ret;
8473}
8474
8475static int rtl8152_system_suspend(struct r8152 *tp)
8476{
8477 struct net_device *netdev = tp->netdev;
8478
8479 netif_device_detach(netdev);
8480
8481 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
8482 struct napi_struct *napi = &tp->napi;
8483
8484 clear_bit(WORK_ENABLE, &tp->flags);
8485 usb_kill_urb(tp->intr_urb);
8486 tasklet_disable(&tp->tx_tl);
8487 napi_disable(napi);
8488 cancel_delayed_work_sync(&tp->schedule);
8489 tp->rtl_ops.down(tp);
8490 napi_enable(napi);
8491 tasklet_enable(&tp->tx_tl);
8492 }
8493
8494 return 0;
8495}
8496
8497static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
8498{
8499 struct r8152 *tp = usb_get_intfdata(intf);
8500 int ret;
8501
8502 mutex_lock(&tp->control);
8503
8504 if (PMSG_IS_AUTO(message))
8505 ret = rtl8152_runtime_suspend(tp);
8506 else
8507 ret = rtl8152_system_suspend(tp);
8508
8509 mutex_unlock(&tp->control);
8510
8511 return ret;
8512}
8513
8514static int rtl8152_resume(struct usb_interface *intf)
8515{
8516 struct r8152 *tp = usb_get_intfdata(intf);
8517 int ret;
8518
8519 mutex_lock(&tp->control);
8520
8521 rtl_reset_ocp_base(tp);
8522
8523 if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
8524 ret = rtl8152_runtime_resume(tp);
8525 else
8526 ret = rtl8152_system_resume(tp);
8527
8528 mutex_unlock(&tp->control);
8529
8530 return ret;
8531}
8532
8533static int rtl8152_reset_resume(struct usb_interface *intf)
8534{
8535 struct r8152 *tp = usb_get_intfdata(intf);
8536
8537 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
8538 rtl_reset_ocp_base(tp);
8539 tp->rtl_ops.init(tp);
8540 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
8541 set_ethernet_addr(tp, true);
8542 return rtl8152_resume(intf);
8543}
8544
8545static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8546{
8547 struct r8152 *tp = netdev_priv(dev);
8548
8549 if (usb_autopm_get_interface(tp->intf) < 0)
8550 return;
8551
8552 if (!rtl_can_wakeup(tp)) {
8553 wol->supported = 0;
8554 wol->wolopts = 0;
8555 } else {
8556 mutex_lock(&tp->control);
8557 wol->supported = WAKE_ANY;
8558 wol->wolopts = __rtl_get_wol(tp);
8559 mutex_unlock(&tp->control);
8560 }
8561
8562 usb_autopm_put_interface(tp->intf);
8563}
8564
8565static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8566{
8567 struct r8152 *tp = netdev_priv(dev);
8568 int ret;
8569
8570 if (!rtl_can_wakeup(tp))
8571 return -EOPNOTSUPP;
8572
8573 if (wol->wolopts & ~WAKE_ANY)
8574 return -EINVAL;
8575
8576 ret = usb_autopm_get_interface(tp->intf);
8577 if (ret < 0)
8578 goto out_set_wol;
8579
8580 mutex_lock(&tp->control);
8581
8582 __rtl_set_wol(tp, wol->wolopts);
8583 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
8584
8585 mutex_unlock(&tp->control);
8586
8587 usb_autopm_put_interface(tp->intf);
8588
8589out_set_wol:
8590 return ret;
8591}
8592
8593static u32 rtl8152_get_msglevel(struct net_device *dev)
8594{
8595 struct r8152 *tp = netdev_priv(dev);
8596
8597 return tp->msg_enable;
8598}
8599
8600static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
8601{
8602 struct r8152 *tp = netdev_priv(dev);
8603
8604 tp->msg_enable = value;
8605}
8606
8607static void rtl8152_get_drvinfo(struct net_device *netdev,
8608 struct ethtool_drvinfo *info)
8609{
8610 struct r8152 *tp = netdev_priv(netdev);
8611
8612 strscpy(info->driver, MODULENAME, sizeof(info->driver));
8613 strscpy(info->version, DRIVER_VERSION, sizeof(info->version));
8614 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
8615 if (!IS_ERR_OR_NULL(tp->rtl_fw.fw))
8616 strscpy(info->fw_version, tp->rtl_fw.version,
8617 sizeof(info->fw_version));
8618}
8619
8620static
8621int rtl8152_get_link_ksettings(struct net_device *netdev,
8622 struct ethtool_link_ksettings *cmd)
8623{
8624 struct r8152 *tp = netdev_priv(netdev);
8625 int ret;
8626
8627 if (!tp->mii.mdio_read)
8628 return -EOPNOTSUPP;
8629
8630 ret = usb_autopm_get_interface(tp->intf);
8631 if (ret < 0)
8632 goto out;
8633
8634 mutex_lock(&tp->control);
8635
8636 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
8637
8638 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8639 cmd->link_modes.supported, tp->support_2500full);
8640
8641 if (tp->support_2500full) {
8642 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8643 cmd->link_modes.advertising,
8644 ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
8645
8646 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8647 cmd->link_modes.lp_advertising,
8648 ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
8649
8650 if (is_speed_2500(rtl8152_get_speed(tp)))
8651 cmd->base.speed = SPEED_2500;
8652 }
8653
8654 mutex_unlock(&tp->control);
8655
8656 usb_autopm_put_interface(tp->intf);
8657
8658out:
8659 return ret;
8660}
8661
8662static int rtl8152_set_link_ksettings(struct net_device *dev,
8663 const struct ethtool_link_ksettings *cmd)
8664{
8665 struct r8152 *tp = netdev_priv(dev);
8666 u32 advertising = 0;
8667 int ret;
8668
8669 ret = usb_autopm_get_interface(tp->intf);
8670 if (ret < 0)
8671 goto out;
8672
8673 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
8674 cmd->link_modes.advertising))
8675 advertising |= RTL_ADVERTISED_10_HALF;
8676
8677 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
8678 cmd->link_modes.advertising))
8679 advertising |= RTL_ADVERTISED_10_FULL;
8680
8681 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
8682 cmd->link_modes.advertising))
8683 advertising |= RTL_ADVERTISED_100_HALF;
8684
8685 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
8686 cmd->link_modes.advertising))
8687 advertising |= RTL_ADVERTISED_100_FULL;
8688
8689 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
8690 cmd->link_modes.advertising))
8691 advertising |= RTL_ADVERTISED_1000_HALF;
8692
8693 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
8694 cmd->link_modes.advertising))
8695 advertising |= RTL_ADVERTISED_1000_FULL;
8696
8697 if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
8698 cmd->link_modes.advertising))
8699 advertising |= RTL_ADVERTISED_2500_FULL;
8700
8701 mutex_lock(&tp->control);
8702
8703 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
8704 cmd->base.duplex, advertising);
8705 if (!ret) {
8706 tp->autoneg = cmd->base.autoneg;
8707 tp->speed = cmd->base.speed;
8708 tp->duplex = cmd->base.duplex;
8709 tp->advertising = advertising;
8710 }
8711
8712 mutex_unlock(&tp->control);
8713
8714 usb_autopm_put_interface(tp->intf);
8715
8716out:
8717 return ret;
8718}
8719
8720static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
8721 "tx_packets",
8722 "rx_packets",
8723 "tx_errors",
8724 "rx_errors",
8725 "rx_missed",
8726 "align_errors",
8727 "tx_single_collisions",
8728 "tx_multi_collisions",
8729 "rx_unicast",
8730 "rx_broadcast",
8731 "rx_multicast",
8732 "tx_aborted",
8733 "tx_underrun",
8734};
8735
8736static int rtl8152_get_sset_count(struct net_device *dev, int sset)
8737{
8738 switch (sset) {
8739 case ETH_SS_STATS:
8740 return ARRAY_SIZE(rtl8152_gstrings);
8741 default:
8742 return -EOPNOTSUPP;
8743 }
8744}
8745
8746static void rtl8152_get_ethtool_stats(struct net_device *dev,
8747 struct ethtool_stats *stats, u64 *data)
8748{
8749 struct r8152 *tp = netdev_priv(dev);
8750 struct tally_counter tally;
8751
8752 if (usb_autopm_get_interface(tp->intf) < 0)
8753 return;
8754
8755 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
8756
8757 usb_autopm_put_interface(tp->intf);
8758
8759 data[0] = le64_to_cpu(tally.tx_packets);
8760 data[1] = le64_to_cpu(tally.rx_packets);
8761 data[2] = le64_to_cpu(tally.tx_errors);
8762 data[3] = le32_to_cpu(tally.rx_errors);
8763 data[4] = le16_to_cpu(tally.rx_missed);
8764 data[5] = le16_to_cpu(tally.align_errors);
8765 data[6] = le32_to_cpu(tally.tx_one_collision);
8766 data[7] = le32_to_cpu(tally.tx_multi_collision);
8767 data[8] = le64_to_cpu(tally.rx_unicast);
8768 data[9] = le64_to_cpu(tally.rx_broadcast);
8769 data[10] = le32_to_cpu(tally.rx_multicast);
8770 data[11] = le16_to_cpu(tally.tx_aborted);
8771 data[12] = le16_to_cpu(tally.tx_underrun);
8772}
8773
8774static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
8775{
8776 switch (stringset) {
8777 case ETH_SS_STATS:
8778 memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings));
8779 break;
8780 }
8781}
8782
8783static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8784{
8785 u32 lp, adv, supported = 0;
8786 u16 val;
8787
8788 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
8789 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8790
8791 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
8792 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8793
8794 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
8795 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8796
8797 eee->eee_enabled = tp->eee_en;
8798 eee->eee_active = !!(supported & adv & lp);
8799 eee->supported = supported;
8800 eee->advertised = tp->eee_adv;
8801 eee->lp_advertised = lp;
8802
8803 return 0;
8804}
8805
8806static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
8807{
8808 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
8809
8810 tp->eee_en = eee->eee_enabled;
8811 tp->eee_adv = val;
8812
8813 rtl_eee_enable(tp, tp->eee_en);
8814
8815 return 0;
8816}
8817
8818static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
8819{
8820 u32 lp, adv, supported = 0;
8821 u16 val;
8822
8823 val = ocp_reg_read(tp, OCP_EEE_ABLE);
8824 supported = mmd_eee_cap_to_ethtool_sup_t(val);
8825
8826 val = ocp_reg_read(tp, OCP_EEE_ADV);
8827 adv = mmd_eee_adv_to_ethtool_adv_t(val);
8828
8829 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
8830 lp = mmd_eee_adv_to_ethtool_adv_t(val);
8831
8832 eee->eee_enabled = tp->eee_en;
8833 eee->eee_active = !!(supported & adv & lp);
8834 eee->supported = supported;
8835 eee->advertised = tp->eee_adv;
8836 eee->lp_advertised = lp;
8837
8838 return 0;
8839}
8840
8841static int
8842rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
8843{
8844 struct r8152 *tp = netdev_priv(net);
8845 int ret;
8846
8847 if (!tp->rtl_ops.eee_get) {
8848 ret = -EOPNOTSUPP;
8849 goto out;
8850 }
8851
8852 ret = usb_autopm_get_interface(tp->intf);
8853 if (ret < 0)
8854 goto out;
8855
8856 mutex_lock(&tp->control);
8857
8858 ret = tp->rtl_ops.eee_get(tp, edata);
8859
8860 mutex_unlock(&tp->control);
8861
8862 usb_autopm_put_interface(tp->intf);
8863
8864out:
8865 return ret;
8866}
8867
8868static int
8869rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
8870{
8871 struct r8152 *tp = netdev_priv(net);
8872 int ret;
8873
8874 if (!tp->rtl_ops.eee_set) {
8875 ret = -EOPNOTSUPP;
8876 goto out;
8877 }
8878
8879 ret = usb_autopm_get_interface(tp->intf);
8880 if (ret < 0)
8881 goto out;
8882
8883 mutex_lock(&tp->control);
8884
8885 ret = tp->rtl_ops.eee_set(tp, edata);
8886 if (!ret)
8887 ret = mii_nway_restart(&tp->mii);
8888
8889 mutex_unlock(&tp->control);
8890
8891 usb_autopm_put_interface(tp->intf);
8892
8893out:
8894 return ret;
8895}
8896
8897static int rtl8152_nway_reset(struct net_device *dev)
8898{
8899 struct r8152 *tp = netdev_priv(dev);
8900 int ret;
8901
8902 ret = usb_autopm_get_interface(tp->intf);
8903 if (ret < 0)
8904 goto out;
8905
8906 mutex_lock(&tp->control);
8907
8908 ret = mii_nway_restart(&tp->mii);
8909
8910 mutex_unlock(&tp->control);
8911
8912 usb_autopm_put_interface(tp->intf);
8913
8914out:
8915 return ret;
8916}
8917
8918static int rtl8152_get_coalesce(struct net_device *netdev,
8919 struct ethtool_coalesce *coalesce,
8920 struct kernel_ethtool_coalesce *kernel_coal,
8921 struct netlink_ext_ack *extack)
8922{
8923 struct r8152 *tp = netdev_priv(netdev);
8924
8925 switch (tp->version) {
8926 case RTL_VER_01:
8927 case RTL_VER_02:
8928 case RTL_VER_07:
8929 return -EOPNOTSUPP;
8930 default:
8931 break;
8932 }
8933
8934 coalesce->rx_coalesce_usecs = tp->coalesce;
8935
8936 return 0;
8937}
8938
8939static int rtl8152_set_coalesce(struct net_device *netdev,
8940 struct ethtool_coalesce *coalesce,
8941 struct kernel_ethtool_coalesce *kernel_coal,
8942 struct netlink_ext_ack *extack)
8943{
8944 struct r8152 *tp = netdev_priv(netdev);
8945 int ret;
8946
8947 switch (tp->version) {
8948 case RTL_VER_01:
8949 case RTL_VER_02:
8950 case RTL_VER_07:
8951 return -EOPNOTSUPP;
8952 default:
8953 break;
8954 }
8955
8956 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
8957 return -EINVAL;
8958
8959 ret = usb_autopm_get_interface(tp->intf);
8960 if (ret < 0)
8961 return ret;
8962
8963 mutex_lock(&tp->control);
8964
8965 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
8966 tp->coalesce = coalesce->rx_coalesce_usecs;
8967
8968 if (netif_running(netdev) && netif_carrier_ok(netdev)) {
8969 netif_stop_queue(netdev);
8970 napi_disable(&tp->napi);
8971 tp->rtl_ops.disable(tp);
8972 tp->rtl_ops.enable(tp);
8973 rtl_start_rx(tp);
8974 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
8975 _rtl8152_set_rx_mode(netdev);
8976 napi_enable(&tp->napi);
8977 netif_wake_queue(netdev);
8978 }
8979 }
8980
8981 mutex_unlock(&tp->control);
8982
8983 usb_autopm_put_interface(tp->intf);
8984
8985 return ret;
8986}
8987
8988static int rtl8152_get_tunable(struct net_device *netdev,
8989 const struct ethtool_tunable *tunable, void *d)
8990{
8991 struct r8152 *tp = netdev_priv(netdev);
8992
8993 switch (tunable->id) {
8994 case ETHTOOL_RX_COPYBREAK:
8995 *(u32 *)d = tp->rx_copybreak;
8996 break;
8997 default:
8998 return -EOPNOTSUPP;
8999 }
9000
9001 return 0;
9002}
9003
9004static int rtl8152_set_tunable(struct net_device *netdev,
9005 const struct ethtool_tunable *tunable,
9006 const void *d)
9007{
9008 struct r8152 *tp = netdev_priv(netdev);
9009 u32 val;
9010
9011 switch (tunable->id) {
9012 case ETHTOOL_RX_COPYBREAK:
9013 val = *(u32 *)d;
9014 if (val < ETH_ZLEN) {
9015 netif_err(tp, rx_err, netdev,
9016 "Invalid rx copy break value\n");
9017 return -EINVAL;
9018 }
9019
9020 if (tp->rx_copybreak != val) {
9021 if (netdev->flags & IFF_UP) {
9022 mutex_lock(&tp->control);
9023 napi_disable(&tp->napi);
9024 tp->rx_copybreak = val;
9025 napi_enable(&tp->napi);
9026 mutex_unlock(&tp->control);
9027 } else {
9028 tp->rx_copybreak = val;
9029 }
9030 }
9031 break;
9032 default:
9033 return -EOPNOTSUPP;
9034 }
9035
9036 return 0;
9037}
9038
9039static void rtl8152_get_ringparam(struct net_device *netdev,
9040 struct ethtool_ringparam *ring,
9041 struct kernel_ethtool_ringparam *kernel_ring,
9042 struct netlink_ext_ack *extack)
9043{
9044 struct r8152 *tp = netdev_priv(netdev);
9045
9046 ring->rx_max_pending = RTL8152_RX_MAX_PENDING;
9047 ring->rx_pending = tp->rx_pending;
9048}
9049
9050static int rtl8152_set_ringparam(struct net_device *netdev,
9051 struct ethtool_ringparam *ring,
9052 struct kernel_ethtool_ringparam *kernel_ring,
9053 struct netlink_ext_ack *extack)
9054{
9055 struct r8152 *tp = netdev_priv(netdev);
9056
9057 if (ring->rx_pending < (RTL8152_MAX_RX * 2))
9058 return -EINVAL;
9059
9060 if (tp->rx_pending != ring->rx_pending) {
9061 if (netdev->flags & IFF_UP) {
9062 mutex_lock(&tp->control);
9063 napi_disable(&tp->napi);
9064 tp->rx_pending = ring->rx_pending;
9065 napi_enable(&tp->napi);
9066 mutex_unlock(&tp->control);
9067 } else {
9068 tp->rx_pending = ring->rx_pending;
9069 }
9070 }
9071
9072 return 0;
9073}
9074
9075static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9076{
9077 struct r8152 *tp = netdev_priv(netdev);
9078 u16 bmcr, lcladv, rmtadv;
9079 u8 cap;
9080
9081 if (usb_autopm_get_interface(tp->intf) < 0)
9082 return;
9083
9084 mutex_lock(&tp->control);
9085
9086 bmcr = r8152_mdio_read(tp, MII_BMCR);
9087 lcladv = r8152_mdio_read(tp, MII_ADVERTISE);
9088 rmtadv = r8152_mdio_read(tp, MII_LPA);
9089
9090 mutex_unlock(&tp->control);
9091
9092 usb_autopm_put_interface(tp->intf);
9093
9094 if (!(bmcr & BMCR_ANENABLE)) {
9095 pause->autoneg = 0;
9096 pause->rx_pause = 0;
9097 pause->tx_pause = 0;
9098 return;
9099 }
9100
9101 pause->autoneg = 1;
9102
9103 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
9104
9105 if (cap & FLOW_CTRL_RX)
9106 pause->rx_pause = 1;
9107
9108 if (cap & FLOW_CTRL_TX)
9109 pause->tx_pause = 1;
9110}
9111
9112static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause)
9113{
9114 struct r8152 *tp = netdev_priv(netdev);
9115 u16 old, new1;
9116 u8 cap = 0;
9117 int ret;
9118
9119 ret = usb_autopm_get_interface(tp->intf);
9120 if (ret < 0)
9121 return ret;
9122
9123 mutex_lock(&tp->control);
9124
9125 if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) {
9126 ret = -EINVAL;
9127 goto out;
9128 }
9129
9130 if (pause->rx_pause)
9131 cap |= FLOW_CTRL_RX;
9132
9133 if (pause->tx_pause)
9134 cap |= FLOW_CTRL_TX;
9135
9136 old = r8152_mdio_read(tp, MII_ADVERTISE);
9137 new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap);
9138 if (old != new1)
9139 r8152_mdio_write(tp, MII_ADVERTISE, new1);
9140
9141out:
9142 mutex_unlock(&tp->control);
9143 usb_autopm_put_interface(tp->intf);
9144
9145 return ret;
9146}
9147
9148static const struct ethtool_ops ops = {
9149 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
9150 .get_drvinfo = rtl8152_get_drvinfo,
9151 .get_link = ethtool_op_get_link,
9152 .nway_reset = rtl8152_nway_reset,
9153 .get_msglevel = rtl8152_get_msglevel,
9154 .set_msglevel = rtl8152_set_msglevel,
9155 .get_wol = rtl8152_get_wol,
9156 .set_wol = rtl8152_set_wol,
9157 .get_strings = rtl8152_get_strings,
9158 .get_sset_count = rtl8152_get_sset_count,
9159 .get_ethtool_stats = rtl8152_get_ethtool_stats,
9160 .get_coalesce = rtl8152_get_coalesce,
9161 .set_coalesce = rtl8152_set_coalesce,
9162 .get_eee = rtl_ethtool_get_eee,
9163 .set_eee = rtl_ethtool_set_eee,
9164 .get_link_ksettings = rtl8152_get_link_ksettings,
9165 .set_link_ksettings = rtl8152_set_link_ksettings,
9166 .get_tunable = rtl8152_get_tunable,
9167 .set_tunable = rtl8152_set_tunable,
9168 .get_ringparam = rtl8152_get_ringparam,
9169 .set_ringparam = rtl8152_set_ringparam,
9170 .get_pauseparam = rtl8152_get_pauseparam,
9171 .set_pauseparam = rtl8152_set_pauseparam,
9172};
9173
9174static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
9175{
9176 struct r8152 *tp = netdev_priv(netdev);
9177 struct mii_ioctl_data *data = if_mii(rq);
9178 int res;
9179
9180 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9181 return -ENODEV;
9182
9183 res = usb_autopm_get_interface(tp->intf);
9184 if (res < 0)
9185 goto out;
9186
9187 switch (cmd) {
9188 case SIOCGMIIPHY:
9189 data->phy_id = R8152_PHY_ID; /* Internal PHY */
9190 break;
9191
9192 case SIOCGMIIREG:
9193 mutex_lock(&tp->control);
9194 data->val_out = r8152_mdio_read(tp, data->reg_num);
9195 mutex_unlock(&tp->control);
9196 break;
9197
9198 case SIOCSMIIREG:
9199 if (!capable(CAP_NET_ADMIN)) {
9200 res = -EPERM;
9201 break;
9202 }
9203 mutex_lock(&tp->control);
9204 r8152_mdio_write(tp, data->reg_num, data->val_in);
9205 mutex_unlock(&tp->control);
9206 break;
9207
9208 default:
9209 res = -EOPNOTSUPP;
9210 }
9211
9212 usb_autopm_put_interface(tp->intf);
9213
9214out:
9215 return res;
9216}
9217
9218static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
9219{
9220 struct r8152 *tp = netdev_priv(dev);
9221 int ret;
9222
9223 switch (tp->version) {
9224 case RTL_VER_01:
9225 case RTL_VER_02:
9226 case RTL_VER_07:
9227 dev->mtu = new_mtu;
9228 return 0;
9229 default:
9230 break;
9231 }
9232
9233 ret = usb_autopm_get_interface(tp->intf);
9234 if (ret < 0)
9235 return ret;
9236
9237 mutex_lock(&tp->control);
9238
9239 dev->mtu = new_mtu;
9240
9241 if (netif_running(dev)) {
9242 if (tp->rtl_ops.change_mtu)
9243 tp->rtl_ops.change_mtu(tp);
9244
9245 if (netif_carrier_ok(dev)) {
9246 netif_stop_queue(dev);
9247 napi_disable(&tp->napi);
9248 tasklet_disable(&tp->tx_tl);
9249 tp->rtl_ops.disable(tp);
9250 tp->rtl_ops.enable(tp);
9251 rtl_start_rx(tp);
9252 tasklet_enable(&tp->tx_tl);
9253 napi_enable(&tp->napi);
9254 rtl8152_set_rx_mode(dev);
9255 netif_wake_queue(dev);
9256 }
9257 }
9258
9259 mutex_unlock(&tp->control);
9260
9261 usb_autopm_put_interface(tp->intf);
9262
9263 return ret;
9264}
9265
9266static const struct net_device_ops rtl8152_netdev_ops = {
9267 .ndo_open = rtl8152_open,
9268 .ndo_stop = rtl8152_close,
9269 .ndo_eth_ioctl = rtl8152_ioctl,
9270 .ndo_start_xmit = rtl8152_start_xmit,
9271 .ndo_tx_timeout = rtl8152_tx_timeout,
9272 .ndo_set_features = rtl8152_set_features,
9273 .ndo_set_rx_mode = rtl8152_set_rx_mode,
9274 .ndo_set_mac_address = rtl8152_set_mac_address,
9275 .ndo_change_mtu = rtl8152_change_mtu,
9276 .ndo_validate_addr = eth_validate_addr,
9277 .ndo_features_check = rtl8152_features_check,
9278};
9279
9280static void rtl8152_unload(struct r8152 *tp)
9281{
9282 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9283 return;
9284
9285 if (tp->version != RTL_VER_01)
9286 r8152_power_cut_en(tp, true);
9287}
9288
9289static void rtl8153_unload(struct r8152 *tp)
9290{
9291 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9292 return;
9293
9294 r8153_power_cut_en(tp, false);
9295}
9296
9297static void rtl8153b_unload(struct r8152 *tp)
9298{
9299 if (test_bit(RTL8152_UNPLUG, &tp->flags))
9300 return;
9301
9302 r8153b_power_cut_en(tp, false);
9303}
9304
9305static int rtl_ops_init(struct r8152 *tp)
9306{
9307 struct rtl_ops *ops = &tp->rtl_ops;
9308 int ret = 0;
9309
9310 switch (tp->version) {
9311 case RTL_VER_01:
9312 case RTL_VER_02:
9313 case RTL_VER_07:
9314 ops->init = r8152b_init;
9315 ops->enable = rtl8152_enable;
9316 ops->disable = rtl8152_disable;
9317 ops->up = rtl8152_up;
9318 ops->down = rtl8152_down;
9319 ops->unload = rtl8152_unload;
9320 ops->eee_get = r8152_get_eee;
9321 ops->eee_set = r8152_set_eee;
9322 ops->in_nway = rtl8152_in_nway;
9323 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
9324 ops->autosuspend_en = rtl_runtime_suspend_enable;
9325 tp->rx_buf_sz = 16 * 1024;
9326 tp->eee_en = true;
9327 tp->eee_adv = MDIO_EEE_100TX;
9328 break;
9329
9330 case RTL_VER_03:
9331 case RTL_VER_04:
9332 case RTL_VER_05:
9333 case RTL_VER_06:
9334 ops->init = r8153_init;
9335 ops->enable = rtl8153_enable;
9336 ops->disable = rtl8153_disable;
9337 ops->up = rtl8153_up;
9338 ops->down = rtl8153_down;
9339 ops->unload = rtl8153_unload;
9340 ops->eee_get = r8153_get_eee;
9341 ops->eee_set = r8152_set_eee;
9342 ops->in_nway = rtl8153_in_nway;
9343 ops->hw_phy_cfg = r8153_hw_phy_cfg;
9344 ops->autosuspend_en = rtl8153_runtime_enable;
9345 ops->change_mtu = rtl8153_change_mtu;
9346 if (tp->udev->speed < USB_SPEED_SUPER)
9347 tp->rx_buf_sz = 16 * 1024;
9348 else
9349 tp->rx_buf_sz = 32 * 1024;
9350 tp->eee_en = true;
9351 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9352 break;
9353
9354 case RTL_VER_08:
9355 case RTL_VER_09:
9356 ops->init = r8153b_init;
9357 ops->enable = rtl8153_enable;
9358 ops->disable = rtl8153_disable;
9359 ops->up = rtl8153b_up;
9360 ops->down = rtl8153b_down;
9361 ops->unload = rtl8153b_unload;
9362 ops->eee_get = r8153_get_eee;
9363 ops->eee_set = r8152_set_eee;
9364 ops->in_nway = rtl8153_in_nway;
9365 ops->hw_phy_cfg = r8153b_hw_phy_cfg;
9366 ops->autosuspend_en = rtl8153b_runtime_enable;
9367 ops->change_mtu = rtl8153_change_mtu;
9368 tp->rx_buf_sz = 32 * 1024;
9369 tp->eee_en = true;
9370 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9371 break;
9372
9373 case RTL_VER_11:
9374 tp->eee_en = true;
9375 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9376 fallthrough;
9377 case RTL_VER_10:
9378 ops->init = r8156_init;
9379 ops->enable = rtl8156_enable;
9380 ops->disable = rtl8153_disable;
9381 ops->up = rtl8156_up;
9382 ops->down = rtl8156_down;
9383 ops->unload = rtl8153_unload;
9384 ops->eee_get = r8153_get_eee;
9385 ops->eee_set = r8152_set_eee;
9386 ops->in_nway = rtl8153_in_nway;
9387 ops->hw_phy_cfg = r8156_hw_phy_cfg;
9388 ops->autosuspend_en = rtl8156_runtime_enable;
9389 ops->change_mtu = rtl8156_change_mtu;
9390 tp->rx_buf_sz = 48 * 1024;
9391 tp->support_2500full = 1;
9392 break;
9393
9394 case RTL_VER_12:
9395 case RTL_VER_13:
9396 tp->support_2500full = 1;
9397 fallthrough;
9398 case RTL_VER_15:
9399 tp->eee_en = true;
9400 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9401 ops->init = r8156b_init;
9402 ops->enable = rtl8156b_enable;
9403 ops->disable = rtl8153_disable;
9404 ops->up = rtl8156_up;
9405 ops->down = rtl8156_down;
9406 ops->unload = rtl8153_unload;
9407 ops->eee_get = r8153_get_eee;
9408 ops->eee_set = r8152_set_eee;
9409 ops->in_nway = rtl8153_in_nway;
9410 ops->hw_phy_cfg = r8156b_hw_phy_cfg;
9411 ops->autosuspend_en = rtl8156_runtime_enable;
9412 ops->change_mtu = rtl8156_change_mtu;
9413 tp->rx_buf_sz = 48 * 1024;
9414 break;
9415
9416 case RTL_VER_14:
9417 ops->init = r8153c_init;
9418 ops->enable = rtl8153_enable;
9419 ops->disable = rtl8153_disable;
9420 ops->up = rtl8153c_up;
9421 ops->down = rtl8153b_down;
9422 ops->unload = rtl8153_unload;
9423 ops->eee_get = r8153_get_eee;
9424 ops->eee_set = r8152_set_eee;
9425 ops->in_nway = rtl8153_in_nway;
9426 ops->hw_phy_cfg = r8153c_hw_phy_cfg;
9427 ops->autosuspend_en = rtl8153c_runtime_enable;
9428 ops->change_mtu = rtl8153c_change_mtu;
9429 tp->rx_buf_sz = 32 * 1024;
9430 tp->eee_en = true;
9431 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
9432 break;
9433
9434 default:
9435 ret = -ENODEV;
9436 dev_err(&tp->intf->dev, "Unknown Device\n");
9437 break;
9438 }
9439
9440 return ret;
9441}
9442
9443#define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw"
9444#define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
9445#define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
9446#define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
9447#define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw"
9448#define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw"
9449#define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw"
9450
9451MODULE_FIRMWARE(FIRMWARE_8153A_2);
9452MODULE_FIRMWARE(FIRMWARE_8153A_3);
9453MODULE_FIRMWARE(FIRMWARE_8153A_4);
9454MODULE_FIRMWARE(FIRMWARE_8153B_2);
9455MODULE_FIRMWARE(FIRMWARE_8153C_1);
9456MODULE_FIRMWARE(FIRMWARE_8156A_2);
9457MODULE_FIRMWARE(FIRMWARE_8156B_2);
9458
9459static int rtl_fw_init(struct r8152 *tp)
9460{
9461 struct rtl_fw *rtl_fw = &tp->rtl_fw;
9462
9463 switch (tp->version) {
9464 case RTL_VER_04:
9465 rtl_fw->fw_name = FIRMWARE_8153A_2;
9466 rtl_fw->pre_fw = r8153_pre_firmware_1;
9467 rtl_fw->post_fw = r8153_post_firmware_1;
9468 break;
9469 case RTL_VER_05:
9470 rtl_fw->fw_name = FIRMWARE_8153A_3;
9471 rtl_fw->pre_fw = r8153_pre_firmware_2;
9472 rtl_fw->post_fw = r8153_post_firmware_2;
9473 break;
9474 case RTL_VER_06:
9475 rtl_fw->fw_name = FIRMWARE_8153A_4;
9476 rtl_fw->post_fw = r8153_post_firmware_3;
9477 break;
9478 case RTL_VER_09:
9479 rtl_fw->fw_name = FIRMWARE_8153B_2;
9480 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9481 rtl_fw->post_fw = r8153b_post_firmware_1;
9482 break;
9483 case RTL_VER_11:
9484 rtl_fw->fw_name = FIRMWARE_8156A_2;
9485 rtl_fw->post_fw = r8156a_post_firmware_1;
9486 break;
9487 case RTL_VER_13:
9488 case RTL_VER_15:
9489 rtl_fw->fw_name = FIRMWARE_8156B_2;
9490 break;
9491 case RTL_VER_14:
9492 rtl_fw->fw_name = FIRMWARE_8153C_1;
9493 rtl_fw->pre_fw = r8153b_pre_firmware_1;
9494 rtl_fw->post_fw = r8153c_post_firmware_1;
9495 break;
9496 default:
9497 break;
9498 }
9499
9500 return 0;
9501}
9502
9503u8 rtl8152_get_version(struct usb_interface *intf)
9504{
9505 struct usb_device *udev = interface_to_usbdev(intf);
9506 u32 ocp_data = 0;
9507 __le32 *tmp;
9508 u8 version;
9509 int ret;
9510
9511 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
9512 if (!tmp)
9513 return 0;
9514
9515 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
9516 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
9517 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
9518 if (ret > 0)
9519 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
9520
9521 kfree(tmp);
9522
9523 switch (ocp_data) {
9524 case 0x4c00:
9525 version = RTL_VER_01;
9526 break;
9527 case 0x4c10:
9528 version = RTL_VER_02;
9529 break;
9530 case 0x5c00:
9531 version = RTL_VER_03;
9532 break;
9533 case 0x5c10:
9534 version = RTL_VER_04;
9535 break;
9536 case 0x5c20:
9537 version = RTL_VER_05;
9538 break;
9539 case 0x5c30:
9540 version = RTL_VER_06;
9541 break;
9542 case 0x4800:
9543 version = RTL_VER_07;
9544 break;
9545 case 0x6000:
9546 version = RTL_VER_08;
9547 break;
9548 case 0x6010:
9549 version = RTL_VER_09;
9550 break;
9551 case 0x7010:
9552 version = RTL_TEST_01;
9553 break;
9554 case 0x7020:
9555 version = RTL_VER_10;
9556 break;
9557 case 0x7030:
9558 version = RTL_VER_11;
9559 break;
9560 case 0x7400:
9561 version = RTL_VER_12;
9562 break;
9563 case 0x7410:
9564 version = RTL_VER_13;
9565 break;
9566 case 0x6400:
9567 version = RTL_VER_14;
9568 break;
9569 case 0x7420:
9570 version = RTL_VER_15;
9571 break;
9572 default:
9573 version = RTL_VER_UNKNOWN;
9574 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
9575 break;
9576 }
9577
9578 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
9579
9580 return version;
9581}
9582EXPORT_SYMBOL_GPL(rtl8152_get_version);
9583
9584static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev)
9585{
9586 int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor);
9587 int product_id = le16_to_cpu(udev->descriptor.idProduct);
9588 int vendor_id = le16_to_cpu(udev->descriptor.idVendor);
9589
9590 if (vendor_id == VENDOR_ID_LENOVO) {
9591 switch (product_id) {
9592 case DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB:
9593 case DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK:
9594 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2:
9595 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2:
9596 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3:
9597 case DEVICE_ID_THINKPAD_USB_C_DONGLE:
9598 return 1;
9599 }
9600 } else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) {
9601 switch (product_id) {
9602 case 0x8153:
9603 return 1;
9604 }
9605 }
9606 return 0;
9607}
9608
9609static int rtl8152_probe(struct usb_interface *intf,
9610 const struct usb_device_id *id)
9611{
9612 struct usb_device *udev = interface_to_usbdev(intf);
9613 u8 version = rtl8152_get_version(intf);
9614 struct r8152 *tp;
9615 struct net_device *netdev;
9616 int ret;
9617
9618 if (version == RTL_VER_UNKNOWN)
9619 return -ENODEV;
9620
9621 if (!rtl_vendor_mode(intf))
9622 return -ENODEV;
9623
9624 usb_reset_device(udev);
9625 netdev = alloc_etherdev(sizeof(struct r8152));
9626 if (!netdev) {
9627 dev_err(&intf->dev, "Out of memory\n");
9628 return -ENOMEM;
9629 }
9630
9631 SET_NETDEV_DEV(netdev, &intf->dev);
9632 tp = netdev_priv(netdev);
9633 tp->msg_enable = 0x7FFF;
9634
9635 tp->udev = udev;
9636 tp->netdev = netdev;
9637 tp->intf = intf;
9638 tp->version = version;
9639
9640 tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0);
9641 tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0);
9642 tp->pipe_in = usb_rcvbulkpipe(udev, 1);
9643 tp->pipe_out = usb_sndbulkpipe(udev, 2);
9644 tp->pipe_intr = usb_rcvintpipe(udev, 3);
9645
9646 switch (version) {
9647 case RTL_VER_01:
9648 case RTL_VER_02:
9649 case RTL_VER_07:
9650 tp->mii.supports_gmii = 0;
9651 break;
9652 default:
9653 tp->mii.supports_gmii = 1;
9654 break;
9655 }
9656
9657 ret = rtl_ops_init(tp);
9658 if (ret)
9659 goto out;
9660
9661 rtl_fw_init(tp);
9662
9663 mutex_init(&tp->control);
9664 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
9665 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
9666 tasklet_setup(&tp->tx_tl, bottom_half);
9667 tasklet_disable(&tp->tx_tl);
9668
9669 netdev->netdev_ops = &rtl8152_netdev_ops;
9670 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
9671
9672 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9673 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
9674 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
9675 NETIF_F_HW_VLAN_CTAG_TX;
9676 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
9677 NETIF_F_TSO | NETIF_F_FRAGLIST |
9678 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
9679 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
9680 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
9681 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
9682 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
9683
9684 if (tp->version == RTL_VER_01) {
9685 netdev->features &= ~NETIF_F_RXCSUM;
9686 netdev->hw_features &= ~NETIF_F_RXCSUM;
9687 }
9688
9689 tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev);
9690
9691 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial &&
9692 (!strcmp(udev->serial, "000001000000") ||
9693 !strcmp(udev->serial, "000002000000"))) {
9694 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
9695 tp->dell_tb_rx_agg_bug = 1;
9696 }
9697
9698 netdev->ethtool_ops = &ops;
9699 netif_set_tso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
9700
9701 /* MTU range: 68 - 1500 or 9194 */
9702 netdev->min_mtu = ETH_MIN_MTU;
9703 switch (tp->version) {
9704 case RTL_VER_03:
9705 case RTL_VER_04:
9706 case RTL_VER_05:
9707 case RTL_VER_06:
9708 case RTL_VER_08:
9709 case RTL_VER_09:
9710 case RTL_VER_14:
9711 netdev->max_mtu = size_to_mtu(9 * 1024);
9712 break;
9713 case RTL_VER_10:
9714 case RTL_VER_11:
9715 netdev->max_mtu = size_to_mtu(15 * 1024);
9716 break;
9717 case RTL_VER_12:
9718 case RTL_VER_13:
9719 case RTL_VER_15:
9720 netdev->max_mtu = size_to_mtu(16 * 1024);
9721 break;
9722 case RTL_VER_01:
9723 case RTL_VER_02:
9724 case RTL_VER_07:
9725 default:
9726 netdev->max_mtu = ETH_DATA_LEN;
9727 break;
9728 }
9729
9730 tp->mii.dev = netdev;
9731 tp->mii.mdio_read = read_mii_word;
9732 tp->mii.mdio_write = write_mii_word;
9733 tp->mii.phy_id_mask = 0x3f;
9734 tp->mii.reg_num_mask = 0x1f;
9735 tp->mii.phy_id = R8152_PHY_ID;
9736
9737 tp->autoneg = AUTONEG_ENABLE;
9738 tp->speed = SPEED_100;
9739 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
9740 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
9741 if (tp->mii.supports_gmii) {
9742 if (tp->support_2500full &&
9743 tp->udev->speed >= USB_SPEED_SUPER) {
9744 tp->speed = SPEED_2500;
9745 tp->advertising |= RTL_ADVERTISED_2500_FULL;
9746 } else {
9747 tp->speed = SPEED_1000;
9748 }
9749 tp->advertising |= RTL_ADVERTISED_1000_FULL;
9750 }
9751 tp->duplex = DUPLEX_FULL;
9752
9753 tp->rx_copybreak = RTL8152_RXFG_HEADSZ;
9754 tp->rx_pending = 10 * RTL8152_MAX_RX;
9755
9756 intf->needs_remote_wakeup = 1;
9757
9758 if (!rtl_can_wakeup(tp))
9759 __rtl_set_wol(tp, 0);
9760 else
9761 tp->saved_wolopts = __rtl_get_wol(tp);
9762
9763 tp->rtl_ops.init(tp);
9764#if IS_BUILTIN(CONFIG_USB_RTL8152)
9765 /* Retry in case request_firmware() is not ready yet. */
9766 tp->rtl_fw.retry = true;
9767#endif
9768 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
9769 set_ethernet_addr(tp, false);
9770
9771 usb_set_intfdata(intf, tp);
9772
9773 netif_napi_add_weight(netdev, &tp->napi, r8152_poll,
9774 tp->support_2500full ? 256 : 64);
9775
9776 ret = register_netdev(netdev);
9777 if (ret != 0) {
9778 dev_err(&intf->dev, "couldn't register the device\n");
9779 goto out1;
9780 }
9781
9782 if (tp->saved_wolopts)
9783 device_set_wakeup_enable(&udev->dev, true);
9784 else
9785 device_set_wakeup_enable(&udev->dev, false);
9786
9787 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
9788
9789 return 0;
9790
9791out1:
9792 tasklet_kill(&tp->tx_tl);
9793 usb_set_intfdata(intf, NULL);
9794out:
9795 free_netdev(netdev);
9796 return ret;
9797}
9798
9799static void rtl8152_disconnect(struct usb_interface *intf)
9800{
9801 struct r8152 *tp = usb_get_intfdata(intf);
9802
9803 usb_set_intfdata(intf, NULL);
9804 if (tp) {
9805 rtl_set_unplug(tp);
9806
9807 unregister_netdev(tp->netdev);
9808 tasklet_kill(&tp->tx_tl);
9809 cancel_delayed_work_sync(&tp->hw_phy_work);
9810 if (tp->rtl_ops.unload)
9811 tp->rtl_ops.unload(tp);
9812 rtl8152_release_firmware(tp);
9813 free_netdev(tp->netdev);
9814 }
9815}
9816
9817#define REALTEK_USB_DEVICE(vend, prod) { \
9818 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC), \
9819}, \
9820{ \
9821 USB_DEVICE_AND_INTERFACE_INFO(vend, prod, USB_CLASS_COMM, \
9822 USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE), \
9823}
9824
9825/* table of devices that work with this driver */
9826static const struct usb_device_id rtl8152_table[] = {
9827 /* Realtek */
9828 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050),
9829 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053),
9830 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152),
9831 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153),
9832 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155),
9833 REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156),
9834
9835 /* Microsoft */
9836 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab),
9837 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6),
9838 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927),
9839 REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e),
9840 REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101),
9841 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f),
9842 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3054),
9843 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062),
9844 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069),
9845 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082),
9846 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205),
9847 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c),
9848 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214),
9849 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x721e),
9850 REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387),
9851 REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041),
9852 REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff),
9853 REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601),
9854 {}
9855};
9856
9857MODULE_DEVICE_TABLE(usb, rtl8152_table);
9858
9859static struct usb_driver rtl8152_driver = {
9860 .name = MODULENAME,
9861 .id_table = rtl8152_table,
9862 .probe = rtl8152_probe,
9863 .disconnect = rtl8152_disconnect,
9864 .suspend = rtl8152_suspend,
9865 .resume = rtl8152_resume,
9866 .reset_resume = rtl8152_reset_resume,
9867 .pre_reset = rtl8152_pre_reset,
9868 .post_reset = rtl8152_post_reset,
9869 .supports_autosuspend = 1,
9870 .disable_hub_initiated_lpm = 1,
9871};
9872
9873module_usb_driver(rtl8152_driver);
9874
9875MODULE_AUTHOR(DRIVER_AUTHOR);
9876MODULE_DESCRIPTION(DRIVER_DESC);
9877MODULE_LICENSE("GPL");
9878MODULE_VERSION(DRIVER_VERSION);