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1/*
2 * drivers/net/phy/broadcom.c
3 *
4 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
5 * transceivers.
6 *
7 * Copyright (c) 2006 Maciej W. Rozycki
8 *
9 * Inspired by code written by Amy Fong.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
17#include <linux/module.h>
18#include <linux/phy.h>
19#include <linux/brcmphy.h>
20
21
22#define BRCM_PHY_MODEL(phydev) \
23 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
24
25#define BRCM_PHY_REV(phydev) \
26 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
27
28/*
29 * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
30 * BCM5482, and possibly some others.
31 */
32#define BCM_LED_SRC_LINKSPD1 0x0
33#define BCM_LED_SRC_LINKSPD2 0x1
34#define BCM_LED_SRC_XMITLED 0x2
35#define BCM_LED_SRC_ACTIVITYLED 0x3
36#define BCM_LED_SRC_FDXLED 0x4
37#define BCM_LED_SRC_SLAVE 0x5
38#define BCM_LED_SRC_INTR 0x6
39#define BCM_LED_SRC_QUALITY 0x7
40#define BCM_LED_SRC_RCVLED 0x8
41#define BCM_LED_SRC_MULTICOLOR1 0xa
42#define BCM_LED_SRC_OPENSHORT 0xb
43#define BCM_LED_SRC_OFF 0xe /* Tied high */
44#define BCM_LED_SRC_ON 0xf /* Tied low */
45
46
47/*
48 * BCM5482: Shadow registers
49 * Shadow values go into bits [14:10] of register 0x1c to select a shadow
50 * register to access.
51 */
52/* 00101: Spare Control Register 3 */
53#define BCM54XX_SHD_SCR3 0x05
54#define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
55#define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002
56#define BCM54XX_SHD_SCR3_TRDDAPD 0x0004
57
58/* 01010: Auto Power-Down */
59#define BCM54XX_SHD_APD 0x0a
60#define BCM54XX_SHD_APD_EN 0x0020
61
62#define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */
63 /* LED3 / ~LINKSPD[2] selector */
64#define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
65 /* LED1 / ~LINKSPD[1] selector */
66#define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)
67#define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */
68#define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
69#define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
70#define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
71#define BCM5482_SHD_MODE 0x1f /* 11111: Mode Control Register */
72#define BCM5482_SHD_MODE_1000BX 0x0001 /* Enable 1000BASE-X registers */
73
74
75/*
76 * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)
77 */
78#define MII_BCM54XX_EXP_AADJ1CH0 0x001f
79#define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200
80#define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100
81#define MII_BCM54XX_EXP_AADJ1CH3 0x601f
82#define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002
83#define MII_BCM54XX_EXP_EXP08 0x0F08
84#define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001
85#define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200
86#define MII_BCM54XX_EXP_EXP75 0x0f75
87#define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c
88#define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001
89#define MII_BCM54XX_EXP_EXP96 0x0f96
90#define MII_BCM54XX_EXP_EXP96_MYST 0x0010
91#define MII_BCM54XX_EXP_EXP97 0x0f97
92#define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c
93
94/*
95 * BCM5482: Secondary SerDes registers
96 */
97#define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */
98#define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */
99#define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */
100#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
101#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
102
103
104/*****************************************************************************/
105/* Fast Ethernet Transceiver definitions. */
106/*****************************************************************************/
107
108#define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */
109#define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */
110#define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */
111#define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */
112#define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */
113#define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */
114
115#define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */
116#define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */
117
118
119/*** Shadow register definitions ***/
120
121#define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */
122#define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */
123
124#define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */
125#define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003
126#define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
127
128#define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */
129#define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */
130
131
132MODULE_DESCRIPTION("Broadcom PHY driver");
133MODULE_AUTHOR("Maciej W. Rozycki");
134MODULE_LICENSE("GPL");
135
136/*
137 * Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T
138 * 0x1c shadow registers.
139 */
140static int bcm54xx_shadow_read(struct phy_device *phydev, u16 shadow)
141{
142 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
143 return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
144}
145
146static int bcm54xx_shadow_write(struct phy_device *phydev, u16 shadow, u16 val)
147{
148 return phy_write(phydev, MII_BCM54XX_SHD,
149 MII_BCM54XX_SHD_WRITE |
150 MII_BCM54XX_SHD_VAL(shadow) |
151 MII_BCM54XX_SHD_DATA(val));
152}
153
154/* Indirect register access functions for the Expansion Registers */
155static int bcm54xx_exp_read(struct phy_device *phydev, u16 regnum)
156{
157 int val;
158
159 val = phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
160 if (val < 0)
161 return val;
162
163 val = phy_read(phydev, MII_BCM54XX_EXP_DATA);
164
165 /* Restore default value. It's O.K. if this write fails. */
166 phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
167
168 return val;
169}
170
171static int bcm54xx_exp_write(struct phy_device *phydev, u16 regnum, u16 val)
172{
173 int ret;
174
175 ret = phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
176 if (ret < 0)
177 return ret;
178
179 ret = phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
180
181 /* Restore default value. It's O.K. if this write fails. */
182 phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
183
184 return ret;
185}
186
187static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
188{
189 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
190}
191
192/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
193static int bcm50610_a0_workaround(struct phy_device *phydev)
194{
195 int err;
196
197 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_AADJ1CH0,
198 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
199 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
200 if (err < 0)
201 return err;
202
203 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_AADJ1CH3,
204 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
205 if (err < 0)
206 return err;
207
208 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP75,
209 MII_BCM54XX_EXP_EXP75_VDACCTRL);
210 if (err < 0)
211 return err;
212
213 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP96,
214 MII_BCM54XX_EXP_EXP96_MYST);
215 if (err < 0)
216 return err;
217
218 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP97,
219 MII_BCM54XX_EXP_EXP97_MYST);
220
221 return err;
222}
223
224static int bcm54xx_phydsp_config(struct phy_device *phydev)
225{
226 int err, err2;
227
228 /* Enable the SMDSP clock */
229 err = bcm54xx_auxctl_write(phydev,
230 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
231 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
232 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
233 if (err < 0)
234 return err;
235
236 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
237 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
238 /* Clear bit 9 to fix a phy interop issue. */
239 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP08,
240 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
241 if (err < 0)
242 goto error;
243
244 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
245 err = bcm50610_a0_workaround(phydev);
246 if (err < 0)
247 goto error;
248 }
249 }
250
251 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
252 int val;
253
254 val = bcm54xx_exp_read(phydev, MII_BCM54XX_EXP_EXP75);
255 if (val < 0)
256 goto error;
257
258 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
259 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP75, val);
260 }
261
262error:
263 /* Disable the SMDSP clock */
264 err2 = bcm54xx_auxctl_write(phydev,
265 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
266 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
267
268 /* Return the first error reported. */
269 return err ? err : err2;
270}
271
272static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
273{
274 u32 orig;
275 int val;
276 bool clk125en = true;
277
278 /* Abort if we are using an untested phy. */
279 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
280 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
281 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M)
282 return;
283
284 val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);
285 if (val < 0)
286 return;
287
288 orig = val;
289
290 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
291 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
292 BRCM_PHY_REV(phydev) >= 0x3) {
293 /*
294 * Here, bit 0 _disables_ CLK125 when set.
295 * This bit is set by default.
296 */
297 clk125en = false;
298 } else {
299 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
300 /* Here, bit 0 _enables_ CLK125 when set */
301 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
302 clk125en = false;
303 }
304 }
305
306 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
307 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
308 else
309 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
310
311 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY)
312 val |= BCM54XX_SHD_SCR3_TRDDAPD;
313
314 if (orig != val)
315 bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);
316
317 val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);
318 if (val < 0)
319 return;
320
321 orig = val;
322
323 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
324 val |= BCM54XX_SHD_APD_EN;
325 else
326 val &= ~BCM54XX_SHD_APD_EN;
327
328 if (orig != val)
329 bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);
330}
331
332static int bcm54xx_config_init(struct phy_device *phydev)
333{
334 int reg, err;
335
336 reg = phy_read(phydev, MII_BCM54XX_ECR);
337 if (reg < 0)
338 return reg;
339
340 /* Mask interrupts globally. */
341 reg |= MII_BCM54XX_ECR_IM;
342 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
343 if (err < 0)
344 return err;
345
346 /* Unmask events we are interested in. */
347 reg = ~(MII_BCM54XX_INT_DUPLEX |
348 MII_BCM54XX_INT_SPEED |
349 MII_BCM54XX_INT_LINK);
350 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
351 if (err < 0)
352 return err;
353
354 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
355 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
356 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
357 bcm54xx_shadow_write(phydev, BCM54XX_SHD_RGMII_MODE, 0);
358
359 if ((phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) ||
360 (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) ||
361 (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
362 bcm54xx_adjust_rxrefclk(phydev);
363
364 bcm54xx_phydsp_config(phydev);
365
366 return 0;
367}
368
369static int bcm5482_config_init(struct phy_device *phydev)
370{
371 int err, reg;
372
373 err = bcm54xx_config_init(phydev);
374
375 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
376 /*
377 * Enable secondary SerDes and its use as an LED source
378 */
379 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_SSD);
380 bcm54xx_shadow_write(phydev, BCM5482_SHD_SSD,
381 reg |
382 BCM5482_SHD_SSD_LEDM |
383 BCM5482_SHD_SSD_EN);
384
385 /*
386 * Enable SGMII slave mode and auto-detection
387 */
388 reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
389 err = bcm54xx_exp_read(phydev, reg);
390 if (err < 0)
391 return err;
392 err = bcm54xx_exp_write(phydev, reg, err |
393 BCM5482_SSD_SGMII_SLAVE_EN |
394 BCM5482_SSD_SGMII_SLAVE_AD);
395 if (err < 0)
396 return err;
397
398 /*
399 * Disable secondary SerDes powerdown
400 */
401 reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
402 err = bcm54xx_exp_read(phydev, reg);
403 if (err < 0)
404 return err;
405 err = bcm54xx_exp_write(phydev, reg,
406 err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
407 if (err < 0)
408 return err;
409
410 /*
411 * Select 1000BASE-X register set (primary SerDes)
412 */
413 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_MODE);
414 bcm54xx_shadow_write(phydev, BCM5482_SHD_MODE,
415 reg | BCM5482_SHD_MODE_1000BX);
416
417 /*
418 * LED1=ACTIVITYLED, LED3=LINKSPD[2]
419 * (Use LED1 as secondary SerDes ACTIVITY LED)
420 */
421 bcm54xx_shadow_write(phydev, BCM5482_SHD_LEDS1,
422 BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
423 BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
424
425 /*
426 * Auto-negotiation doesn't seem to work quite right
427 * in this mode, so we disable it and force it to the
428 * right speed/duplex setting. Only 'link status'
429 * is important.
430 */
431 phydev->autoneg = AUTONEG_DISABLE;
432 phydev->speed = SPEED_1000;
433 phydev->duplex = DUPLEX_FULL;
434 }
435
436 return err;
437}
438
439static int bcm5482_read_status(struct phy_device *phydev)
440{
441 int err;
442
443 err = genphy_read_status(phydev);
444
445 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
446 /*
447 * Only link status matters for 1000Base-X mode, so force
448 * 1000 Mbit/s full-duplex status
449 */
450 if (phydev->link) {
451 phydev->speed = SPEED_1000;
452 phydev->duplex = DUPLEX_FULL;
453 }
454 }
455
456 return err;
457}
458
459static int bcm54xx_ack_interrupt(struct phy_device *phydev)
460{
461 int reg;
462
463 /* Clear pending interrupts. */
464 reg = phy_read(phydev, MII_BCM54XX_ISR);
465 if (reg < 0)
466 return reg;
467
468 return 0;
469}
470
471static int bcm54xx_config_intr(struct phy_device *phydev)
472{
473 int reg, err;
474
475 reg = phy_read(phydev, MII_BCM54XX_ECR);
476 if (reg < 0)
477 return reg;
478
479 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
480 reg &= ~MII_BCM54XX_ECR_IM;
481 else
482 reg |= MII_BCM54XX_ECR_IM;
483
484 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
485 return err;
486}
487
488static int bcm5481_config_aneg(struct phy_device *phydev)
489{
490 int ret;
491
492 /* Aneg firsly. */
493 ret = genphy_config_aneg(phydev);
494
495 /* Then we can set up the delay. */
496 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
497 u16 reg;
498
499 /*
500 * There is no BCM5481 specification available, so down
501 * here is everything we know about "register 0x18". This
502 * at least helps BCM5481 to successfully receive packets
503 * on MPC8360E-RDK board. Peter Barada <peterb@logicpd.com>
504 * says: "This sets delay between the RXD and RXC signals
505 * instead of using trace lengths to achieve timing".
506 */
507
508 /* Set RDX clk delay. */
509 reg = 0x7 | (0x7 << 12);
510 phy_write(phydev, 0x18, reg);
511
512 reg = phy_read(phydev, 0x18);
513 /* Set RDX-RXC skew. */
514 reg |= (1 << 8);
515 /* Write bits 14:0. */
516 reg |= (1 << 15);
517 phy_write(phydev, 0x18, reg);
518 }
519
520 return ret;
521}
522
523static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
524{
525 int val;
526
527 val = phy_read(phydev, reg);
528 if (val < 0)
529 return val;
530
531 return phy_write(phydev, reg, val | set);
532}
533
534static int brcm_fet_config_init(struct phy_device *phydev)
535{
536 int reg, err, err2, brcmtest;
537
538 /* Reset the PHY to bring it to a known state. */
539 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
540 if (err < 0)
541 return err;
542
543 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
544 if (reg < 0)
545 return reg;
546
547 /* Unmask events we are interested in and mask interrupts globally. */
548 reg = MII_BRCM_FET_IR_DUPLEX_EN |
549 MII_BRCM_FET_IR_SPEED_EN |
550 MII_BRCM_FET_IR_LINK_EN |
551 MII_BRCM_FET_IR_ENABLE |
552 MII_BRCM_FET_IR_MASK;
553
554 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
555 if (err < 0)
556 return err;
557
558 /* Enable shadow register access */
559 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
560 if (brcmtest < 0)
561 return brcmtest;
562
563 reg = brcmtest | MII_BRCM_FET_BT_SRE;
564
565 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
566 if (err < 0)
567 return err;
568
569 /* Set the LED mode */
570 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
571 if (reg < 0) {
572 err = reg;
573 goto done;
574 }
575
576 reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
577 reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
578
579 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
580 if (err < 0)
581 goto done;
582
583 /* Enable auto MDIX */
584 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
585 MII_BRCM_FET_SHDW_MC_FAME);
586 if (err < 0)
587 goto done;
588
589 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
590 /* Enable auto power down */
591 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
592 MII_BRCM_FET_SHDW_AS2_APDE);
593 }
594
595done:
596 /* Disable shadow register access */
597 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
598 if (!err)
599 err = err2;
600
601 return err;
602}
603
604static int brcm_fet_ack_interrupt(struct phy_device *phydev)
605{
606 int reg;
607
608 /* Clear pending interrupts. */
609 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
610 if (reg < 0)
611 return reg;
612
613 return 0;
614}
615
616static int brcm_fet_config_intr(struct phy_device *phydev)
617{
618 int reg, err;
619
620 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
621 if (reg < 0)
622 return reg;
623
624 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
625 reg &= ~MII_BRCM_FET_IR_MASK;
626 else
627 reg |= MII_BRCM_FET_IR_MASK;
628
629 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
630 return err;
631}
632
633static struct phy_driver broadcom_drivers[] = {
634{
635 .phy_id = PHY_ID_BCM5411,
636 .phy_id_mask = 0xfffffff0,
637 .name = "Broadcom BCM5411",
638 .features = PHY_GBIT_FEATURES |
639 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
640 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
641 .config_init = bcm54xx_config_init,
642 .config_aneg = genphy_config_aneg,
643 .read_status = genphy_read_status,
644 .ack_interrupt = bcm54xx_ack_interrupt,
645 .config_intr = bcm54xx_config_intr,
646 .driver = { .owner = THIS_MODULE },
647}, {
648 .phy_id = PHY_ID_BCM5421,
649 .phy_id_mask = 0xfffffff0,
650 .name = "Broadcom BCM5421",
651 .features = PHY_GBIT_FEATURES |
652 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
653 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
654 .config_init = bcm54xx_config_init,
655 .config_aneg = genphy_config_aneg,
656 .read_status = genphy_read_status,
657 .ack_interrupt = bcm54xx_ack_interrupt,
658 .config_intr = bcm54xx_config_intr,
659 .driver = { .owner = THIS_MODULE },
660}, {
661 .phy_id = PHY_ID_BCM5461,
662 .phy_id_mask = 0xfffffff0,
663 .name = "Broadcom BCM5461",
664 .features = PHY_GBIT_FEATURES |
665 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
666 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
667 .config_init = bcm54xx_config_init,
668 .config_aneg = genphy_config_aneg,
669 .read_status = genphy_read_status,
670 .ack_interrupt = bcm54xx_ack_interrupt,
671 .config_intr = bcm54xx_config_intr,
672 .driver = { .owner = THIS_MODULE },
673}, {
674 .phy_id = PHY_ID_BCM5464,
675 .phy_id_mask = 0xfffffff0,
676 .name = "Broadcom BCM5464",
677 .features = PHY_GBIT_FEATURES |
678 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
679 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
680 .config_init = bcm54xx_config_init,
681 .config_aneg = genphy_config_aneg,
682 .read_status = genphy_read_status,
683 .ack_interrupt = bcm54xx_ack_interrupt,
684 .config_intr = bcm54xx_config_intr,
685 .driver = { .owner = THIS_MODULE },
686}, {
687 .phy_id = PHY_ID_BCM5481,
688 .phy_id_mask = 0xfffffff0,
689 .name = "Broadcom BCM5481",
690 .features = PHY_GBIT_FEATURES |
691 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
692 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
693 .config_init = bcm54xx_config_init,
694 .config_aneg = bcm5481_config_aneg,
695 .read_status = genphy_read_status,
696 .ack_interrupt = bcm54xx_ack_interrupt,
697 .config_intr = bcm54xx_config_intr,
698 .driver = { .owner = THIS_MODULE },
699}, {
700 .phy_id = PHY_ID_BCM5482,
701 .phy_id_mask = 0xfffffff0,
702 .name = "Broadcom BCM5482",
703 .features = PHY_GBIT_FEATURES |
704 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
705 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
706 .config_init = bcm5482_config_init,
707 .config_aneg = genphy_config_aneg,
708 .read_status = bcm5482_read_status,
709 .ack_interrupt = bcm54xx_ack_interrupt,
710 .config_intr = bcm54xx_config_intr,
711 .driver = { .owner = THIS_MODULE },
712}, {
713 .phy_id = PHY_ID_BCM50610,
714 .phy_id_mask = 0xfffffff0,
715 .name = "Broadcom BCM50610",
716 .features = PHY_GBIT_FEATURES |
717 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
718 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
719 .config_init = bcm54xx_config_init,
720 .config_aneg = genphy_config_aneg,
721 .read_status = genphy_read_status,
722 .ack_interrupt = bcm54xx_ack_interrupt,
723 .config_intr = bcm54xx_config_intr,
724 .driver = { .owner = THIS_MODULE },
725}, {
726 .phy_id = PHY_ID_BCM50610M,
727 .phy_id_mask = 0xfffffff0,
728 .name = "Broadcom BCM50610M",
729 .features = PHY_GBIT_FEATURES |
730 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
731 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
732 .config_init = bcm54xx_config_init,
733 .config_aneg = genphy_config_aneg,
734 .read_status = genphy_read_status,
735 .ack_interrupt = bcm54xx_ack_interrupt,
736 .config_intr = bcm54xx_config_intr,
737 .driver = { .owner = THIS_MODULE },
738}, {
739 .phy_id = PHY_ID_BCM57780,
740 .phy_id_mask = 0xfffffff0,
741 .name = "Broadcom BCM57780",
742 .features = PHY_GBIT_FEATURES |
743 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
744 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
745 .config_init = bcm54xx_config_init,
746 .config_aneg = genphy_config_aneg,
747 .read_status = genphy_read_status,
748 .ack_interrupt = bcm54xx_ack_interrupt,
749 .config_intr = bcm54xx_config_intr,
750 .driver = { .owner = THIS_MODULE },
751}, {
752 .phy_id = PHY_ID_BCMAC131,
753 .phy_id_mask = 0xfffffff0,
754 .name = "Broadcom BCMAC131",
755 .features = PHY_BASIC_FEATURES |
756 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
757 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
758 .config_init = brcm_fet_config_init,
759 .config_aneg = genphy_config_aneg,
760 .read_status = genphy_read_status,
761 .ack_interrupt = brcm_fet_ack_interrupt,
762 .config_intr = brcm_fet_config_intr,
763 .driver = { .owner = THIS_MODULE },
764}, {
765 .phy_id = PHY_ID_BCM5241,
766 .phy_id_mask = 0xfffffff0,
767 .name = "Broadcom BCM5241",
768 .features = PHY_BASIC_FEATURES |
769 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
770 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
771 .config_init = brcm_fet_config_init,
772 .config_aneg = genphy_config_aneg,
773 .read_status = genphy_read_status,
774 .ack_interrupt = brcm_fet_ack_interrupt,
775 .config_intr = brcm_fet_config_intr,
776 .driver = { .owner = THIS_MODULE },
777} };
778
779static int __init broadcom_init(void)
780{
781 return phy_drivers_register(broadcom_drivers,
782 ARRAY_SIZE(broadcom_drivers));
783}
784
785static void __exit broadcom_exit(void)
786{
787 phy_drivers_unregister(broadcom_drivers,
788 ARRAY_SIZE(broadcom_drivers));
789}
790
791module_init(broadcom_init);
792module_exit(broadcom_exit);
793
794static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
795 { PHY_ID_BCM5411, 0xfffffff0 },
796 { PHY_ID_BCM5421, 0xfffffff0 },
797 { PHY_ID_BCM5461, 0xfffffff0 },
798 { PHY_ID_BCM5464, 0xfffffff0 },
799 { PHY_ID_BCM5482, 0xfffffff0 },
800 { PHY_ID_BCM5482, 0xfffffff0 },
801 { PHY_ID_BCM50610, 0xfffffff0 },
802 { PHY_ID_BCM50610M, 0xfffffff0 },
803 { PHY_ID_BCM57780, 0xfffffff0 },
804 { PHY_ID_BCMAC131, 0xfffffff0 },
805 { PHY_ID_BCM5241, 0xfffffff0 },
806 { }
807};
808
809MODULE_DEVICE_TABLE(mdio, broadcom_tbl);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/broadcom.c
4 *
5 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
6 * transceivers.
7 *
8 * Copyright (c) 2006 Maciej W. Rozycki
9 *
10 * Inspired by code written by Amy Fong.
11 */
12
13#include "bcm-phy-lib.h"
14#include <linux/delay.h>
15#include <linux/module.h>
16#include <linux/phy.h>
17#include <linux/brcmphy.h>
18#include <linux/of.h>
19
20#define BRCM_PHY_MODEL(phydev) \
21 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
22
23#define BRCM_PHY_REV(phydev) \
24 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
25
26MODULE_DESCRIPTION("Broadcom PHY driver");
27MODULE_AUTHOR("Maciej W. Rozycki");
28MODULE_LICENSE("GPL");
29
30struct bcm54xx_phy_priv {
31 u64 *stats;
32 struct bcm_ptp_private *ptp;
33};
34
35static int bcm54xx_config_clock_delay(struct phy_device *phydev)
36{
37 int rc, val;
38
39 /* handling PHY's internal RX clock delay */
40 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
41 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
42 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
43 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
44 /* Disable RGMII RXC-RXD skew */
45 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
46 }
47 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
48 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
49 /* Enable RGMII RXC-RXD skew */
50 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
51 }
52 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
53 val);
54 if (rc < 0)
55 return rc;
56
57 /* handling PHY's internal TX clock delay */
58 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
59 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
60 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
61 /* Disable internal TX clock delay */
62 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
63 }
64 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
65 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
66 /* Enable internal TX clock delay */
67 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
68 }
69 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
70 if (rc < 0)
71 return rc;
72
73 return 0;
74}
75
76static int bcm54210e_config_init(struct phy_device *phydev)
77{
78 int val;
79
80 bcm54xx_config_clock_delay(phydev);
81
82 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
83 val = phy_read(phydev, MII_CTRL1000);
84 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
85 phy_write(phydev, MII_CTRL1000, val);
86 }
87
88 return 0;
89}
90
91static int bcm54612e_config_init(struct phy_device *phydev)
92{
93 int reg;
94
95 bcm54xx_config_clock_delay(phydev);
96
97 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
98 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
99 int err;
100
101 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
102 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
103 BCM54612E_LED4_CLK125OUT_EN | reg);
104
105 if (err < 0)
106 return err;
107 }
108
109 return 0;
110}
111
112static int bcm54616s_config_init(struct phy_device *phydev)
113{
114 int rc, val;
115
116 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
117 phydev->interface != PHY_INTERFACE_MODE_1000BASEX)
118 return 0;
119
120 /* Ensure proper interface mode is selected. */
121 /* Disable RGMII mode */
122 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
123 if (val < 0)
124 return val;
125 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN;
126 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
127 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
128 val);
129 if (rc < 0)
130 return rc;
131
132 /* Select 1000BASE-X register set (primary SerDes) */
133 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
134 if (val < 0)
135 return val;
136 val |= BCM54XX_SHD_MODE_1000BX;
137 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
138 if (rc < 0)
139 return rc;
140
141 /* Power down SerDes interface */
142 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
143 if (rc < 0)
144 return rc;
145
146 /* Select proper interface mode */
147 val &= ~BCM54XX_SHD_INTF_SEL_MASK;
148 val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ?
149 BCM54XX_SHD_INTF_SEL_SGMII :
150 BCM54XX_SHD_INTF_SEL_GBIC;
151 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
152 if (rc < 0)
153 return rc;
154
155 /* Power up SerDes interface */
156 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
157 if (rc < 0)
158 return rc;
159
160 /* Select copper register set */
161 val &= ~BCM54XX_SHD_MODE_1000BX;
162 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
163 if (rc < 0)
164 return rc;
165
166 /* Power up copper interface */
167 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
168}
169
170/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
171static int bcm50610_a0_workaround(struct phy_device *phydev)
172{
173 int err;
174
175 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
176 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
177 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
178 if (err < 0)
179 return err;
180
181 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
182 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
183 if (err < 0)
184 return err;
185
186 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
187 MII_BCM54XX_EXP_EXP75_VDACCTRL);
188 if (err < 0)
189 return err;
190
191 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
192 MII_BCM54XX_EXP_EXP96_MYST);
193 if (err < 0)
194 return err;
195
196 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
197 MII_BCM54XX_EXP_EXP97_MYST);
198
199 return err;
200}
201
202static int bcm54xx_phydsp_config(struct phy_device *phydev)
203{
204 int err, err2;
205
206 /* Enable the SMDSP clock */
207 err = bcm54xx_auxctl_write(phydev,
208 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
209 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
210 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
211 if (err < 0)
212 return err;
213
214 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
215 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
216 /* Clear bit 9 to fix a phy interop issue. */
217 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
218 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
219 if (err < 0)
220 goto error;
221
222 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
223 err = bcm50610_a0_workaround(phydev);
224 if (err < 0)
225 goto error;
226 }
227 }
228
229 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
230 int val;
231
232 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
233 if (val < 0)
234 goto error;
235
236 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
237 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
238 }
239
240error:
241 /* Disable the SMDSP clock */
242 err2 = bcm54xx_auxctl_write(phydev,
243 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
244 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
245
246 /* Return the first error reported. */
247 return err ? err : err2;
248}
249
250static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
251{
252 u32 orig;
253 int val;
254 bool clk125en = true;
255
256 /* Abort if we are using an untested phy. */
257 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
258 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
259 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M &&
260 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54210E &&
261 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 &&
262 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811)
263 return;
264
265 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
266 if (val < 0)
267 return;
268
269 orig = val;
270
271 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
272 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
273 BRCM_PHY_REV(phydev) >= 0x3) {
274 /*
275 * Here, bit 0 _disables_ CLK125 when set.
276 * This bit is set by default.
277 */
278 clk125en = false;
279 } else {
280 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
281 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) {
282 /* Here, bit 0 _enables_ CLK125 when set */
283 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
284 }
285 clk125en = false;
286 }
287 }
288
289 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
290 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
291 else
292 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
293
294 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) {
295 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E ||
296 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 ||
297 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811)
298 val |= BCM54XX_SHD_SCR3_RXCTXC_DIS;
299 else
300 val |= BCM54XX_SHD_SCR3_TRDDAPD;
301 }
302
303 if (orig != val)
304 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
305
306 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
307 if (val < 0)
308 return;
309
310 orig = val;
311
312 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
313 val |= BCM54XX_SHD_APD_EN;
314 else
315 val &= ~BCM54XX_SHD_APD_EN;
316
317 if (orig != val)
318 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
319}
320
321static void bcm54xx_ptp_stop(struct phy_device *phydev)
322{
323 struct bcm54xx_phy_priv *priv = phydev->priv;
324
325 if (priv->ptp)
326 bcm_ptp_stop(priv->ptp);
327}
328
329static void bcm54xx_ptp_config_init(struct phy_device *phydev)
330{
331 struct bcm54xx_phy_priv *priv = phydev->priv;
332
333 if (priv->ptp)
334 bcm_ptp_config_init(phydev);
335}
336
337static int bcm54xx_config_init(struct phy_device *phydev)
338{
339 int reg, err, val;
340
341 reg = phy_read(phydev, MII_BCM54XX_ECR);
342 if (reg < 0)
343 return reg;
344
345 /* Mask interrupts globally. */
346 reg |= MII_BCM54XX_ECR_IM;
347 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
348 if (err < 0)
349 return err;
350
351 /* Unmask events we are interested in. */
352 reg = ~(MII_BCM54XX_INT_DUPLEX |
353 MII_BCM54XX_INT_SPEED |
354 MII_BCM54XX_INT_LINK);
355 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
356 if (err < 0)
357 return err;
358
359 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
360 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
361 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
362 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
363
364 bcm54xx_adjust_rxrefclk(phydev);
365
366 switch (BRCM_PHY_MODEL(phydev)) {
367 case PHY_ID_BCM50610:
368 case PHY_ID_BCM50610M:
369 err = bcm54xx_config_clock_delay(phydev);
370 break;
371 case PHY_ID_BCM54210E:
372 err = bcm54210e_config_init(phydev);
373 break;
374 case PHY_ID_BCM54612E:
375 err = bcm54612e_config_init(phydev);
376 break;
377 case PHY_ID_BCM54616S:
378 err = bcm54616s_config_init(phydev);
379 break;
380 case PHY_ID_BCM54810:
381 /* For BCM54810, we need to disable BroadR-Reach function */
382 val = bcm_phy_read_exp(phydev,
383 BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
384 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
385 err = bcm_phy_write_exp(phydev,
386 BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
387 val);
388 break;
389 }
390 if (err)
391 return err;
392
393 bcm54xx_phydsp_config(phydev);
394
395 /* For non-SFP setups, encode link speed into LED1 and LED3 pair
396 * (green/amber).
397 * Also flash these two LEDs on activity. This means configuring
398 * them for MULTICOLOR and encoding link/activity into them.
399 * Don't do this for devices on an SFP module, since some of these
400 * use the LED outputs to control the SFP LOS signal, and changing
401 * these settings will cause LOS to malfunction.
402 */
403 if (!phy_on_sfp(phydev)) {
404 val = BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) |
405 BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1);
406 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, val);
407
408 val = BCM_LED_MULTICOLOR_IN_PHASE |
409 BCM5482_SHD_LEDS1_LED1(BCM_LED_MULTICOLOR_LINK_ACT) |
410 BCM5482_SHD_LEDS1_LED3(BCM_LED_MULTICOLOR_LINK_ACT);
411 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val);
412 }
413
414 bcm54xx_ptp_config_init(phydev);
415
416 return 0;
417}
418
419static int bcm54xx_iddq_set(struct phy_device *phydev, bool enable)
420{
421 int ret = 0;
422
423 if (!(phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND))
424 return ret;
425
426 ret = bcm_phy_read_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL);
427 if (ret < 0)
428 goto out;
429
430 if (enable)
431 ret |= BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP;
432 else
433 ret &= ~(BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP);
434
435 ret = bcm_phy_write_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL, ret);
436out:
437 return ret;
438}
439
440static int bcm54xx_suspend(struct phy_device *phydev)
441{
442 int ret;
443
444 bcm54xx_ptp_stop(phydev);
445
446 /* We cannot use a read/modify/write here otherwise the PHY gets into
447 * a bad state where its LEDs keep flashing, thus defeating the purpose
448 * of low power mode.
449 */
450 ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN);
451 if (ret < 0)
452 return ret;
453
454 return bcm54xx_iddq_set(phydev, true);
455}
456
457static int bcm54xx_resume(struct phy_device *phydev)
458{
459 int ret;
460
461 ret = bcm54xx_iddq_set(phydev, false);
462 if (ret < 0)
463 return ret;
464
465 /* Writes to register other than BMCR would be ignored
466 * unless we clear the PDOWN bit first
467 */
468 ret = genphy_resume(phydev);
469 if (ret < 0)
470 return ret;
471
472 /* Upon exiting power down, the PHY remains in an internal reset state
473 * for 40us
474 */
475 fsleep(40);
476
477 /* Issue a soft reset after clearing the power down bit
478 * and before doing any other configuration.
479 */
480 if (phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND) {
481 ret = genphy_soft_reset(phydev);
482 if (ret < 0)
483 return ret;
484 }
485
486 return bcm54xx_config_init(phydev);
487}
488
489static int bcm54811_config_init(struct phy_device *phydev)
490{
491 int err, reg;
492
493 /* Disable BroadR-Reach function. */
494 reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
495 reg &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
496 err = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
497 reg);
498 if (err < 0)
499 return err;
500
501 err = bcm54xx_config_init(phydev);
502
503 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
504 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
505 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
506 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
507 BCM54612E_LED4_CLK125OUT_EN | reg);
508 if (err < 0)
509 return err;
510 }
511
512 return err;
513}
514
515static int bcm5481_config_aneg(struct phy_device *phydev)
516{
517 struct device_node *np = phydev->mdio.dev.of_node;
518 int ret;
519
520 /* Aneg firstly. */
521 ret = genphy_config_aneg(phydev);
522
523 /* Then we can set up the delay. */
524 bcm54xx_config_clock_delay(phydev);
525
526 if (of_property_read_bool(np, "enet-phy-lane-swap")) {
527 /* Lane Swap - Undocumented register...magic! */
528 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
529 0x11B);
530 if (ret < 0)
531 return ret;
532 }
533
534 return ret;
535}
536
537struct bcm54616s_phy_priv {
538 bool mode_1000bx_en;
539};
540
541static int bcm54616s_probe(struct phy_device *phydev)
542{
543 struct bcm54616s_phy_priv *priv;
544 int val;
545
546 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
547 if (!priv)
548 return -ENOMEM;
549
550 phydev->priv = priv;
551
552 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
553 if (val < 0)
554 return val;
555
556 /* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0]
557 * is 01b, and the link between PHY and its link partner can be
558 * either 1000Base-X or 100Base-FX.
559 * RGMII-1000Base-X is properly supported, but RGMII-100Base-FX
560 * support is still missing as of now.
561 */
562 if ((val & BCM54XX_SHD_INTF_SEL_MASK) == BCM54XX_SHD_INTF_SEL_RGMII) {
563 val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
564 if (val < 0)
565 return val;
566
567 /* Bit 0 of the SerDes 100-FX Control register, when set
568 * to 1, sets the MII/RGMII -> 100BASE-FX configuration.
569 * When this bit is set to 0, it sets the GMII/RGMII ->
570 * 1000BASE-X configuration.
571 */
572 if (!(val & BCM54616S_100FX_MODE))
573 priv->mode_1000bx_en = true;
574
575 phydev->port = PORT_FIBRE;
576 }
577
578 return 0;
579}
580
581static int bcm54616s_config_aneg(struct phy_device *phydev)
582{
583 struct bcm54616s_phy_priv *priv = phydev->priv;
584 int ret;
585
586 /* Aneg firstly. */
587 if (priv->mode_1000bx_en)
588 ret = genphy_c37_config_aneg(phydev);
589 else
590 ret = genphy_config_aneg(phydev);
591
592 /* Then we can set up the delay. */
593 bcm54xx_config_clock_delay(phydev);
594
595 return ret;
596}
597
598static int bcm54616s_read_status(struct phy_device *phydev)
599{
600 struct bcm54616s_phy_priv *priv = phydev->priv;
601 int err;
602
603 if (priv->mode_1000bx_en)
604 err = genphy_c37_read_status(phydev);
605 else
606 err = genphy_read_status(phydev);
607
608 return err;
609}
610
611static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
612{
613 int val;
614
615 val = phy_read(phydev, reg);
616 if (val < 0)
617 return val;
618
619 return phy_write(phydev, reg, val | set);
620}
621
622static int brcm_fet_config_init(struct phy_device *phydev)
623{
624 int reg, err, err2, brcmtest;
625
626 /* Reset the PHY to bring it to a known state. */
627 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
628 if (err < 0)
629 return err;
630
631 /* The datasheet indicates the PHY needs up to 1us to complete a reset,
632 * build some slack here.
633 */
634 usleep_range(1000, 2000);
635
636 /* The PHY requires 65 MDC clock cycles to complete a write operation
637 * and turnaround the line properly.
638 *
639 * We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac)
640 * may flag the lack of turn-around as a read failure. This is
641 * particularly true with this combination since the MDIO controller
642 * only used 64 MDC cycles. This is not a critical failure in this
643 * specific case and it has no functional impact otherwise, so we let
644 * that one go through. If there is a genuine bus error, the next read
645 * of MII_BRCM_FET_INTREG will error out.
646 */
647 err = phy_read(phydev, MII_BMCR);
648 if (err < 0 && err != -EIO)
649 return err;
650
651 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
652 if (reg < 0)
653 return reg;
654
655 /* Unmask events we are interested in and mask interrupts globally. */
656 reg = MII_BRCM_FET_IR_DUPLEX_EN |
657 MII_BRCM_FET_IR_SPEED_EN |
658 MII_BRCM_FET_IR_LINK_EN |
659 MII_BRCM_FET_IR_ENABLE |
660 MII_BRCM_FET_IR_MASK;
661
662 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
663 if (err < 0)
664 return err;
665
666 /* Enable shadow register access */
667 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
668 if (brcmtest < 0)
669 return brcmtest;
670
671 reg = brcmtest | MII_BRCM_FET_BT_SRE;
672
673 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
674 if (err < 0)
675 return err;
676
677 /* Set the LED mode */
678 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
679 if (reg < 0) {
680 err = reg;
681 goto done;
682 }
683
684 reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
685 reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
686
687 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
688 if (err < 0)
689 goto done;
690
691 /* Enable auto MDIX */
692 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
693 MII_BRCM_FET_SHDW_MC_FAME);
694 if (err < 0)
695 goto done;
696
697 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
698 /* Enable auto power down */
699 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
700 MII_BRCM_FET_SHDW_AS2_APDE);
701 }
702
703done:
704 /* Disable shadow register access */
705 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
706 if (!err)
707 err = err2;
708
709 return err;
710}
711
712static int brcm_fet_ack_interrupt(struct phy_device *phydev)
713{
714 int reg;
715
716 /* Clear pending interrupts. */
717 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
718 if (reg < 0)
719 return reg;
720
721 return 0;
722}
723
724static int brcm_fet_config_intr(struct phy_device *phydev)
725{
726 int reg, err;
727
728 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
729 if (reg < 0)
730 return reg;
731
732 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
733 err = brcm_fet_ack_interrupt(phydev);
734 if (err)
735 return err;
736
737 reg &= ~MII_BRCM_FET_IR_MASK;
738 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
739 } else {
740 reg |= MII_BRCM_FET_IR_MASK;
741 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
742 if (err)
743 return err;
744
745 err = brcm_fet_ack_interrupt(phydev);
746 }
747
748 return err;
749}
750
751static irqreturn_t brcm_fet_handle_interrupt(struct phy_device *phydev)
752{
753 int irq_status;
754
755 irq_status = phy_read(phydev, MII_BRCM_FET_INTREG);
756 if (irq_status < 0) {
757 phy_error(phydev);
758 return IRQ_NONE;
759 }
760
761 if (irq_status == 0)
762 return IRQ_NONE;
763
764 phy_trigger_machine(phydev);
765
766 return IRQ_HANDLED;
767}
768
769static int brcm_fet_suspend(struct phy_device *phydev)
770{
771 int reg, err, err2, brcmtest;
772
773 /* We cannot use a read/modify/write here otherwise the PHY continues
774 * to drive LEDs which defeats the purpose of low power mode.
775 */
776 err = phy_write(phydev, MII_BMCR, BMCR_PDOWN);
777 if (err < 0)
778 return err;
779
780 /* Enable shadow register access */
781 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
782 if (brcmtest < 0)
783 return brcmtest;
784
785 reg = brcmtest | MII_BRCM_FET_BT_SRE;
786
787 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
788 if (err < 0)
789 return err;
790
791 /* Set standby mode */
792 err = phy_modify(phydev, MII_BRCM_FET_SHDW_AUXMODE4,
793 MII_BRCM_FET_SHDW_AM4_STANDBY,
794 MII_BRCM_FET_SHDW_AM4_STANDBY);
795
796 /* Disable shadow register access */
797 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
798 if (!err)
799 err = err2;
800
801 return err;
802}
803
804static int bcm54xx_phy_probe(struct phy_device *phydev)
805{
806 struct bcm54xx_phy_priv *priv;
807
808 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
809 if (!priv)
810 return -ENOMEM;
811
812 phydev->priv = priv;
813
814 priv->stats = devm_kcalloc(&phydev->mdio.dev,
815 bcm_phy_get_sset_count(phydev), sizeof(u64),
816 GFP_KERNEL);
817 if (!priv->stats)
818 return -ENOMEM;
819
820 priv->ptp = bcm_ptp_probe(phydev);
821 if (IS_ERR(priv->ptp))
822 return PTR_ERR(priv->ptp);
823
824 return 0;
825}
826
827static void bcm54xx_get_stats(struct phy_device *phydev,
828 struct ethtool_stats *stats, u64 *data)
829{
830 struct bcm54xx_phy_priv *priv = phydev->priv;
831
832 bcm_phy_get_stats(phydev, priv->stats, stats, data);
833}
834
835static void bcm54xx_link_change_notify(struct phy_device *phydev)
836{
837 u16 mask = MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE |
838 MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE;
839 int ret;
840
841 if (phydev->state != PHY_RUNNING)
842 return;
843
844 /* Don't change the DAC wake settings if auto power down
845 * is not requested.
846 */
847 if (!(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
848 return;
849
850 ret = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP08);
851 if (ret < 0)
852 return;
853
854 /* Enable/disable 10BaseT auto and forced early DAC wake depending
855 * on the negotiated speed, those settings should only be done
856 * for 10Mbits/sec.
857 */
858 if (phydev->speed == SPEED_10)
859 ret |= mask;
860 else
861 ret &= ~mask;
862 bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, ret);
863}
864
865static struct phy_driver broadcom_drivers[] = {
866{
867 .phy_id = PHY_ID_BCM5411,
868 .phy_id_mask = 0xfffffff0,
869 .name = "Broadcom BCM5411",
870 /* PHY_GBIT_FEATURES */
871 .get_sset_count = bcm_phy_get_sset_count,
872 .get_strings = bcm_phy_get_strings,
873 .get_stats = bcm54xx_get_stats,
874 .probe = bcm54xx_phy_probe,
875 .config_init = bcm54xx_config_init,
876 .config_intr = bcm_phy_config_intr,
877 .handle_interrupt = bcm_phy_handle_interrupt,
878 .link_change_notify = bcm54xx_link_change_notify,
879}, {
880 .phy_id = PHY_ID_BCM5421,
881 .phy_id_mask = 0xfffffff0,
882 .name = "Broadcom BCM5421",
883 /* PHY_GBIT_FEATURES */
884 .get_sset_count = bcm_phy_get_sset_count,
885 .get_strings = bcm_phy_get_strings,
886 .get_stats = bcm54xx_get_stats,
887 .probe = bcm54xx_phy_probe,
888 .config_init = bcm54xx_config_init,
889 .config_intr = bcm_phy_config_intr,
890 .handle_interrupt = bcm_phy_handle_interrupt,
891 .link_change_notify = bcm54xx_link_change_notify,
892}, {
893 .phy_id = PHY_ID_BCM54210E,
894 .phy_id_mask = 0xfffffff0,
895 .name = "Broadcom BCM54210E",
896 /* PHY_GBIT_FEATURES */
897 .get_sset_count = bcm_phy_get_sset_count,
898 .get_strings = bcm_phy_get_strings,
899 .get_stats = bcm54xx_get_stats,
900 .probe = bcm54xx_phy_probe,
901 .config_init = bcm54xx_config_init,
902 .config_intr = bcm_phy_config_intr,
903 .handle_interrupt = bcm_phy_handle_interrupt,
904 .link_change_notify = bcm54xx_link_change_notify,
905 .suspend = bcm54xx_suspend,
906 .resume = bcm54xx_resume,
907}, {
908 .phy_id = PHY_ID_BCM5461,
909 .phy_id_mask = 0xfffffff0,
910 .name = "Broadcom BCM5461",
911 /* PHY_GBIT_FEATURES */
912 .get_sset_count = bcm_phy_get_sset_count,
913 .get_strings = bcm_phy_get_strings,
914 .get_stats = bcm54xx_get_stats,
915 .probe = bcm54xx_phy_probe,
916 .config_init = bcm54xx_config_init,
917 .config_intr = bcm_phy_config_intr,
918 .handle_interrupt = bcm_phy_handle_interrupt,
919 .link_change_notify = bcm54xx_link_change_notify,
920}, {
921 .phy_id = PHY_ID_BCM54612E,
922 .phy_id_mask = 0xfffffff0,
923 .name = "Broadcom BCM54612E",
924 /* PHY_GBIT_FEATURES */
925 .get_sset_count = bcm_phy_get_sset_count,
926 .get_strings = bcm_phy_get_strings,
927 .get_stats = bcm54xx_get_stats,
928 .probe = bcm54xx_phy_probe,
929 .config_init = bcm54xx_config_init,
930 .config_intr = bcm_phy_config_intr,
931 .handle_interrupt = bcm_phy_handle_interrupt,
932 .link_change_notify = bcm54xx_link_change_notify,
933}, {
934 .phy_id = PHY_ID_BCM54616S,
935 .phy_id_mask = 0xfffffff0,
936 .name = "Broadcom BCM54616S",
937 /* PHY_GBIT_FEATURES */
938 .soft_reset = genphy_soft_reset,
939 .config_init = bcm54xx_config_init,
940 .config_aneg = bcm54616s_config_aneg,
941 .config_intr = bcm_phy_config_intr,
942 .handle_interrupt = bcm_phy_handle_interrupt,
943 .read_status = bcm54616s_read_status,
944 .probe = bcm54616s_probe,
945 .link_change_notify = bcm54xx_link_change_notify,
946}, {
947 .phy_id = PHY_ID_BCM5464,
948 .phy_id_mask = 0xfffffff0,
949 .name = "Broadcom BCM5464",
950 /* PHY_GBIT_FEATURES */
951 .get_sset_count = bcm_phy_get_sset_count,
952 .get_strings = bcm_phy_get_strings,
953 .get_stats = bcm54xx_get_stats,
954 .probe = bcm54xx_phy_probe,
955 .config_init = bcm54xx_config_init,
956 .config_intr = bcm_phy_config_intr,
957 .handle_interrupt = bcm_phy_handle_interrupt,
958 .suspend = genphy_suspend,
959 .resume = genphy_resume,
960 .link_change_notify = bcm54xx_link_change_notify,
961}, {
962 .phy_id = PHY_ID_BCM5481,
963 .phy_id_mask = 0xfffffff0,
964 .name = "Broadcom BCM5481",
965 /* PHY_GBIT_FEATURES */
966 .get_sset_count = bcm_phy_get_sset_count,
967 .get_strings = bcm_phy_get_strings,
968 .get_stats = bcm54xx_get_stats,
969 .probe = bcm54xx_phy_probe,
970 .config_init = bcm54xx_config_init,
971 .config_aneg = bcm5481_config_aneg,
972 .config_intr = bcm_phy_config_intr,
973 .handle_interrupt = bcm_phy_handle_interrupt,
974 .link_change_notify = bcm54xx_link_change_notify,
975}, {
976 .phy_id = PHY_ID_BCM54810,
977 .phy_id_mask = 0xfffffff0,
978 .name = "Broadcom BCM54810",
979 /* PHY_GBIT_FEATURES */
980 .get_sset_count = bcm_phy_get_sset_count,
981 .get_strings = bcm_phy_get_strings,
982 .get_stats = bcm54xx_get_stats,
983 .probe = bcm54xx_phy_probe,
984 .config_init = bcm54xx_config_init,
985 .config_aneg = bcm5481_config_aneg,
986 .config_intr = bcm_phy_config_intr,
987 .handle_interrupt = bcm_phy_handle_interrupt,
988 .suspend = bcm54xx_suspend,
989 .resume = bcm54xx_resume,
990 .link_change_notify = bcm54xx_link_change_notify,
991}, {
992 .phy_id = PHY_ID_BCM54811,
993 .phy_id_mask = 0xfffffff0,
994 .name = "Broadcom BCM54811",
995 /* PHY_GBIT_FEATURES */
996 .get_sset_count = bcm_phy_get_sset_count,
997 .get_strings = bcm_phy_get_strings,
998 .get_stats = bcm54xx_get_stats,
999 .probe = bcm54xx_phy_probe,
1000 .config_init = bcm54811_config_init,
1001 .config_aneg = bcm5481_config_aneg,
1002 .config_intr = bcm_phy_config_intr,
1003 .handle_interrupt = bcm_phy_handle_interrupt,
1004 .suspend = bcm54xx_suspend,
1005 .resume = bcm54xx_resume,
1006 .link_change_notify = bcm54xx_link_change_notify,
1007}, {
1008 .phy_id = PHY_ID_BCM5482,
1009 .phy_id_mask = 0xfffffff0,
1010 .name = "Broadcom BCM5482",
1011 /* PHY_GBIT_FEATURES */
1012 .get_sset_count = bcm_phy_get_sset_count,
1013 .get_strings = bcm_phy_get_strings,
1014 .get_stats = bcm54xx_get_stats,
1015 .probe = bcm54xx_phy_probe,
1016 .config_init = bcm54xx_config_init,
1017 .config_intr = bcm_phy_config_intr,
1018 .handle_interrupt = bcm_phy_handle_interrupt,
1019 .link_change_notify = bcm54xx_link_change_notify,
1020}, {
1021 .phy_id = PHY_ID_BCM50610,
1022 .phy_id_mask = 0xfffffff0,
1023 .name = "Broadcom BCM50610",
1024 /* PHY_GBIT_FEATURES */
1025 .get_sset_count = bcm_phy_get_sset_count,
1026 .get_strings = bcm_phy_get_strings,
1027 .get_stats = bcm54xx_get_stats,
1028 .probe = bcm54xx_phy_probe,
1029 .config_init = bcm54xx_config_init,
1030 .config_intr = bcm_phy_config_intr,
1031 .handle_interrupt = bcm_phy_handle_interrupt,
1032 .link_change_notify = bcm54xx_link_change_notify,
1033 .suspend = bcm54xx_suspend,
1034 .resume = bcm54xx_resume,
1035}, {
1036 .phy_id = PHY_ID_BCM50610M,
1037 .phy_id_mask = 0xfffffff0,
1038 .name = "Broadcom BCM50610M",
1039 /* PHY_GBIT_FEATURES */
1040 .get_sset_count = bcm_phy_get_sset_count,
1041 .get_strings = bcm_phy_get_strings,
1042 .get_stats = bcm54xx_get_stats,
1043 .probe = bcm54xx_phy_probe,
1044 .config_init = bcm54xx_config_init,
1045 .config_intr = bcm_phy_config_intr,
1046 .handle_interrupt = bcm_phy_handle_interrupt,
1047 .link_change_notify = bcm54xx_link_change_notify,
1048 .suspend = bcm54xx_suspend,
1049 .resume = bcm54xx_resume,
1050}, {
1051 .phy_id = PHY_ID_BCM57780,
1052 .phy_id_mask = 0xfffffff0,
1053 .name = "Broadcom BCM57780",
1054 /* PHY_GBIT_FEATURES */
1055 .get_sset_count = bcm_phy_get_sset_count,
1056 .get_strings = bcm_phy_get_strings,
1057 .get_stats = bcm54xx_get_stats,
1058 .probe = bcm54xx_phy_probe,
1059 .config_init = bcm54xx_config_init,
1060 .config_intr = bcm_phy_config_intr,
1061 .handle_interrupt = bcm_phy_handle_interrupt,
1062 .link_change_notify = bcm54xx_link_change_notify,
1063}, {
1064 .phy_id = PHY_ID_BCMAC131,
1065 .phy_id_mask = 0xfffffff0,
1066 .name = "Broadcom BCMAC131",
1067 /* PHY_BASIC_FEATURES */
1068 .config_init = brcm_fet_config_init,
1069 .config_intr = brcm_fet_config_intr,
1070 .handle_interrupt = brcm_fet_handle_interrupt,
1071 .suspend = brcm_fet_suspend,
1072 .resume = brcm_fet_config_init,
1073}, {
1074 .phy_id = PHY_ID_BCM5241,
1075 .phy_id_mask = 0xfffffff0,
1076 .name = "Broadcom BCM5241",
1077 /* PHY_BASIC_FEATURES */
1078 .config_init = brcm_fet_config_init,
1079 .config_intr = brcm_fet_config_intr,
1080 .handle_interrupt = brcm_fet_handle_interrupt,
1081 .suspend = brcm_fet_suspend,
1082 .resume = brcm_fet_config_init,
1083}, {
1084 .phy_id = PHY_ID_BCM5395,
1085 .phy_id_mask = 0xfffffff0,
1086 .name = "Broadcom BCM5395",
1087 .flags = PHY_IS_INTERNAL,
1088 /* PHY_GBIT_FEATURES */
1089 .get_sset_count = bcm_phy_get_sset_count,
1090 .get_strings = bcm_phy_get_strings,
1091 .get_stats = bcm54xx_get_stats,
1092 .probe = bcm54xx_phy_probe,
1093 .link_change_notify = bcm54xx_link_change_notify,
1094}, {
1095 .phy_id = PHY_ID_BCM53125,
1096 .phy_id_mask = 0xfffffff0,
1097 .name = "Broadcom BCM53125",
1098 .flags = PHY_IS_INTERNAL,
1099 /* PHY_GBIT_FEATURES */
1100 .get_sset_count = bcm_phy_get_sset_count,
1101 .get_strings = bcm_phy_get_strings,
1102 .get_stats = bcm54xx_get_stats,
1103 .probe = bcm54xx_phy_probe,
1104 .config_init = bcm54xx_config_init,
1105 .config_intr = bcm_phy_config_intr,
1106 .handle_interrupt = bcm_phy_handle_interrupt,
1107 .link_change_notify = bcm54xx_link_change_notify,
1108}, {
1109 .phy_id = PHY_ID_BCM53128,
1110 .phy_id_mask = 0xfffffff0,
1111 .name = "Broadcom BCM53128",
1112 .flags = PHY_IS_INTERNAL,
1113 /* PHY_GBIT_FEATURES */
1114 .get_sset_count = bcm_phy_get_sset_count,
1115 .get_strings = bcm_phy_get_strings,
1116 .get_stats = bcm54xx_get_stats,
1117 .probe = bcm54xx_phy_probe,
1118 .config_init = bcm54xx_config_init,
1119 .config_intr = bcm_phy_config_intr,
1120 .handle_interrupt = bcm_phy_handle_interrupt,
1121 .link_change_notify = bcm54xx_link_change_notify,
1122}, {
1123 .phy_id = PHY_ID_BCM89610,
1124 .phy_id_mask = 0xfffffff0,
1125 .name = "Broadcom BCM89610",
1126 /* PHY_GBIT_FEATURES */
1127 .get_sset_count = bcm_phy_get_sset_count,
1128 .get_strings = bcm_phy_get_strings,
1129 .get_stats = bcm54xx_get_stats,
1130 .probe = bcm54xx_phy_probe,
1131 .config_init = bcm54xx_config_init,
1132 .config_intr = bcm_phy_config_intr,
1133 .handle_interrupt = bcm_phy_handle_interrupt,
1134 .link_change_notify = bcm54xx_link_change_notify,
1135} };
1136
1137module_phy_driver(broadcom_drivers);
1138
1139static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
1140 { PHY_ID_BCM5411, 0xfffffff0 },
1141 { PHY_ID_BCM5421, 0xfffffff0 },
1142 { PHY_ID_BCM54210E, 0xfffffff0 },
1143 { PHY_ID_BCM5461, 0xfffffff0 },
1144 { PHY_ID_BCM54612E, 0xfffffff0 },
1145 { PHY_ID_BCM54616S, 0xfffffff0 },
1146 { PHY_ID_BCM5464, 0xfffffff0 },
1147 { PHY_ID_BCM5481, 0xfffffff0 },
1148 { PHY_ID_BCM54810, 0xfffffff0 },
1149 { PHY_ID_BCM54811, 0xfffffff0 },
1150 { PHY_ID_BCM5482, 0xfffffff0 },
1151 { PHY_ID_BCM50610, 0xfffffff0 },
1152 { PHY_ID_BCM50610M, 0xfffffff0 },
1153 { PHY_ID_BCM57780, 0xfffffff0 },
1154 { PHY_ID_BCMAC131, 0xfffffff0 },
1155 { PHY_ID_BCM5241, 0xfffffff0 },
1156 { PHY_ID_BCM5395, 0xfffffff0 },
1157 { PHY_ID_BCM53125, 0xfffffff0 },
1158 { PHY_ID_BCM53128, 0xfffffff0 },
1159 { PHY_ID_BCM89610, 0xfffffff0 },
1160 { }
1161};
1162
1163MODULE_DEVICE_TABLE(mdio, broadcom_tbl);