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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Marvell 88E6xxx SERDES manipulation, via SMI bus
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 */
9
10#ifndef _MV88E6XXX_SERDES_H
11#define _MV88E6XXX_SERDES_H
12
13#include "chip.h"
14
15#define MV88E6352_ADDR_SERDES 0x0f
16#define MV88E6352_SERDES_PAGE_FIBER 0x01
17#define MV88E6352_SERDES_IRQ 0x0b
18#define MV88E6352_SERDES_INT_ENABLE 0x12
19#define MV88E6352_SERDES_INT_SPEED_CHANGE BIT(14)
20#define MV88E6352_SERDES_INT_DUPLEX_CHANGE BIT(13)
21#define MV88E6352_SERDES_INT_PAGE_RX BIT(12)
22#define MV88E6352_SERDES_INT_AN_COMPLETE BIT(11)
23#define MV88E6352_SERDES_INT_LINK_CHANGE BIT(10)
24#define MV88E6352_SERDES_INT_SYMBOL_ERROR BIT(9)
25#define MV88E6352_SERDES_INT_FALSE_CARRIER BIT(8)
26#define MV88E6352_SERDES_INT_FIFO_OVER_UNDER BIT(7)
27#define MV88E6352_SERDES_INT_FIBRE_ENERGY BIT(4)
28#define MV88E6352_SERDES_INT_STATUS 0x13
29
30#define MV88E6352_SERDES_SPEC_CTRL2 0x1a
31#define MV88E6352_SERDES_OUT_AMP_MASK 0x0007
32
33#define MV88E6341_PORT5_LANE 0x15
34
35#define MV88E6390_PORT9_LANE0 0x09
36#define MV88E6390_PORT9_LANE1 0x12
37#define MV88E6390_PORT9_LANE2 0x13
38#define MV88E6390_PORT9_LANE3 0x14
39#define MV88E6390_PORT10_LANE0 0x0a
40#define MV88E6390_PORT10_LANE1 0x15
41#define MV88E6390_PORT10_LANE2 0x16
42#define MV88E6390_PORT10_LANE3 0x17
43
44/* 10GBASE-R and 10GBASE-X4/X2 */
45#define MV88E6390_10G_CTRL1 (0x1000 + MDIO_CTRL1)
46#define MV88E6390_10G_STAT1 (0x1000 + MDIO_STAT1)
47#define MV88E6393X_10G_INT_ENABLE 0x9000
48#define MV88E6393X_10G_INT_LINK_CHANGE BIT(2)
49#define MV88E6393X_10G_INT_STATUS 0x9001
50
51/* 1000BASE-X and SGMII */
52#define MV88E6390_SGMII_BMCR (0x2000 + MII_BMCR)
53#define MV88E6390_SGMII_BMSR (0x2000 + MII_BMSR)
54#define MV88E6390_SGMII_ADVERTISE (0x2000 + MII_ADVERTISE)
55#define MV88E6390_SGMII_LPA (0x2000 + MII_LPA)
56#define MV88E6390_SGMII_INT_ENABLE 0xa001
57#define MV88E6390_SGMII_INT_SPEED_CHANGE BIT(14)
58#define MV88E6390_SGMII_INT_DUPLEX_CHANGE BIT(13)
59#define MV88E6390_SGMII_INT_PAGE_RX BIT(12)
60#define MV88E6390_SGMII_INT_AN_COMPLETE BIT(11)
61#define MV88E6390_SGMII_INT_LINK_DOWN BIT(10)
62#define MV88E6390_SGMII_INT_LINK_UP BIT(9)
63#define MV88E6390_SGMII_INT_SYMBOL_ERROR BIT(8)
64#define MV88E6390_SGMII_INT_FALSE_CARRIER BIT(7)
65#define MV88E6390_SGMII_INT_STATUS 0xa002
66#define MV88E6390_SGMII_PHY_STATUS 0xa003
67#define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK GENMASK(15, 14)
68#define MV88E6390_SGMII_PHY_STATUS_SPEED_1000 0x8000
69#define MV88E6390_SGMII_PHY_STATUS_SPEED_100 0x4000
70#define MV88E6390_SGMII_PHY_STATUS_SPEED_10 0x0000
71#define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL BIT(13)
72#define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11)
73#define MV88E6390_SGMII_PHY_STATUS_LINK BIT(10)
74#define MV88E6390_SGMII_PHY_STATUS_TX_PAUSE BIT(3)
75#define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE BIT(2)
76
77/* Packet generator pad packet checker */
78#define MV88E6390_PG_CONTROL 0xf010
79#define MV88E6390_PG_CONTROL_ENABLE_PC BIT(0)
80
81#define MV88E6393X_PORT0_LANE 0x00
82#define MV88E6393X_PORT9_LANE 0x09
83#define MV88E6393X_PORT10_LANE 0x0a
84
85/* Port Operational Configuration */
86#define MV88E6393X_SERDES_POC 0xf002
87#define MV88E6393X_SERDES_POC_PCS_1000BASEX 0x0000
88#define MV88E6393X_SERDES_POC_PCS_2500BASEX 0x0001
89#define MV88E6393X_SERDES_POC_PCS_SGMII_PHY 0x0002
90#define MV88E6393X_SERDES_POC_PCS_SGMII_MAC 0x0003
91#define MV88E6393X_SERDES_POC_PCS_5GBASER 0x0004
92#define MV88E6393X_SERDES_POC_PCS_10GBASER 0x0005
93#define MV88E6393X_SERDES_POC_PCS_USXGMII_PHY 0x0006
94#define MV88E6393X_SERDES_POC_PCS_USXGMII_MAC 0x0007
95#define MV88E6393X_SERDES_POC_PCS_MASK 0x0007
96#define MV88E6393X_SERDES_POC_RESET BIT(15)
97#define MV88E6393X_SERDES_POC_PDOWN BIT(5)
98#define MV88E6393X_SERDES_POC_AN BIT(3)
99#define MV88E6393X_SERDES_CTRL1 0xf003
100#define MV88E6393X_SERDES_CTRL1_TX_PDOWN BIT(9)
101#define MV88E6393X_SERDES_CTRL1_RX_PDOWN BIT(8)
102
103#define MV88E6393X_ERRATA_4_8_REG 0xF074
104#define MV88E6393X_ERRATA_4_8_BIT BIT(14)
105
106int mv88e6185_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
107int mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
108int mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
109int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
110int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
111int mv88e6393x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
112int mv88e6352_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
113 int lane, unsigned int mode,
114 phy_interface_t interface,
115 const unsigned long *advertise);
116int mv88e6390_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
117 int lane, unsigned int mode,
118 phy_interface_t interface,
119 const unsigned long *advertise);
120int mv88e6185_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
121 int lane, struct phylink_link_state *state);
122int mv88e6352_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
123 int lane, struct phylink_link_state *state);
124int mv88e6390_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
125 int lane, struct phylink_link_state *state);
126int mv88e6393x_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
127 int lane, struct phylink_link_state *state);
128int mv88e6352_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port,
129 int lane);
130int mv88e6390_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port,
131 int lane);
132int mv88e6352_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
133 int lane, int speed, int duplex);
134int mv88e6390_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
135 int lane, int speed, int duplex);
136unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
137 int port);
138unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
139 int port);
140int mv88e6185_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
141 bool up);
142int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
143 bool on);
144int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
145 bool on);
146int mv88e6393x_serdes_power(struct mv88e6xxx_chip *chip, int port, int lane,
147 bool on);
148int mv88e6393x_serdes_setup_errata(struct mv88e6xxx_chip *chip);
149int mv88e6097_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane,
150 bool enable);
151int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane,
152 bool enable);
153int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, int lane,
154 bool enable);
155int mv88e6393x_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port,
156 int lane, bool enable);
157irqreturn_t mv88e6097_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
158 int lane);
159irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
160 int lane);
161irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
162 int lane);
163irqreturn_t mv88e6393x_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
164 int lane);
165int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
166int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip,
167 int port, uint8_t *data);
168int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
169 uint64_t *data);
170int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
171int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip,
172 int port, uint8_t *data);
173int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
174 uint64_t *data);
175
176int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
177void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
178int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
179void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
180
181int mv88e6352_serdes_set_tx_amplitude(struct mv88e6xxx_chip *chip, int port,
182 int val);
183
184/* Return the (first) SERDES lane address a port is using, -errno otherwise. */
185static inline int mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip,
186 int port)
187{
188 if (!chip->info->ops->serdes_get_lane)
189 return -EOPNOTSUPP;
190
191 return chip->info->ops->serdes_get_lane(chip, port);
192}
193
194static inline int mv88e6xxx_serdes_power_up(struct mv88e6xxx_chip *chip,
195 int port, int lane)
196{
197 if (!chip->info->ops->serdes_power)
198 return -EOPNOTSUPP;
199
200 return chip->info->ops->serdes_power(chip, port, lane, true);
201}
202
203static inline int mv88e6xxx_serdes_power_down(struct mv88e6xxx_chip *chip,
204 int port, int lane)
205{
206 if (!chip->info->ops->serdes_power)
207 return -EOPNOTSUPP;
208
209 return chip->info->ops->serdes_power(chip, port, lane, false);
210}
211
212static inline unsigned int
213mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
214{
215 if (!chip->info->ops->serdes_irq_mapping)
216 return 0;
217
218 return chip->info->ops->serdes_irq_mapping(chip, port);
219}
220
221static inline int mv88e6xxx_serdes_irq_enable(struct mv88e6xxx_chip *chip,
222 int port, int lane)
223{
224 if (!chip->info->ops->serdes_irq_enable)
225 return -EOPNOTSUPP;
226
227 return chip->info->ops->serdes_irq_enable(chip, port, lane, true);
228}
229
230static inline int mv88e6xxx_serdes_irq_disable(struct mv88e6xxx_chip *chip,
231 int port, int lane)
232{
233 if (!chip->info->ops->serdes_irq_enable)
234 return -EOPNOTSUPP;
235
236 return chip->info->ops->serdes_irq_enable(chip, port, lane, false);
237}
238
239static inline irqreturn_t
240mv88e6xxx_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, int lane)
241{
242 if (!chip->info->ops->serdes_irq_status)
243 return IRQ_NONE;
244
245 return chip->info->ops->serdes_irq_status(chip, port, lane);
246}
247
248#endif