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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21#include "irq.h"
22#include "mmu.h"
23#include "x86.h"
24#include "kvm_cache_regs.h"
25
26#include <linux/kvm_host.h>
27#include <linux/types.h>
28#include <linux/string.h>
29#include <linux/mm.h>
30#include <linux/highmem.h>
31#include <linux/module.h>
32#include <linux/swap.h>
33#include <linux/hugetlb.h>
34#include <linux/compiler.h>
35#include <linux/srcu.h>
36#include <linux/slab.h>
37#include <linux/uaccess.h>
38
39#include <asm/page.h>
40#include <asm/cmpxchg.h>
41#include <asm/io.h>
42#include <asm/vmx.h>
43
44/*
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
50 */
51bool tdp_enabled = false;
52
53enum {
54 AUDIT_PRE_PAGE_FAULT,
55 AUDIT_POST_PAGE_FAULT,
56 AUDIT_PRE_PTE_WRITE,
57 AUDIT_POST_PTE_WRITE,
58 AUDIT_PRE_SYNC,
59 AUDIT_POST_SYNC
60};
61
62#undef MMU_DEBUG
63
64#ifdef MMU_DEBUG
65
66#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
67#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
68
69#else
70
71#define pgprintk(x...) do { } while (0)
72#define rmap_printk(x...) do { } while (0)
73
74#endif
75
76#ifdef MMU_DEBUG
77static bool dbg = 0;
78module_param(dbg, bool, 0644);
79#endif
80
81#ifndef MMU_DEBUG
82#define ASSERT(x) do { } while (0)
83#else
84#define ASSERT(x) \
85 if (!(x)) { \
86 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
87 __FILE__, __LINE__, #x); \
88 }
89#endif
90
91#define PTE_PREFETCH_NUM 8
92
93#define PT_FIRST_AVAIL_BITS_SHIFT 10
94#define PT64_SECOND_AVAIL_BITS_SHIFT 52
95
96#define PT64_LEVEL_BITS 9
97
98#define PT64_LEVEL_SHIFT(level) \
99 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
100
101#define PT64_INDEX(address, level)\
102 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
103
104
105#define PT32_LEVEL_BITS 10
106
107#define PT32_LEVEL_SHIFT(level) \
108 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
109
110#define PT32_LVL_OFFSET_MASK(level) \
111 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
112 * PT32_LEVEL_BITS))) - 1))
113
114#define PT32_INDEX(address, level)\
115 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
116
117
118#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
119#define PT64_DIR_BASE_ADDR_MASK \
120 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
121#define PT64_LVL_ADDR_MASK(level) \
122 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT64_LEVEL_BITS))) - 1))
124#define PT64_LVL_OFFSET_MASK(level) \
125 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
126 * PT64_LEVEL_BITS))) - 1))
127
128#define PT32_BASE_ADDR_MASK PAGE_MASK
129#define PT32_DIR_BASE_ADDR_MASK \
130 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
131#define PT32_LVL_ADDR_MASK(level) \
132 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
133 * PT32_LEVEL_BITS))) - 1))
134
135#define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
136 | shadow_x_mask | shadow_nx_mask)
137
138#define ACC_EXEC_MASK 1
139#define ACC_WRITE_MASK PT_WRITABLE_MASK
140#define ACC_USER_MASK PT_USER_MASK
141#define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
142
143#include <trace/events/kvm.h>
144
145#define CREATE_TRACE_POINTS
146#include "mmutrace.h"
147
148#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
149#define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
150
151#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
152
153/* make pte_list_desc fit well in cache line */
154#define PTE_LIST_EXT 3
155
156struct pte_list_desc {
157 u64 *sptes[PTE_LIST_EXT];
158 struct pte_list_desc *more;
159};
160
161struct kvm_shadow_walk_iterator {
162 u64 addr;
163 hpa_t shadow_addr;
164 u64 *sptep;
165 int level;
166 unsigned index;
167};
168
169#define for_each_shadow_entry(_vcpu, _addr, _walker) \
170 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
171 shadow_walk_okay(&(_walker)); \
172 shadow_walk_next(&(_walker)))
173
174#define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
175 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
176 shadow_walk_okay(&(_walker)) && \
177 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
178 __shadow_walk_next(&(_walker), spte))
179
180static struct kmem_cache *pte_list_desc_cache;
181static struct kmem_cache *mmu_page_header_cache;
182static struct percpu_counter kvm_total_used_mmu_pages;
183
184static u64 __read_mostly shadow_nx_mask;
185static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
186static u64 __read_mostly shadow_user_mask;
187static u64 __read_mostly shadow_accessed_mask;
188static u64 __read_mostly shadow_dirty_mask;
189static u64 __read_mostly shadow_mmio_mask;
190
191static void mmu_spte_set(u64 *sptep, u64 spte);
192static void mmu_free_roots(struct kvm_vcpu *vcpu);
193
194void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
195{
196 shadow_mmio_mask = mmio_mask;
197}
198EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
199
200/*
201 * spte bits of bit 3 ~ bit 11 are used as low 9 bits of generation number,
202 * the bits of bits 52 ~ bit 61 are used as high 10 bits of generation
203 * number.
204 */
205#define MMIO_SPTE_GEN_LOW_SHIFT 3
206#define MMIO_SPTE_GEN_HIGH_SHIFT 52
207
208#define MMIO_GEN_SHIFT 19
209#define MMIO_GEN_LOW_SHIFT 9
210#define MMIO_GEN_LOW_MASK ((1 << MMIO_GEN_LOW_SHIFT) - 1)
211#define MMIO_GEN_MASK ((1 << MMIO_GEN_SHIFT) - 1)
212#define MMIO_MAX_GEN ((1 << MMIO_GEN_SHIFT) - 1)
213
214static u64 generation_mmio_spte_mask(unsigned int gen)
215{
216 u64 mask;
217
218 WARN_ON(gen > MMIO_MAX_GEN);
219
220 mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
221 mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
222 return mask;
223}
224
225static unsigned int get_mmio_spte_generation(u64 spte)
226{
227 unsigned int gen;
228
229 spte &= ~shadow_mmio_mask;
230
231 gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
232 gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
233 return gen;
234}
235
236static unsigned int kvm_current_mmio_generation(struct kvm *kvm)
237{
238 /*
239 * Init kvm generation close to MMIO_MAX_GEN to easily test the
240 * code of handling generation number wrap-around.
241 */
242 return (kvm_memslots(kvm)->generation +
243 MMIO_MAX_GEN - 150) & MMIO_GEN_MASK;
244}
245
246static void mark_mmio_spte(struct kvm *kvm, u64 *sptep, u64 gfn,
247 unsigned access)
248{
249 unsigned int gen = kvm_current_mmio_generation(kvm);
250 u64 mask = generation_mmio_spte_mask(gen);
251
252 access &= ACC_WRITE_MASK | ACC_USER_MASK;
253 mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
254
255 trace_mark_mmio_spte(sptep, gfn, access, gen);
256 mmu_spte_set(sptep, mask);
257}
258
259static bool is_mmio_spte(u64 spte)
260{
261 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
262}
263
264static gfn_t get_mmio_spte_gfn(u64 spte)
265{
266 u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
267 return (spte & ~mask) >> PAGE_SHIFT;
268}
269
270static unsigned get_mmio_spte_access(u64 spte)
271{
272 u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
273 return (spte & ~mask) & ~PAGE_MASK;
274}
275
276static bool set_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
277 pfn_t pfn, unsigned access)
278{
279 if (unlikely(is_noslot_pfn(pfn))) {
280 mark_mmio_spte(kvm, sptep, gfn, access);
281 return true;
282 }
283
284 return false;
285}
286
287static bool check_mmio_spte(struct kvm *kvm, u64 spte)
288{
289 unsigned int kvm_gen, spte_gen;
290
291 kvm_gen = kvm_current_mmio_generation(kvm);
292 spte_gen = get_mmio_spte_generation(spte);
293
294 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
295 return likely(kvm_gen == spte_gen);
296}
297
298static inline u64 rsvd_bits(int s, int e)
299{
300 return ((1ULL << (e - s + 1)) - 1) << s;
301}
302
303void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
304 u64 dirty_mask, u64 nx_mask, u64 x_mask)
305{
306 shadow_user_mask = user_mask;
307 shadow_accessed_mask = accessed_mask;
308 shadow_dirty_mask = dirty_mask;
309 shadow_nx_mask = nx_mask;
310 shadow_x_mask = x_mask;
311}
312EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
313
314static int is_cpuid_PSE36(void)
315{
316 return 1;
317}
318
319static int is_nx(struct kvm_vcpu *vcpu)
320{
321 return vcpu->arch.efer & EFER_NX;
322}
323
324static int is_shadow_present_pte(u64 pte)
325{
326 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
327}
328
329static int is_large_pte(u64 pte)
330{
331 return pte & PT_PAGE_SIZE_MASK;
332}
333
334static int is_rmap_spte(u64 pte)
335{
336 return is_shadow_present_pte(pte);
337}
338
339static int is_last_spte(u64 pte, int level)
340{
341 if (level == PT_PAGE_TABLE_LEVEL)
342 return 1;
343 if (is_large_pte(pte))
344 return 1;
345 return 0;
346}
347
348static pfn_t spte_to_pfn(u64 pte)
349{
350 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
351}
352
353static gfn_t pse36_gfn_delta(u32 gpte)
354{
355 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
356
357 return (gpte & PT32_DIR_PSE36_MASK) << shift;
358}
359
360#ifdef CONFIG_X86_64
361static void __set_spte(u64 *sptep, u64 spte)
362{
363 *sptep = spte;
364}
365
366static void __update_clear_spte_fast(u64 *sptep, u64 spte)
367{
368 *sptep = spte;
369}
370
371static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
372{
373 return xchg(sptep, spte);
374}
375
376static u64 __get_spte_lockless(u64 *sptep)
377{
378 return ACCESS_ONCE(*sptep);
379}
380
381static bool __check_direct_spte_mmio_pf(u64 spte)
382{
383 /* It is valid if the spte is zapped. */
384 return spte == 0ull;
385}
386#else
387union split_spte {
388 struct {
389 u32 spte_low;
390 u32 spte_high;
391 };
392 u64 spte;
393};
394
395static void count_spte_clear(u64 *sptep, u64 spte)
396{
397 struct kvm_mmu_page *sp = page_header(__pa(sptep));
398
399 if (is_shadow_present_pte(spte))
400 return;
401
402 /* Ensure the spte is completely set before we increase the count */
403 smp_wmb();
404 sp->clear_spte_count++;
405}
406
407static void __set_spte(u64 *sptep, u64 spte)
408{
409 union split_spte *ssptep, sspte;
410
411 ssptep = (union split_spte *)sptep;
412 sspte = (union split_spte)spte;
413
414 ssptep->spte_high = sspte.spte_high;
415
416 /*
417 * If we map the spte from nonpresent to present, We should store
418 * the high bits firstly, then set present bit, so cpu can not
419 * fetch this spte while we are setting the spte.
420 */
421 smp_wmb();
422
423 ssptep->spte_low = sspte.spte_low;
424}
425
426static void __update_clear_spte_fast(u64 *sptep, u64 spte)
427{
428 union split_spte *ssptep, sspte;
429
430 ssptep = (union split_spte *)sptep;
431 sspte = (union split_spte)spte;
432
433 ssptep->spte_low = sspte.spte_low;
434
435 /*
436 * If we map the spte from present to nonpresent, we should clear
437 * present bit firstly to avoid vcpu fetch the old high bits.
438 */
439 smp_wmb();
440
441 ssptep->spte_high = sspte.spte_high;
442 count_spte_clear(sptep, spte);
443}
444
445static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
446{
447 union split_spte *ssptep, sspte, orig;
448
449 ssptep = (union split_spte *)sptep;
450 sspte = (union split_spte)spte;
451
452 /* xchg acts as a barrier before the setting of the high bits */
453 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
454 orig.spte_high = ssptep->spte_high;
455 ssptep->spte_high = sspte.spte_high;
456 count_spte_clear(sptep, spte);
457
458 return orig.spte;
459}
460
461/*
462 * The idea using the light way get the spte on x86_32 guest is from
463 * gup_get_pte(arch/x86/mm/gup.c).
464 *
465 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
466 * coalesces them and we are running out of the MMU lock. Therefore
467 * we need to protect against in-progress updates of the spte.
468 *
469 * Reading the spte while an update is in progress may get the old value
470 * for the high part of the spte. The race is fine for a present->non-present
471 * change (because the high part of the spte is ignored for non-present spte),
472 * but for a present->present change we must reread the spte.
473 *
474 * All such changes are done in two steps (present->non-present and
475 * non-present->present), hence it is enough to count the number of
476 * present->non-present updates: if it changed while reading the spte,
477 * we might have hit the race. This is done using clear_spte_count.
478 */
479static u64 __get_spte_lockless(u64 *sptep)
480{
481 struct kvm_mmu_page *sp = page_header(__pa(sptep));
482 union split_spte spte, *orig = (union split_spte *)sptep;
483 int count;
484
485retry:
486 count = sp->clear_spte_count;
487 smp_rmb();
488
489 spte.spte_low = orig->spte_low;
490 smp_rmb();
491
492 spte.spte_high = orig->spte_high;
493 smp_rmb();
494
495 if (unlikely(spte.spte_low != orig->spte_low ||
496 count != sp->clear_spte_count))
497 goto retry;
498
499 return spte.spte;
500}
501
502static bool __check_direct_spte_mmio_pf(u64 spte)
503{
504 union split_spte sspte = (union split_spte)spte;
505 u32 high_mmio_mask = shadow_mmio_mask >> 32;
506
507 /* It is valid if the spte is zapped. */
508 if (spte == 0ull)
509 return true;
510
511 /* It is valid if the spte is being zapped. */
512 if (sspte.spte_low == 0ull &&
513 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
514 return true;
515
516 return false;
517}
518#endif
519
520static bool spte_is_locklessly_modifiable(u64 spte)
521{
522 return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
523 (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
524}
525
526static bool spte_has_volatile_bits(u64 spte)
527{
528 /*
529 * Always atomicly update spte if it can be updated
530 * out of mmu-lock, it can ensure dirty bit is not lost,
531 * also, it can help us to get a stable is_writable_pte()
532 * to ensure tlb flush is not missed.
533 */
534 if (spte_is_locklessly_modifiable(spte))
535 return true;
536
537 if (!shadow_accessed_mask)
538 return false;
539
540 if (!is_shadow_present_pte(spte))
541 return false;
542
543 if ((spte & shadow_accessed_mask) &&
544 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
545 return false;
546
547 return true;
548}
549
550static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
551{
552 return (old_spte & bit_mask) && !(new_spte & bit_mask);
553}
554
555/* Rules for using mmu_spte_set:
556 * Set the sptep from nonpresent to present.
557 * Note: the sptep being assigned *must* be either not present
558 * or in a state where the hardware will not attempt to update
559 * the spte.
560 */
561static void mmu_spte_set(u64 *sptep, u64 new_spte)
562{
563 WARN_ON(is_shadow_present_pte(*sptep));
564 __set_spte(sptep, new_spte);
565}
566
567/* Rules for using mmu_spte_update:
568 * Update the state bits, it means the mapped pfn is not changged.
569 *
570 * Whenever we overwrite a writable spte with a read-only one we
571 * should flush remote TLBs. Otherwise rmap_write_protect
572 * will find a read-only spte, even though the writable spte
573 * might be cached on a CPU's TLB, the return value indicates this
574 * case.
575 */
576static bool mmu_spte_update(u64 *sptep, u64 new_spte)
577{
578 u64 old_spte = *sptep;
579 bool ret = false;
580
581 WARN_ON(!is_rmap_spte(new_spte));
582
583 if (!is_shadow_present_pte(old_spte)) {
584 mmu_spte_set(sptep, new_spte);
585 return ret;
586 }
587
588 if (!spte_has_volatile_bits(old_spte))
589 __update_clear_spte_fast(sptep, new_spte);
590 else
591 old_spte = __update_clear_spte_slow(sptep, new_spte);
592
593 /*
594 * For the spte updated out of mmu-lock is safe, since
595 * we always atomicly update it, see the comments in
596 * spte_has_volatile_bits().
597 */
598 if (is_writable_pte(old_spte) && !is_writable_pte(new_spte))
599 ret = true;
600
601 if (!shadow_accessed_mask)
602 return ret;
603
604 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
605 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
606 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
607 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
608
609 return ret;
610}
611
612/*
613 * Rules for using mmu_spte_clear_track_bits:
614 * It sets the sptep from present to nonpresent, and track the
615 * state bits, it is used to clear the last level sptep.
616 */
617static int mmu_spte_clear_track_bits(u64 *sptep)
618{
619 pfn_t pfn;
620 u64 old_spte = *sptep;
621
622 if (!spte_has_volatile_bits(old_spte))
623 __update_clear_spte_fast(sptep, 0ull);
624 else
625 old_spte = __update_clear_spte_slow(sptep, 0ull);
626
627 if (!is_rmap_spte(old_spte))
628 return 0;
629
630 pfn = spte_to_pfn(old_spte);
631
632 /*
633 * KVM does not hold the refcount of the page used by
634 * kvm mmu, before reclaiming the page, we should
635 * unmap it from mmu first.
636 */
637 WARN_ON(!kvm_is_mmio_pfn(pfn) && !page_count(pfn_to_page(pfn)));
638
639 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
640 kvm_set_pfn_accessed(pfn);
641 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
642 kvm_set_pfn_dirty(pfn);
643 return 1;
644}
645
646/*
647 * Rules for using mmu_spte_clear_no_track:
648 * Directly clear spte without caring the state bits of sptep,
649 * it is used to set the upper level spte.
650 */
651static void mmu_spte_clear_no_track(u64 *sptep)
652{
653 __update_clear_spte_fast(sptep, 0ull);
654}
655
656static u64 mmu_spte_get_lockless(u64 *sptep)
657{
658 return __get_spte_lockless(sptep);
659}
660
661static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
662{
663 /*
664 * Prevent page table teardown by making any free-er wait during
665 * kvm_flush_remote_tlbs() IPI to all active vcpus.
666 */
667 local_irq_disable();
668 vcpu->mode = READING_SHADOW_PAGE_TABLES;
669 /*
670 * Make sure a following spte read is not reordered ahead of the write
671 * to vcpu->mode.
672 */
673 smp_mb();
674}
675
676static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
677{
678 /*
679 * Make sure the write to vcpu->mode is not reordered in front of
680 * reads to sptes. If it does, kvm_commit_zap_page() can see us
681 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
682 */
683 smp_mb();
684 vcpu->mode = OUTSIDE_GUEST_MODE;
685 local_irq_enable();
686}
687
688static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
689 struct kmem_cache *base_cache, int min)
690{
691 void *obj;
692
693 if (cache->nobjs >= min)
694 return 0;
695 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
696 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
697 if (!obj)
698 return -ENOMEM;
699 cache->objects[cache->nobjs++] = obj;
700 }
701 return 0;
702}
703
704static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache)
705{
706 return cache->nobjs;
707}
708
709static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
710 struct kmem_cache *cache)
711{
712 while (mc->nobjs)
713 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
714}
715
716static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
717 int min)
718{
719 void *page;
720
721 if (cache->nobjs >= min)
722 return 0;
723 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
724 page = (void *)__get_free_page(GFP_KERNEL);
725 if (!page)
726 return -ENOMEM;
727 cache->objects[cache->nobjs++] = page;
728 }
729 return 0;
730}
731
732static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
733{
734 while (mc->nobjs)
735 free_page((unsigned long)mc->objects[--mc->nobjs]);
736}
737
738static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
739{
740 int r;
741
742 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
743 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
744 if (r)
745 goto out;
746 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
747 if (r)
748 goto out;
749 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
750 mmu_page_header_cache, 4);
751out:
752 return r;
753}
754
755static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
756{
757 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
758 pte_list_desc_cache);
759 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
760 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
761 mmu_page_header_cache);
762}
763
764static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
765{
766 void *p;
767
768 BUG_ON(!mc->nobjs);
769 p = mc->objects[--mc->nobjs];
770 return p;
771}
772
773static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
774{
775 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
776}
777
778static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
779{
780 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
781}
782
783static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
784{
785 if (!sp->role.direct)
786 return sp->gfns[index];
787
788 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
789}
790
791static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
792{
793 if (sp->role.direct)
794 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
795 else
796 sp->gfns[index] = gfn;
797}
798
799/*
800 * Return the pointer to the large page information for a given gfn,
801 * handling slots that are not large page aligned.
802 */
803static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
804 struct kvm_memory_slot *slot,
805 int level)
806{
807 unsigned long idx;
808
809 idx = gfn_to_index(gfn, slot->base_gfn, level);
810 return &slot->arch.lpage_info[level - 2][idx];
811}
812
813static void account_shadowed(struct kvm *kvm, gfn_t gfn)
814{
815 struct kvm_memory_slot *slot;
816 struct kvm_lpage_info *linfo;
817 int i;
818
819 slot = gfn_to_memslot(kvm, gfn);
820 for (i = PT_DIRECTORY_LEVEL;
821 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
822 linfo = lpage_info_slot(gfn, slot, i);
823 linfo->write_count += 1;
824 }
825 kvm->arch.indirect_shadow_pages++;
826}
827
828static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
829{
830 struct kvm_memory_slot *slot;
831 struct kvm_lpage_info *linfo;
832 int i;
833
834 slot = gfn_to_memslot(kvm, gfn);
835 for (i = PT_DIRECTORY_LEVEL;
836 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
837 linfo = lpage_info_slot(gfn, slot, i);
838 linfo->write_count -= 1;
839 WARN_ON(linfo->write_count < 0);
840 }
841 kvm->arch.indirect_shadow_pages--;
842}
843
844static int has_wrprotected_page(struct kvm *kvm,
845 gfn_t gfn,
846 int level)
847{
848 struct kvm_memory_slot *slot;
849 struct kvm_lpage_info *linfo;
850
851 slot = gfn_to_memslot(kvm, gfn);
852 if (slot) {
853 linfo = lpage_info_slot(gfn, slot, level);
854 return linfo->write_count;
855 }
856
857 return 1;
858}
859
860static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
861{
862 unsigned long page_size;
863 int i, ret = 0;
864
865 page_size = kvm_host_page_size(kvm, gfn);
866
867 for (i = PT_PAGE_TABLE_LEVEL;
868 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
869 if (page_size >= KVM_HPAGE_SIZE(i))
870 ret = i;
871 else
872 break;
873 }
874
875 return ret;
876}
877
878static struct kvm_memory_slot *
879gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
880 bool no_dirty_log)
881{
882 struct kvm_memory_slot *slot;
883
884 slot = gfn_to_memslot(vcpu->kvm, gfn);
885 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
886 (no_dirty_log && slot->dirty_bitmap))
887 slot = NULL;
888
889 return slot;
890}
891
892static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
893{
894 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
895}
896
897static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
898{
899 int host_level, level, max_level;
900
901 host_level = host_mapping_level(vcpu->kvm, large_gfn);
902
903 if (host_level == PT_PAGE_TABLE_LEVEL)
904 return host_level;
905
906 max_level = min(kvm_x86_ops->get_lpage_level(), host_level);
907
908 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
909 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
910 break;
911
912 return level - 1;
913}
914
915/*
916 * Pte mapping structures:
917 *
918 * If pte_list bit zero is zero, then pte_list point to the spte.
919 *
920 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
921 * pte_list_desc containing more mappings.
922 *
923 * Returns the number of pte entries before the spte was added or zero if
924 * the spte was not added.
925 *
926 */
927static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
928 unsigned long *pte_list)
929{
930 struct pte_list_desc *desc;
931 int i, count = 0;
932
933 if (!*pte_list) {
934 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
935 *pte_list = (unsigned long)spte;
936 } else if (!(*pte_list & 1)) {
937 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
938 desc = mmu_alloc_pte_list_desc(vcpu);
939 desc->sptes[0] = (u64 *)*pte_list;
940 desc->sptes[1] = spte;
941 *pte_list = (unsigned long)desc | 1;
942 ++count;
943 } else {
944 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
945 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
946 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
947 desc = desc->more;
948 count += PTE_LIST_EXT;
949 }
950 if (desc->sptes[PTE_LIST_EXT-1]) {
951 desc->more = mmu_alloc_pte_list_desc(vcpu);
952 desc = desc->more;
953 }
954 for (i = 0; desc->sptes[i]; ++i)
955 ++count;
956 desc->sptes[i] = spte;
957 }
958 return count;
959}
960
961static void
962pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
963 int i, struct pte_list_desc *prev_desc)
964{
965 int j;
966
967 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
968 ;
969 desc->sptes[i] = desc->sptes[j];
970 desc->sptes[j] = NULL;
971 if (j != 0)
972 return;
973 if (!prev_desc && !desc->more)
974 *pte_list = (unsigned long)desc->sptes[0];
975 else
976 if (prev_desc)
977 prev_desc->more = desc->more;
978 else
979 *pte_list = (unsigned long)desc->more | 1;
980 mmu_free_pte_list_desc(desc);
981}
982
983static void pte_list_remove(u64 *spte, unsigned long *pte_list)
984{
985 struct pte_list_desc *desc;
986 struct pte_list_desc *prev_desc;
987 int i;
988
989 if (!*pte_list) {
990 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
991 BUG();
992 } else if (!(*pte_list & 1)) {
993 rmap_printk("pte_list_remove: %p 1->0\n", spte);
994 if ((u64 *)*pte_list != spte) {
995 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
996 BUG();
997 }
998 *pte_list = 0;
999 } else {
1000 rmap_printk("pte_list_remove: %p many->many\n", spte);
1001 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
1002 prev_desc = NULL;
1003 while (desc) {
1004 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
1005 if (desc->sptes[i] == spte) {
1006 pte_list_desc_remove_entry(pte_list,
1007 desc, i,
1008 prev_desc);
1009 return;
1010 }
1011 prev_desc = desc;
1012 desc = desc->more;
1013 }
1014 pr_err("pte_list_remove: %p many->many\n", spte);
1015 BUG();
1016 }
1017}
1018
1019typedef void (*pte_list_walk_fn) (u64 *spte);
1020static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
1021{
1022 struct pte_list_desc *desc;
1023 int i;
1024
1025 if (!*pte_list)
1026 return;
1027
1028 if (!(*pte_list & 1))
1029 return fn((u64 *)*pte_list);
1030
1031 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
1032 while (desc) {
1033 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
1034 fn(desc->sptes[i]);
1035 desc = desc->more;
1036 }
1037}
1038
1039static unsigned long *__gfn_to_rmap(gfn_t gfn, int level,
1040 struct kvm_memory_slot *slot)
1041{
1042 unsigned long idx;
1043
1044 idx = gfn_to_index(gfn, slot->base_gfn, level);
1045 return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx];
1046}
1047
1048/*
1049 * Take gfn and return the reverse mapping to it.
1050 */
1051static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
1052{
1053 struct kvm_memory_slot *slot;
1054
1055 slot = gfn_to_memslot(kvm, gfn);
1056 return __gfn_to_rmap(gfn, level, slot);
1057}
1058
1059static bool rmap_can_add(struct kvm_vcpu *vcpu)
1060{
1061 struct kvm_mmu_memory_cache *cache;
1062
1063 cache = &vcpu->arch.mmu_pte_list_desc_cache;
1064 return mmu_memory_cache_free_objects(cache);
1065}
1066
1067static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1068{
1069 struct kvm_mmu_page *sp;
1070 unsigned long *rmapp;
1071
1072 sp = page_header(__pa(spte));
1073 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
1074 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1075 return pte_list_add(vcpu, spte, rmapp);
1076}
1077
1078static void rmap_remove(struct kvm *kvm, u64 *spte)
1079{
1080 struct kvm_mmu_page *sp;
1081 gfn_t gfn;
1082 unsigned long *rmapp;
1083
1084 sp = page_header(__pa(spte));
1085 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1086 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
1087 pte_list_remove(spte, rmapp);
1088}
1089
1090/*
1091 * Used by the following functions to iterate through the sptes linked by a
1092 * rmap. All fields are private and not assumed to be used outside.
1093 */
1094struct rmap_iterator {
1095 /* private fields */
1096 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1097 int pos; /* index of the sptep */
1098};
1099
1100/*
1101 * Iteration must be started by this function. This should also be used after
1102 * removing/dropping sptes from the rmap link because in such cases the
1103 * information in the itererator may not be valid.
1104 *
1105 * Returns sptep if found, NULL otherwise.
1106 */
1107static u64 *rmap_get_first(unsigned long rmap, struct rmap_iterator *iter)
1108{
1109 if (!rmap)
1110 return NULL;
1111
1112 if (!(rmap & 1)) {
1113 iter->desc = NULL;
1114 return (u64 *)rmap;
1115 }
1116
1117 iter->desc = (struct pte_list_desc *)(rmap & ~1ul);
1118 iter->pos = 0;
1119 return iter->desc->sptes[iter->pos];
1120}
1121
1122/*
1123 * Must be used with a valid iterator: e.g. after rmap_get_first().
1124 *
1125 * Returns sptep if found, NULL otherwise.
1126 */
1127static u64 *rmap_get_next(struct rmap_iterator *iter)
1128{
1129 if (iter->desc) {
1130 if (iter->pos < PTE_LIST_EXT - 1) {
1131 u64 *sptep;
1132
1133 ++iter->pos;
1134 sptep = iter->desc->sptes[iter->pos];
1135 if (sptep)
1136 return sptep;
1137 }
1138
1139 iter->desc = iter->desc->more;
1140
1141 if (iter->desc) {
1142 iter->pos = 0;
1143 /* desc->sptes[0] cannot be NULL */
1144 return iter->desc->sptes[iter->pos];
1145 }
1146 }
1147
1148 return NULL;
1149}
1150
1151static void drop_spte(struct kvm *kvm, u64 *sptep)
1152{
1153 if (mmu_spte_clear_track_bits(sptep))
1154 rmap_remove(kvm, sptep);
1155}
1156
1157
1158static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1159{
1160 if (is_large_pte(*sptep)) {
1161 WARN_ON(page_header(__pa(sptep))->role.level ==
1162 PT_PAGE_TABLE_LEVEL);
1163 drop_spte(kvm, sptep);
1164 --kvm->stat.lpages;
1165 return true;
1166 }
1167
1168 return false;
1169}
1170
1171static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1172{
1173 if (__drop_large_spte(vcpu->kvm, sptep))
1174 kvm_flush_remote_tlbs(vcpu->kvm);
1175}
1176
1177/*
1178 * Write-protect on the specified @sptep, @pt_protect indicates whether
1179 * spte writ-protection is caused by protecting shadow page table.
1180 * @flush indicates whether tlb need be flushed.
1181 *
1182 * Note: write protection is difference between drity logging and spte
1183 * protection:
1184 * - for dirty logging, the spte can be set to writable at anytime if
1185 * its dirty bitmap is properly set.
1186 * - for spte protection, the spte can be writable only after unsync-ing
1187 * shadow page.
1188 *
1189 * Return true if the spte is dropped.
1190 */
1191static bool
1192spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect)
1193{
1194 u64 spte = *sptep;
1195
1196 if (!is_writable_pte(spte) &&
1197 !(pt_protect && spte_is_locklessly_modifiable(spte)))
1198 return false;
1199
1200 rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
1201
1202 if (__drop_large_spte(kvm, sptep)) {
1203 *flush |= true;
1204 return true;
1205 }
1206
1207 if (pt_protect)
1208 spte &= ~SPTE_MMU_WRITEABLE;
1209 spte = spte & ~PT_WRITABLE_MASK;
1210
1211 *flush |= mmu_spte_update(sptep, spte);
1212 return false;
1213}
1214
1215static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
1216 bool pt_protect)
1217{
1218 u64 *sptep;
1219 struct rmap_iterator iter;
1220 bool flush = false;
1221
1222 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1223 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1224 if (spte_write_protect(kvm, sptep, &flush, pt_protect)) {
1225 sptep = rmap_get_first(*rmapp, &iter);
1226 continue;
1227 }
1228
1229 sptep = rmap_get_next(&iter);
1230 }
1231
1232 return flush;
1233}
1234
1235/**
1236 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1237 * @kvm: kvm instance
1238 * @slot: slot to protect
1239 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1240 * @mask: indicates which pages we should protect
1241 *
1242 * Used when we do not need to care about huge page mappings: e.g. during dirty
1243 * logging we do not have any such mappings.
1244 */
1245void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1246 struct kvm_memory_slot *slot,
1247 gfn_t gfn_offset, unsigned long mask)
1248{
1249 unsigned long *rmapp;
1250
1251 while (mask) {
1252 rmapp = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1253 PT_PAGE_TABLE_LEVEL, slot);
1254 __rmap_write_protect(kvm, rmapp, false);
1255
1256 /* clear the first set bit */
1257 mask &= mask - 1;
1258 }
1259}
1260
1261static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
1262{
1263 struct kvm_memory_slot *slot;
1264 unsigned long *rmapp;
1265 int i;
1266 bool write_protected = false;
1267
1268 slot = gfn_to_memslot(kvm, gfn);
1269
1270 for (i = PT_PAGE_TABLE_LEVEL;
1271 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1272 rmapp = __gfn_to_rmap(gfn, i, slot);
1273 write_protected |= __rmap_write_protect(kvm, rmapp, true);
1274 }
1275
1276 return write_protected;
1277}
1278
1279static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1280 struct kvm_memory_slot *slot, unsigned long data)
1281{
1282 u64 *sptep;
1283 struct rmap_iterator iter;
1284 int need_tlb_flush = 0;
1285
1286 while ((sptep = rmap_get_first(*rmapp, &iter))) {
1287 BUG_ON(!(*sptep & PT_PRESENT_MASK));
1288 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", sptep, *sptep);
1289
1290 drop_spte(kvm, sptep);
1291 need_tlb_flush = 1;
1292 }
1293
1294 return need_tlb_flush;
1295}
1296
1297static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1298 struct kvm_memory_slot *slot, unsigned long data)
1299{
1300 u64 *sptep;
1301 struct rmap_iterator iter;
1302 int need_flush = 0;
1303 u64 new_spte;
1304 pte_t *ptep = (pte_t *)data;
1305 pfn_t new_pfn;
1306
1307 WARN_ON(pte_huge(*ptep));
1308 new_pfn = pte_pfn(*ptep);
1309
1310 for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
1311 BUG_ON(!is_shadow_present_pte(*sptep));
1312 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", sptep, *sptep);
1313
1314 need_flush = 1;
1315
1316 if (pte_write(*ptep)) {
1317 drop_spte(kvm, sptep);
1318 sptep = rmap_get_first(*rmapp, &iter);
1319 } else {
1320 new_spte = *sptep & ~PT64_BASE_ADDR_MASK;
1321 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1322
1323 new_spte &= ~PT_WRITABLE_MASK;
1324 new_spte &= ~SPTE_HOST_WRITEABLE;
1325 new_spte &= ~shadow_accessed_mask;
1326
1327 mmu_spte_clear_track_bits(sptep);
1328 mmu_spte_set(sptep, new_spte);
1329 sptep = rmap_get_next(&iter);
1330 }
1331 }
1332
1333 if (need_flush)
1334 kvm_flush_remote_tlbs(kvm);
1335
1336 return 0;
1337}
1338
1339static int kvm_handle_hva_range(struct kvm *kvm,
1340 unsigned long start,
1341 unsigned long end,
1342 unsigned long data,
1343 int (*handler)(struct kvm *kvm,
1344 unsigned long *rmapp,
1345 struct kvm_memory_slot *slot,
1346 unsigned long data))
1347{
1348 int j;
1349 int ret = 0;
1350 struct kvm_memslots *slots;
1351 struct kvm_memory_slot *memslot;
1352
1353 slots = kvm_memslots(kvm);
1354
1355 kvm_for_each_memslot(memslot, slots) {
1356 unsigned long hva_start, hva_end;
1357 gfn_t gfn_start, gfn_end;
1358
1359 hva_start = max(start, memslot->userspace_addr);
1360 hva_end = min(end, memslot->userspace_addr +
1361 (memslot->npages << PAGE_SHIFT));
1362 if (hva_start >= hva_end)
1363 continue;
1364 /*
1365 * {gfn(page) | page intersects with [hva_start, hva_end)} =
1366 * {gfn_start, gfn_start+1, ..., gfn_end-1}.
1367 */
1368 gfn_start = hva_to_gfn_memslot(hva_start, memslot);
1369 gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot);
1370
1371 for (j = PT_PAGE_TABLE_LEVEL;
1372 j < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++j) {
1373 unsigned long idx, idx_end;
1374 unsigned long *rmapp;
1375
1376 /*
1377 * {idx(page_j) | page_j intersects with
1378 * [hva_start, hva_end)} = {idx, idx+1, ..., idx_end}.
1379 */
1380 idx = gfn_to_index(gfn_start, memslot->base_gfn, j);
1381 idx_end = gfn_to_index(gfn_end - 1, memslot->base_gfn, j);
1382
1383 rmapp = __gfn_to_rmap(gfn_start, j, memslot);
1384
1385 for (; idx <= idx_end; ++idx)
1386 ret |= handler(kvm, rmapp++, memslot, data);
1387 }
1388 }
1389
1390 return ret;
1391}
1392
1393static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1394 unsigned long data,
1395 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1396 struct kvm_memory_slot *slot,
1397 unsigned long data))
1398{
1399 return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler);
1400}
1401
1402int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1403{
1404 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1405}
1406
1407int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
1408{
1409 return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp);
1410}
1411
1412void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1413{
1414 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1415}
1416
1417static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1418 struct kvm_memory_slot *slot, unsigned long data)
1419{
1420 u64 *sptep;
1421 struct rmap_iterator uninitialized_var(iter);
1422 int young = 0;
1423
1424 /*
1425 * In case of absence of EPT Access and Dirty Bits supports,
1426 * emulate the accessed bit for EPT, by checking if this page has
1427 * an EPT mapping, and clearing it if it does. On the next access,
1428 * a new EPT mapping will be established.
1429 * This has some overhead, but not as much as the cost of swapping
1430 * out actively used pages or breaking up actively used hugepages.
1431 */
1432 if (!shadow_accessed_mask) {
1433 young = kvm_unmap_rmapp(kvm, rmapp, slot, data);
1434 goto out;
1435 }
1436
1437 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1438 sptep = rmap_get_next(&iter)) {
1439 BUG_ON(!is_shadow_present_pte(*sptep));
1440
1441 if (*sptep & shadow_accessed_mask) {
1442 young = 1;
1443 clear_bit((ffs(shadow_accessed_mask) - 1),
1444 (unsigned long *)sptep);
1445 }
1446 }
1447out:
1448 /* @data has hva passed to kvm_age_hva(). */
1449 trace_kvm_age_page(data, slot, young);
1450 return young;
1451}
1452
1453static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1454 struct kvm_memory_slot *slot, unsigned long data)
1455{
1456 u64 *sptep;
1457 struct rmap_iterator iter;
1458 int young = 0;
1459
1460 /*
1461 * If there's no access bit in the secondary pte set by the
1462 * hardware it's up to gup-fast/gup to set the access bit in
1463 * the primary pte or in the page structure.
1464 */
1465 if (!shadow_accessed_mask)
1466 goto out;
1467
1468 for (sptep = rmap_get_first(*rmapp, &iter); sptep;
1469 sptep = rmap_get_next(&iter)) {
1470 BUG_ON(!is_shadow_present_pte(*sptep));
1471
1472 if (*sptep & shadow_accessed_mask) {
1473 young = 1;
1474 break;
1475 }
1476 }
1477out:
1478 return young;
1479}
1480
1481#define RMAP_RECYCLE_THRESHOLD 1000
1482
1483static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1484{
1485 unsigned long *rmapp;
1486 struct kvm_mmu_page *sp;
1487
1488 sp = page_header(__pa(spte));
1489
1490 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1491
1492 kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, 0);
1493 kvm_flush_remote_tlbs(vcpu->kvm);
1494}
1495
1496int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1497{
1498 return kvm_handle_hva(kvm, hva, hva, kvm_age_rmapp);
1499}
1500
1501int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1502{
1503 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1504}
1505
1506#ifdef MMU_DEBUG
1507static int is_empty_shadow_page(u64 *spt)
1508{
1509 u64 *pos;
1510 u64 *end;
1511
1512 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1513 if (is_shadow_present_pte(*pos)) {
1514 printk(KERN_ERR "%s: %p %llx\n", __func__,
1515 pos, *pos);
1516 return 0;
1517 }
1518 return 1;
1519}
1520#endif
1521
1522/*
1523 * This value is the sum of all of the kvm instances's
1524 * kvm->arch.n_used_mmu_pages values. We need a global,
1525 * aggregate version in order to make the slab shrinker
1526 * faster
1527 */
1528static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1529{
1530 kvm->arch.n_used_mmu_pages += nr;
1531 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1532}
1533
1534static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1535{
1536 ASSERT(is_empty_shadow_page(sp->spt));
1537 hlist_del(&sp->hash_link);
1538 list_del(&sp->link);
1539 free_page((unsigned long)sp->spt);
1540 if (!sp->role.direct)
1541 free_page((unsigned long)sp->gfns);
1542 kmem_cache_free(mmu_page_header_cache, sp);
1543}
1544
1545static unsigned kvm_page_table_hashfn(gfn_t gfn)
1546{
1547 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1548}
1549
1550static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1551 struct kvm_mmu_page *sp, u64 *parent_pte)
1552{
1553 if (!parent_pte)
1554 return;
1555
1556 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1557}
1558
1559static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1560 u64 *parent_pte)
1561{
1562 pte_list_remove(parent_pte, &sp->parent_ptes);
1563}
1564
1565static void drop_parent_pte(struct kvm_mmu_page *sp,
1566 u64 *parent_pte)
1567{
1568 mmu_page_remove_parent_pte(sp, parent_pte);
1569 mmu_spte_clear_no_track(parent_pte);
1570}
1571
1572static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1573 u64 *parent_pte, int direct)
1574{
1575 struct kvm_mmu_page *sp;
1576
1577 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1578 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1579 if (!direct)
1580 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
1581 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1582
1583 /*
1584 * The active_mmu_pages list is the FIFO list, do not move the
1585 * page until it is zapped. kvm_zap_obsolete_pages depends on
1586 * this feature. See the comments in kvm_zap_obsolete_pages().
1587 */
1588 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1589 sp->parent_ptes = 0;
1590 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1591 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1592 return sp;
1593}
1594
1595static void mark_unsync(u64 *spte);
1596static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1597{
1598 pte_list_walk(&sp->parent_ptes, mark_unsync);
1599}
1600
1601static void mark_unsync(u64 *spte)
1602{
1603 struct kvm_mmu_page *sp;
1604 unsigned int index;
1605
1606 sp = page_header(__pa(spte));
1607 index = spte - sp->spt;
1608 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1609 return;
1610 if (sp->unsync_children++)
1611 return;
1612 kvm_mmu_mark_parents_unsync(sp);
1613}
1614
1615static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1616 struct kvm_mmu_page *sp)
1617{
1618 return 1;
1619}
1620
1621static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1622{
1623}
1624
1625static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1626 struct kvm_mmu_page *sp, u64 *spte,
1627 const void *pte)
1628{
1629 WARN_ON(1);
1630}
1631
1632#define KVM_PAGE_ARRAY_NR 16
1633
1634struct kvm_mmu_pages {
1635 struct mmu_page_and_offset {
1636 struct kvm_mmu_page *sp;
1637 unsigned int idx;
1638 } page[KVM_PAGE_ARRAY_NR];
1639 unsigned int nr;
1640};
1641
1642static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1643 int idx)
1644{
1645 int i;
1646
1647 if (sp->unsync)
1648 for (i=0; i < pvec->nr; i++)
1649 if (pvec->page[i].sp == sp)
1650 return 0;
1651
1652 pvec->page[pvec->nr].sp = sp;
1653 pvec->page[pvec->nr].idx = idx;
1654 pvec->nr++;
1655 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1656}
1657
1658static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1659 struct kvm_mmu_pages *pvec)
1660{
1661 int i, ret, nr_unsync_leaf = 0;
1662
1663 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1664 struct kvm_mmu_page *child;
1665 u64 ent = sp->spt[i];
1666
1667 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1668 goto clear_child_bitmap;
1669
1670 child = page_header(ent & PT64_BASE_ADDR_MASK);
1671
1672 if (child->unsync_children) {
1673 if (mmu_pages_add(pvec, child, i))
1674 return -ENOSPC;
1675
1676 ret = __mmu_unsync_walk(child, pvec);
1677 if (!ret)
1678 goto clear_child_bitmap;
1679 else if (ret > 0)
1680 nr_unsync_leaf += ret;
1681 else
1682 return ret;
1683 } else if (child->unsync) {
1684 nr_unsync_leaf++;
1685 if (mmu_pages_add(pvec, child, i))
1686 return -ENOSPC;
1687 } else
1688 goto clear_child_bitmap;
1689
1690 continue;
1691
1692clear_child_bitmap:
1693 __clear_bit(i, sp->unsync_child_bitmap);
1694 sp->unsync_children--;
1695 WARN_ON((int)sp->unsync_children < 0);
1696 }
1697
1698
1699 return nr_unsync_leaf;
1700}
1701
1702static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1703 struct kvm_mmu_pages *pvec)
1704{
1705 if (!sp->unsync_children)
1706 return 0;
1707
1708 mmu_pages_add(pvec, sp, 0);
1709 return __mmu_unsync_walk(sp, pvec);
1710}
1711
1712static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1713{
1714 WARN_ON(!sp->unsync);
1715 trace_kvm_mmu_sync_page(sp);
1716 sp->unsync = 0;
1717 --kvm->stat.mmu_unsync;
1718}
1719
1720static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1721 struct list_head *invalid_list);
1722static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1723 struct list_head *invalid_list);
1724
1725/*
1726 * NOTE: we should pay more attention on the zapped-obsolete page
1727 * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
1728 * since it has been deleted from active_mmu_pages but still can be found
1729 * at hast list.
1730 *
1731 * for_each_gfn_indirect_valid_sp has skipped that kind of page and
1732 * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped
1733 * all the obsolete pages.
1734 */
1735#define for_each_gfn_sp(_kvm, _sp, _gfn) \
1736 hlist_for_each_entry(_sp, \
1737 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
1738 if ((_sp)->gfn != (_gfn)) {} else
1739
1740#define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1741 for_each_gfn_sp(_kvm, _sp, _gfn) \
1742 if ((_sp)->role.direct || (_sp)->role.invalid) {} else
1743
1744/* @sp->gfn should be write-protected at the call site */
1745static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1746 struct list_head *invalid_list, bool clear_unsync)
1747{
1748 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1749 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1750 return 1;
1751 }
1752
1753 if (clear_unsync)
1754 kvm_unlink_unsync_page(vcpu->kvm, sp);
1755
1756 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1757 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1758 return 1;
1759 }
1760
1761 kvm_mmu_flush_tlb(vcpu);
1762 return 0;
1763}
1764
1765static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1766 struct kvm_mmu_page *sp)
1767{
1768 LIST_HEAD(invalid_list);
1769 int ret;
1770
1771 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1772 if (ret)
1773 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1774
1775 return ret;
1776}
1777
1778#ifdef CONFIG_KVM_MMU_AUDIT
1779#include "mmu_audit.c"
1780#else
1781static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1782static void mmu_audit_disable(void) { }
1783#endif
1784
1785static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1786 struct list_head *invalid_list)
1787{
1788 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1789}
1790
1791/* @gfn should be write-protected at the call site */
1792static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1793{
1794 struct kvm_mmu_page *s;
1795 LIST_HEAD(invalid_list);
1796 bool flush = false;
1797
1798 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
1799 if (!s->unsync)
1800 continue;
1801
1802 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1803 kvm_unlink_unsync_page(vcpu->kvm, s);
1804 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1805 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1806 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1807 continue;
1808 }
1809 flush = true;
1810 }
1811
1812 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1813 if (flush)
1814 kvm_mmu_flush_tlb(vcpu);
1815}
1816
1817struct mmu_page_path {
1818 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1819 unsigned int idx[PT64_ROOT_LEVEL-1];
1820};
1821
1822#define for_each_sp(pvec, sp, parents, i) \
1823 for (i = mmu_pages_next(&pvec, &parents, -1), \
1824 sp = pvec.page[i].sp; \
1825 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1826 i = mmu_pages_next(&pvec, &parents, i))
1827
1828static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1829 struct mmu_page_path *parents,
1830 int i)
1831{
1832 int n;
1833
1834 for (n = i+1; n < pvec->nr; n++) {
1835 struct kvm_mmu_page *sp = pvec->page[n].sp;
1836
1837 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1838 parents->idx[0] = pvec->page[n].idx;
1839 return n;
1840 }
1841
1842 parents->parent[sp->role.level-2] = sp;
1843 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1844 }
1845
1846 return n;
1847}
1848
1849static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1850{
1851 struct kvm_mmu_page *sp;
1852 unsigned int level = 0;
1853
1854 do {
1855 unsigned int idx = parents->idx[level];
1856
1857 sp = parents->parent[level];
1858 if (!sp)
1859 return;
1860
1861 --sp->unsync_children;
1862 WARN_ON((int)sp->unsync_children < 0);
1863 __clear_bit(idx, sp->unsync_child_bitmap);
1864 level++;
1865 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1866}
1867
1868static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1869 struct mmu_page_path *parents,
1870 struct kvm_mmu_pages *pvec)
1871{
1872 parents->parent[parent->role.level-1] = NULL;
1873 pvec->nr = 0;
1874}
1875
1876static void mmu_sync_children(struct kvm_vcpu *vcpu,
1877 struct kvm_mmu_page *parent)
1878{
1879 int i;
1880 struct kvm_mmu_page *sp;
1881 struct mmu_page_path parents;
1882 struct kvm_mmu_pages pages;
1883 LIST_HEAD(invalid_list);
1884
1885 kvm_mmu_pages_init(parent, &parents, &pages);
1886 while (mmu_unsync_walk(parent, &pages)) {
1887 bool protected = false;
1888
1889 for_each_sp(pages, sp, parents, i)
1890 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1891
1892 if (protected)
1893 kvm_flush_remote_tlbs(vcpu->kvm);
1894
1895 for_each_sp(pages, sp, parents, i) {
1896 kvm_sync_page(vcpu, sp, &invalid_list);
1897 mmu_pages_clear_parents(&parents);
1898 }
1899 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1900 cond_resched_lock(&vcpu->kvm->mmu_lock);
1901 kvm_mmu_pages_init(parent, &parents, &pages);
1902 }
1903}
1904
1905static void init_shadow_page_table(struct kvm_mmu_page *sp)
1906{
1907 int i;
1908
1909 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1910 sp->spt[i] = 0ull;
1911}
1912
1913static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1914{
1915 sp->write_flooding_count = 0;
1916}
1917
1918static void clear_sp_write_flooding_count(u64 *spte)
1919{
1920 struct kvm_mmu_page *sp = page_header(__pa(spte));
1921
1922 __clear_sp_write_flooding_count(sp);
1923}
1924
1925static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1926{
1927 return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1928}
1929
1930static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1931 gfn_t gfn,
1932 gva_t gaddr,
1933 unsigned level,
1934 int direct,
1935 unsigned access,
1936 u64 *parent_pte)
1937{
1938 union kvm_mmu_page_role role;
1939 unsigned quadrant;
1940 struct kvm_mmu_page *sp;
1941 bool need_sync = false;
1942
1943 role = vcpu->arch.mmu.base_role;
1944 role.level = level;
1945 role.direct = direct;
1946 if (role.direct)
1947 role.cr4_pae = 0;
1948 role.access = access;
1949 if (!vcpu->arch.mmu.direct_map
1950 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1951 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1952 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1953 role.quadrant = quadrant;
1954 }
1955 for_each_gfn_sp(vcpu->kvm, sp, gfn) {
1956 if (is_obsolete_sp(vcpu->kvm, sp))
1957 continue;
1958
1959 if (!need_sync && sp->unsync)
1960 need_sync = true;
1961
1962 if (sp->role.word != role.word)
1963 continue;
1964
1965 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1966 break;
1967
1968 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1969 if (sp->unsync_children) {
1970 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1971 kvm_mmu_mark_parents_unsync(sp);
1972 } else if (sp->unsync)
1973 kvm_mmu_mark_parents_unsync(sp);
1974
1975 __clear_sp_write_flooding_count(sp);
1976 trace_kvm_mmu_get_page(sp, false);
1977 return sp;
1978 }
1979 ++vcpu->kvm->stat.mmu_cache_miss;
1980 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1981 if (!sp)
1982 return sp;
1983 sp->gfn = gfn;
1984 sp->role = role;
1985 hlist_add_head(&sp->hash_link,
1986 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1987 if (!direct) {
1988 if (rmap_write_protect(vcpu->kvm, gfn))
1989 kvm_flush_remote_tlbs(vcpu->kvm);
1990 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1991 kvm_sync_pages(vcpu, gfn);
1992
1993 account_shadowed(vcpu->kvm, gfn);
1994 }
1995 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1996 init_shadow_page_table(sp);
1997 trace_kvm_mmu_get_page(sp, true);
1998 return sp;
1999}
2000
2001static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2002 struct kvm_vcpu *vcpu, u64 addr)
2003{
2004 iterator->addr = addr;
2005 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
2006 iterator->level = vcpu->arch.mmu.shadow_root_level;
2007
2008 if (iterator->level == PT64_ROOT_LEVEL &&
2009 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
2010 !vcpu->arch.mmu.direct_map)
2011 --iterator->level;
2012
2013 if (iterator->level == PT32E_ROOT_LEVEL) {
2014 iterator->shadow_addr
2015 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
2016 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2017 --iterator->level;
2018 if (!iterator->shadow_addr)
2019 iterator->level = 0;
2020 }
2021}
2022
2023static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2024{
2025 if (iterator->level < PT_PAGE_TABLE_LEVEL)
2026 return false;
2027
2028 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2029 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2030 return true;
2031}
2032
2033static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2034 u64 spte)
2035{
2036 if (is_last_spte(spte, iterator->level)) {
2037 iterator->level = 0;
2038 return;
2039 }
2040
2041 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2042 --iterator->level;
2043}
2044
2045static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2046{
2047 return __shadow_walk_next(iterator, *iterator->sptep);
2048}
2049
2050static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp, bool accessed)
2051{
2052 u64 spte;
2053
2054 BUILD_BUG_ON(VMX_EPT_READABLE_MASK != PT_PRESENT_MASK ||
2055 VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2056
2057 spte = __pa(sp->spt) | PT_PRESENT_MASK | PT_WRITABLE_MASK |
2058 shadow_user_mask | shadow_x_mask;
2059
2060 if (accessed)
2061 spte |= shadow_accessed_mask;
2062
2063 mmu_spte_set(sptep, spte);
2064}
2065
2066static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2067 unsigned direct_access)
2068{
2069 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2070 struct kvm_mmu_page *child;
2071
2072 /*
2073 * For the direct sp, if the guest pte's dirty bit
2074 * changed form clean to dirty, it will corrupt the
2075 * sp's access: allow writable in the read-only sp,
2076 * so we should update the spte at this point to get
2077 * a new sp with the correct access.
2078 */
2079 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
2080 if (child->role.access == direct_access)
2081 return;
2082
2083 drop_parent_pte(child, sptep);
2084 kvm_flush_remote_tlbs(vcpu->kvm);
2085 }
2086}
2087
2088static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2089 u64 *spte)
2090{
2091 u64 pte;
2092 struct kvm_mmu_page *child;
2093
2094 pte = *spte;
2095 if (is_shadow_present_pte(pte)) {
2096 if (is_last_spte(pte, sp->role.level)) {
2097 drop_spte(kvm, spte);
2098 if (is_large_pte(pte))
2099 --kvm->stat.lpages;
2100 } else {
2101 child = page_header(pte & PT64_BASE_ADDR_MASK);
2102 drop_parent_pte(child, spte);
2103 }
2104 return true;
2105 }
2106
2107 if (is_mmio_spte(pte))
2108 mmu_spte_clear_no_track(spte);
2109
2110 return false;
2111}
2112
2113static void kvm_mmu_page_unlink_children(struct kvm *kvm,
2114 struct kvm_mmu_page *sp)
2115{
2116 unsigned i;
2117
2118 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2119 mmu_page_zap_pte(kvm, sp, sp->spt + i);
2120}
2121
2122static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
2123{
2124 mmu_page_remove_parent_pte(sp, parent_pte);
2125}
2126
2127static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2128{
2129 u64 *sptep;
2130 struct rmap_iterator iter;
2131
2132 while ((sptep = rmap_get_first(sp->parent_ptes, &iter)))
2133 drop_parent_pte(sp, sptep);
2134}
2135
2136static int mmu_zap_unsync_children(struct kvm *kvm,
2137 struct kvm_mmu_page *parent,
2138 struct list_head *invalid_list)
2139{
2140 int i, zapped = 0;
2141 struct mmu_page_path parents;
2142 struct kvm_mmu_pages pages;
2143
2144 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
2145 return 0;
2146
2147 kvm_mmu_pages_init(parent, &parents, &pages);
2148 while (mmu_unsync_walk(parent, &pages)) {
2149 struct kvm_mmu_page *sp;
2150
2151 for_each_sp(pages, sp, parents, i) {
2152 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2153 mmu_pages_clear_parents(&parents);
2154 zapped++;
2155 }
2156 kvm_mmu_pages_init(parent, &parents, &pages);
2157 }
2158
2159 return zapped;
2160}
2161
2162static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2163 struct list_head *invalid_list)
2164{
2165 int ret;
2166
2167 trace_kvm_mmu_prepare_zap_page(sp);
2168 ++kvm->stat.mmu_shadow_zapped;
2169 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
2170 kvm_mmu_page_unlink_children(kvm, sp);
2171 kvm_mmu_unlink_parents(kvm, sp);
2172
2173 if (!sp->role.invalid && !sp->role.direct)
2174 unaccount_shadowed(kvm, sp->gfn);
2175
2176 if (sp->unsync)
2177 kvm_unlink_unsync_page(kvm, sp);
2178 if (!sp->root_count) {
2179 /* Count self */
2180 ret++;
2181 list_move(&sp->link, invalid_list);
2182 kvm_mod_used_mmu_pages(kvm, -1);
2183 } else {
2184 list_move(&sp->link, &kvm->arch.active_mmu_pages);
2185
2186 /*
2187 * The obsolete pages can not be used on any vcpus.
2188 * See the comments in kvm_mmu_invalidate_zap_all_pages().
2189 */
2190 if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
2191 kvm_reload_remote_mmus(kvm);
2192 }
2193
2194 sp->role.invalid = 1;
2195 return ret;
2196}
2197
2198static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2199 struct list_head *invalid_list)
2200{
2201 struct kvm_mmu_page *sp, *nsp;
2202
2203 if (list_empty(invalid_list))
2204 return;
2205
2206 /*
2207 * wmb: make sure everyone sees our modifications to the page tables
2208 * rmb: make sure we see changes to vcpu->mode
2209 */
2210 smp_mb();
2211
2212 /*
2213 * Wait for all vcpus to exit guest mode and/or lockless shadow
2214 * page table walks.
2215 */
2216 kvm_flush_remote_tlbs(kvm);
2217
2218 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2219 WARN_ON(!sp->role.invalid || sp->root_count);
2220 kvm_mmu_free_page(sp);
2221 }
2222}
2223
2224static bool prepare_zap_oldest_mmu_page(struct kvm *kvm,
2225 struct list_head *invalid_list)
2226{
2227 struct kvm_mmu_page *sp;
2228
2229 if (list_empty(&kvm->arch.active_mmu_pages))
2230 return false;
2231
2232 sp = list_entry(kvm->arch.active_mmu_pages.prev,
2233 struct kvm_mmu_page, link);
2234 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2235
2236 return true;
2237}
2238
2239/*
2240 * Changing the number of mmu pages allocated to the vm
2241 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2242 */
2243void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
2244{
2245 LIST_HEAD(invalid_list);
2246
2247 spin_lock(&kvm->mmu_lock);
2248
2249 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2250 /* Need to free some mmu pages to achieve the goal. */
2251 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages)
2252 if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list))
2253 break;
2254
2255 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2256 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2257 }
2258
2259 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2260
2261 spin_unlock(&kvm->mmu_lock);
2262}
2263
2264int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2265{
2266 struct kvm_mmu_page *sp;
2267 LIST_HEAD(invalid_list);
2268 int r;
2269
2270 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2271 r = 0;
2272 spin_lock(&kvm->mmu_lock);
2273 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2274 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2275 sp->role.word);
2276 r = 1;
2277 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2278 }
2279 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2280 spin_unlock(&kvm->mmu_lock);
2281
2282 return r;
2283}
2284EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page);
2285
2286/*
2287 * The function is based on mtrr_type_lookup() in
2288 * arch/x86/kernel/cpu/mtrr/generic.c
2289 */
2290static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2291 u64 start, u64 end)
2292{
2293 int i;
2294 u64 base, mask;
2295 u8 prev_match, curr_match;
2296 int num_var_ranges = KVM_NR_VAR_MTRR;
2297
2298 if (!mtrr_state->enabled)
2299 return 0xFF;
2300
2301 /* Make end inclusive end, instead of exclusive */
2302 end--;
2303
2304 /* Look in fixed ranges. Just return the type as per start */
2305 if (mtrr_state->have_fixed && (start < 0x100000)) {
2306 int idx;
2307
2308 if (start < 0x80000) {
2309 idx = 0;
2310 idx += (start >> 16);
2311 return mtrr_state->fixed_ranges[idx];
2312 } else if (start < 0xC0000) {
2313 idx = 1 * 8;
2314 idx += ((start - 0x80000) >> 14);
2315 return mtrr_state->fixed_ranges[idx];
2316 } else if (start < 0x1000000) {
2317 idx = 3 * 8;
2318 idx += ((start - 0xC0000) >> 12);
2319 return mtrr_state->fixed_ranges[idx];
2320 }
2321 }
2322
2323 /*
2324 * Look in variable ranges
2325 * Look of multiple ranges matching this address and pick type
2326 * as per MTRR precedence
2327 */
2328 if (!(mtrr_state->enabled & 2))
2329 return mtrr_state->def_type;
2330
2331 prev_match = 0xFF;
2332 for (i = 0; i < num_var_ranges; ++i) {
2333 unsigned short start_state, end_state;
2334
2335 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2336 continue;
2337
2338 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2339 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2340 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2341 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2342
2343 start_state = ((start & mask) == (base & mask));
2344 end_state = ((end & mask) == (base & mask));
2345 if (start_state != end_state)
2346 return 0xFE;
2347
2348 if ((start & mask) != (base & mask))
2349 continue;
2350
2351 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2352 if (prev_match == 0xFF) {
2353 prev_match = curr_match;
2354 continue;
2355 }
2356
2357 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2358 curr_match == MTRR_TYPE_UNCACHABLE)
2359 return MTRR_TYPE_UNCACHABLE;
2360
2361 if ((prev_match == MTRR_TYPE_WRBACK &&
2362 curr_match == MTRR_TYPE_WRTHROUGH) ||
2363 (prev_match == MTRR_TYPE_WRTHROUGH &&
2364 curr_match == MTRR_TYPE_WRBACK)) {
2365 prev_match = MTRR_TYPE_WRTHROUGH;
2366 curr_match = MTRR_TYPE_WRTHROUGH;
2367 }
2368
2369 if (prev_match != curr_match)
2370 return MTRR_TYPE_UNCACHABLE;
2371 }
2372
2373 if (prev_match != 0xFF)
2374 return prev_match;
2375
2376 return mtrr_state->def_type;
2377}
2378
2379u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2380{
2381 u8 mtrr;
2382
2383 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2384 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2385 if (mtrr == 0xfe || mtrr == 0xff)
2386 mtrr = MTRR_TYPE_WRBACK;
2387 return mtrr;
2388}
2389EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2390
2391static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2392{
2393 trace_kvm_mmu_unsync_page(sp);
2394 ++vcpu->kvm->stat.mmu_unsync;
2395 sp->unsync = 1;
2396
2397 kvm_mmu_mark_parents_unsync(sp);
2398}
2399
2400static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2401{
2402 struct kvm_mmu_page *s;
2403
2404 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2405 if (s->unsync)
2406 continue;
2407 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2408 __kvm_unsync_page(vcpu, s);
2409 }
2410}
2411
2412static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2413 bool can_unsync)
2414{
2415 struct kvm_mmu_page *s;
2416 bool need_unsync = false;
2417
2418 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) {
2419 if (!can_unsync)
2420 return 1;
2421
2422 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2423 return 1;
2424
2425 if (!s->unsync)
2426 need_unsync = true;
2427 }
2428 if (need_unsync)
2429 kvm_unsync_pages(vcpu, gfn);
2430 return 0;
2431}
2432
2433static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2434 unsigned pte_access, int level,
2435 gfn_t gfn, pfn_t pfn, bool speculative,
2436 bool can_unsync, bool host_writable)
2437{
2438 u64 spte;
2439 int ret = 0;
2440
2441 if (set_mmio_spte(vcpu->kvm, sptep, gfn, pfn, pte_access))
2442 return 0;
2443
2444 spte = PT_PRESENT_MASK;
2445 if (!speculative)
2446 spte |= shadow_accessed_mask;
2447
2448 if (pte_access & ACC_EXEC_MASK)
2449 spte |= shadow_x_mask;
2450 else
2451 spte |= shadow_nx_mask;
2452
2453 if (pte_access & ACC_USER_MASK)
2454 spte |= shadow_user_mask;
2455
2456 if (level > PT_PAGE_TABLE_LEVEL)
2457 spte |= PT_PAGE_SIZE_MASK;
2458 if (tdp_enabled)
2459 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2460 kvm_is_mmio_pfn(pfn));
2461
2462 if (host_writable)
2463 spte |= SPTE_HOST_WRITEABLE;
2464 else
2465 pte_access &= ~ACC_WRITE_MASK;
2466
2467 spte |= (u64)pfn << PAGE_SHIFT;
2468
2469 if (pte_access & ACC_WRITE_MASK) {
2470
2471 /*
2472 * Other vcpu creates new sp in the window between
2473 * mapping_level() and acquiring mmu-lock. We can
2474 * allow guest to retry the access, the mapping can
2475 * be fixed if guest refault.
2476 */
2477 if (level > PT_PAGE_TABLE_LEVEL &&
2478 has_wrprotected_page(vcpu->kvm, gfn, level))
2479 goto done;
2480
2481 spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
2482
2483 /*
2484 * Optimization: for pte sync, if spte was writable the hash
2485 * lookup is unnecessary (and expensive). Write protection
2486 * is responsibility of mmu_get_page / kvm_sync_page.
2487 * Same reasoning can be applied to dirty page accounting.
2488 */
2489 if (!can_unsync && is_writable_pte(*sptep))
2490 goto set_pte;
2491
2492 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2493 pgprintk("%s: found shadow page for %llx, marking ro\n",
2494 __func__, gfn);
2495 ret = 1;
2496 pte_access &= ~ACC_WRITE_MASK;
2497 spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
2498 }
2499 }
2500
2501 if (pte_access & ACC_WRITE_MASK)
2502 mark_page_dirty(vcpu->kvm, gfn);
2503
2504set_pte:
2505 if (mmu_spte_update(sptep, spte))
2506 kvm_flush_remote_tlbs(vcpu->kvm);
2507done:
2508 return ret;
2509}
2510
2511static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2512 unsigned pte_access, int write_fault, int *emulate,
2513 int level, gfn_t gfn, pfn_t pfn, bool speculative,
2514 bool host_writable)
2515{
2516 int was_rmapped = 0;
2517 int rmap_count;
2518
2519 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2520 *sptep, write_fault, gfn);
2521
2522 if (is_rmap_spte(*sptep)) {
2523 /*
2524 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2525 * the parent of the now unreachable PTE.
2526 */
2527 if (level > PT_PAGE_TABLE_LEVEL &&
2528 !is_large_pte(*sptep)) {
2529 struct kvm_mmu_page *child;
2530 u64 pte = *sptep;
2531
2532 child = page_header(pte & PT64_BASE_ADDR_MASK);
2533 drop_parent_pte(child, sptep);
2534 kvm_flush_remote_tlbs(vcpu->kvm);
2535 } else if (pfn != spte_to_pfn(*sptep)) {
2536 pgprintk("hfn old %llx new %llx\n",
2537 spte_to_pfn(*sptep), pfn);
2538 drop_spte(vcpu->kvm, sptep);
2539 kvm_flush_remote_tlbs(vcpu->kvm);
2540 } else
2541 was_rmapped = 1;
2542 }
2543
2544 if (set_spte(vcpu, sptep, pte_access, level, gfn, pfn, speculative,
2545 true, host_writable)) {
2546 if (write_fault)
2547 *emulate = 1;
2548 kvm_mmu_flush_tlb(vcpu);
2549 }
2550
2551 if (unlikely(is_mmio_spte(*sptep) && emulate))
2552 *emulate = 1;
2553
2554 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2555 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2556 is_large_pte(*sptep)? "2MB" : "4kB",
2557 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2558 *sptep, sptep);
2559 if (!was_rmapped && is_large_pte(*sptep))
2560 ++vcpu->kvm->stat.lpages;
2561
2562 if (is_shadow_present_pte(*sptep)) {
2563 if (!was_rmapped) {
2564 rmap_count = rmap_add(vcpu, sptep, gfn);
2565 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2566 rmap_recycle(vcpu, sptep, gfn);
2567 }
2568 }
2569
2570 kvm_release_pfn_clean(pfn);
2571}
2572
2573static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2574 bool no_dirty_log)
2575{
2576 struct kvm_memory_slot *slot;
2577
2578 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2579 if (!slot)
2580 return KVM_PFN_ERR_FAULT;
2581
2582 return gfn_to_pfn_memslot_atomic(slot, gfn);
2583}
2584
2585static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2586 struct kvm_mmu_page *sp,
2587 u64 *start, u64 *end)
2588{
2589 struct page *pages[PTE_PREFETCH_NUM];
2590 unsigned access = sp->role.access;
2591 int i, ret;
2592 gfn_t gfn;
2593
2594 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2595 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2596 return -1;
2597
2598 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2599 if (ret <= 0)
2600 return -1;
2601
2602 for (i = 0; i < ret; i++, gfn++, start++)
2603 mmu_set_spte(vcpu, start, access, 0, NULL,
2604 sp->role.level, gfn, page_to_pfn(pages[i]),
2605 true, true);
2606
2607 return 0;
2608}
2609
2610static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2611 struct kvm_mmu_page *sp, u64 *sptep)
2612{
2613 u64 *spte, *start = NULL;
2614 int i;
2615
2616 WARN_ON(!sp->role.direct);
2617
2618 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2619 spte = sp->spt + i;
2620
2621 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2622 if (is_shadow_present_pte(*spte) || spte == sptep) {
2623 if (!start)
2624 continue;
2625 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2626 break;
2627 start = NULL;
2628 } else if (!start)
2629 start = spte;
2630 }
2631}
2632
2633static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2634{
2635 struct kvm_mmu_page *sp;
2636
2637 /*
2638 * Since it's no accessed bit on EPT, it's no way to
2639 * distinguish between actually accessed translations
2640 * and prefetched, so disable pte prefetch if EPT is
2641 * enabled.
2642 */
2643 if (!shadow_accessed_mask)
2644 return;
2645
2646 sp = page_header(__pa(sptep));
2647 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2648 return;
2649
2650 __direct_pte_prefetch(vcpu, sp, sptep);
2651}
2652
2653static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2654 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2655 bool prefault)
2656{
2657 struct kvm_shadow_walk_iterator iterator;
2658 struct kvm_mmu_page *sp;
2659 int emulate = 0;
2660 gfn_t pseudo_gfn;
2661
2662 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2663 return 0;
2664
2665 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2666 if (iterator.level == level) {
2667 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL,
2668 write, &emulate, level, gfn, pfn,
2669 prefault, map_writable);
2670 direct_pte_prefetch(vcpu, iterator.sptep);
2671 ++vcpu->stat.pf_fixed;
2672 break;
2673 }
2674
2675 drop_large_spte(vcpu, iterator.sptep);
2676 if (!is_shadow_present_pte(*iterator.sptep)) {
2677 u64 base_addr = iterator.addr;
2678
2679 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2680 pseudo_gfn = base_addr >> PAGE_SHIFT;
2681 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2682 iterator.level - 1,
2683 1, ACC_ALL, iterator.sptep);
2684
2685 link_shadow_page(iterator.sptep, sp, true);
2686 }
2687 }
2688 return emulate;
2689}
2690
2691static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2692{
2693 siginfo_t info;
2694
2695 info.si_signo = SIGBUS;
2696 info.si_errno = 0;
2697 info.si_code = BUS_MCEERR_AR;
2698 info.si_addr = (void __user *)address;
2699 info.si_addr_lsb = PAGE_SHIFT;
2700
2701 send_sig_info(SIGBUS, &info, tsk);
2702}
2703
2704static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2705{
2706 /*
2707 * Do not cache the mmio info caused by writing the readonly gfn
2708 * into the spte otherwise read access on readonly gfn also can
2709 * caused mmio page fault and treat it as mmio access.
2710 * Return 1 to tell kvm to emulate it.
2711 */
2712 if (pfn == KVM_PFN_ERR_RO_FAULT)
2713 return 1;
2714
2715 if (pfn == KVM_PFN_ERR_HWPOISON) {
2716 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2717 return 0;
2718 }
2719
2720 return -EFAULT;
2721}
2722
2723static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2724 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2725{
2726 pfn_t pfn = *pfnp;
2727 gfn_t gfn = *gfnp;
2728 int level = *levelp;
2729
2730 /*
2731 * Check if it's a transparent hugepage. If this would be an
2732 * hugetlbfs page, level wouldn't be set to
2733 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2734 * here.
2735 */
2736 if (!is_error_noslot_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2737 level == PT_PAGE_TABLE_LEVEL &&
2738 PageTransCompound(pfn_to_page(pfn)) &&
2739 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2740 unsigned long mask;
2741 /*
2742 * mmu_notifier_retry was successful and we hold the
2743 * mmu_lock here, so the pmd can't become splitting
2744 * from under us, and in turn
2745 * __split_huge_page_refcount() can't run from under
2746 * us and we can safely transfer the refcount from
2747 * PG_tail to PG_head as we switch the pfn to tail to
2748 * head.
2749 */
2750 *levelp = level = PT_DIRECTORY_LEVEL;
2751 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2752 VM_BUG_ON((gfn & mask) != (pfn & mask));
2753 if (pfn & mask) {
2754 gfn &= ~mask;
2755 *gfnp = gfn;
2756 kvm_release_pfn_clean(pfn);
2757 pfn &= ~mask;
2758 kvm_get_pfn(pfn);
2759 *pfnp = pfn;
2760 }
2761 }
2762}
2763
2764static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2765 pfn_t pfn, unsigned access, int *ret_val)
2766{
2767 bool ret = true;
2768
2769 /* The pfn is invalid, report the error! */
2770 if (unlikely(is_error_pfn(pfn))) {
2771 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2772 goto exit;
2773 }
2774
2775 if (unlikely(is_noslot_pfn(pfn)))
2776 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2777
2778 ret = false;
2779exit:
2780 return ret;
2781}
2782
2783static bool page_fault_can_be_fast(u32 error_code)
2784{
2785 /*
2786 * Do not fix the mmio spte with invalid generation number which
2787 * need to be updated by slow page fault path.
2788 */
2789 if (unlikely(error_code & PFERR_RSVD_MASK))
2790 return false;
2791
2792 /*
2793 * #PF can be fast only if the shadow page table is present and it
2794 * is caused by write-protect, that means we just need change the
2795 * W bit of the spte which can be done out of mmu-lock.
2796 */
2797 if (!(error_code & PFERR_PRESENT_MASK) ||
2798 !(error_code & PFERR_WRITE_MASK))
2799 return false;
2800
2801 return true;
2802}
2803
2804static bool
2805fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte)
2806{
2807 struct kvm_mmu_page *sp = page_header(__pa(sptep));
2808 gfn_t gfn;
2809
2810 WARN_ON(!sp->role.direct);
2811
2812 /*
2813 * The gfn of direct spte is stable since it is calculated
2814 * by sp->gfn.
2815 */
2816 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
2817
2818 if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
2819 mark_page_dirty(vcpu->kvm, gfn);
2820
2821 return true;
2822}
2823
2824/*
2825 * Return value:
2826 * - true: let the vcpu to access on the same address again.
2827 * - false: let the real page fault path to fix it.
2828 */
2829static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
2830 u32 error_code)
2831{
2832 struct kvm_shadow_walk_iterator iterator;
2833 bool ret = false;
2834 u64 spte = 0ull;
2835
2836 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2837 return false;
2838
2839 if (!page_fault_can_be_fast(error_code))
2840 return false;
2841
2842 walk_shadow_page_lockless_begin(vcpu);
2843 for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
2844 if (!is_shadow_present_pte(spte) || iterator.level < level)
2845 break;
2846
2847 /*
2848 * If the mapping has been changed, let the vcpu fault on the
2849 * same address again.
2850 */
2851 if (!is_rmap_spte(spte)) {
2852 ret = true;
2853 goto exit;
2854 }
2855
2856 if (!is_last_spte(spte, level))
2857 goto exit;
2858
2859 /*
2860 * Check if it is a spurious fault caused by TLB lazily flushed.
2861 *
2862 * Need not check the access of upper level table entries since
2863 * they are always ACC_ALL.
2864 */
2865 if (is_writable_pte(spte)) {
2866 ret = true;
2867 goto exit;
2868 }
2869
2870 /*
2871 * Currently, to simplify the code, only the spte write-protected
2872 * by dirty-log can be fast fixed.
2873 */
2874 if (!spte_is_locklessly_modifiable(spte))
2875 goto exit;
2876
2877 /*
2878 * Currently, fast page fault only works for direct mapping since
2879 * the gfn is not stable for indirect shadow page.
2880 * See Documentation/virtual/kvm/locking.txt to get more detail.
2881 */
2882 ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte);
2883exit:
2884 trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
2885 spte, ret);
2886 walk_shadow_page_lockless_end(vcpu);
2887
2888 return ret;
2889}
2890
2891static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2892 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2893static void make_mmu_pages_available(struct kvm_vcpu *vcpu);
2894
2895static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
2896 gfn_t gfn, bool prefault)
2897{
2898 int r;
2899 int level;
2900 int force_pt_level;
2901 pfn_t pfn;
2902 unsigned long mmu_seq;
2903 bool map_writable, write = error_code & PFERR_WRITE_MASK;
2904
2905 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2906 if (likely(!force_pt_level)) {
2907 level = mapping_level(vcpu, gfn);
2908 /*
2909 * This path builds a PAE pagetable - so we can map
2910 * 2mb pages at maximum. Therefore check if the level
2911 * is larger than that.
2912 */
2913 if (level > PT_DIRECTORY_LEVEL)
2914 level = PT_DIRECTORY_LEVEL;
2915
2916 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2917 } else
2918 level = PT_PAGE_TABLE_LEVEL;
2919
2920 if (fast_page_fault(vcpu, v, level, error_code))
2921 return 0;
2922
2923 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2924 smp_rmb();
2925
2926 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2927 return 0;
2928
2929 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2930 return r;
2931
2932 spin_lock(&vcpu->kvm->mmu_lock);
2933 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
2934 goto out_unlock;
2935 make_mmu_pages_available(vcpu);
2936 if (likely(!force_pt_level))
2937 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2938 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2939 prefault);
2940 spin_unlock(&vcpu->kvm->mmu_lock);
2941
2942
2943 return r;
2944
2945out_unlock:
2946 spin_unlock(&vcpu->kvm->mmu_lock);
2947 kvm_release_pfn_clean(pfn);
2948 return 0;
2949}
2950
2951
2952static void mmu_free_roots(struct kvm_vcpu *vcpu)
2953{
2954 int i;
2955 struct kvm_mmu_page *sp;
2956 LIST_HEAD(invalid_list);
2957
2958 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2959 return;
2960
2961 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2962 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2963 vcpu->arch.mmu.direct_map)) {
2964 hpa_t root = vcpu->arch.mmu.root_hpa;
2965
2966 spin_lock(&vcpu->kvm->mmu_lock);
2967 sp = page_header(root);
2968 --sp->root_count;
2969 if (!sp->root_count && sp->role.invalid) {
2970 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2971 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2972 }
2973 spin_unlock(&vcpu->kvm->mmu_lock);
2974 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2975 return;
2976 }
2977
2978 spin_lock(&vcpu->kvm->mmu_lock);
2979 for (i = 0; i < 4; ++i) {
2980 hpa_t root = vcpu->arch.mmu.pae_root[i];
2981
2982 if (root) {
2983 root &= PT64_BASE_ADDR_MASK;
2984 sp = page_header(root);
2985 --sp->root_count;
2986 if (!sp->root_count && sp->role.invalid)
2987 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2988 &invalid_list);
2989 }
2990 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2991 }
2992 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2993 spin_unlock(&vcpu->kvm->mmu_lock);
2994 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2995}
2996
2997static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2998{
2999 int ret = 0;
3000
3001 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
3002 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3003 ret = 1;
3004 }
3005
3006 return ret;
3007}
3008
3009static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3010{
3011 struct kvm_mmu_page *sp;
3012 unsigned i;
3013
3014 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3015 spin_lock(&vcpu->kvm->mmu_lock);
3016 make_mmu_pages_available(vcpu);
3017 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
3018 1, ACC_ALL, NULL);
3019 ++sp->root_count;
3020 spin_unlock(&vcpu->kvm->mmu_lock);
3021 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
3022 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
3023 for (i = 0; i < 4; ++i) {
3024 hpa_t root = vcpu->arch.mmu.pae_root[i];
3025
3026 ASSERT(!VALID_PAGE(root));
3027 spin_lock(&vcpu->kvm->mmu_lock);
3028 make_mmu_pages_available(vcpu);
3029 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
3030 i << 30,
3031 PT32_ROOT_LEVEL, 1, ACC_ALL,
3032 NULL);
3033 root = __pa(sp->spt);
3034 ++sp->root_count;
3035 spin_unlock(&vcpu->kvm->mmu_lock);
3036 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
3037 }
3038 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3039 } else
3040 BUG();
3041
3042 return 0;
3043}
3044
3045static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3046{
3047 struct kvm_mmu_page *sp;
3048 u64 pdptr, pm_mask;
3049 gfn_t root_gfn;
3050 int i;
3051
3052 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
3053
3054 if (mmu_check_root(vcpu, root_gfn))
3055 return 1;
3056
3057 /*
3058 * Do we shadow a long mode page table? If so we need to
3059 * write-protect the guests page table root.
3060 */
3061 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3062 hpa_t root = vcpu->arch.mmu.root_hpa;
3063
3064 ASSERT(!VALID_PAGE(root));
3065
3066 spin_lock(&vcpu->kvm->mmu_lock);
3067 make_mmu_pages_available(vcpu);
3068 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
3069 0, ACC_ALL, NULL);
3070 root = __pa(sp->spt);
3071 ++sp->root_count;
3072 spin_unlock(&vcpu->kvm->mmu_lock);
3073 vcpu->arch.mmu.root_hpa = root;
3074 return 0;
3075 }
3076
3077 /*
3078 * We shadow a 32 bit page table. This may be a legacy 2-level
3079 * or a PAE 3-level page table. In either case we need to be aware that
3080 * the shadow page table may be a PAE or a long mode page table.
3081 */
3082 pm_mask = PT_PRESENT_MASK;
3083 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
3084 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3085
3086 for (i = 0; i < 4; ++i) {
3087 hpa_t root = vcpu->arch.mmu.pae_root[i];
3088
3089 ASSERT(!VALID_PAGE(root));
3090 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
3091 pdptr = vcpu->arch.mmu.get_pdptr(vcpu, i);
3092 if (!is_present_gpte(pdptr)) {
3093 vcpu->arch.mmu.pae_root[i] = 0;
3094 continue;
3095 }
3096 root_gfn = pdptr >> PAGE_SHIFT;
3097 if (mmu_check_root(vcpu, root_gfn))
3098 return 1;
3099 }
3100 spin_lock(&vcpu->kvm->mmu_lock);
3101 make_mmu_pages_available(vcpu);
3102 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
3103 PT32_ROOT_LEVEL, 0,
3104 ACC_ALL, NULL);
3105 root = __pa(sp->spt);
3106 ++sp->root_count;
3107 spin_unlock(&vcpu->kvm->mmu_lock);
3108
3109 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
3110 }
3111 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
3112
3113 /*
3114 * If we shadow a 32 bit page table with a long mode page
3115 * table we enter this path.
3116 */
3117 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3118 if (vcpu->arch.mmu.lm_root == NULL) {
3119 /*
3120 * The additional page necessary for this is only
3121 * allocated on demand.
3122 */
3123
3124 u64 *lm_root;
3125
3126 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
3127 if (lm_root == NULL)
3128 return 1;
3129
3130 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
3131
3132 vcpu->arch.mmu.lm_root = lm_root;
3133 }
3134
3135 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
3136 }
3137
3138 return 0;
3139}
3140
3141static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
3142{
3143 if (vcpu->arch.mmu.direct_map)
3144 return mmu_alloc_direct_roots(vcpu);
3145 else
3146 return mmu_alloc_shadow_roots(vcpu);
3147}
3148
3149static void mmu_sync_roots(struct kvm_vcpu *vcpu)
3150{
3151 int i;
3152 struct kvm_mmu_page *sp;
3153
3154 if (vcpu->arch.mmu.direct_map)
3155 return;
3156
3157 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3158 return;
3159
3160 vcpu_clear_mmio_info(vcpu, ~0ul);
3161 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3162 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
3163 hpa_t root = vcpu->arch.mmu.root_hpa;
3164 sp = page_header(root);
3165 mmu_sync_children(vcpu, sp);
3166 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3167 return;
3168 }
3169 for (i = 0; i < 4; ++i) {
3170 hpa_t root = vcpu->arch.mmu.pae_root[i];
3171
3172 if (root && VALID_PAGE(root)) {
3173 root &= PT64_BASE_ADDR_MASK;
3174 sp = page_header(root);
3175 mmu_sync_children(vcpu, sp);
3176 }
3177 }
3178 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3179}
3180
3181void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3182{
3183 spin_lock(&vcpu->kvm->mmu_lock);
3184 mmu_sync_roots(vcpu);
3185 spin_unlock(&vcpu->kvm->mmu_lock);
3186}
3187EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots);
3188
3189static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
3190 u32 access, struct x86_exception *exception)
3191{
3192 if (exception)
3193 exception->error_code = 0;
3194 return vaddr;
3195}
3196
3197static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
3198 u32 access,
3199 struct x86_exception *exception)
3200{
3201 if (exception)
3202 exception->error_code = 0;
3203 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
3204}
3205
3206static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3207{
3208 if (direct)
3209 return vcpu_match_mmio_gpa(vcpu, addr);
3210
3211 return vcpu_match_mmio_gva(vcpu, addr);
3212}
3213
3214
3215/*
3216 * On direct hosts, the last spte is only allows two states
3217 * for mmio page fault:
3218 * - It is the mmio spte
3219 * - It is zapped or it is being zapped.
3220 *
3221 * This function completely checks the spte when the last spte
3222 * is not the mmio spte.
3223 */
3224static bool check_direct_spte_mmio_pf(u64 spte)
3225{
3226 return __check_direct_spte_mmio_pf(spte);
3227}
3228
3229static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
3230{
3231 struct kvm_shadow_walk_iterator iterator;
3232 u64 spte = 0ull;
3233
3234 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3235 return spte;
3236
3237 walk_shadow_page_lockless_begin(vcpu);
3238 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
3239 if (!is_shadow_present_pte(spte))
3240 break;
3241 walk_shadow_page_lockless_end(vcpu);
3242
3243 return spte;
3244}
3245
3246int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3247{
3248 u64 spte;
3249
3250 if (quickly_check_mmio_pf(vcpu, addr, direct))
3251 return RET_MMIO_PF_EMULATE;
3252
3253 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
3254
3255 if (is_mmio_spte(spte)) {
3256 gfn_t gfn = get_mmio_spte_gfn(spte);
3257 unsigned access = get_mmio_spte_access(spte);
3258
3259 if (!check_mmio_spte(vcpu->kvm, spte))
3260 return RET_MMIO_PF_INVALID;
3261
3262 if (direct)
3263 addr = 0;
3264
3265 trace_handle_mmio_page_fault(addr, gfn, access);
3266 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3267 return RET_MMIO_PF_EMULATE;
3268 }
3269
3270 /*
3271 * It's ok if the gva is remapped by other cpus on shadow guest,
3272 * it's a BUG if the gfn is not a mmio page.
3273 */
3274 if (direct && !check_direct_spte_mmio_pf(spte))
3275 return RET_MMIO_PF_BUG;
3276
3277 /*
3278 * If the page table is zapped by other cpus, let CPU fault again on
3279 * the address.
3280 */
3281 return RET_MMIO_PF_RETRY;
3282}
3283EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
3284
3285static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
3286 u32 error_code, bool direct)
3287{
3288 int ret;
3289
3290 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
3291 WARN_ON(ret == RET_MMIO_PF_BUG);
3292 return ret;
3293}
3294
3295static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
3296 u32 error_code, bool prefault)
3297{
3298 gfn_t gfn;
3299 int r;
3300
3301 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
3302
3303 if (unlikely(error_code & PFERR_RSVD_MASK)) {
3304 r = handle_mmio_page_fault(vcpu, gva, error_code, true);
3305
3306 if (likely(r != RET_MMIO_PF_INVALID))
3307 return r;
3308 }
3309
3310 r = mmu_topup_memory_caches(vcpu);
3311 if (r)
3312 return r;
3313
3314 ASSERT(vcpu);
3315 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3316
3317 gfn = gva >> PAGE_SHIFT;
3318
3319 return nonpaging_map(vcpu, gva & PAGE_MASK,
3320 error_code, gfn, prefault);
3321}
3322
3323static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3324{
3325 struct kvm_arch_async_pf arch;
3326
3327 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3328 arch.gfn = gfn;
3329 arch.direct_map = vcpu->arch.mmu.direct_map;
3330 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3331
3332 return kvm_setup_async_pf(vcpu, gva, gfn_to_hva(vcpu->kvm, gfn), &arch);
3333}
3334
3335static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3336{
3337 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3338 kvm_event_needs_reinjection(vcpu)))
3339 return false;
3340
3341 return kvm_x86_ops->interrupt_allowed(vcpu);
3342}
3343
3344static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3345 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3346{
3347 bool async;
3348
3349 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3350
3351 if (!async)
3352 return false; /* *pfn has correct page already */
3353
3354 if (!prefault && can_do_async_pf(vcpu)) {
3355 trace_kvm_try_async_get_page(gva, gfn);
3356 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3357 trace_kvm_async_pf_doublefault(gva, gfn);
3358 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3359 return true;
3360 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3361 return true;
3362 }
3363
3364 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3365
3366 return false;
3367}
3368
3369static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3370 bool prefault)
3371{
3372 pfn_t pfn;
3373 int r;
3374 int level;
3375 int force_pt_level;
3376 gfn_t gfn = gpa >> PAGE_SHIFT;
3377 unsigned long mmu_seq;
3378 int write = error_code & PFERR_WRITE_MASK;
3379 bool map_writable;
3380
3381 ASSERT(vcpu);
3382 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3383
3384 if (unlikely(error_code & PFERR_RSVD_MASK)) {
3385 r = handle_mmio_page_fault(vcpu, gpa, error_code, true);
3386
3387 if (likely(r != RET_MMIO_PF_INVALID))
3388 return r;
3389 }
3390
3391 r = mmu_topup_memory_caches(vcpu);
3392 if (r)
3393 return r;
3394
3395 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3396 if (likely(!force_pt_level)) {
3397 level = mapping_level(vcpu, gfn);
3398 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3399 } else
3400 level = PT_PAGE_TABLE_LEVEL;
3401
3402 if (fast_page_fault(vcpu, gpa, level, error_code))
3403 return 0;
3404
3405 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3406 smp_rmb();
3407
3408 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3409 return 0;
3410
3411 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3412 return r;
3413
3414 spin_lock(&vcpu->kvm->mmu_lock);
3415 if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
3416 goto out_unlock;
3417 make_mmu_pages_available(vcpu);
3418 if (likely(!force_pt_level))
3419 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3420 r = __direct_map(vcpu, gpa, write, map_writable,
3421 level, gfn, pfn, prefault);
3422 spin_unlock(&vcpu->kvm->mmu_lock);
3423
3424 return r;
3425
3426out_unlock:
3427 spin_unlock(&vcpu->kvm->mmu_lock);
3428 kvm_release_pfn_clean(pfn);
3429 return 0;
3430}
3431
3432static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3433 struct kvm_mmu *context)
3434{
3435 context->page_fault = nonpaging_page_fault;
3436 context->gva_to_gpa = nonpaging_gva_to_gpa;
3437 context->sync_page = nonpaging_sync_page;
3438 context->invlpg = nonpaging_invlpg;
3439 context->update_pte = nonpaging_update_pte;
3440 context->root_level = 0;
3441 context->shadow_root_level = PT32E_ROOT_LEVEL;
3442 context->root_hpa = INVALID_PAGE;
3443 context->direct_map = true;
3444 context->nx = false;
3445}
3446
3447void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3448{
3449 ++vcpu->stat.tlb_flush;
3450 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3451}
3452EXPORT_SYMBOL_GPL(kvm_mmu_flush_tlb);
3453
3454void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu)
3455{
3456 mmu_free_roots(vcpu);
3457}
3458
3459static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3460{
3461 return kvm_read_cr3(vcpu);
3462}
3463
3464static void inject_page_fault(struct kvm_vcpu *vcpu,
3465 struct x86_exception *fault)
3466{
3467 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3468}
3469
3470static bool sync_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
3471 unsigned access, int *nr_present)
3472{
3473 if (unlikely(is_mmio_spte(*sptep))) {
3474 if (gfn != get_mmio_spte_gfn(*sptep)) {
3475 mmu_spte_clear_no_track(sptep);
3476 return true;
3477 }
3478
3479 (*nr_present)++;
3480 mark_mmio_spte(kvm, sptep, gfn, access);
3481 return true;
3482 }
3483
3484 return false;
3485}
3486
3487static inline bool is_last_gpte(struct kvm_mmu *mmu, unsigned level, unsigned gpte)
3488{
3489 unsigned index;
3490
3491 index = level - 1;
3492 index |= (gpte & PT_PAGE_SIZE_MASK) >> (PT_PAGE_SIZE_SHIFT - 2);
3493 return mmu->last_pte_bitmap & (1 << index);
3494}
3495
3496#define PTTYPE_EPT 18 /* arbitrary */
3497#define PTTYPE PTTYPE_EPT
3498#include "paging_tmpl.h"
3499#undef PTTYPE
3500
3501#define PTTYPE 64
3502#include "paging_tmpl.h"
3503#undef PTTYPE
3504
3505#define PTTYPE 32
3506#include "paging_tmpl.h"
3507#undef PTTYPE
3508
3509static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3510 struct kvm_mmu *context)
3511{
3512 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3513 u64 exb_bit_rsvd = 0;
3514
3515 context->bad_mt_xwr = 0;
3516
3517 if (!context->nx)
3518 exb_bit_rsvd = rsvd_bits(63, 63);
3519 switch (context->root_level) {
3520 case PT32_ROOT_LEVEL:
3521 /* no rsvd bits for 2 level 4K page table entries */
3522 context->rsvd_bits_mask[0][1] = 0;
3523 context->rsvd_bits_mask[0][0] = 0;
3524 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3525
3526 if (!is_pse(vcpu)) {
3527 context->rsvd_bits_mask[1][1] = 0;
3528 break;
3529 }
3530
3531 if (is_cpuid_PSE36())
3532 /* 36bits PSE 4MB page */
3533 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3534 else
3535 /* 32 bits PSE 4MB page */
3536 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3537 break;
3538 case PT32E_ROOT_LEVEL:
3539 context->rsvd_bits_mask[0][2] =
3540 rsvd_bits(maxphyaddr, 63) |
3541 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3542 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3543 rsvd_bits(maxphyaddr, 62); /* PDE */
3544 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3545 rsvd_bits(maxphyaddr, 62); /* PTE */
3546 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3547 rsvd_bits(maxphyaddr, 62) |
3548 rsvd_bits(13, 20); /* large page */
3549 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3550 break;
3551 case PT64_ROOT_LEVEL:
3552 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3553 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3554 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3555 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3556 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3557 rsvd_bits(maxphyaddr, 51);
3558 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3559 rsvd_bits(maxphyaddr, 51);
3560 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3561 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3562 rsvd_bits(maxphyaddr, 51) |
3563 rsvd_bits(13, 29);
3564 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3565 rsvd_bits(maxphyaddr, 51) |
3566 rsvd_bits(13, 20); /* large page */
3567 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3568 break;
3569 }
3570}
3571
3572static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
3573 struct kvm_mmu *context, bool execonly)
3574{
3575 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3576 int pte;
3577
3578 context->rsvd_bits_mask[0][3] =
3579 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
3580 context->rsvd_bits_mask[0][2] =
3581 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3582 context->rsvd_bits_mask[0][1] =
3583 rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
3584 context->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
3585
3586 /* large page */
3587 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3588 context->rsvd_bits_mask[1][2] =
3589 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
3590 context->rsvd_bits_mask[1][1] =
3591 rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
3592 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3593
3594 for (pte = 0; pte < 64; pte++) {
3595 int rwx_bits = pte & 7;
3596 int mt = pte >> 3;
3597 if (mt == 0x2 || mt == 0x3 || mt == 0x7 ||
3598 rwx_bits == 0x2 || rwx_bits == 0x6 ||
3599 (rwx_bits == 0x4 && !execonly))
3600 context->bad_mt_xwr |= (1ull << pte);
3601 }
3602}
3603
3604void update_permission_bitmask(struct kvm_vcpu *vcpu,
3605 struct kvm_mmu *mmu, bool ept)
3606{
3607 unsigned bit, byte, pfec;
3608 u8 map;
3609 bool fault, x, w, u, wf, uf, ff, smapf, cr4_smap, cr4_smep, smap = 0;
3610
3611 cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3612 cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
3613 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
3614 pfec = byte << 1;
3615 map = 0;
3616 wf = pfec & PFERR_WRITE_MASK;
3617 uf = pfec & PFERR_USER_MASK;
3618 ff = pfec & PFERR_FETCH_MASK;
3619 /*
3620 * PFERR_RSVD_MASK bit is set in PFEC if the access is not
3621 * subject to SMAP restrictions, and cleared otherwise. The
3622 * bit is only meaningful if the SMAP bit is set in CR4.
3623 */
3624 smapf = !(pfec & PFERR_RSVD_MASK);
3625 for (bit = 0; bit < 8; ++bit) {
3626 x = bit & ACC_EXEC_MASK;
3627 w = bit & ACC_WRITE_MASK;
3628 u = bit & ACC_USER_MASK;
3629
3630 if (!ept) {
3631 /* Not really needed: !nx will cause pte.nx to fault */
3632 x |= !mmu->nx;
3633 /* Allow supervisor writes if !cr0.wp */
3634 w |= !is_write_protection(vcpu) && !uf;
3635 /* Disallow supervisor fetches of user code if cr4.smep */
3636 x &= !(cr4_smep && u && !uf);
3637
3638 /*
3639 * SMAP:kernel-mode data accesses from user-mode
3640 * mappings should fault. A fault is considered
3641 * as a SMAP violation if all of the following
3642 * conditions are ture:
3643 * - X86_CR4_SMAP is set in CR4
3644 * - An user page is accessed
3645 * - Page fault in kernel mode
3646 * - if CPL = 3 or X86_EFLAGS_AC is clear
3647 *
3648 * Here, we cover the first three conditions.
3649 * The fourth is computed dynamically in
3650 * permission_fault() and is in smapf.
3651 *
3652 * Also, SMAP does not affect instruction
3653 * fetches, add the !ff check here to make it
3654 * clearer.
3655 */
3656 smap = cr4_smap && u && !uf && !ff;
3657 } else
3658 /* Not really needed: no U/S accesses on ept */
3659 u = 1;
3660
3661 fault = (ff && !x) || (uf && !u) || (wf && !w) ||
3662 (smapf && smap);
3663 map |= fault << bit;
3664 }
3665 mmu->permissions[byte] = map;
3666 }
3667}
3668
3669static void update_last_pte_bitmap(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3670{
3671 u8 map;
3672 unsigned level, root_level = mmu->root_level;
3673 const unsigned ps_set_index = 1 << 2; /* bit 2 of index: ps */
3674
3675 if (root_level == PT32E_ROOT_LEVEL)
3676 --root_level;
3677 /* PT_PAGE_TABLE_LEVEL always terminates */
3678 map = 1 | (1 << ps_set_index);
3679 for (level = PT_DIRECTORY_LEVEL; level <= root_level; ++level) {
3680 if (level <= PT_PDPE_LEVEL
3681 && (mmu->root_level >= PT32E_ROOT_LEVEL || is_pse(vcpu)))
3682 map |= 1 << (ps_set_index | (level - 1));
3683 }
3684 mmu->last_pte_bitmap = map;
3685}
3686
3687static void paging64_init_context_common(struct kvm_vcpu *vcpu,
3688 struct kvm_mmu *context,
3689 int level)
3690{
3691 context->nx = is_nx(vcpu);
3692 context->root_level = level;
3693
3694 reset_rsvds_bits_mask(vcpu, context);
3695 update_permission_bitmask(vcpu, context, false);
3696 update_last_pte_bitmap(vcpu, context);
3697
3698 ASSERT(is_pae(vcpu));
3699 context->page_fault = paging64_page_fault;
3700 context->gva_to_gpa = paging64_gva_to_gpa;
3701 context->sync_page = paging64_sync_page;
3702 context->invlpg = paging64_invlpg;
3703 context->update_pte = paging64_update_pte;
3704 context->shadow_root_level = level;
3705 context->root_hpa = INVALID_PAGE;
3706 context->direct_map = false;
3707}
3708
3709static void paging64_init_context(struct kvm_vcpu *vcpu,
3710 struct kvm_mmu *context)
3711{
3712 paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3713}
3714
3715static void paging32_init_context(struct kvm_vcpu *vcpu,
3716 struct kvm_mmu *context)
3717{
3718 context->nx = false;
3719 context->root_level = PT32_ROOT_LEVEL;
3720
3721 reset_rsvds_bits_mask(vcpu, context);
3722 update_permission_bitmask(vcpu, context, false);
3723 update_last_pte_bitmap(vcpu, context);
3724
3725 context->page_fault = paging32_page_fault;
3726 context->gva_to_gpa = paging32_gva_to_gpa;
3727 context->sync_page = paging32_sync_page;
3728 context->invlpg = paging32_invlpg;
3729 context->update_pte = paging32_update_pte;
3730 context->shadow_root_level = PT32E_ROOT_LEVEL;
3731 context->root_hpa = INVALID_PAGE;
3732 context->direct_map = false;
3733}
3734
3735static void paging32E_init_context(struct kvm_vcpu *vcpu,
3736 struct kvm_mmu *context)
3737{
3738 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3739}
3740
3741static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3742{
3743 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3744
3745 context->base_role.word = 0;
3746 context->page_fault = tdp_page_fault;
3747 context->sync_page = nonpaging_sync_page;
3748 context->invlpg = nonpaging_invlpg;
3749 context->update_pte = nonpaging_update_pte;
3750 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3751 context->root_hpa = INVALID_PAGE;
3752 context->direct_map = true;
3753 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3754 context->get_cr3 = get_cr3;
3755 context->get_pdptr = kvm_pdptr_read;
3756 context->inject_page_fault = kvm_inject_page_fault;
3757
3758 if (!is_paging(vcpu)) {
3759 context->nx = false;
3760 context->gva_to_gpa = nonpaging_gva_to_gpa;
3761 context->root_level = 0;
3762 } else if (is_long_mode(vcpu)) {
3763 context->nx = is_nx(vcpu);
3764 context->root_level = PT64_ROOT_LEVEL;
3765 reset_rsvds_bits_mask(vcpu, context);
3766 context->gva_to_gpa = paging64_gva_to_gpa;
3767 } else if (is_pae(vcpu)) {
3768 context->nx = is_nx(vcpu);
3769 context->root_level = PT32E_ROOT_LEVEL;
3770 reset_rsvds_bits_mask(vcpu, context);
3771 context->gva_to_gpa = paging64_gva_to_gpa;
3772 } else {
3773 context->nx = false;
3774 context->root_level = PT32_ROOT_LEVEL;
3775 reset_rsvds_bits_mask(vcpu, context);
3776 context->gva_to_gpa = paging32_gva_to_gpa;
3777 }
3778
3779 update_permission_bitmask(vcpu, context, false);
3780 update_last_pte_bitmap(vcpu, context);
3781}
3782
3783void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3784{
3785 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3786 ASSERT(vcpu);
3787 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3788
3789 if (!is_paging(vcpu))
3790 nonpaging_init_context(vcpu, context);
3791 else if (is_long_mode(vcpu))
3792 paging64_init_context(vcpu, context);
3793 else if (is_pae(vcpu))
3794 paging32E_init_context(vcpu, context);
3795 else
3796 paging32_init_context(vcpu, context);
3797
3798 vcpu->arch.mmu.base_role.nxe = is_nx(vcpu);
3799 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3800 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3801 vcpu->arch.mmu.base_role.smep_andnot_wp
3802 = smep && !is_write_protection(vcpu);
3803}
3804EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3805
3806void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
3807 bool execonly)
3808{
3809 ASSERT(vcpu);
3810 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3811
3812 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3813
3814 context->nx = true;
3815 context->page_fault = ept_page_fault;
3816 context->gva_to_gpa = ept_gva_to_gpa;
3817 context->sync_page = ept_sync_page;
3818 context->invlpg = ept_invlpg;
3819 context->update_pte = ept_update_pte;
3820 context->root_level = context->shadow_root_level;
3821 context->root_hpa = INVALID_PAGE;
3822 context->direct_map = false;
3823
3824 update_permission_bitmask(vcpu, context, true);
3825 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
3826}
3827EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
3828
3829static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
3830{
3831 kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3832 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3833 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3834 vcpu->arch.walk_mmu->get_pdptr = kvm_pdptr_read;
3835 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3836}
3837
3838static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3839{
3840 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3841
3842 g_context->get_cr3 = get_cr3;
3843 g_context->get_pdptr = kvm_pdptr_read;
3844 g_context->inject_page_fault = kvm_inject_page_fault;
3845
3846 /*
3847 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3848 * translation of l2_gpa to l1_gpa addresses is done using the
3849 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3850 * functions between mmu and nested_mmu are swapped.
3851 */
3852 if (!is_paging(vcpu)) {
3853 g_context->nx = false;
3854 g_context->root_level = 0;
3855 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3856 } else if (is_long_mode(vcpu)) {
3857 g_context->nx = is_nx(vcpu);
3858 g_context->root_level = PT64_ROOT_LEVEL;
3859 reset_rsvds_bits_mask(vcpu, g_context);
3860 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3861 } else if (is_pae(vcpu)) {
3862 g_context->nx = is_nx(vcpu);
3863 g_context->root_level = PT32E_ROOT_LEVEL;
3864 reset_rsvds_bits_mask(vcpu, g_context);
3865 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3866 } else {
3867 g_context->nx = false;
3868 g_context->root_level = PT32_ROOT_LEVEL;
3869 reset_rsvds_bits_mask(vcpu, g_context);
3870 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3871 }
3872
3873 update_permission_bitmask(vcpu, g_context, false);
3874 update_last_pte_bitmap(vcpu, g_context);
3875}
3876
3877static void init_kvm_mmu(struct kvm_vcpu *vcpu)
3878{
3879 if (mmu_is_nested(vcpu))
3880 return init_kvm_nested_mmu(vcpu);
3881 else if (tdp_enabled)
3882 return init_kvm_tdp_mmu(vcpu);
3883 else
3884 return init_kvm_softmmu(vcpu);
3885}
3886
3887void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3888{
3889 ASSERT(vcpu);
3890
3891 kvm_mmu_unload(vcpu);
3892 init_kvm_mmu(vcpu);
3893}
3894EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3895
3896int kvm_mmu_load(struct kvm_vcpu *vcpu)
3897{
3898 int r;
3899
3900 r = mmu_topup_memory_caches(vcpu);
3901 if (r)
3902 goto out;
3903 r = mmu_alloc_roots(vcpu);
3904 kvm_mmu_sync_roots(vcpu);
3905 if (r)
3906 goto out;
3907 /* set_cr3() should ensure TLB has been flushed */
3908 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3909out:
3910 return r;
3911}
3912EXPORT_SYMBOL_GPL(kvm_mmu_load);
3913
3914void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3915{
3916 mmu_free_roots(vcpu);
3917 WARN_ON(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3918}
3919EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3920
3921static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3922 struct kvm_mmu_page *sp, u64 *spte,
3923 const void *new)
3924{
3925 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3926 ++vcpu->kvm->stat.mmu_pde_zapped;
3927 return;
3928 }
3929
3930 ++vcpu->kvm->stat.mmu_pte_updated;
3931 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3932}
3933
3934static bool need_remote_flush(u64 old, u64 new)
3935{
3936 if (!is_shadow_present_pte(old))
3937 return false;
3938 if (!is_shadow_present_pte(new))
3939 return true;
3940 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3941 return true;
3942 old ^= shadow_nx_mask;
3943 new ^= shadow_nx_mask;
3944 return (old & ~new & PT64_PERM_MASK) != 0;
3945}
3946
3947static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3948 bool remote_flush, bool local_flush)
3949{
3950 if (zap_page)
3951 return;
3952
3953 if (remote_flush)
3954 kvm_flush_remote_tlbs(vcpu->kvm);
3955 else if (local_flush)
3956 kvm_mmu_flush_tlb(vcpu);
3957}
3958
3959static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
3960 const u8 *new, int *bytes)
3961{
3962 u64 gentry;
3963 int r;
3964
3965 /*
3966 * Assume that the pte write on a page table of the same type
3967 * as the current vcpu paging mode since we update the sptes only
3968 * when they have the same mode.
3969 */
3970 if (is_pae(vcpu) && *bytes == 4) {
3971 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3972 *gpa &= ~(gpa_t)7;
3973 *bytes = 8;
3974 r = kvm_read_guest(vcpu->kvm, *gpa, &gentry, 8);
3975 if (r)
3976 gentry = 0;
3977 new = (const u8 *)&gentry;
3978 }
3979
3980 switch (*bytes) {
3981 case 4:
3982 gentry = *(const u32 *)new;
3983 break;
3984 case 8:
3985 gentry = *(const u64 *)new;
3986 break;
3987 default:
3988 gentry = 0;
3989 break;
3990 }
3991
3992 return gentry;
3993}
3994
3995/*
3996 * If we're seeing too many writes to a page, it may no longer be a page table,
3997 * or we may be forking, in which case it is better to unmap the page.
3998 */
3999static bool detect_write_flooding(struct kvm_mmu_page *sp)
4000{
4001 /*
4002 * Skip write-flooding detected for the sp whose level is 1, because
4003 * it can become unsync, then the guest page is not write-protected.
4004 */
4005 if (sp->role.level == PT_PAGE_TABLE_LEVEL)
4006 return false;
4007
4008 return ++sp->write_flooding_count >= 3;
4009}
4010
4011/*
4012 * Misaligned accesses are too much trouble to fix up; also, they usually
4013 * indicate a page is not used as a page table.
4014 */
4015static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
4016 int bytes)
4017{
4018 unsigned offset, pte_size, misaligned;
4019
4020 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
4021 gpa, bytes, sp->role.word);
4022
4023 offset = offset_in_page(gpa);
4024 pte_size = sp->role.cr4_pae ? 8 : 4;
4025
4026 /*
4027 * Sometimes, the OS only writes the last one bytes to update status
4028 * bits, for example, in linux, andb instruction is used in clear_bit().
4029 */
4030 if (!(offset & (pte_size - 1)) && bytes == 1)
4031 return false;
4032
4033 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
4034 misaligned |= bytes < 4;
4035
4036 return misaligned;
4037}
4038
4039static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
4040{
4041 unsigned page_offset, quadrant;
4042 u64 *spte;
4043 int level;
4044
4045 page_offset = offset_in_page(gpa);
4046 level = sp->role.level;
4047 *nspte = 1;
4048 if (!sp->role.cr4_pae) {
4049 page_offset <<= 1; /* 32->64 */
4050 /*
4051 * A 32-bit pde maps 4MB while the shadow pdes map
4052 * only 2MB. So we need to double the offset again
4053 * and zap two pdes instead of one.
4054 */
4055 if (level == PT32_ROOT_LEVEL) {
4056 page_offset &= ~7; /* kill rounding error */
4057 page_offset <<= 1;
4058 *nspte = 2;
4059 }
4060 quadrant = page_offset >> PAGE_SHIFT;
4061 page_offset &= ~PAGE_MASK;
4062 if (quadrant != sp->role.quadrant)
4063 return NULL;
4064 }
4065
4066 spte = &sp->spt[page_offset / sizeof(*spte)];
4067 return spte;
4068}
4069
4070void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
4071 const u8 *new, int bytes)
4072{
4073 gfn_t gfn = gpa >> PAGE_SHIFT;
4074 union kvm_mmu_page_role mask = { .word = 0 };
4075 struct kvm_mmu_page *sp;
4076 LIST_HEAD(invalid_list);
4077 u64 entry, gentry, *spte;
4078 int npte;
4079 bool remote_flush, local_flush, zap_page;
4080
4081 /*
4082 * If we don't have indirect shadow pages, it means no page is
4083 * write-protected, so we can exit simply.
4084 */
4085 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
4086 return;
4087
4088 zap_page = remote_flush = local_flush = false;
4089
4090 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
4091
4092 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, new, &bytes);
4093
4094 /*
4095 * No need to care whether allocation memory is successful
4096 * or not since pte prefetch is skiped if it does not have
4097 * enough objects in the cache.
4098 */
4099 mmu_topup_memory_caches(vcpu);
4100
4101 spin_lock(&vcpu->kvm->mmu_lock);
4102 ++vcpu->kvm->stat.mmu_pte_write;
4103 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
4104
4105 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
4106 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
4107 if (detect_write_misaligned(sp, gpa, bytes) ||
4108 detect_write_flooding(sp)) {
4109 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
4110 &invalid_list);
4111 ++vcpu->kvm->stat.mmu_flooded;
4112 continue;
4113 }
4114
4115 spte = get_written_sptes(sp, gpa, &npte);
4116 if (!spte)
4117 continue;
4118
4119 local_flush = true;
4120 while (npte--) {
4121 entry = *spte;
4122 mmu_page_zap_pte(vcpu->kvm, sp, spte);
4123 if (gentry &&
4124 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
4125 & mask.word) && rmap_can_add(vcpu))
4126 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
4127 if (need_remote_flush(entry, *spte))
4128 remote_flush = true;
4129 ++spte;
4130 }
4131 }
4132 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
4133 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4134 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
4135 spin_unlock(&vcpu->kvm->mmu_lock);
4136}
4137
4138int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
4139{
4140 gpa_t gpa;
4141 int r;
4142
4143 if (vcpu->arch.mmu.direct_map)
4144 return 0;
4145
4146 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
4147
4148 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4149
4150 return r;
4151}
4152EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
4153
4154static void make_mmu_pages_available(struct kvm_vcpu *vcpu)
4155{
4156 LIST_HEAD(invalid_list);
4157
4158 if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES))
4159 return;
4160
4161 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) {
4162 if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list))
4163 break;
4164
4165 ++vcpu->kvm->stat.mmu_recycled;
4166 }
4167 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
4168}
4169
4170static bool is_mmio_page_fault(struct kvm_vcpu *vcpu, gva_t addr)
4171{
4172 if (vcpu->arch.mmu.direct_map || mmu_is_nested(vcpu))
4173 return vcpu_match_mmio_gpa(vcpu, addr);
4174
4175 return vcpu_match_mmio_gva(vcpu, addr);
4176}
4177
4178int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
4179 void *insn, int insn_len)
4180{
4181 int r, emulation_type = EMULTYPE_RETRY;
4182 enum emulation_result er;
4183
4184 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
4185 if (r < 0)
4186 goto out;
4187
4188 if (!r) {
4189 r = 1;
4190 goto out;
4191 }
4192
4193 if (is_mmio_page_fault(vcpu, cr2))
4194 emulation_type = 0;
4195
4196 er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len);
4197
4198 switch (er) {
4199 case EMULATE_DONE:
4200 return 1;
4201 case EMULATE_USER_EXIT:
4202 ++vcpu->stat.mmio_exits;
4203 /* fall through */
4204 case EMULATE_FAIL:
4205 return 0;
4206 default:
4207 BUG();
4208 }
4209out:
4210 return r;
4211}
4212EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
4213
4214void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
4215{
4216 vcpu->arch.mmu.invlpg(vcpu, gva);
4217 kvm_mmu_flush_tlb(vcpu);
4218 ++vcpu->stat.invlpg;
4219}
4220EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
4221
4222void kvm_enable_tdp(void)
4223{
4224 tdp_enabled = true;
4225}
4226EXPORT_SYMBOL_GPL(kvm_enable_tdp);
4227
4228void kvm_disable_tdp(void)
4229{
4230 tdp_enabled = false;
4231}
4232EXPORT_SYMBOL_GPL(kvm_disable_tdp);
4233
4234static void free_mmu_pages(struct kvm_vcpu *vcpu)
4235{
4236 free_page((unsigned long)vcpu->arch.mmu.pae_root);
4237 if (vcpu->arch.mmu.lm_root != NULL)
4238 free_page((unsigned long)vcpu->arch.mmu.lm_root);
4239}
4240
4241static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
4242{
4243 struct page *page;
4244 int i;
4245
4246 ASSERT(vcpu);
4247
4248 /*
4249 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
4250 * Therefore we need to allocate shadow page tables in the first
4251 * 4GB of memory, which happens to fit the DMA32 zone.
4252 */
4253 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
4254 if (!page)
4255 return -ENOMEM;
4256
4257 vcpu->arch.mmu.pae_root = page_address(page);
4258 for (i = 0; i < 4; ++i)
4259 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
4260
4261 return 0;
4262}
4263
4264int kvm_mmu_create(struct kvm_vcpu *vcpu)
4265{
4266 ASSERT(vcpu);
4267
4268 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
4269 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
4270 vcpu->arch.mmu.translate_gpa = translate_gpa;
4271 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
4272
4273 return alloc_mmu_pages(vcpu);
4274}
4275
4276void kvm_mmu_setup(struct kvm_vcpu *vcpu)
4277{
4278 ASSERT(vcpu);
4279 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
4280
4281 init_kvm_mmu(vcpu);
4282}
4283
4284void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
4285{
4286 struct kvm_memory_slot *memslot;
4287 gfn_t last_gfn;
4288 int i;
4289
4290 memslot = id_to_memslot(kvm->memslots, slot);
4291 last_gfn = memslot->base_gfn + memslot->npages - 1;
4292
4293 spin_lock(&kvm->mmu_lock);
4294
4295 for (i = PT_PAGE_TABLE_LEVEL;
4296 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
4297 unsigned long *rmapp;
4298 unsigned long last_index, index;
4299
4300 rmapp = memslot->arch.rmap[i - PT_PAGE_TABLE_LEVEL];
4301 last_index = gfn_to_index(last_gfn, memslot->base_gfn, i);
4302
4303 for (index = 0; index <= last_index; ++index, ++rmapp) {
4304 if (*rmapp)
4305 __rmap_write_protect(kvm, rmapp, false);
4306
4307 if (need_resched() || spin_needbreak(&kvm->mmu_lock)) {
4308 kvm_flush_remote_tlbs(kvm);
4309 cond_resched_lock(&kvm->mmu_lock);
4310 }
4311 }
4312 }
4313
4314 kvm_flush_remote_tlbs(kvm);
4315 spin_unlock(&kvm->mmu_lock);
4316}
4317
4318#define BATCH_ZAP_PAGES 10
4319static void kvm_zap_obsolete_pages(struct kvm *kvm)
4320{
4321 struct kvm_mmu_page *sp, *node;
4322 int batch = 0;
4323
4324restart:
4325 list_for_each_entry_safe_reverse(sp, node,
4326 &kvm->arch.active_mmu_pages, link) {
4327 int ret;
4328
4329 /*
4330 * No obsolete page exists before new created page since
4331 * active_mmu_pages is the FIFO list.
4332 */
4333 if (!is_obsolete_sp(kvm, sp))
4334 break;
4335
4336 /*
4337 * Since we are reversely walking the list and the invalid
4338 * list will be moved to the head, skip the invalid page
4339 * can help us to avoid the infinity list walking.
4340 */
4341 if (sp->role.invalid)
4342 continue;
4343
4344 /*
4345 * Need not flush tlb since we only zap the sp with invalid
4346 * generation number.
4347 */
4348 if (batch >= BATCH_ZAP_PAGES &&
4349 cond_resched_lock(&kvm->mmu_lock)) {
4350 batch = 0;
4351 goto restart;
4352 }
4353
4354 ret = kvm_mmu_prepare_zap_page(kvm, sp,
4355 &kvm->arch.zapped_obsolete_pages);
4356 batch += ret;
4357
4358 if (ret)
4359 goto restart;
4360 }
4361
4362 /*
4363 * Should flush tlb before free page tables since lockless-walking
4364 * may use the pages.
4365 */
4366 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
4367}
4368
4369/*
4370 * Fast invalidate all shadow pages and use lock-break technique
4371 * to zap obsolete pages.
4372 *
4373 * It's required when memslot is being deleted or VM is being
4374 * destroyed, in these cases, we should ensure that KVM MMU does
4375 * not use any resource of the being-deleted slot or all slots
4376 * after calling the function.
4377 */
4378void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
4379{
4380 spin_lock(&kvm->mmu_lock);
4381 trace_kvm_mmu_invalidate_zap_all_pages(kvm);
4382 kvm->arch.mmu_valid_gen++;
4383
4384 /*
4385 * Notify all vcpus to reload its shadow page table
4386 * and flush TLB. Then all vcpus will switch to new
4387 * shadow page table with the new mmu_valid_gen.
4388 *
4389 * Note: we should do this under the protection of
4390 * mmu-lock, otherwise, vcpu would purge shadow page
4391 * but miss tlb flush.
4392 */
4393 kvm_reload_remote_mmus(kvm);
4394
4395 kvm_zap_obsolete_pages(kvm);
4396 spin_unlock(&kvm->mmu_lock);
4397}
4398
4399static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
4400{
4401 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
4402}
4403
4404void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm)
4405{
4406 /*
4407 * The very rare case: if the generation-number is round,
4408 * zap all shadow pages.
4409 */
4410 if (unlikely(kvm_current_mmio_generation(kvm) >= MMIO_MAX_GEN)) {
4411 printk_ratelimited(KERN_INFO "kvm: zapping shadow pages for mmio generation wraparound\n");
4412 kvm_mmu_invalidate_zap_all_pages(kvm);
4413 }
4414}
4415
4416static unsigned long
4417mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
4418{
4419 struct kvm *kvm;
4420 int nr_to_scan = sc->nr_to_scan;
4421 unsigned long freed = 0;
4422
4423 spin_lock(&kvm_lock);
4424
4425 list_for_each_entry(kvm, &vm_list, vm_list) {
4426 int idx;
4427 LIST_HEAD(invalid_list);
4428
4429 /*
4430 * Never scan more than sc->nr_to_scan VM instances.
4431 * Will not hit this condition practically since we do not try
4432 * to shrink more than one VM and it is very unlikely to see
4433 * !n_used_mmu_pages so many times.
4434 */
4435 if (!nr_to_scan--)
4436 break;
4437 /*
4438 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
4439 * here. We may skip a VM instance errorneosly, but we do not
4440 * want to shrink a VM that only started to populate its MMU
4441 * anyway.
4442 */
4443 if (!kvm->arch.n_used_mmu_pages &&
4444 !kvm_has_zapped_obsolete_pages(kvm))
4445 continue;
4446
4447 idx = srcu_read_lock(&kvm->srcu);
4448 spin_lock(&kvm->mmu_lock);
4449
4450 if (kvm_has_zapped_obsolete_pages(kvm)) {
4451 kvm_mmu_commit_zap_page(kvm,
4452 &kvm->arch.zapped_obsolete_pages);
4453 goto unlock;
4454 }
4455
4456 if (prepare_zap_oldest_mmu_page(kvm, &invalid_list))
4457 freed++;
4458 kvm_mmu_commit_zap_page(kvm, &invalid_list);
4459
4460unlock:
4461 spin_unlock(&kvm->mmu_lock);
4462 srcu_read_unlock(&kvm->srcu, idx);
4463
4464 /*
4465 * unfair on small ones
4466 * per-vm shrinkers cry out
4467 * sadness comes quickly
4468 */
4469 list_move_tail(&kvm->vm_list, &vm_list);
4470 break;
4471 }
4472
4473 spin_unlock(&kvm_lock);
4474 return freed;
4475}
4476
4477static unsigned long
4478mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
4479{
4480 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
4481}
4482
4483static struct shrinker mmu_shrinker = {
4484 .count_objects = mmu_shrink_count,
4485 .scan_objects = mmu_shrink_scan,
4486 .seeks = DEFAULT_SEEKS * 10,
4487};
4488
4489static void mmu_destroy_caches(void)
4490{
4491 if (pte_list_desc_cache)
4492 kmem_cache_destroy(pte_list_desc_cache);
4493 if (mmu_page_header_cache)
4494 kmem_cache_destroy(mmu_page_header_cache);
4495}
4496
4497int kvm_mmu_module_init(void)
4498{
4499 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
4500 sizeof(struct pte_list_desc),
4501 0, 0, NULL);
4502 if (!pte_list_desc_cache)
4503 goto nomem;
4504
4505 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
4506 sizeof(struct kvm_mmu_page),
4507 0, 0, NULL);
4508 if (!mmu_page_header_cache)
4509 goto nomem;
4510
4511 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
4512 goto nomem;
4513
4514 register_shrinker(&mmu_shrinker);
4515
4516 return 0;
4517
4518nomem:
4519 mmu_destroy_caches();
4520 return -ENOMEM;
4521}
4522
4523/*
4524 * Caculate mmu pages needed for kvm.
4525 */
4526unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
4527{
4528 unsigned int nr_mmu_pages;
4529 unsigned int nr_pages = 0;
4530 struct kvm_memslots *slots;
4531 struct kvm_memory_slot *memslot;
4532
4533 slots = kvm_memslots(kvm);
4534
4535 kvm_for_each_memslot(memslot, slots)
4536 nr_pages += memslot->npages;
4537
4538 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
4539 nr_mmu_pages = max(nr_mmu_pages,
4540 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
4541
4542 return nr_mmu_pages;
4543}
4544
4545int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4546{
4547 struct kvm_shadow_walk_iterator iterator;
4548 u64 spte;
4549 int nr_sptes = 0;
4550
4551 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4552 return nr_sptes;
4553
4554 walk_shadow_page_lockless_begin(vcpu);
4555 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4556 sptes[iterator.level-1] = spte;
4557 nr_sptes++;
4558 if (!is_shadow_present_pte(spte))
4559 break;
4560 }
4561 walk_shadow_page_lockless_end(vcpu);
4562
4563 return nr_sptes;
4564}
4565EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4566
4567void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4568{
4569 ASSERT(vcpu);
4570
4571 kvm_mmu_unload(vcpu);
4572 free_mmu_pages(vcpu);
4573 mmu_free_memory_caches(vcpu);
4574}
4575
4576void kvm_mmu_module_exit(void)
4577{
4578 mmu_destroy_caches();
4579 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4580 unregister_shrinker(&mmu_shrinker);
4581 mmu_audit_disable();
4582}