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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * AMD Encrypted Register State Support
4 *
5 * Author: Joerg Roedel <jroedel@suse.de>
6 */
7
8/*
9 * misc.h needs to be first because it knows how to include the other kernel
10 * headers in the pre-decompression code in a way that does not break
11 * compilation.
12 */
13#include "misc.h"
14
15#include <asm/pgtable_types.h>
16#include <asm/sev.h>
17#include <asm/trapnr.h>
18#include <asm/trap_pf.h>
19#include <asm/msr-index.h>
20#include <asm/fpu/xcr.h>
21#include <asm/ptrace.h>
22#include <asm/svm.h>
23#include <asm/cpuid.h>
24
25#include "error.h"
26#include "../msr.h"
27
28struct ghcb boot_ghcb_page __aligned(PAGE_SIZE);
29struct ghcb *boot_ghcb;
30
31/*
32 * Copy a version of this function here - insn-eval.c can't be used in
33 * pre-decompression code.
34 */
35static bool insn_has_rep_prefix(struct insn *insn)
36{
37 insn_byte_t p;
38 int i;
39
40 insn_get_prefixes(insn);
41
42 for_each_insn_prefix(insn, i, p) {
43 if (p == 0xf2 || p == 0xf3)
44 return true;
45 }
46
47 return false;
48}
49
50/*
51 * Only a dummy for insn_get_seg_base() - Early boot-code is 64bit only and
52 * doesn't use segments.
53 */
54static unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx)
55{
56 return 0UL;
57}
58
59static inline u64 sev_es_rd_ghcb_msr(void)
60{
61 struct msr m;
62
63 boot_rdmsr(MSR_AMD64_SEV_ES_GHCB, &m);
64
65 return m.q;
66}
67
68static inline void sev_es_wr_ghcb_msr(u64 val)
69{
70 struct msr m;
71
72 m.q = val;
73 boot_wrmsr(MSR_AMD64_SEV_ES_GHCB, &m);
74}
75
76static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt)
77{
78 char buffer[MAX_INSN_SIZE];
79 int ret;
80
81 memcpy(buffer, (unsigned char *)ctxt->regs->ip, MAX_INSN_SIZE);
82
83 ret = insn_decode(&ctxt->insn, buffer, MAX_INSN_SIZE, INSN_MODE_64);
84 if (ret < 0)
85 return ES_DECODE_FAILED;
86
87 return ES_OK;
88}
89
90static enum es_result vc_write_mem(struct es_em_ctxt *ctxt,
91 void *dst, char *buf, size_t size)
92{
93 memcpy(dst, buf, size);
94
95 return ES_OK;
96}
97
98static enum es_result vc_read_mem(struct es_em_ctxt *ctxt,
99 void *src, char *buf, size_t size)
100{
101 memcpy(buf, src, size);
102
103 return ES_OK;
104}
105
106#undef __init
107#undef __pa
108#define __init
109#define __pa(x) ((unsigned long)(x))
110
111#define __BOOT_COMPRESSED
112
113/* Basic instruction decoding support needed */
114#include "../../lib/inat.c"
115#include "../../lib/insn.c"
116
117/* Include code for early handlers */
118#include "../../kernel/sev-shared.c"
119
120static inline bool sev_snp_enabled(void)
121{
122 return sev_status & MSR_AMD64_SEV_SNP_ENABLED;
123}
124
125static void __page_state_change(unsigned long paddr, enum psc_op op)
126{
127 u64 val;
128
129 if (!sev_snp_enabled())
130 return;
131
132 /*
133 * If private -> shared then invalidate the page before requesting the
134 * state change in the RMP table.
135 */
136 if (op == SNP_PAGE_STATE_SHARED && pvalidate(paddr, RMP_PG_SIZE_4K, 0))
137 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PVALIDATE);
138
139 /* Issue VMGEXIT to change the page state in RMP table. */
140 sev_es_wr_ghcb_msr(GHCB_MSR_PSC_REQ_GFN(paddr >> PAGE_SHIFT, op));
141 VMGEXIT();
142
143 /* Read the response of the VMGEXIT. */
144 val = sev_es_rd_ghcb_msr();
145 if ((GHCB_RESP_CODE(val) != GHCB_MSR_PSC_RESP) || GHCB_MSR_PSC_RESP_VAL(val))
146 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PSC);
147
148 /*
149 * Now that page state is changed in the RMP table, validate it so that it is
150 * consistent with the RMP entry.
151 */
152 if (op == SNP_PAGE_STATE_PRIVATE && pvalidate(paddr, RMP_PG_SIZE_4K, 1))
153 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PVALIDATE);
154}
155
156void snp_set_page_private(unsigned long paddr)
157{
158 __page_state_change(paddr, SNP_PAGE_STATE_PRIVATE);
159}
160
161void snp_set_page_shared(unsigned long paddr)
162{
163 __page_state_change(paddr, SNP_PAGE_STATE_SHARED);
164}
165
166static bool early_setup_ghcb(void)
167{
168 if (set_page_decrypted((unsigned long)&boot_ghcb_page))
169 return false;
170
171 /* Page is now mapped decrypted, clear it */
172 memset(&boot_ghcb_page, 0, sizeof(boot_ghcb_page));
173
174 boot_ghcb = &boot_ghcb_page;
175
176 /* Initialize lookup tables for the instruction decoder */
177 inat_init_tables();
178
179 /* SNP guest requires the GHCB GPA must be registered */
180 if (sev_snp_enabled())
181 snp_register_ghcb_early(__pa(&boot_ghcb_page));
182
183 return true;
184}
185
186void sev_es_shutdown_ghcb(void)
187{
188 if (!boot_ghcb)
189 return;
190
191 if (!sev_es_check_cpu_features())
192 error("SEV-ES CPU Features missing.");
193
194 /*
195 * GHCB Page must be flushed from the cache and mapped encrypted again.
196 * Otherwise the running kernel will see strange cache effects when
197 * trying to use that page.
198 */
199 if (set_page_encrypted((unsigned long)&boot_ghcb_page))
200 error("Can't map GHCB page encrypted");
201
202 /*
203 * GHCB page is mapped encrypted again and flushed from the cache.
204 * Mark it non-present now to catch bugs when #VC exceptions trigger
205 * after this point.
206 */
207 if (set_page_non_present((unsigned long)&boot_ghcb_page))
208 error("Can't unmap GHCB page");
209}
210
211static void __noreturn sev_es_ghcb_terminate(struct ghcb *ghcb, unsigned int set,
212 unsigned int reason, u64 exit_info_2)
213{
214 u64 exit_info_1 = SVM_VMGEXIT_TERM_REASON(set, reason);
215
216 vc_ghcb_invalidate(ghcb);
217 ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_TERM_REQUEST);
218 ghcb_set_sw_exit_info_1(ghcb, exit_info_1);
219 ghcb_set_sw_exit_info_2(ghcb, exit_info_2);
220
221 sev_es_wr_ghcb_msr(__pa(ghcb));
222 VMGEXIT();
223
224 while (true)
225 asm volatile("hlt\n" : : : "memory");
226}
227
228bool sev_es_check_ghcb_fault(unsigned long address)
229{
230 /* Check whether the fault was on the GHCB page */
231 return ((address & PAGE_MASK) == (unsigned long)&boot_ghcb_page);
232}
233
234void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code)
235{
236 struct es_em_ctxt ctxt;
237 enum es_result result;
238
239 if (!boot_ghcb && !early_setup_ghcb())
240 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ);
241
242 vc_ghcb_invalidate(boot_ghcb);
243 result = vc_init_em_ctxt(&ctxt, regs, exit_code);
244 if (result != ES_OK)
245 goto finish;
246
247 switch (exit_code) {
248 case SVM_EXIT_RDTSC:
249 case SVM_EXIT_RDTSCP:
250 result = vc_handle_rdtsc(boot_ghcb, &ctxt, exit_code);
251 break;
252 case SVM_EXIT_IOIO:
253 result = vc_handle_ioio(boot_ghcb, &ctxt);
254 break;
255 case SVM_EXIT_CPUID:
256 result = vc_handle_cpuid(boot_ghcb, &ctxt);
257 break;
258 default:
259 result = ES_UNSUPPORTED;
260 break;
261 }
262
263finish:
264 if (result == ES_OK)
265 vc_finish_insn(&ctxt);
266 else if (result != ES_RETRY)
267 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ);
268}
269
270static void enforce_vmpl0(void)
271{
272 u64 attrs;
273 int err;
274
275 /*
276 * RMPADJUST modifies RMP permissions of a lesser-privileged (numerically
277 * higher) privilege level. Here, clear the VMPL1 permission mask of the
278 * GHCB page. If the guest is not running at VMPL0, this will fail.
279 *
280 * If the guest is running at VMPL0, it will succeed. Even if that operation
281 * modifies permission bits, it is still ok to do so currently because Linux
282 * SNP guests are supported only on VMPL0 so VMPL1 or higher permission masks
283 * changing is a don't-care.
284 */
285 attrs = 1;
286 if (rmpadjust((unsigned long)&boot_ghcb_page, RMP_PG_SIZE_4K, attrs))
287 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_NOT_VMPL0);
288}
289
290/*
291 * SNP_FEATURES_IMPL_REQ is the mask of SNP features that will need
292 * guest side implementation for proper functioning of the guest. If any
293 * of these features are enabled in the hypervisor but are lacking guest
294 * side implementation, the behavior of the guest will be undefined. The
295 * guest could fail in non-obvious way making it difficult to debug.
296 *
297 * As the behavior of reserved feature bits is unknown to be on the
298 * safe side add them to the required features mask.
299 */
300#define SNP_FEATURES_IMPL_REQ (MSR_AMD64_SNP_VTOM | \
301 MSR_AMD64_SNP_REFLECT_VC | \
302 MSR_AMD64_SNP_RESTRICTED_INJ | \
303 MSR_AMD64_SNP_ALT_INJ | \
304 MSR_AMD64_SNP_DEBUG_SWAP | \
305 MSR_AMD64_SNP_VMPL_SSS | \
306 MSR_AMD64_SNP_SECURE_TSC | \
307 MSR_AMD64_SNP_VMGEXIT_PARAM | \
308 MSR_AMD64_SNP_VMSA_REG_PROTECTION | \
309 MSR_AMD64_SNP_RESERVED_BIT13 | \
310 MSR_AMD64_SNP_RESERVED_BIT15 | \
311 MSR_AMD64_SNP_RESERVED_MASK)
312
313/*
314 * SNP_FEATURES_PRESENT is the mask of SNP features that are implemented
315 * by the guest kernel. As and when a new feature is implemented in the
316 * guest kernel, a corresponding bit should be added to the mask.
317 */
318#define SNP_FEATURES_PRESENT (0)
319
320void snp_check_features(void)
321{
322 u64 unsupported;
323
324 if (!(sev_status & MSR_AMD64_SEV_SNP_ENABLED))
325 return;
326
327 /*
328 * Terminate the boot if hypervisor has enabled any feature lacking
329 * guest side implementation. Pass on the unsupported features mask through
330 * EXIT_INFO_2 of the GHCB protocol so that those features can be reported
331 * as part of the guest boot failure.
332 */
333 unsupported = sev_status & SNP_FEATURES_IMPL_REQ & ~SNP_FEATURES_PRESENT;
334 if (unsupported) {
335 if (ghcb_version < 2 || (!boot_ghcb && !early_setup_ghcb()))
336 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SNP_UNSUPPORTED);
337
338 sev_es_ghcb_terminate(boot_ghcb, SEV_TERM_SET_GEN,
339 GHCB_SNP_UNSUPPORTED, unsupported);
340 }
341}
342
343void sev_enable(struct boot_params *bp)
344{
345 unsigned int eax, ebx, ecx, edx;
346 struct msr m;
347 bool snp;
348
349 /*
350 * bp->cc_blob_address should only be set by boot/compressed kernel.
351 * Initialize it to 0 to ensure that uninitialized values from
352 * buggy bootloaders aren't propagated.
353 */
354 if (bp)
355 bp->cc_blob_address = 0;
356
357 /*
358 * Setup/preliminary detection of SNP. This will be sanity-checked
359 * against CPUID/MSR values later.
360 */
361 snp = snp_init(bp);
362
363 /* Check for the SME/SEV support leaf */
364 eax = 0x80000000;
365 ecx = 0;
366 native_cpuid(&eax, &ebx, &ecx, &edx);
367 if (eax < 0x8000001f)
368 return;
369
370 /*
371 * Check for the SME/SEV feature:
372 * CPUID Fn8000_001F[EAX]
373 * - Bit 0 - Secure Memory Encryption support
374 * - Bit 1 - Secure Encrypted Virtualization support
375 * CPUID Fn8000_001F[EBX]
376 * - Bits 5:0 - Pagetable bit position used to indicate encryption
377 */
378 eax = 0x8000001f;
379 ecx = 0;
380 native_cpuid(&eax, &ebx, &ecx, &edx);
381 /* Check whether SEV is supported */
382 if (!(eax & BIT(1))) {
383 if (snp)
384 error("SEV-SNP support indicated by CC blob, but not CPUID.");
385 return;
386 }
387
388 /* Set the SME mask if this is an SEV guest. */
389 boot_rdmsr(MSR_AMD64_SEV, &m);
390 sev_status = m.q;
391 if (!(sev_status & MSR_AMD64_SEV_ENABLED))
392 return;
393
394 /* Negotiate the GHCB protocol version. */
395 if (sev_status & MSR_AMD64_SEV_ES_ENABLED) {
396 if (!sev_es_negotiate_protocol())
397 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_PROT_UNSUPPORTED);
398 }
399
400 /*
401 * SNP is supported in v2 of the GHCB spec which mandates support for HV
402 * features.
403 */
404 if (sev_status & MSR_AMD64_SEV_SNP_ENABLED) {
405 if (!(get_hv_features() & GHCB_HV_FT_SNP))
406 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SNP_UNSUPPORTED);
407
408 enforce_vmpl0();
409 }
410
411 if (snp && !(sev_status & MSR_AMD64_SEV_SNP_ENABLED))
412 error("SEV-SNP supported indicated by CC blob, but not SEV status MSR.");
413
414 sme_me_mask = BIT_ULL(ebx & 0x3f);
415}
416
417/* Search for Confidential Computing blob in the EFI config table. */
418static struct cc_blob_sev_info *find_cc_blob_efi(struct boot_params *bp)
419{
420 unsigned long cfg_table_pa;
421 unsigned int cfg_table_len;
422 int ret;
423
424 ret = efi_get_conf_table(bp, &cfg_table_pa, &cfg_table_len);
425 if (ret)
426 return NULL;
427
428 return (struct cc_blob_sev_info *)efi_find_vendor_table(bp, cfg_table_pa,
429 cfg_table_len,
430 EFI_CC_BLOB_GUID);
431}
432
433/*
434 * Initial set up of SNP relies on information provided by the
435 * Confidential Computing blob, which can be passed to the boot kernel
436 * by firmware/bootloader in the following ways:
437 *
438 * - via an entry in the EFI config table
439 * - via a setup_data structure, as defined by the Linux Boot Protocol
440 *
441 * Scan for the blob in that order.
442 */
443static struct cc_blob_sev_info *find_cc_blob(struct boot_params *bp)
444{
445 struct cc_blob_sev_info *cc_info;
446
447 cc_info = find_cc_blob_efi(bp);
448 if (cc_info)
449 goto found_cc_info;
450
451 cc_info = find_cc_blob_setup_data(bp);
452 if (!cc_info)
453 return NULL;
454
455found_cc_info:
456 if (cc_info->magic != CC_BLOB_SEV_HDR_MAGIC)
457 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SNP_UNSUPPORTED);
458
459 return cc_info;
460}
461
462/*
463 * Indicate SNP based on presence of SNP-specific CC blob. Subsequent checks
464 * will verify the SNP CPUID/MSR bits.
465 */
466bool snp_init(struct boot_params *bp)
467{
468 struct cc_blob_sev_info *cc_info;
469
470 if (!bp)
471 return false;
472
473 cc_info = find_cc_blob(bp);
474 if (!cc_info)
475 return false;
476
477 /*
478 * If a SNP-specific Confidential Computing blob is present, then
479 * firmware/bootloader have indicated SNP support. Verifying this
480 * involves CPUID checks which will be more reliable if the SNP
481 * CPUID table is used. See comments over snp_setup_cpuid_table() for
482 * more details.
483 */
484 setup_cpuid_table(cc_info);
485
486 /*
487 * Pass run-time kernel a pointer to CC info via boot_params so EFI
488 * config table doesn't need to be searched again during early startup
489 * phase.
490 */
491 bp->cc_blob_address = (u32)(unsigned long)cc_info;
492
493 return true;
494}
495
496void sev_prep_identity_maps(unsigned long top_level_pgt)
497{
498 /*
499 * The Confidential Computing blob is used very early in uncompressed
500 * kernel to find the in-memory CPUID table to handle CPUID
501 * instructions. Make sure an identity-mapping exists so it can be
502 * accessed after switchover.
503 */
504 if (sev_snp_enabled()) {
505 unsigned long cc_info_pa = boot_params->cc_blob_address;
506 struct cc_blob_sev_info *cc_info;
507
508 kernel_add_identity_map(cc_info_pa, cc_info_pa + sizeof(*cc_info));
509
510 cc_info = (struct cc_blob_sev_info *)cc_info_pa;
511 kernel_add_identity_map(cc_info->cpuid_phys, cc_info->cpuid_phys + cc_info->cpuid_len);
512 }
513
514 sev_verify_cbit(top_level_pgt);
515}