1/*
 2 * arch/sh/kernel/cpu/sh4a/clock-sh7770.c
 3 *
 4 * SH7770 support for the clock framework
 5 *
 6 *  Copyright (C) 2005  Paul Mundt
 7 *
 8 * This file is subject to the terms and conditions of the GNU General Public
 9 * License.  See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <asm/clock.h>
15#include <asm/freq.h>
16#include <asm/io.h>
17
18static int ifc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 1 };
19static int bfc_divisors[] = { 1, 1, 1, 1, 1, 8,12, 1 };
20static int pfc_divisors[] = { 1, 8, 1,10,12,16, 1, 1 };
21
22static void master_clk_init(struct clk *clk)
23{
24	clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f];
25}
26
27static struct sh_clk_ops sh7770_master_clk_ops = {
28	.init		= master_clk_init,
29};
30
31static unsigned long module_clk_recalc(struct clk *clk)
32{
33	int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f);
34	return clk->parent->rate / pfc_divisors[idx];
35}
36
37static struct sh_clk_ops sh7770_module_clk_ops = {
38	.recalc		= module_clk_recalc,
39};
40
41static unsigned long bus_clk_recalc(struct clk *clk)
42{
43	int idx = (__raw_readl(FRQCR) & 0x000f);
44	return clk->parent->rate / bfc_divisors[idx];
45}
46
47static struct sh_clk_ops sh7770_bus_clk_ops = {
48	.recalc		= bus_clk_recalc,
49};
50
51static unsigned long cpu_clk_recalc(struct clk *clk)
52{
53	int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f);
54	return clk->parent->rate / ifc_divisors[idx];
55}
56
57static struct sh_clk_ops sh7770_cpu_clk_ops = {
58	.recalc		= cpu_clk_recalc,
59};
60
61static struct sh_clk_ops *sh7770_clk_ops[] = {
62	&sh7770_master_clk_ops,
63	&sh7770_module_clk_ops,
64	&sh7770_bus_clk_ops,
65	&sh7770_cpu_clk_ops,
66};
67
68void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
69{
70	if (idx < ARRAY_SIZE(sh7770_clk_ops))
71		*ops = sh7770_clk_ops[idx];
72}
73

 1// SPDX-License-Identifier: GPL-2.0
 2/*
 3 * arch/sh/kernel/cpu/sh4a/clock-sh7770.c
 4 *
 5 * SH7770 support for the clock framework
 6 *
 7 *  Copyright (C) 2005  Paul Mundt
 
 
 
 
 8 */
 9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <asm/clock.h>
12#include <asm/freq.h>
13#include <asm/io.h>
14
15static int ifc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 1 };
16static int bfc_divisors[] = { 1, 1, 1, 1, 1, 8,12, 1 };
17static int pfc_divisors[] = { 1, 8, 1,10,12,16, 1, 1 };
18
19static void master_clk_init(struct clk *clk)
20{
21	clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f];
22}
23
24static struct sh_clk_ops sh7770_master_clk_ops = {
25	.init		= master_clk_init,
26};
27
28static unsigned long module_clk_recalc(struct clk *clk)
29{
30	int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f);
31	return clk->parent->rate / pfc_divisors[idx];
32}
33
34static struct sh_clk_ops sh7770_module_clk_ops = {
35	.recalc		= module_clk_recalc,
36};
37
38static unsigned long bus_clk_recalc(struct clk *clk)
39{
40	int idx = (__raw_readl(FRQCR) & 0x000f);
41	return clk->parent->rate / bfc_divisors[idx];
42}
43
44static struct sh_clk_ops sh7770_bus_clk_ops = {
45	.recalc		= bus_clk_recalc,
46};
47
48static unsigned long cpu_clk_recalc(struct clk *clk)
49{
50	int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f);
51	return clk->parent->rate / ifc_divisors[idx];
52}
53
54static struct sh_clk_ops sh7770_cpu_clk_ops = {
55	.recalc		= cpu_clk_recalc,
56};
57
58static struct sh_clk_ops *sh7770_clk_ops[] = {
59	&sh7770_master_clk_ops,
60	&sh7770_module_clk_ops,
61	&sh7770_bus_clk_ops,
62	&sh7770_cpu_clk_ops,
63};
64
65void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
66{
67	if (idx < ARRAY_SIZE(sh7770_clk_ops))
68		*ops = sh7770_clk_ops[idx];
69}
70