1/*
 2 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
 3 *
 4 * Loongson 1 Clock Register Definitions.
 5 *
 6 * This program is free software; you can redistribute	it and/or modify it
 7 * under  the terms of	the GNU General	 Public License as published by the
 8 * Free Software Foundation;  either version 2 of the  License, or (at your
 9 * option) any later version.
10 */
11
12#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H
13#define __ASM_MACH_LOONGSON1_REGS_CLK_H
14
15#define LS1X_CLK_REG(x) \
16		((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))
17
18#define LS1X_CLK_PLL_FREQ		LS1X_CLK_REG(0x0)
19#define LS1X_CLK_PLL_DIV		LS1X_CLK_REG(0x4)
20
21/* Clock PLL Divisor Register Bits */
22#define DIV_DC_EN			(0x1 << 31)
23#define DIV_CPU_EN			(0x1 << 25)
24#define DIV_DDR_EN			(0x1 << 19)
25
26#define DIV_DC_SHIFT			26
27#define DIV_CPU_SHIFT			20
28#define DIV_DDR_SHIFT			14
29
30#define DIV_DC_WIDTH			5
31#define DIV_CPU_WIDTH			5
32#define DIV_DDR_WIDTH			5
33
34#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */