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1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
12 *
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24
25#include <asm/tlb.h>
26#include <asm/mach/map.h>
27
28#include <linux/omap-dma.h>
29
30#include "omap_hwmod.h"
31#include "soc.h"
32#include "iomap.h"
33#include "voltage.h"
34#include "powerdomain.h"
35#include "clockdomain.h"
36#include "common.h"
37#include "clock.h"
38#include "clock2xxx.h"
39#include "clock3xxx.h"
40#include "clock44xx.h"
41#include "omap-pm.h"
42#include "sdrc.h"
43#include "control.h"
44#include "serial.h"
45#include "sram.h"
46#include "cm2xxx.h"
47#include "cm3xxx.h"
48#include "prm.h"
49#include "cm.h"
50#include "prcm_mpu44xx.h"
51#include "prminst44xx.h"
52#include "cminst44xx.h"
53#include "prm2xxx.h"
54#include "prm3xxx.h"
55#include "prm44xx.h"
56
57/*
58 * omap_clk_soc_init: points to a function that does the SoC-specific
59 * clock initializations
60 */
61static int (*omap_clk_soc_init)(void);
62
63/*
64 * The machine specific code may provide the extra mapping besides the
65 * default mapping provided here.
66 */
67
68#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
69static struct map_desc omap24xx_io_desc[] __initdata = {
70 {
71 .virtual = L3_24XX_VIRT,
72 .pfn = __phys_to_pfn(L3_24XX_PHYS),
73 .length = L3_24XX_SIZE,
74 .type = MT_DEVICE
75 },
76 {
77 .virtual = L4_24XX_VIRT,
78 .pfn = __phys_to_pfn(L4_24XX_PHYS),
79 .length = L4_24XX_SIZE,
80 .type = MT_DEVICE
81 },
82};
83
84#ifdef CONFIG_SOC_OMAP2420
85static struct map_desc omap242x_io_desc[] __initdata = {
86 {
87 .virtual = DSP_MEM_2420_VIRT,
88 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
89 .length = DSP_MEM_2420_SIZE,
90 .type = MT_DEVICE
91 },
92 {
93 .virtual = DSP_IPI_2420_VIRT,
94 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
95 .length = DSP_IPI_2420_SIZE,
96 .type = MT_DEVICE
97 },
98 {
99 .virtual = DSP_MMU_2420_VIRT,
100 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
101 .length = DSP_MMU_2420_SIZE,
102 .type = MT_DEVICE
103 },
104};
105
106#endif
107
108#ifdef CONFIG_SOC_OMAP2430
109static struct map_desc omap243x_io_desc[] __initdata = {
110 {
111 .virtual = L4_WK_243X_VIRT,
112 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
113 .length = L4_WK_243X_SIZE,
114 .type = MT_DEVICE
115 },
116 {
117 .virtual = OMAP243X_GPMC_VIRT,
118 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
119 .length = OMAP243X_GPMC_SIZE,
120 .type = MT_DEVICE
121 },
122 {
123 .virtual = OMAP243X_SDRC_VIRT,
124 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
125 .length = OMAP243X_SDRC_SIZE,
126 .type = MT_DEVICE
127 },
128 {
129 .virtual = OMAP243X_SMS_VIRT,
130 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
131 .length = OMAP243X_SMS_SIZE,
132 .type = MT_DEVICE
133 },
134};
135#endif
136#endif
137
138#ifdef CONFIG_ARCH_OMAP3
139static struct map_desc omap34xx_io_desc[] __initdata = {
140 {
141 .virtual = L3_34XX_VIRT,
142 .pfn = __phys_to_pfn(L3_34XX_PHYS),
143 .length = L3_34XX_SIZE,
144 .type = MT_DEVICE
145 },
146 {
147 .virtual = L4_34XX_VIRT,
148 .pfn = __phys_to_pfn(L4_34XX_PHYS),
149 .length = L4_34XX_SIZE,
150 .type = MT_DEVICE
151 },
152 {
153 .virtual = OMAP34XX_GPMC_VIRT,
154 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
155 .length = OMAP34XX_GPMC_SIZE,
156 .type = MT_DEVICE
157 },
158 {
159 .virtual = OMAP343X_SMS_VIRT,
160 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
161 .length = OMAP343X_SMS_SIZE,
162 .type = MT_DEVICE
163 },
164 {
165 .virtual = OMAP343X_SDRC_VIRT,
166 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
167 .length = OMAP343X_SDRC_SIZE,
168 .type = MT_DEVICE
169 },
170 {
171 .virtual = L4_PER_34XX_VIRT,
172 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
173 .length = L4_PER_34XX_SIZE,
174 .type = MT_DEVICE
175 },
176 {
177 .virtual = L4_EMU_34XX_VIRT,
178 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
179 .length = L4_EMU_34XX_SIZE,
180 .type = MT_DEVICE
181 },
182};
183#endif
184
185#ifdef CONFIG_SOC_TI81XX
186static struct map_desc omapti81xx_io_desc[] __initdata = {
187 {
188 .virtual = L4_34XX_VIRT,
189 .pfn = __phys_to_pfn(L4_34XX_PHYS),
190 .length = L4_34XX_SIZE,
191 .type = MT_DEVICE
192 }
193};
194#endif
195
196#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
197static struct map_desc omapam33xx_io_desc[] __initdata = {
198 {
199 .virtual = L4_34XX_VIRT,
200 .pfn = __phys_to_pfn(L4_34XX_PHYS),
201 .length = L4_34XX_SIZE,
202 .type = MT_DEVICE
203 },
204 {
205 .virtual = L4_WK_AM33XX_VIRT,
206 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
207 .length = L4_WK_AM33XX_SIZE,
208 .type = MT_DEVICE
209 }
210};
211#endif
212
213#ifdef CONFIG_ARCH_OMAP4
214static struct map_desc omap44xx_io_desc[] __initdata = {
215 {
216 .virtual = L3_44XX_VIRT,
217 .pfn = __phys_to_pfn(L3_44XX_PHYS),
218 .length = L3_44XX_SIZE,
219 .type = MT_DEVICE,
220 },
221 {
222 .virtual = L4_44XX_VIRT,
223 .pfn = __phys_to_pfn(L4_44XX_PHYS),
224 .length = L4_44XX_SIZE,
225 .type = MT_DEVICE,
226 },
227 {
228 .virtual = L4_PER_44XX_VIRT,
229 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
230 .length = L4_PER_44XX_SIZE,
231 .type = MT_DEVICE,
232 },
233#ifdef CONFIG_OMAP4_ERRATA_I688
234 {
235 .virtual = OMAP4_SRAM_VA,
236 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
237 .length = PAGE_SIZE,
238 .type = MT_MEMORY_RW_SO,
239 },
240#endif
241
242};
243#endif
244
245#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
246static struct map_desc omap54xx_io_desc[] __initdata = {
247 {
248 .virtual = L3_54XX_VIRT,
249 .pfn = __phys_to_pfn(L3_54XX_PHYS),
250 .length = L3_54XX_SIZE,
251 .type = MT_DEVICE,
252 },
253 {
254 .virtual = L4_54XX_VIRT,
255 .pfn = __phys_to_pfn(L4_54XX_PHYS),
256 .length = L4_54XX_SIZE,
257 .type = MT_DEVICE,
258 },
259 {
260 .virtual = L4_WK_54XX_VIRT,
261 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
262 .length = L4_WK_54XX_SIZE,
263 .type = MT_DEVICE,
264 },
265 {
266 .virtual = L4_PER_54XX_VIRT,
267 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
268 .length = L4_PER_54XX_SIZE,
269 .type = MT_DEVICE,
270 },
271#ifdef CONFIG_OMAP4_ERRATA_I688
272 {
273 .virtual = OMAP4_SRAM_VA,
274 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
275 .length = PAGE_SIZE,
276 .type = MT_MEMORY_RW_SO,
277 },
278#endif
279};
280#endif
281
282#ifdef CONFIG_SOC_OMAP2420
283void __init omap242x_map_io(void)
284{
285 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
286 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
287}
288#endif
289
290#ifdef CONFIG_SOC_OMAP2430
291void __init omap243x_map_io(void)
292{
293 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
294 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
295}
296#endif
297
298#ifdef CONFIG_ARCH_OMAP3
299void __init omap3_map_io(void)
300{
301 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
302}
303#endif
304
305#ifdef CONFIG_SOC_TI81XX
306void __init ti81xx_map_io(void)
307{
308 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
309}
310#endif
311
312#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
313void __init am33xx_map_io(void)
314{
315 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
316}
317#endif
318
319#ifdef CONFIG_ARCH_OMAP4
320void __init omap4_map_io(void)
321{
322 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
323 omap_barriers_init();
324}
325#endif
326
327#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
328void __init omap5_map_io(void)
329{
330 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
331 omap_barriers_init();
332}
333#endif
334/*
335 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
336 *
337 * Sets the CORE DPLL3 M2 divider to the same value that it's at
338 * currently. This has the effect of setting the SDRC SDRAM AC timing
339 * registers to the values currently defined by the kernel. Currently
340 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
341 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
342 * or passes along the return value of clk_set_rate().
343 */
344static int __init _omap2_init_reprogram_sdrc(void)
345{
346 struct clk *dpll3_m2_ck;
347 int v = -EINVAL;
348 long rate;
349
350 if (!cpu_is_omap34xx())
351 return 0;
352
353 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
354 if (IS_ERR(dpll3_m2_ck))
355 return -EINVAL;
356
357 rate = clk_get_rate(dpll3_m2_ck);
358 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
359 v = clk_set_rate(dpll3_m2_ck, rate);
360 if (v)
361 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
362
363 clk_put(dpll3_m2_ck);
364
365 return v;
366}
367
368static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
369{
370 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
371}
372
373static void __init omap_hwmod_init_postsetup(void)
374{
375 u8 postsetup_state;
376
377 /* Set the default postsetup state for all hwmods */
378#ifdef CONFIG_PM_RUNTIME
379 postsetup_state = _HWMOD_STATE_IDLE;
380#else
381 postsetup_state = _HWMOD_STATE_ENABLED;
382#endif
383 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
384
385 omap_pm_if_early_init();
386}
387
388static void __init __maybe_unused omap_common_late_init(void)
389{
390 omap_mux_late_init();
391 omap2_common_pm_late_init();
392 omap_soc_device_init();
393}
394
395#ifdef CONFIG_SOC_OMAP2420
396void __init omap2420_init_early(void)
397{
398 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
399 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
400 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
401 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
402 NULL);
403 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
404 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
405 omap2xxx_check_revision();
406 omap2xxx_prm_init();
407 omap2xxx_cm_init();
408 omap2xxx_voltagedomains_init();
409 omap242x_powerdomains_init();
410 omap242x_clockdomains_init();
411 omap2420_hwmod_init();
412 omap_hwmod_init_postsetup();
413 omap_clk_soc_init = omap2420_clk_init;
414}
415
416void __init omap2420_init_late(void)
417{
418 omap_common_late_init();
419 omap2_pm_init();
420 omap2_clk_enable_autoidle_all();
421}
422#endif
423
424#ifdef CONFIG_SOC_OMAP2430
425void __init omap2430_init_early(void)
426{
427 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
428 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
429 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
430 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
431 NULL);
432 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
433 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
434 omap2xxx_check_revision();
435 omap2xxx_prm_init();
436 omap2xxx_cm_init();
437 omap2xxx_voltagedomains_init();
438 omap243x_powerdomains_init();
439 omap243x_clockdomains_init();
440 omap2430_hwmod_init();
441 omap_hwmod_init_postsetup();
442 omap_clk_soc_init = omap2430_clk_init;
443}
444
445void __init omap2430_init_late(void)
446{
447 omap_common_late_init();
448 omap2_pm_init();
449 omap2_clk_enable_autoidle_all();
450}
451#endif
452
453/*
454 * Currently only board-omap3beagle.c should call this because of the
455 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
456 */
457#ifdef CONFIG_ARCH_OMAP3
458void __init omap3_init_early(void)
459{
460 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
461 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
462 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
463 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
464 NULL);
465 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
466 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
467 omap3xxx_check_revision();
468 omap3xxx_check_features();
469 omap3xxx_prm_init();
470 omap3xxx_cm_init();
471 omap3xxx_voltagedomains_init();
472 omap3xxx_powerdomains_init();
473 omap3xxx_clockdomains_init();
474 omap3xxx_hwmod_init();
475 omap_hwmod_init_postsetup();
476 omap_clk_soc_init = omap3xxx_clk_init;
477}
478
479void __init omap3430_init_early(void)
480{
481 omap3_init_early();
482 if (of_have_populated_dt())
483 omap_clk_soc_init = omap3430_dt_clk_init;
484}
485
486void __init omap35xx_init_early(void)
487{
488 omap3_init_early();
489 if (of_have_populated_dt())
490 omap_clk_soc_init = omap3430_dt_clk_init;
491}
492
493void __init omap3630_init_early(void)
494{
495 omap3_init_early();
496 if (of_have_populated_dt())
497 omap_clk_soc_init = omap3630_dt_clk_init;
498}
499
500void __init am35xx_init_early(void)
501{
502 omap3_init_early();
503 if (of_have_populated_dt())
504 omap_clk_soc_init = am35xx_dt_clk_init;
505}
506
507void __init ti81xx_init_early(void)
508{
509 omap2_set_globals_tap(OMAP343X_CLASS,
510 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
511 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
512 NULL);
513 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
514 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
515 omap3xxx_check_revision();
516 ti81xx_check_features();
517 omap3xxx_voltagedomains_init();
518 omap3xxx_powerdomains_init();
519 omap3xxx_clockdomains_init();
520 omap3xxx_hwmod_init();
521 omap_hwmod_init_postsetup();
522 if (of_have_populated_dt())
523 omap_clk_soc_init = ti81xx_dt_clk_init;
524 else
525 omap_clk_soc_init = omap3xxx_clk_init;
526}
527
528void __init omap3_init_late(void)
529{
530 omap_common_late_init();
531 omap3_pm_init();
532 omap2_clk_enable_autoidle_all();
533}
534
535void __init omap3430_init_late(void)
536{
537 omap_common_late_init();
538 omap3_pm_init();
539 omap2_clk_enable_autoidle_all();
540}
541
542void __init omap35xx_init_late(void)
543{
544 omap_common_late_init();
545 omap3_pm_init();
546 omap2_clk_enable_autoidle_all();
547}
548
549void __init omap3630_init_late(void)
550{
551 omap_common_late_init();
552 omap3_pm_init();
553 omap2_clk_enable_autoidle_all();
554}
555
556void __init am35xx_init_late(void)
557{
558 omap_common_late_init();
559 omap3_pm_init();
560 omap2_clk_enable_autoidle_all();
561}
562
563void __init ti81xx_init_late(void)
564{
565 omap_common_late_init();
566 omap3_pm_init();
567 omap2_clk_enable_autoidle_all();
568}
569#endif
570
571#ifdef CONFIG_SOC_AM33XX
572void __init am33xx_init_early(void)
573{
574 omap2_set_globals_tap(AM335X_CLASS,
575 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
576 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
577 NULL);
578 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
579 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
580 omap3xxx_check_revision();
581 am33xx_check_features();
582 am33xx_powerdomains_init();
583 am33xx_clockdomains_init();
584 am33xx_hwmod_init();
585 omap_hwmod_init_postsetup();
586 omap_clk_soc_init = am33xx_dt_clk_init;
587}
588
589void __init am33xx_init_late(void)
590{
591 omap_common_late_init();
592}
593#endif
594
595#ifdef CONFIG_SOC_AM43XX
596void __init am43xx_init_early(void)
597{
598 omap2_set_globals_tap(AM335X_CLASS,
599 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
600 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
601 NULL);
602 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
603 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
604 omap_prm_base_init();
605 omap_cm_base_init();
606 omap3xxx_check_revision();
607 am33xx_check_features();
608 am43xx_powerdomains_init();
609 am43xx_clockdomains_init();
610 am43xx_hwmod_init();
611 omap_hwmod_init_postsetup();
612 omap_clk_soc_init = am43xx_dt_clk_init;
613}
614
615void __init am43xx_init_late(void)
616{
617 omap_common_late_init();
618}
619#endif
620
621#ifdef CONFIG_ARCH_OMAP4
622void __init omap4430_init_early(void)
623{
624 omap2_set_globals_tap(OMAP443X_CLASS,
625 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
626 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
627 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
628 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
629 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
630 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
631 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
632 omap_prm_base_init();
633 omap_cm_base_init();
634 omap4xxx_check_revision();
635 omap4xxx_check_features();
636 omap4_pm_init_early();
637 omap44xx_prm_init();
638 omap44xx_voltagedomains_init();
639 omap44xx_powerdomains_init();
640 omap44xx_clockdomains_init();
641 omap44xx_hwmod_init();
642 omap_hwmod_init_postsetup();
643 omap_clk_soc_init = omap4xxx_dt_clk_init;
644}
645
646void __init omap4430_init_late(void)
647{
648 omap_common_late_init();
649 omap4_pm_init();
650 omap2_clk_enable_autoidle_all();
651}
652#endif
653
654#ifdef CONFIG_SOC_OMAP5
655void __init omap5_init_early(void)
656{
657 omap2_set_globals_tap(OMAP54XX_CLASS,
658 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
659 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
660 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
661 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
662 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
663 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
664 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
665 omap_prm_base_init();
666 omap_cm_base_init();
667 omap44xx_prm_init();
668 omap5xxx_check_revision();
669 omap54xx_voltagedomains_init();
670 omap54xx_powerdomains_init();
671 omap54xx_clockdomains_init();
672 omap54xx_hwmod_init();
673 omap_hwmod_init_postsetup();
674 omap_clk_soc_init = omap5xxx_dt_clk_init;
675}
676
677void __init omap5_init_late(void)
678{
679 omap_common_late_init();
680}
681#endif
682
683#ifdef CONFIG_SOC_DRA7XX
684void __init dra7xx_init_early(void)
685{
686 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
687 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
688 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
689 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
690 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
691 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
692 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
693 omap_prm_base_init();
694 omap_cm_base_init();
695 omap44xx_prm_init();
696 dra7xx_powerdomains_init();
697 dra7xx_clockdomains_init();
698 dra7xx_hwmod_init();
699 omap_hwmod_init_postsetup();
700 omap_clk_soc_init = dra7xx_dt_clk_init;
701}
702
703void __init dra7xx_init_late(void)
704{
705 omap_common_late_init();
706}
707#endif
708
709
710void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
711 struct omap_sdrc_params *sdrc_cs1)
712{
713 omap_sram_init();
714
715 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
716 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
717 _omap2_init_reprogram_sdrc();
718 }
719}
720
721int __init omap_clk_init(void)
722{
723 int ret = 0;
724
725 if (!omap_clk_soc_init)
726 return 0;
727
728 ret = of_prcm_init();
729 if (!ret)
730 ret = omap_clk_soc_init();
731
732 return ret;
733}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-omap2/io.c
4 *
5 * OMAP2 I/O mapping code
6 *
7 * Copyright (C) 2005 Nokia Corporation
8 * Copyright (C) 2007-2009 Texas Instruments
9 *
10 * Author:
11 * Juha Yrjola <juha.yrjola@nokia.com>
12 * Syed Khasim <x0khasim@ti.com>
13 *
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 */
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/clk.h>
21
22#include <asm/tlb.h>
23#include <asm/mach/map.h>
24
25#include <linux/omap-dma.h>
26
27#include "omap_hwmod.h"
28#include "soc.h"
29#include "iomap.h"
30#include "voltage.h"
31#include "powerdomain.h"
32#include "clockdomain.h"
33#include "common.h"
34#include "clock.h"
35#include "clock2xxx.h"
36#include "clock3xxx.h"
37#include "sdrc.h"
38#include "control.h"
39#include "serial.h"
40#include "sram.h"
41#include "cm2xxx.h"
42#include "cm3xxx.h"
43#include "cm33xx.h"
44#include "cm44xx.h"
45#include "prm.h"
46#include "cm.h"
47#include "prcm_mpu44xx.h"
48#include "prminst44xx.h"
49#include "prm2xxx.h"
50#include "prm3xxx.h"
51#include "prm33xx.h"
52#include "prm44xx.h"
53#include "opp2xxx.h"
54#include "omap-secure.h"
55
56/*
57 * omap_clk_soc_init: points to a function that does the SoC-specific
58 * clock initializations
59 */
60static int (*omap_clk_soc_init)(void);
61
62/*
63 * The machine specific code may provide the extra mapping besides the
64 * default mapping provided here.
65 */
66
67#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
68static struct map_desc omap24xx_io_desc[] __initdata = {
69 {
70 .virtual = L3_24XX_VIRT,
71 .pfn = __phys_to_pfn(L3_24XX_PHYS),
72 .length = L3_24XX_SIZE,
73 .type = MT_DEVICE
74 },
75 {
76 .virtual = L4_24XX_VIRT,
77 .pfn = __phys_to_pfn(L4_24XX_PHYS),
78 .length = L4_24XX_SIZE,
79 .type = MT_DEVICE
80 },
81};
82
83#ifdef CONFIG_SOC_OMAP2420
84static struct map_desc omap242x_io_desc[] __initdata = {
85 {
86 .virtual = DSP_MEM_2420_VIRT,
87 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
88 .length = DSP_MEM_2420_SIZE,
89 .type = MT_DEVICE
90 },
91 {
92 .virtual = DSP_IPI_2420_VIRT,
93 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
94 .length = DSP_IPI_2420_SIZE,
95 .type = MT_DEVICE
96 },
97 {
98 .virtual = DSP_MMU_2420_VIRT,
99 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
100 .length = DSP_MMU_2420_SIZE,
101 .type = MT_DEVICE
102 },
103};
104
105#endif
106
107#ifdef CONFIG_SOC_OMAP2430
108static struct map_desc omap243x_io_desc[] __initdata = {
109 {
110 .virtual = L4_WK_243X_VIRT,
111 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
112 .length = L4_WK_243X_SIZE,
113 .type = MT_DEVICE
114 },
115 {
116 .virtual = OMAP243X_GPMC_VIRT,
117 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
118 .length = OMAP243X_GPMC_SIZE,
119 .type = MT_DEVICE
120 },
121 {
122 .virtual = OMAP243X_SDRC_VIRT,
123 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
124 .length = OMAP243X_SDRC_SIZE,
125 .type = MT_DEVICE
126 },
127 {
128 .virtual = OMAP243X_SMS_VIRT,
129 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
130 .length = OMAP243X_SMS_SIZE,
131 .type = MT_DEVICE
132 },
133};
134#endif
135#endif
136
137#ifdef CONFIG_ARCH_OMAP3
138static struct map_desc omap34xx_io_desc[] __initdata = {
139 {
140 .virtual = L3_34XX_VIRT,
141 .pfn = __phys_to_pfn(L3_34XX_PHYS),
142 .length = L3_34XX_SIZE,
143 .type = MT_DEVICE
144 },
145 {
146 .virtual = L4_34XX_VIRT,
147 .pfn = __phys_to_pfn(L4_34XX_PHYS),
148 .length = L4_34XX_SIZE,
149 .type = MT_DEVICE
150 },
151 {
152 .virtual = OMAP34XX_GPMC_VIRT,
153 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
154 .length = OMAP34XX_GPMC_SIZE,
155 .type = MT_DEVICE
156 },
157 {
158 .virtual = OMAP343X_SMS_VIRT,
159 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
160 .length = OMAP343X_SMS_SIZE,
161 .type = MT_DEVICE
162 },
163 {
164 .virtual = OMAP343X_SDRC_VIRT,
165 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
166 .length = OMAP343X_SDRC_SIZE,
167 .type = MT_DEVICE
168 },
169 {
170 .virtual = L4_PER_34XX_VIRT,
171 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
172 .length = L4_PER_34XX_SIZE,
173 .type = MT_DEVICE
174 },
175 {
176 .virtual = L4_EMU_34XX_VIRT,
177 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
178 .length = L4_EMU_34XX_SIZE,
179 .type = MT_DEVICE
180 },
181};
182#endif
183
184#ifdef CONFIG_SOC_TI81XX
185static struct map_desc omapti81xx_io_desc[] __initdata = {
186 {
187 .virtual = L4_34XX_VIRT,
188 .pfn = __phys_to_pfn(L4_34XX_PHYS),
189 .length = L4_34XX_SIZE,
190 .type = MT_DEVICE
191 }
192};
193#endif
194
195#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
196static struct map_desc omapam33xx_io_desc[] __initdata = {
197 {
198 .virtual = L4_34XX_VIRT,
199 .pfn = __phys_to_pfn(L4_34XX_PHYS),
200 .length = L4_34XX_SIZE,
201 .type = MT_DEVICE
202 },
203 {
204 .virtual = L4_WK_AM33XX_VIRT,
205 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
206 .length = L4_WK_AM33XX_SIZE,
207 .type = MT_DEVICE
208 }
209};
210#endif
211
212#ifdef CONFIG_ARCH_OMAP4
213static struct map_desc omap44xx_io_desc[] __initdata = {
214 {
215 .virtual = L3_44XX_VIRT,
216 .pfn = __phys_to_pfn(L3_44XX_PHYS),
217 .length = L3_44XX_SIZE,
218 .type = MT_DEVICE,
219 },
220 {
221 .virtual = L4_44XX_VIRT,
222 .pfn = __phys_to_pfn(L4_44XX_PHYS),
223 .length = L4_44XX_SIZE,
224 .type = MT_DEVICE,
225 },
226 {
227 .virtual = L4_PER_44XX_VIRT,
228 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
229 .length = L4_PER_44XX_SIZE,
230 .type = MT_DEVICE,
231 },
232};
233#endif
234
235#ifdef CONFIG_SOC_OMAP5
236static struct map_desc omap54xx_io_desc[] __initdata = {
237 {
238 .virtual = L3_54XX_VIRT,
239 .pfn = __phys_to_pfn(L3_54XX_PHYS),
240 .length = L3_54XX_SIZE,
241 .type = MT_DEVICE,
242 },
243 {
244 .virtual = L4_54XX_VIRT,
245 .pfn = __phys_to_pfn(L4_54XX_PHYS),
246 .length = L4_54XX_SIZE,
247 .type = MT_DEVICE,
248 },
249 {
250 .virtual = L4_WK_54XX_VIRT,
251 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
252 .length = L4_WK_54XX_SIZE,
253 .type = MT_DEVICE,
254 },
255 {
256 .virtual = L4_PER_54XX_VIRT,
257 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
258 .length = L4_PER_54XX_SIZE,
259 .type = MT_DEVICE,
260 },
261};
262#endif
263
264#ifdef CONFIG_SOC_DRA7XX
265static struct map_desc dra7xx_io_desc[] __initdata = {
266 {
267 .virtual = L4_CFG_MPU_DRA7XX_VIRT,
268 .pfn = __phys_to_pfn(L4_CFG_MPU_DRA7XX_PHYS),
269 .length = L4_CFG_MPU_DRA7XX_SIZE,
270 .type = MT_DEVICE,
271 },
272 {
273 .virtual = L3_MAIN_SN_DRA7XX_VIRT,
274 .pfn = __phys_to_pfn(L3_MAIN_SN_DRA7XX_PHYS),
275 .length = L3_MAIN_SN_DRA7XX_SIZE,
276 .type = MT_DEVICE,
277 },
278 {
279 .virtual = L4_PER1_DRA7XX_VIRT,
280 .pfn = __phys_to_pfn(L4_PER1_DRA7XX_PHYS),
281 .length = L4_PER1_DRA7XX_SIZE,
282 .type = MT_DEVICE,
283 },
284 {
285 .virtual = L4_PER2_DRA7XX_VIRT,
286 .pfn = __phys_to_pfn(L4_PER2_DRA7XX_PHYS),
287 .length = L4_PER2_DRA7XX_SIZE,
288 .type = MT_DEVICE,
289 },
290 {
291 .virtual = L4_PER3_DRA7XX_VIRT,
292 .pfn = __phys_to_pfn(L4_PER3_DRA7XX_PHYS),
293 .length = L4_PER3_DRA7XX_SIZE,
294 .type = MT_DEVICE,
295 },
296 {
297 .virtual = L4_CFG_DRA7XX_VIRT,
298 .pfn = __phys_to_pfn(L4_CFG_DRA7XX_PHYS),
299 .length = L4_CFG_DRA7XX_SIZE,
300 .type = MT_DEVICE,
301 },
302 {
303 .virtual = L4_WKUP_DRA7XX_VIRT,
304 .pfn = __phys_to_pfn(L4_WKUP_DRA7XX_PHYS),
305 .length = L4_WKUP_DRA7XX_SIZE,
306 .type = MT_DEVICE,
307 },
308};
309#endif
310
311#ifdef CONFIG_SOC_OMAP2420
312void __init omap242x_map_io(void)
313{
314 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
315 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
316}
317#endif
318
319#ifdef CONFIG_SOC_OMAP2430
320void __init omap243x_map_io(void)
321{
322 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
323 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
324}
325#endif
326
327#ifdef CONFIG_ARCH_OMAP3
328void __init omap3_map_io(void)
329{
330 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
331}
332#endif
333
334#ifdef CONFIG_SOC_TI81XX
335void __init ti81xx_map_io(void)
336{
337 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
338}
339#endif
340
341#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
342void __init am33xx_map_io(void)
343{
344 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
345}
346#endif
347
348#ifdef CONFIG_ARCH_OMAP4
349void __init omap4_map_io(void)
350{
351 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
352 omap_barriers_init();
353}
354#endif
355
356#ifdef CONFIG_SOC_OMAP5
357void __init omap5_map_io(void)
358{
359 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
360 omap_barriers_init();
361}
362#endif
363
364#ifdef CONFIG_SOC_DRA7XX
365void __init dra7xx_map_io(void)
366{
367 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
368 omap_barriers_init();
369}
370#endif
371/*
372 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
373 *
374 * Sets the CORE DPLL3 M2 divider to the same value that it's at
375 * currently. This has the effect of setting the SDRC SDRAM AC timing
376 * registers to the values currently defined by the kernel. Currently
377 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
378 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
379 * or passes along the return value of clk_set_rate().
380 */
381static int __init _omap2_init_reprogram_sdrc(void)
382{
383 struct clk *dpll3_m2_ck;
384 int v = -EINVAL;
385 long rate;
386
387 if (!cpu_is_omap34xx())
388 return 0;
389
390 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
391 if (IS_ERR(dpll3_m2_ck))
392 return -EINVAL;
393
394 rate = clk_get_rate(dpll3_m2_ck);
395 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
396 v = clk_set_rate(dpll3_m2_ck, rate);
397 if (v)
398 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
399
400 clk_put(dpll3_m2_ck);
401
402 return v;
403}
404
405#ifdef CONFIG_OMAP_HWMOD
406static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
407{
408 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
409}
410
411static void __init __maybe_unused omap_hwmod_init_postsetup(void)
412{
413 u8 postsetup_state = _HWMOD_STATE_DEFAULT;
414
415 /* Set the default postsetup state for all hwmods */
416 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
417}
418#else
419static inline void omap_hwmod_init_postsetup(void)
420{
421}
422#endif
423
424#ifdef CONFIG_SOC_OMAP2420
425void __init omap2420_init_early(void)
426{
427 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
428 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
429 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
430 omap2_control_base_init();
431 omap2xxx_check_revision();
432 omap2_prcm_base_init();
433 omap2xxx_voltagedomains_init();
434 omap242x_powerdomains_init();
435 omap242x_clockdomains_init();
436 omap2420_hwmod_init();
437 omap_hwmod_init_postsetup();
438 omap_clk_soc_init = omap2420_dt_clk_init;
439 rate_table = omap2420_rate_table;
440}
441
442void __init omap2420_init_late(void)
443{
444 omap_pm_soc_init = omap2_pm_init;
445}
446#endif
447
448#ifdef CONFIG_SOC_OMAP2430
449void __init omap2430_init_early(void)
450{
451 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
452 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
453 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
454 omap2_control_base_init();
455 omap2xxx_check_revision();
456 omap2_prcm_base_init();
457 omap2xxx_voltagedomains_init();
458 omap243x_powerdomains_init();
459 omap243x_clockdomains_init();
460 omap2430_hwmod_init();
461 omap_hwmod_init_postsetup();
462 omap_clk_soc_init = omap2430_dt_clk_init;
463 rate_table = omap2430_rate_table;
464}
465
466void __init omap2430_init_late(void)
467{
468 omap_pm_soc_init = omap2_pm_init;
469}
470#endif
471
472/*
473 * Currently only board-omap3beagle.c should call this because of the
474 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
475 */
476#ifdef CONFIG_ARCH_OMAP3
477void __init omap3_init_early(void)
478{
479 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
480 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
481 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
482 omap2_control_base_init();
483 omap3xxx_check_revision();
484 omap3xxx_check_features();
485 omap2_prcm_base_init();
486 omap3xxx_voltagedomains_init();
487 omap3xxx_powerdomains_init();
488 omap3xxx_clockdomains_init();
489 omap3xxx_hwmod_init();
490 omap_hwmod_init_postsetup();
491 omap_secure_init();
492}
493
494void __init omap3430_init_early(void)
495{
496 omap3_init_early();
497 omap_clk_soc_init = omap3430_dt_clk_init;
498}
499
500void __init omap35xx_init_early(void)
501{
502 omap3_init_early();
503 omap_clk_soc_init = omap3430_dt_clk_init;
504}
505
506void __init omap3630_init_early(void)
507{
508 omap3_init_early();
509 omap_clk_soc_init = omap3630_dt_clk_init;
510}
511
512void __init am35xx_init_early(void)
513{
514 omap3_init_early();
515 omap_clk_soc_init = am35xx_dt_clk_init;
516}
517
518void __init omap3_init_late(void)
519{
520 omap_pm_soc_init = omap3_pm_init;
521}
522
523void __init ti81xx_init_late(void)
524{
525 omap_pm_soc_init = omap_pm_nop_init;
526}
527#endif
528
529#ifdef CONFIG_SOC_TI81XX
530void __init ti814x_init_early(void)
531{
532 omap2_set_globals_tap(TI814X_CLASS,
533 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
534 omap2_control_base_init();
535 omap3xxx_check_revision();
536 ti81xx_check_features();
537 omap2_prcm_base_init();
538 omap3xxx_voltagedomains_init();
539 omap3xxx_powerdomains_init();
540 ti814x_clockdomains_init();
541 dm814x_hwmod_init();
542 omap_hwmod_init_postsetup();
543 omap_clk_soc_init = dm814x_dt_clk_init;
544 omap_secure_init();
545}
546
547void __init ti816x_init_early(void)
548{
549 omap2_set_globals_tap(TI816X_CLASS,
550 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
551 omap2_control_base_init();
552 omap3xxx_check_revision();
553 ti81xx_check_features();
554 omap2_prcm_base_init();
555 omap3xxx_voltagedomains_init();
556 omap3xxx_powerdomains_init();
557 ti816x_clockdomains_init();
558 dm816x_hwmod_init();
559 omap_hwmod_init_postsetup();
560 omap_clk_soc_init = dm816x_dt_clk_init;
561 omap_secure_init();
562}
563#endif
564
565#ifdef CONFIG_SOC_AM33XX
566void __init am33xx_init_early(void)
567{
568 omap2_set_globals_tap(AM335X_CLASS,
569 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
570 omap2_control_base_init();
571 omap3xxx_check_revision();
572 am33xx_check_features();
573 omap2_prcm_base_init();
574 am33xx_powerdomains_init();
575 am33xx_clockdomains_init();
576 omap_clk_soc_init = am33xx_dt_clk_init;
577 omap_secure_init();
578}
579
580void __init am33xx_init_late(void)
581{
582 omap_pm_soc_init = amx3_common_pm_init;
583}
584#endif
585
586#ifdef CONFIG_SOC_AM43XX
587void __init am43xx_init_early(void)
588{
589 omap2_set_globals_tap(AM335X_CLASS,
590 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
591 omap2_control_base_init();
592 omap3xxx_check_revision();
593 am33xx_check_features();
594 omap2_prcm_base_init();
595 am43xx_powerdomains_init();
596 am43xx_clockdomains_init();
597 omap_l2_cache_init();
598 omap_clk_soc_init = am43xx_dt_clk_init;
599 omap_secure_init();
600}
601
602void __init am43xx_init_late(void)
603{
604 omap_pm_soc_init = amx3_common_pm_init;
605}
606#endif
607
608#ifdef CONFIG_ARCH_OMAP4
609void __init omap4430_init_early(void)
610{
611 omap2_set_globals_tap(OMAP443X_CLASS,
612 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
613 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
614 omap2_control_base_init();
615 omap4xxx_check_revision();
616 omap4xxx_check_features();
617 omap2_prcm_base_init();
618 omap4_sar_ram_init();
619 omap4_mpuss_early_init();
620 omap4_pm_init_early();
621 omap44xx_voltagedomains_init();
622 omap44xx_powerdomains_init();
623 omap44xx_clockdomains_init();
624 omap_l2_cache_init();
625 omap_clk_soc_init = omap4xxx_dt_clk_init;
626 omap_secure_init();
627}
628
629void __init omap4430_init_late(void)
630{
631 omap_pm_soc_init = omap4_pm_init;
632}
633#endif
634
635#ifdef CONFIG_SOC_OMAP5
636void __init omap5_init_early(void)
637{
638 omap2_set_globals_tap(OMAP54XX_CLASS,
639 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
640 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
641 omap2_control_base_init();
642 omap2_prcm_base_init();
643 omap5xxx_check_revision();
644 omap4_sar_ram_init();
645 omap4_mpuss_early_init();
646 omap4_pm_init_early();
647 omap54xx_voltagedomains_init();
648 omap54xx_powerdomains_init();
649 omap54xx_clockdomains_init();
650 omap_clk_soc_init = omap5xxx_dt_clk_init;
651 omap_secure_init();
652}
653
654void __init omap5_init_late(void)
655{
656 omap_pm_soc_init = omap4_pm_init;
657}
658#endif
659
660#ifdef CONFIG_SOC_DRA7XX
661void __init dra7xx_init_early(void)
662{
663 omap2_set_globals_tap(DRA7XX_CLASS,
664 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
665 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
666 omap2_control_base_init();
667 omap4_pm_init_early();
668 omap2_prcm_base_init();
669 dra7xxx_check_revision();
670 dra7xx_powerdomains_init();
671 dra7xx_clockdomains_init();
672 omap_clk_soc_init = dra7xx_dt_clk_init;
673 omap_secure_init();
674}
675
676void __init dra7xx_init_late(void)
677{
678 omap_pm_soc_init = omap4_pm_init;
679}
680#endif
681
682
683void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
684 struct omap_sdrc_params *sdrc_cs1)
685{
686 omap_sram_init();
687
688 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
689 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
690 _omap2_init_reprogram_sdrc();
691 }
692}
693
694int __init omap_clk_init(void)
695{
696 int ret = 0;
697
698 if (!omap_clk_soc_init)
699 return 0;
700
701 ti_clk_init_features();
702
703 omap2_clk_setup_ll_ops();
704
705 ret = omap_control_init();
706 if (ret)
707 return ret;
708
709 ret = omap_prcm_init();
710 if (ret)
711 return ret;
712
713 of_clk_init(NULL);
714
715 ti_dt_clk_init_retry_clks();
716
717 ti_dt_clockdomains_setup();
718
719 ret = omap_clk_soc_init();
720
721 return ret;
722}