1/*
   2 * Copyright (c) 2000-2013 LSI Corporation.
   3 *
   4 *
   5 *          Name:  mpi2_ioc.h
   6 *         Title:  MPI IOC, Port, Event, FW Download, and FW Upload messages
   7 * Creation Date:  October 11, 2006
   8 *
   9 * mpi2_ioc.h Version:  02.00.22
  10 *
  11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
  12 *       prefix are for use only on MPI v2.5 products, and must not be used
  13 *       with MPI v2.0 products. Unless otherwise noted, names beginning with
  14 *       MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
  15 *
  16 * Version History
  17 * ---------------
  18 *
  19 * Date      Version   Description
  20 * --------  --------  ------------------------------------------------------
  21 * 04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  22 * 06-04-07  02.00.01  In IOCFacts Reply structure, renamed MaxDevices to
  23 *                     MaxTargets.
  24 *                     Added TotalImageSize field to FWDownload Request.
  25 *                     Added reserved words to FWUpload Request.
  26 * 06-26-07  02.00.02  Added IR Configuration Change List Event.
  27 * 08-31-07  02.00.03  Removed SystemReplyQueueDepth field from the IOCInit
  28 *                     request and replaced it with
  29 *                     ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
  30 *                     Replaced the MinReplyQueueDepth field of the IOCFacts
  31 *                     reply with MaxReplyDescriptorPostQueueDepth.
  32 *                     Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
  33 *                     depth for the Reply Descriptor Post Queue.
  34 *                     Added SASAddress field to Initiator Device Table
  35 *                     Overflow Event data.
  36 * 10-31-07  02.00.04  Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
  37 *                     for SAS Initiator Device Status Change Event data.
  38 *                     Modified Reason Code defines for SAS Topology Change
  39 *                     List Event data, including adding a bit for PHY Vacant
  40 *                     status, and adding a mask for the Reason Code.
  41 *                     Added define for
  42 *                     MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
  43 *                     Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
  44 * 12-18-07  02.00.05  Added Boot Status defines for the IOCExceptions field of
  45 *                     the IOCFacts Reply.
  46 *                     Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  47 *                     Moved MPI2_VERSION_UNION to mpi2.h.
  48 *                     Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
  49 *                     instead of enables, and added SASBroadcastPrimitiveMasks
  50 *                     field.
  51 *                     Added Log Entry Added Event and related structure.
  52 * 02-29-08  02.00.06  Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
  53 *                     Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
  54 *                     Added MaxVolumes and MaxPersistentEntries fields to
  55 *                     IOCFacts reply.
  56 *                     Added ProtocalFlags and IOCCapabilities fields to
  57 *                     MPI2_FW_IMAGE_HEADER.
  58 *                     Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
  59 * 03-03-08  02.00.07  Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
  60 *                     a U16 (from a U32).
  61 *                     Removed extra 's' from EventMasks name.
  62 * 06-27-08  02.00.08  Fixed an offset in a comment.
  63 * 10-02-08  02.00.09  Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
  64 *                     Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
  65 *                     renamed MinReplyFrameSize to ReplyFrameSize.
  66 *                     Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
  67 *                     Added two new RAIDOperation values for Integrated RAID
  68 *                     Operations Status Event data.
  69 *                     Added four new IR Configuration Change List Event data
  70 *                     ReasonCode values.
  71 *                     Added two new ReasonCode defines for SAS Device Status
  72 *                     Change Event data.
  73 *                     Added three new DiscoveryStatus bits for the SAS
  74 *                     Discovery event data.
  75 *                     Added Multiplexing Status Change bit to the PhyStatus
  76 *                     field of the SAS Topology Change List event data.
  77 *                     Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
  78 *                     BootFlags are now product-specific.
  79 *                     Added defines for the indivdual signature bytes
  80 *                     for MPI2_INIT_IMAGE_FOOTER.
  81 * 01-19-09  02.00.10  Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
  82 *                     Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
  83 *                     define.
  84 *                     Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
  85 *                     define.
  86 *                     Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
  87 * 05-06-09  02.00.11  Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
  88 *                     Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
  89 *                     Added two new reason codes for SAS Device Status Change
  90 *                     Event.
  91 *                     Added new event: SAS PHY Counter.
  92 * 07-30-09  02.00.12  Added GPIO Interrupt event define and structure.
  93 *                     Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  94 *                     Added new product id family for 2208.
  95 * 10-28-09  02.00.13  Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
  96 *                     Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
  97 *                     Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
  98 *                     Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
  99 *                     Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
 100 *                     Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
 101 *                     Added Host Based Discovery Phy Event data.
 102 *                     Added defines for ProductID Product field
 103 *                     (MPI2_FW_HEADER_PID_).
 104 *                     Modified values for SAS ProductID Family
 105 *                     (MPI2_FW_HEADER_PID_FAMILY_).
 106 * 02-10-10  02.00.14  Added SAS Quiesce Event structure and defines.
 107 *                     Added PowerManagementControl Request structures and
 108 *                     defines.
 109 * 05-12-10  02.00.15  Marked Task Set Full Event as obsolete.
 110 *                     Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
 111 * 11-10-10  02.00.16  Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
 112 * 02-23-11  02.00.17  Added SAS NOTIFY Primitive event, and added
 113 *                     SASNotifyPrimitiveMasks field to
 114 *                     MPI2_EVENT_NOTIFICATION_REQUEST.
 115 *                     Added Temperature Threshold Event.
 116 *                     Added Host Message Event.
 117 *                     Added Send Host Message request and reply.
 118 * 05-25-11  02.00.18  For Extended Image Header, added
 119 *                     MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
 120 *                     MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
 121 *                     Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
 122 * 08-24-11  02.00.19  Added PhysicalPort field to
 123 *                     MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
 124 *                     Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
 125 * 11-18-11  02.00.20  Incorporating additions for MPI v2.5.
 126 * 03-29-12  02.00.21  Added a product specific range to event values.
 127 * 07-26-12  02.00.22  Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
 128 *                     Added ElapsedSeconds field to
 129 *                     MPI2_EVENT_DATA_IR_OPERATION_STATUS.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 130 * --------------------------------------------------------------------------
 131 */
 132
 133#ifndef MPI2_IOC_H
 134#define MPI2_IOC_H
 135
 136/*****************************************************************************
 137*
 138*              IOC Messages
 139*
 140*****************************************************************************/
 141
 142/****************************************************************************
 143* IOCInit message
 144****************************************************************************/
 145
 146/*IOCInit Request message */
 147typedef struct _MPI2_IOC_INIT_REQUEST {
 148	U8 WhoInit;		/*0x00 */
 149	U8 Reserved1;		/*0x01 */
 150	U8 ChainOffset;		/*0x02 */
 151	U8 Function;		/*0x03 */
 152	U16 Reserved2;		/*0x04 */
 153	U8 Reserved3;		/*0x06 */
 154	U8 MsgFlags;		/*0x07 */
 155	U8 VP_ID;		/*0x08 */
 156	U8 VF_ID;		/*0x09 */
 157	U16 Reserved4;		/*0x0A */
 158	U16 MsgVersion;		/*0x0C */
 159	U16 HeaderVersion;	/*0x0E */
 160	U32 Reserved5;		/*0x10 */
 161	U16 Reserved6;		/*0x14 */
 162	U8 Reserved7;		/*0x16 */
 163	U8 HostMSIxVectors;	/*0x17 */
 164	U16 Reserved8;		/*0x18 */
 165	U16 SystemRequestFrameSize;	/*0x1A */
 166	U16 ReplyDescriptorPostQueueDepth;	/*0x1C */
 167	U16 ReplyFreeQueueDepth;	/*0x1E */
 168	U32 SenseBufferAddressHigh;	/*0x20 */
 169	U32 SystemReplyAddressHigh;	/*0x24 */
 170	U64 SystemRequestFrameBaseAddress;	/*0x28 */
 171	U64 ReplyDescriptorPostQueueAddress;	/*0x30 */
 172	U64 ReplyFreeQueueAddress;	/*0x38 */
 173	U64 TimeStamp;		/*0x40 */
 174} MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST,
 175	Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t;
 176
 177/*WhoInit values */
 178#define MPI2_WHOINIT_NOT_INITIALIZED            (0x00)
 179#define MPI2_WHOINIT_SYSTEM_BIOS                (0x01)
 180#define MPI2_WHOINIT_ROM_BIOS                   (0x02)
 181#define MPI2_WHOINIT_PCI_PEER                   (0x03)
 182#define MPI2_WHOINIT_HOST_DRIVER                (0x04)
 183#define MPI2_WHOINIT_MANUFACTURER               (0x05)
 184
 
 
 
 
 185/*MsgVersion */
 186#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK      (0xFF00)
 187#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT     (8)
 188#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK      (0x00FF)
 189#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT     (0)
 190
 191/*HeaderVersion */
 192#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK       (0xFF00)
 193#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT      (8)
 194#define MPI2_IOCINIT_HDRVERSION_DEV_MASK        (0x00FF)
 195#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT       (0)
 196
 197/*minimum depth for the Reply Descriptor Post Queue */
 
 
 
 
 198#define MPI2_RDPQ_DEPTH_MIN                     (16)
 199
 
 
 
 
 
 
 
 
 
 
 200/*IOCInit Reply message */
 201typedef struct _MPI2_IOC_INIT_REPLY {
 202	U8 WhoInit;		/*0x00 */
 203	U8 Reserved1;		/*0x01 */
 204	U8 MsgLength;		/*0x02 */
 205	U8 Function;		/*0x03 */
 206	U16 Reserved2;		/*0x04 */
 207	U8 Reserved3;		/*0x06 */
 208	U8 MsgFlags;		/*0x07 */
 209	U8 VP_ID;		/*0x08 */
 210	U8 VF_ID;		/*0x09 */
 211	U16 Reserved4;		/*0x0A */
 212	U16 Reserved5;		/*0x0C */
 213	U16 IOCStatus;		/*0x0E */
 214	U32 IOCLogInfo;		/*0x10 */
 215} MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY,
 216	Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t;
 217
 218/****************************************************************************
 219* IOCFacts message
 220****************************************************************************/
 221
 222/*IOCFacts Request message */
 223typedef struct _MPI2_IOC_FACTS_REQUEST {
 224	U16 Reserved1;		/*0x00 */
 225	U8 ChainOffset;		/*0x02 */
 226	U8 Function;		/*0x03 */
 227	U16 Reserved2;		/*0x04 */
 228	U8 Reserved3;		/*0x06 */
 229	U8 MsgFlags;		/*0x07 */
 230	U8 VP_ID;		/*0x08 */
 231	U8 VF_ID;		/*0x09 */
 232	U16 Reserved4;		/*0x0A */
 233} MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST,
 234	Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t;
 235
 236/*IOCFacts Reply message */
 237typedef struct _MPI2_IOC_FACTS_REPLY {
 238	U16 MsgVersion;		/*0x00 */
 239	U8 MsgLength;		/*0x02 */
 240	U8 Function;		/*0x03 */
 241	U16 HeaderVersion;	/*0x04 */
 242	U8 IOCNumber;		/*0x06 */
 243	U8 MsgFlags;		/*0x07 */
 244	U8 VP_ID;		/*0x08 */
 245	U8 VF_ID;		/*0x09 */
 246	U16 Reserved1;		/*0x0A */
 247	U16 IOCExceptions;	/*0x0C */
 248	U16 IOCStatus;		/*0x0E */
 249	U32 IOCLogInfo;		/*0x10 */
 250	U8 MaxChainDepth;	/*0x14 */
 251	U8 WhoInit;		/*0x15 */
 252	U8 NumberOfPorts;	/*0x16 */
 253	U8 MaxMSIxVectors;	/*0x17 */
 254	U16 RequestCredit;	/*0x18 */
 255	U16 ProductID;		/*0x1A */
 256	U32 IOCCapabilities;	/*0x1C */
 257	MPI2_VERSION_UNION FWVersion;	/*0x20 */
 258	U16 IOCRequestFrameSize;	/*0x24 */
 259	U16 IOCMaxChainSegmentSize;	/*0x26 */
 260	U16 MaxInitiators;	/*0x28 */
 261	U16 MaxTargets;		/*0x2A */
 262	U16 MaxSasExpanders;	/*0x2C */
 263	U16 MaxEnclosures;	/*0x2E */
 264	U16 ProtocolFlags;	/*0x30 */
 265	U16 HighPriorityCredit;	/*0x32 */
 266	U16 MaxReplyDescriptorPostQueueDepth;	/*0x34 */
 267	U8 ReplyFrameSize;	/*0x36 */
 268	U8 MaxVolumes;		/*0x37 */
 269	U16 MaxDevHandle;	/*0x38 */
 270	U16 MaxPersistentEntries;	/*0x3A */
 271	U16 MinDevHandle;	/*0x3C */
 272	U16 Reserved4;		/*0x3E */
 
 
 
 
 
 273} MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY,
 274	Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t;
 275
 276/*MsgVersion */
 277#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK             (0xFF00)
 278#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT            (8)
 279#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK             (0x00FF)
 280#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT            (0)
 281
 282/*HeaderVersion */
 283#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK              (0xFF00)
 284#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT             (8)
 285#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK               (0x00FF)
 286#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT              (0)
 287
 288/*IOCExceptions */
 
 289#define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE     (0x0200)
 290#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX      (0x0100)
 291
 292#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK              (0x00E0)
 293#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD              (0x0000)
 294#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP            (0x0020)
 295#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED          (0x0040)
 296#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP    (0x0060)
 297
 298#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED       (0x0010)
 299#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL     (0x0008)
 300#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL           (0x0004)
 301#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID        (0x0002)
 302#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL       (0x0001)
 303
 304/*defines for WhoInit field are after the IOCInit Request */
 305
 306/*ProductID field uses MPI2_FW_HEADER_PID_ */
 307
 308/*IOCCapabilities */
 
 
 
 
 309#define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE     (0x00020000)
 310#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY   (0x00010000)
 311#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX            (0x00008000)
 312#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR       (0x00004000)
 313#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY           (0x00002000)
 314#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID        (0x00001000)
 315#define MPI2_IOCFACTS_CAPABILITY_TLR                    (0x00000800)
 316#define MPI2_IOCFACTS_CAPABILITY_MULTICAST              (0x00000100)
 317#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET   (0x00000080)
 318#define MPI2_IOCFACTS_CAPABILITY_EEDP                   (0x00000040)
 319#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER        (0x00000020)
 320#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER        (0x00000010)
 321#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER      (0x00000008)
 322#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
 323
 324/*ProtocolFlags */
 325#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET              (0x0001)
 326#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR           (0x0002)
 
 327
 328/****************************************************************************
 329* PortFacts message
 330****************************************************************************/
 331
 332/*PortFacts Request message */
 333typedef struct _MPI2_PORT_FACTS_REQUEST {
 334	U16 Reserved1;		/*0x00 */
 335	U8 ChainOffset;		/*0x02 */
 336	U8 Function;		/*0x03 */
 337	U16 Reserved2;		/*0x04 */
 338	U8 PortNumber;		/*0x06 */
 339	U8 MsgFlags;		/*0x07 */
 340	U8 VP_ID;		/*0x08 */
 341	U8 VF_ID;		/*0x09 */
 342	U16 Reserved3;		/*0x0A */
 343} MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST,
 344	Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t;
 345
 346/*PortFacts Reply message */
 347typedef struct _MPI2_PORT_FACTS_REPLY {
 348	U16 Reserved1;		/*0x00 */
 349	U8 MsgLength;		/*0x02 */
 350	U8 Function;		/*0x03 */
 351	U16 Reserved2;		/*0x04 */
 352	U8 PortNumber;		/*0x06 */
 353	U8 MsgFlags;		/*0x07 */
 354	U8 VP_ID;		/*0x08 */
 355	U8 VF_ID;		/*0x09 */
 356	U16 Reserved3;		/*0x0A */
 357	U16 Reserved4;		/*0x0C */
 358	U16 IOCStatus;		/*0x0E */
 359	U32 IOCLogInfo;		/*0x10 */
 360	U8 Reserved5;		/*0x14 */
 361	U8 PortType;		/*0x15 */
 362	U16 Reserved6;		/*0x16 */
 363	U16 MaxPostedCmdBuffers;	/*0x18 */
 364	U16 Reserved7;		/*0x1A */
 365} MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY,
 366	Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t;
 367
 368/*PortType values */
 369#define MPI2_PORTFACTS_PORTTYPE_INACTIVE            (0x00)
 370#define MPI2_PORTFACTS_PORTTYPE_FC                  (0x10)
 371#define MPI2_PORTFACTS_PORTTYPE_ISCSI               (0x20)
 372#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL        (0x30)
 373#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL         (0x31)
 
 
 374
 375/****************************************************************************
 376* PortEnable message
 377****************************************************************************/
 378
 379/*PortEnable Request message */
 380typedef struct _MPI2_PORT_ENABLE_REQUEST {
 381	U16 Reserved1;		/*0x00 */
 382	U8 ChainOffset;		/*0x02 */
 383	U8 Function;		/*0x03 */
 384	U8 Reserved2;		/*0x04 */
 385	U8 PortFlags;		/*0x05 */
 386	U8 Reserved3;		/*0x06 */
 387	U8 MsgFlags;		/*0x07 */
 388	U8 VP_ID;		/*0x08 */
 389	U8 VF_ID;		/*0x09 */
 390	U16 Reserved4;		/*0x0A */
 391} MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST,
 392	Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t;
 393
 394/*PortEnable Reply message */
 395typedef struct _MPI2_PORT_ENABLE_REPLY {
 396	U16 Reserved1;		/*0x00 */
 397	U8 MsgLength;		/*0x02 */
 398	U8 Function;		/*0x03 */
 399	U8 Reserved2;		/*0x04 */
 400	U8 PortFlags;		/*0x05 */
 401	U8 Reserved3;		/*0x06 */
 402	U8 MsgFlags;		/*0x07 */
 403	U8 VP_ID;		/*0x08 */
 404	U8 VF_ID;		/*0x09 */
 405	U16 Reserved4;		/*0x0A */
 406	U16 Reserved5;		/*0x0C */
 407	U16 IOCStatus;		/*0x0E */
 408	U32 IOCLogInfo;		/*0x10 */
 409} MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY,
 410	Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t;
 411
 412/****************************************************************************
 413* EventNotification message
 414****************************************************************************/
 415
 416/*EventNotification Request message */
 417#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS           (4)
 418
 419typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST {
 420	U16 Reserved1;		/*0x00 */
 421	U8 ChainOffset;		/*0x02 */
 422	U8 Function;		/*0x03 */
 423	U16 Reserved2;		/*0x04 */
 424	U8 Reserved3;		/*0x06 */
 425	U8 MsgFlags;		/*0x07 */
 426	U8 VP_ID;		/*0x08 */
 427	U8 VF_ID;		/*0x09 */
 428	U16 Reserved4;		/*0x0A */
 429	U32 Reserved5;		/*0x0C */
 430	U32 Reserved6;		/*0x10 */
 431	U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];	/*0x14 */
 432	U16 SASBroadcastPrimitiveMasks;	/*0x24 */
 433	U16 SASNotifyPrimitiveMasks;	/*0x26 */
 434	U32 Reserved8;		/*0x28 */
 435} MPI2_EVENT_NOTIFICATION_REQUEST,
 436	*PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
 437	Mpi2EventNotificationRequest_t,
 438	*pMpi2EventNotificationRequest_t;
 439
 440/*EventNotification Reply message */
 441typedef struct _MPI2_EVENT_NOTIFICATION_REPLY {
 442	U16 EventDataLength;	/*0x00 */
 443	U8 MsgLength;		/*0x02 */
 444	U8 Function;		/*0x03 */
 445	U16 Reserved1;		/*0x04 */
 446	U8 AckRequired;		/*0x06 */
 447	U8 MsgFlags;		/*0x07 */
 448	U8 VP_ID;		/*0x08 */
 449	U8 VF_ID;		/*0x09 */
 450	U16 Reserved2;		/*0x0A */
 451	U16 Reserved3;		/*0x0C */
 452	U16 IOCStatus;		/*0x0E */
 453	U32 IOCLogInfo;		/*0x10 */
 454	U16 Event;		/*0x14 */
 455	U16 Reserved4;		/*0x16 */
 456	U32 EventContext;	/*0x18 */
 457	U32 EventData[1];	/*0x1C */
 458} MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY,
 459	Mpi2EventNotificationReply_t,
 460	*pMpi2EventNotificationReply_t;
 461
 462/*AckRequired */
 463#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED    (0x00)
 464#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED        (0x01)
 465
 466/*Event */
 467#define MPI2_EVENT_LOG_DATA                         (0x0001)
 468#define MPI2_EVENT_STATE_CHANGE                     (0x0002)
 469#define MPI2_EVENT_HARD_RESET_RECEIVED              (0x0005)
 470#define MPI2_EVENT_EVENT_CHANGE                     (0x000A)
 471#define MPI2_EVENT_TASK_SET_FULL                    (0x000E)	/*obsolete */
 472#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE         (0x000F)
 473#define MPI2_EVENT_IR_OPERATION_STATUS              (0x0014)
 474#define MPI2_EVENT_SAS_DISCOVERY                    (0x0016)
 475#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE          (0x0017)
 476#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE    (0x0018)
 477#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW          (0x0019)
 478#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST         (0x001C)
 479#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE    (0x001D)
 
 480#define MPI2_EVENT_IR_VOLUME                        (0x001E)
 481#define MPI2_EVENT_IR_PHYSICAL_DISK                 (0x001F)
 482#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST     (0x0020)
 483#define MPI2_EVENT_LOG_ENTRY_ADDED                  (0x0021)
 484#define MPI2_EVENT_SAS_PHY_COUNTER                  (0x0022)
 485#define MPI2_EVENT_GPIO_INTERRUPT                   (0x0023)
 486#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY         (0x0024)
 487#define MPI2_EVENT_SAS_QUIESCE                      (0x0025)
 488#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE             (0x0026)
 489#define MPI2_EVENT_TEMP_THRESHOLD                   (0x0027)
 490#define MPI2_EVENT_HOST_MESSAGE                     (0x0028)
 491#define MPI2_EVENT_POWER_PERFORMANCE_CHANGE         (0x0029)
 
 
 
 
 
 
 492#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC             (0x006E)
 493#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC             (0x007F)
 494
 495/*Log Entry Added Event data */
 496
 497/*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
 498#define MPI2_EVENT_DATA_LOG_DATA_LENGTH             (0x1C)
 499
 500typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED {
 501	U64 TimeStamp;		/*0x00 */
 502	U32 Reserved1;		/*0x08 */
 503	U16 LogSequence;	/*0x0C */
 504	U16 LogEntryQualifier;	/*0x0E */
 505	U8 VP_ID;		/*0x10 */
 506	U8 VF_ID;		/*0x11 */
 507	U16 Reserved2;		/*0x12 */
 508	U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];	/*0x14 */
 509} MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 510	*PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 511	Mpi2EventDataLogEntryAdded_t,
 512	*pMpi2EventDataLogEntryAdded_t;
 513
 514/*GPIO Interrupt Event data */
 515
 516typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
 517	U8 GPIONum;		/*0x00 */
 518	U8 Reserved1;		/*0x01 */
 519	U16 Reserved2;		/*0x02 */
 520} MPI2_EVENT_DATA_GPIO_INTERRUPT,
 521	*PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
 522	Mpi2EventDataGpioInterrupt_t,
 523	*pMpi2EventDataGpioInterrupt_t;
 524
 525/*Temperature Threshold Event data */
 526
 527typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
 528	U16 Status;		/*0x00 */
 529	U8 SensorNum;		/*0x02 */
 530	U8 Reserved1;		/*0x03 */
 531	U16 CurrentTemperature;	/*0x04 */
 532	U16 Reserved2;		/*0x06 */
 533	U32 Reserved3;		/*0x08 */
 534	U32 Reserved4;		/*0x0C */
 535} MPI2_EVENT_DATA_TEMPERATURE,
 536	*PTR_MPI2_EVENT_DATA_TEMPERATURE,
 537	Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t;
 538
 539/*Temperature Threshold Event data Status bits */
 540#define MPI2_EVENT_TEMPERATURE3_EXCEEDED            (0x0008)
 541#define MPI2_EVENT_TEMPERATURE2_EXCEEDED            (0x0004)
 542#define MPI2_EVENT_TEMPERATURE1_EXCEEDED            (0x0002)
 543#define MPI2_EVENT_TEMPERATURE0_EXCEEDED            (0x0001)
 544
 545/*Host Message Event data */
 546
 547typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
 548	U8 SourceVF_ID;		/*0x00 */
 549	U8 Reserved1;		/*0x01 */
 550	U16 Reserved2;		/*0x02 */
 551	U32 Reserved3;		/*0x04 */
 552	U32 HostData[1];	/*0x08 */
 553} MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
 554	Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t;
 555
 556/*Power Performance Change Event */
 557
 558typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE {
 559	U8 CurrentPowerMode;	/*0x00 */
 560	U8 PreviousPowerMode;	/*0x01 */
 561	U16 Reserved1;		/*0x02 */
 562} MPI2_EVENT_DATA_POWER_PERF_CHANGE,
 563	*PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
 564	Mpi2EventDataPowerPerfChange_t,
 565	*pMpi2EventDataPowerPerfChange_t;
 566
 567/*defines for CurrentPowerMode and PreviousPowerMode fields */
 568#define MPI2_EVENT_PM_INIT_MASK              (0xC0)
 569#define MPI2_EVENT_PM_INIT_UNAVAILABLE       (0x00)
 570#define MPI2_EVENT_PM_INIT_HOST              (0x40)
 571#define MPI2_EVENT_PM_INIT_IO_UNIT           (0x80)
 572#define MPI2_EVENT_PM_INIT_PCIE_DPA          (0xC0)
 573
 574#define MPI2_EVENT_PM_MODE_MASK              (0x07)
 575#define MPI2_EVENT_PM_MODE_UNAVAILABLE       (0x00)
 576#define MPI2_EVENT_PM_MODE_UNKNOWN           (0x01)
 577#define MPI2_EVENT_PM_MODE_FULL_POWER        (0x04)
 578#define MPI2_EVENT_PM_MODE_REDUCED_POWER     (0x05)
 579#define MPI2_EVENT_PM_MODE_STANDBY           (0x06)
 580
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 581/*Hard Reset Received Event data */
 582
 583typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED {
 584	U8 Reserved1;		/*0x00 */
 585	U8 Port;		/*0x01 */
 586	U16 Reserved2;		/*0x02 */
 587} MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 588	*PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 589	Mpi2EventDataHardResetReceived_t,
 590	*pMpi2EventDataHardResetReceived_t;
 591
 592/*Task Set Full Event data */
 593/*  this event is obsolete */
 594
 595typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL {
 596	U16 DevHandle;		/*0x00 */
 597	U16 CurrentDepth;	/*0x02 */
 598} MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
 599	Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t;
 600
 601/*SAS Device Status Change Event data */
 602
 603typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE {
 604	U16 TaskTag;		/*0x00 */
 605	U8 ReasonCode;		/*0x02 */
 606	U8 PhysicalPort;	/*0x03 */
 607	U8 ASC;			/*0x04 */
 608	U8 ASCQ;		/*0x05 */
 609	U16 DevHandle;		/*0x06 */
 610	U32 Reserved2;		/*0x08 */
 611	U64 SASAddress;		/*0x0C */
 612	U8 LUN[8];		/*0x14 */
 613} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 614	*PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 615	Mpi2EventDataSasDeviceStatusChange_t,
 616	*pMpi2EventDataSasDeviceStatusChange_t;
 617
 618/*SAS Device Status Change Event data ReasonCode values */
 619#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA                           (0x05)
 620#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED                          (0x07)
 621#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET                (0x08)
 622#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL                  (0x09)
 623#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL              (0x0A)
 624#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL              (0x0B)
 625#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL                  (0x0C)
 626#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION                   (0x0D)
 627#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET               (0x0E)
 628#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL              (0x0F)
 629#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE                    (0x10)
 630#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY       (0x11)
 631#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY   (0x12)
 632
 633/*Integrated RAID Operation Status Event data */
 634
 635typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS {
 636	U16 VolDevHandle;	/*0x00 */
 637	U16 Reserved1;		/*0x02 */
 638	U8 RAIDOperation;	/*0x04 */
 639	U8 PercentComplete;	/*0x05 */
 640	U16 Reserved2;		/*0x06 */
 641	U32 ElapsedSeconds;	/*0x08 */
 642} MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 643	*PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 644	Mpi2EventDataIrOperationStatus_t,
 645	*pMpi2EventDataIrOperationStatus_t;
 646
 647/*Integrated RAID Operation Status Event data RAIDOperation values */
 648#define MPI2_EVENT_IR_RAIDOP_RESYNC                     (0x00)
 649#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION       (0x01)
 650#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK          (0x02)
 651#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT            (0x03)
 652#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT       (0x04)
 653
 654/*Integrated RAID Volume Event data */
 655
 656typedef struct _MPI2_EVENT_DATA_IR_VOLUME {
 657	U16 VolDevHandle;	/*0x00 */
 658	U8 ReasonCode;		/*0x02 */
 659	U8 Reserved1;		/*0x03 */
 660	U32 NewValue;		/*0x04 */
 661	U32 PreviousValue;	/*0x08 */
 662} MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME,
 663	Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t;
 664
 665/*Integrated RAID Volume Event data ReasonCode values */
 666#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED        (0x01)
 667#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED    (0x02)
 668#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED           (0x03)
 669
 670/*Integrated RAID Physical Disk Event data */
 671
 672typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK {
 673	U16 Reserved1;		/*0x00 */
 674	U8 ReasonCode;		/*0x02 */
 675	U8 PhysDiskNum;		/*0x03 */
 676	U16 PhysDiskDevHandle;	/*0x04 */
 677	U16 Reserved2;		/*0x06 */
 678	U16 Slot;		/*0x08 */
 679	U16 EnclosureHandle;	/*0x0A */
 680	U32 NewValue;		/*0x0C */
 681	U32 PreviousValue;	/*0x10 */
 682} MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 683	*PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 684	Mpi2EventDataIrPhysicalDisk_t,
 685	*pMpi2EventDataIrPhysicalDisk_t;
 686
 687/*Integrated RAID Physical Disk Event data ReasonCode values */
 688#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED      (0x01)
 689#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED  (0x02)
 690#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED         (0x03)
 691
 692/*Integrated RAID Configuration Change List Event data */
 693
 694/*
 695 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 696 *one and check NumElements at runtime.
 697 */
 698#ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
 699#define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT          (1)
 700#endif
 701
 702typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT {
 703	U16 ElementFlags;	/*0x00 */
 704	U16 VolDevHandle;	/*0x02 */
 705	U8 ReasonCode;		/*0x04 */
 706	U8 PhysDiskNum;		/*0x05 */
 707	U16 PhysDiskDevHandle;	/*0x06 */
 708} MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
 709	Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t;
 710
 711/*IR Configuration Change List Event data ElementFlags values */
 712#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK   (0x000F)
 713#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT      (0x0000)
 714#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
 715#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT    (0x0002)
 716
 717/*IR Configuration Change List Event data ReasonCode values */
 718#define MPI2_EVENT_IR_CHANGE_RC_ADDED                   (0x01)
 719#define MPI2_EVENT_IR_CHANGE_RC_REMOVED                 (0x02)
 720#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE               (0x03)
 721#define MPI2_EVENT_IR_CHANGE_RC_HIDE                    (0x04)
 722#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE                  (0x05)
 723#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED          (0x06)
 724#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED          (0x07)
 725#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED              (0x08)
 726#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED              (0x09)
 727
 728typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST {
 729	U8 NumElements;		/*0x00 */
 730	U8 Reserved1;		/*0x01 */
 731	U8 Reserved2;		/*0x02 */
 732	U8 ConfigNum;		/*0x03 */
 733	U32 Flags;		/*0x04 */
 734	MPI2_EVENT_IR_CONFIG_ELEMENT
 735		ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];/*0x08 */
 736} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 737	*PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 738	Mpi2EventDataIrConfigChangeList_t,
 739	*pMpi2EventDataIrConfigChangeList_t;
 740
 741/*IR Configuration Change List Event data Flags values */
 742#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG   (0x00000001)
 743
 744/*SAS Discovery Event data */
 745
 746typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY {
 747	U8 Flags;		/*0x00 */
 748	U8 ReasonCode;		/*0x01 */
 749	U8 PhysicalPort;	/*0x02 */
 750	U8 Reserved1;		/*0x03 */
 751	U32 DiscoveryStatus;	/*0x04 */
 752} MPI2_EVENT_DATA_SAS_DISCOVERY,
 753	*PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
 754	Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t;
 755
 756/*SAS Discovery Event data Flags values */
 757#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE                   (0x02)
 758#define MPI2_EVENT_SAS_DISC_IN_PROGRESS                     (0x01)
 759
 760/*SAS Discovery Event data ReasonCode values */
 761#define MPI2_EVENT_SAS_DISC_RC_STARTED                      (0x01)
 762#define MPI2_EVENT_SAS_DISC_RC_COMPLETED                    (0x02)
 763
 764/*SAS Discovery Event data DiscoveryStatus values */
 765#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
 766#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
 767#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED               (0x20000000)
 768#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
 769#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR             (0x08000000)
 770#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
 771#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
 772#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN                (0x00002000)
 773#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
 774#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE               (0x00000800)
 775#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK                       (0x00000400)
 776#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK                 (0x00000200)
 777#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR                    (0x00000100)
 778#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED              (0x00000080)
 779#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST                  (0x00000040)
 780#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES                (0x00000020)
 781#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT                      (0x00000010)
 782#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS                   (0x00000004)
 783#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE             (0x00000002)
 784#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED                    (0x00000001)
 785
 786/*SAS Broadcast Primitive Event data */
 787
 788typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE {
 789	U8 PhyNum;		/*0x00 */
 790	U8 Port;		/*0x01 */
 791	U8 PortWidth;		/*0x02 */
 792	U8 Primitive;		/*0x03 */
 793} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 794	*PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 795	Mpi2EventDataSasBroadcastPrimitive_t,
 796	*pMpi2EventDataSasBroadcastPrimitive_t;
 797
 798/*defines for the Primitive field */
 799#define MPI2_EVENT_PRIMITIVE_CHANGE                         (0x01)
 800#define MPI2_EVENT_PRIMITIVE_SES                            (0x02)
 801#define MPI2_EVENT_PRIMITIVE_EXPANDER                       (0x03)
 802#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT             (0x04)
 803#define MPI2_EVENT_PRIMITIVE_RESERVED3                      (0x05)
 804#define MPI2_EVENT_PRIMITIVE_RESERVED4                      (0x06)
 805#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED               (0x07)
 806#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED               (0x08)
 807
 808/*SAS Notify Primitive Event data */
 809
 810typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
 811	U8 PhyNum;		/*0x00 */
 812	U8 Port;		/*0x01 */
 813	U8 Reserved1;		/*0x02 */
 814	U8 Primitive;		/*0x03 */
 815} MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 816	*PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 817	Mpi2EventDataSasNotifyPrimitive_t,
 818	*pMpi2EventDataSasNotifyPrimitive_t;
 819
 820/*defines for the Primitive field */
 821#define MPI2_EVENT_NOTIFY_ENABLE_SPINUP                     (0x01)
 822#define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED               (0x02)
 823#define MPI2_EVENT_NOTIFY_RESERVED1                         (0x03)
 824#define MPI2_EVENT_NOTIFY_RESERVED2                         (0x04)
 825
 826/*SAS Initiator Device Status Change Event data */
 827
 828typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE {
 829	U8 ReasonCode;		/*0x00 */
 830	U8 PhysicalPort;	/*0x01 */
 831	U16 DevHandle;		/*0x02 */
 832	U64 SASAddress;		/*0x04 */
 833} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 834	*PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 835	Mpi2EventDataSasInitDevStatusChange_t,
 836	*pMpi2EventDataSasInitDevStatusChange_t;
 837
 838/*SAS Initiator Device Status Change event ReasonCode values */
 839#define MPI2_EVENT_SAS_INIT_RC_ADDED                (0x01)
 840#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING       (0x02)
 841
 842/*SAS Initiator Device Table Overflow Event data */
 843
 844typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW {
 845	U16 MaxInit;		/*0x00 */
 846	U16 CurrentInit;	/*0x02 */
 847	U64 SASAddress;		/*0x04 */
 848} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 849	*PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 850	Mpi2EventDataSasInitTableOverflow_t,
 851	*pMpi2EventDataSasInitTableOverflow_t;
 852
 853/*SAS Topology Change List Event data */
 854
 855/*
 856 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 857 *one and check NumEntries at runtime.
 858 */
 859#ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
 860#define MPI2_EVENT_SAS_TOPO_PHY_COUNT           (1)
 861#endif
 862
 863typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY {
 864	U16 AttachedDevHandle;	/*0x00 */
 865	U8 LinkRate;		/*0x02 */
 866	U8 PhyStatus;		/*0x03 */
 867} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
 868	Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t;
 869
 870typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST {
 871	U16 EnclosureHandle;	/*0x00 */
 872	U16 ExpanderDevHandle;	/*0x02 */
 873	U8 NumPhys;		/*0x04 */
 874	U8 Reserved1;		/*0x05 */
 875	U16 Reserved2;		/*0x06 */
 876	U8 NumEntries;		/*0x08 */
 877	U8 StartPhyNum;		/*0x09 */
 878	U8 ExpStatus;		/*0x0A */
 879	U8 PhysicalPort;	/*0x0B */
 880	MPI2_EVENT_SAS_TOPO_PHY_ENTRY
 881	PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT];	/*0x0C */
 882} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 883	*PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 884	Mpi2EventDataSasTopologyChangeList_t,
 885	*pMpi2EventDataSasTopologyChangeList_t;
 886
 887/*values for the ExpStatus field */
 888#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER                  (0x00)
 889#define MPI2_EVENT_SAS_TOPO_ES_ADDED                        (0x01)
 890#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING               (0x02)
 891#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING                   (0x03)
 892#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING         (0x04)
 893
 894/*defines for the LinkRate field */
 895#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK                 (0xF0)
 896#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT                (4)
 897#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK                    (0x0F)
 898#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT                   (0)
 899
 900#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE            (0x00)
 901#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED                 (0x01)
 902#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED           (0x02)
 903#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE            (0x03)
 904#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR                (0x04)
 905#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS        (0x05)
 906#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY              (0x06)
 907#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5                     (0x08)
 908#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0                     (0x09)
 909#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0                     (0x0A)
 910#define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0                   (0x0B)
 
 911
 912/*values for the PhyStatus field */
 913#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT                (0x80)
 914#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE             (0x10)
 915/*values for the PhyStatus ReasonCode sub-field */
 916#define MPI2_EVENT_SAS_TOPO_RC_MASK                         (0x0F)
 917#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED                   (0x01)
 918#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING          (0x02)
 919#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED                  (0x03)
 920#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE                    (0x04)
 921#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING         (0x05)
 922
 923/*SAS Enclosure Device Status Change Event data */
 924
 925typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE {
 926	U16 EnclosureHandle;	/*0x00 */
 927	U8 ReasonCode;		/*0x02 */
 928	U8 PhysicalPort;	/*0x03 */
 929	U64 EnclosureLogicalID;	/*0x04 */
 930	U16 NumSlots;		/*0x0C */
 931	U16 StartSlot;		/*0x0E */
 932	U32 PhyBits;		/*0x10 */
 933} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 934	*PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 935	Mpi2EventDataSasEnclDevStatusChange_t,
 936	*pMpi2EventDataSasEnclDevStatusChange_t;
 
 
 
 
 937
 938/*SAS Enclosure Device Status Change event ReasonCode values */
 939#define MPI2_EVENT_SAS_ENCL_RC_ADDED                (0x01)
 940#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING       (0x02)
 941
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 942/*SAS PHY Counter Event data */
 943
 944typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
 945	U64 TimeStamp;		/*0x00 */
 946	U32 Reserved1;		/*0x08 */
 947	U8 PhyEventCode;	/*0x0C */
 948	U8 PhyNum;		/*0x0D */
 949	U16 Reserved2;		/*0x0E */
 950	U32 PhyEventInfo;	/*0x10 */
 951	U8 CounterType;		/*0x14 */
 952	U8 ThresholdWindow;	/*0x15 */
 953	U8 TimeUnits;		/*0x16 */
 954	U8 Reserved3;		/*0x17 */
 955	U32 EventThreshold;	/*0x18 */
 956	U16 ThresholdFlags;	/*0x1C */
 957	U16 Reserved4;		/*0x1E */
 958} MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 959	*PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 960	Mpi2EventDataSasPhyCounter_t,
 961	*pMpi2EventDataSasPhyCounter_t;
 962
 963/*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h
 964 *for the PhyEventCode field */
 965
 966/*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h
 967 *for the CounterType field */
 968
 969/*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h
 970 *for the TimeUnits field */
 971
 972/*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h
 973 *for the ThresholdFlags field */
 974
 975/*SAS Quiesce Event data */
 976
 977typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
 978	U8 ReasonCode;		/*0x00 */
 979	U8 Reserved1;		/*0x01 */
 980	U16 Reserved2;		/*0x02 */
 981	U32 Reserved3;		/*0x04 */
 982} MPI2_EVENT_DATA_SAS_QUIESCE,
 983	*PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
 984	Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t;
 985
 986/*SAS Quiesce Event data ReasonCode values */
 987#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED                   (0x01)
 988#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED                 (0x02)
 989
 990/*Host Based Discovery Phy Event data */
 991
 992typedef struct _MPI2_EVENT_HBD_PHY_SAS {
 993	U8 Flags;		/*0x00 */
 994	U8 NegotiatedLinkRate;	/*0x01 */
 995	U8 PhyNum;		/*0x02 */
 996	U8 PhysicalPort;	/*0x03 */
 997	U32 Reserved1;		/*0x04 */
 998	U8 InitialFrame[28];	/*0x08 */
 999} MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS,
1000	Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t;
1001
1002/*values for the Flags field */
1003#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID        (0x02)
1004#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME         (0x01)
1005
1006/*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h
1007 *for the NegotiatedLinkRate field */
1008
1009typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1010	MPI2_EVENT_HBD_PHY_SAS Sas;
1011} MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1012	Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t;
1013
1014typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1015	U8 DescriptorType;	/*0x00 */
1016	U8 Reserved1;		/*0x01 */
1017	U16 Reserved2;		/*0x02 */
1018	U32 Reserved3;		/*0x04 */
1019	MPI2_EVENT_HBD_DESCRIPTOR Descriptor;	/*0x08 */
1020} MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY,
1021	Mpi2EventDataHbdPhy_t,
1022	*pMpi2EventDataMpi2EventDataHbdPhy_t;
1023
1024/*values for the DescriptorType field */
1025#define MPI2_EVENT_HBD_DT_SAS               (0x01)
1026
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1027/****************************************************************************
1028* EventAck message
1029****************************************************************************/
1030
1031/*EventAck Request message */
1032typedef struct _MPI2_EVENT_ACK_REQUEST {
1033	U16 Reserved1;		/*0x00 */
1034	U8 ChainOffset;		/*0x02 */
1035	U8 Function;		/*0x03 */
1036	U16 Reserved2;		/*0x04 */
1037	U8 Reserved3;		/*0x06 */
1038	U8 MsgFlags;		/*0x07 */
1039	U8 VP_ID;		/*0x08 */
1040	U8 VF_ID;		/*0x09 */
1041	U16 Reserved4;		/*0x0A */
1042	U16 Event;		/*0x0C */
1043	U16 Reserved5;		/*0x0E */
1044	U32 EventContext;	/*0x10 */
1045} MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST,
1046	Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t;
1047
1048/*EventAck Reply message */
1049typedef struct _MPI2_EVENT_ACK_REPLY {
1050	U16 Reserved1;		/*0x00 */
1051	U8 MsgLength;		/*0x02 */
1052	U8 Function;		/*0x03 */
1053	U16 Reserved2;		/*0x04 */
1054	U8 Reserved3;		/*0x06 */
1055	U8 MsgFlags;		/*0x07 */
1056	U8 VP_ID;		/*0x08 */
1057	U8 VF_ID;		/*0x09 */
1058	U16 Reserved4;		/*0x0A */
1059	U16 Reserved5;		/*0x0C */
1060	U16 IOCStatus;		/*0x0E */
1061	U32 IOCLogInfo;		/*0x10 */
1062} MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY,
1063	Mpi2EventAckReply_t, *pMpi2EventAckReply_t;
1064
1065/****************************************************************************
1066* SendHostMessage message
1067****************************************************************************/
1068
1069/*SendHostMessage Request message */
1070typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1071	U16 HostDataLength;	/*0x00 */
1072	U8 ChainOffset;		/*0x02 */
1073	U8 Function;		/*0x03 */
1074	U16 Reserved1;		/*0x04 */
1075	U8 Reserved2;		/*0x06 */
1076	U8 MsgFlags;		/*0x07 */
1077	U8 VP_ID;		/*0x08 */
1078	U8 VF_ID;		/*0x09 */
1079	U16 Reserved3;		/*0x0A */
1080	U8 Reserved4;		/*0x0C */
1081	U8 DestVF_ID;		/*0x0D */
1082	U16 Reserved5;		/*0x0E */
1083	U32 Reserved6;		/*0x10 */
1084	U32 Reserved7;		/*0x14 */
1085	U32 Reserved8;		/*0x18 */
1086	U32 Reserved9;		/*0x1C */
1087	U32 Reserved10;		/*0x20 */
1088	U32 HostData[1];	/*0x24 */
1089} MPI2_SEND_HOST_MESSAGE_REQUEST,
1090	*PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1091	Mpi2SendHostMessageRequest_t,
1092	*pMpi2SendHostMessageRequest_t;
1093
1094/*SendHostMessage Reply message */
1095typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1096	U16 HostDataLength;	/*0x00 */
1097	U8 MsgLength;		/*0x02 */
1098	U8 Function;		/*0x03 */
1099	U16 Reserved1;		/*0x04 */
1100	U8 Reserved2;		/*0x06 */
1101	U8 MsgFlags;		/*0x07 */
1102	U8 VP_ID;		/*0x08 */
1103	U8 VF_ID;		/*0x09 */
1104	U16 Reserved3;		/*0x0A */
1105	U16 Reserved4;		/*0x0C */
1106	U16 IOCStatus;		/*0x0E */
1107	U32 IOCLogInfo;		/*0x10 */
1108} MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1109	Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t;
1110
1111/****************************************************************************
1112* FWDownload message
1113****************************************************************************/
1114
1115/*MPI v2.0 FWDownload Request message */
1116typedef struct _MPI2_FW_DOWNLOAD_REQUEST {
1117	U8 ImageType;		/*0x00 */
1118	U8 Reserved1;		/*0x01 */
1119	U8 ChainOffset;		/*0x02 */
1120	U8 Function;		/*0x03 */
1121	U16 Reserved2;		/*0x04 */
1122	U8 Reserved3;		/*0x06 */
1123	U8 MsgFlags;		/*0x07 */
1124	U8 VP_ID;		/*0x08 */
1125	U8 VF_ID;		/*0x09 */
1126	U16 Reserved4;		/*0x0A */
1127	U32 TotalImageSize;	/*0x0C */
1128	U32 Reserved5;		/*0x10 */
1129	MPI2_MPI_SGE_UNION SGL;	/*0x14 */
1130} MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST,
1131	Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest;
1132
1133#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT   (0x01)
1134
1135#define MPI2_FW_DOWNLOAD_ITYPE_FW                   (0x01)
1136#define MPI2_FW_DOWNLOAD_ITYPE_BIOS                 (0x02)
1137#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING        (0x06)
1138#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1             (0x07)
1139#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2             (0x08)
1140#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID             (0x09)
1141#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE             (0x0A)
1142#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK    (0x0B)
 
 
 
 
 
 
 
 
 
 
 
 
 
1143#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1144
1145/*MPI v2.0 FWDownload TransactionContext Element */
1146typedef struct _MPI2_FW_DOWNLOAD_TCSGE {
1147	U8 Reserved1;		/*0x00 */
1148	U8 ContextSize;		/*0x01 */
1149	U8 DetailsLength;	/*0x02 */
1150	U8 Flags;		/*0x03 */
1151	U32 Reserved2;		/*0x04 */
1152	U32 ImageOffset;	/*0x08 */
1153	U32 ImageSize;		/*0x0C */
1154} MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE,
1155	Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t;
1156
1157/*MPI v2.5 FWDownload Request message */
1158typedef struct _MPI25_FW_DOWNLOAD_REQUEST {
1159	U8 ImageType;		/*0x00 */
1160	U8 Reserved1;		/*0x01 */
1161	U8 ChainOffset;		/*0x02 */
1162	U8 Function;		/*0x03 */
1163	U16 Reserved2;		/*0x04 */
1164	U8 Reserved3;		/*0x06 */
1165	U8 MsgFlags;		/*0x07 */
1166	U8 VP_ID;		/*0x08 */
1167	U8 VF_ID;		/*0x09 */
1168	U16 Reserved4;		/*0x0A */
1169	U32 TotalImageSize;	/*0x0C */
1170	U32 Reserved5;		/*0x10 */
1171	U32 Reserved6;		/*0x14 */
1172	U32 ImageOffset;	/*0x18 */
1173	U32 ImageSize;		/*0x1C */
1174	MPI25_SGE_IO_UNION SGL;	/*0x20 */
1175} MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST,
1176	Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest;
1177
1178/*FWDownload Reply message */
1179typedef struct _MPI2_FW_DOWNLOAD_REPLY {
1180	U8 ImageType;		/*0x00 */
1181	U8 Reserved1;		/*0x01 */
1182	U8 MsgLength;		/*0x02 */
1183	U8 Function;		/*0x03 */
1184	U16 Reserved2;		/*0x04 */
1185	U8 Reserved3;		/*0x06 */
1186	U8 MsgFlags;		/*0x07 */
1187	U8 VP_ID;		/*0x08 */
1188	U8 VF_ID;		/*0x09 */
1189	U16 Reserved4;		/*0x0A */
1190	U16 Reserved5;		/*0x0C */
1191	U16 IOCStatus;		/*0x0E */
1192	U32 IOCLogInfo;		/*0x10 */
1193} MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY,
1194	Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t;
1195
1196/****************************************************************************
1197* FWUpload message
1198****************************************************************************/
1199
1200/*MPI v2.0 FWUpload Request message */
1201typedef struct _MPI2_FW_UPLOAD_REQUEST {
1202	U8 ImageType;		/*0x00 */
1203	U8 Reserved1;		/*0x01 */
1204	U8 ChainOffset;		/*0x02 */
1205	U8 Function;		/*0x03 */
1206	U16 Reserved2;		/*0x04 */
1207	U8 Reserved3;		/*0x06 */
1208	U8 MsgFlags;		/*0x07 */
1209	U8 VP_ID;		/*0x08 */
1210	U8 VF_ID;		/*0x09 */
1211	U16 Reserved4;		/*0x0A */
1212	U32 Reserved5;		/*0x0C */
1213	U32 Reserved6;		/*0x10 */
1214	MPI2_MPI_SGE_UNION SGL;	/*0x14 */
1215} MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST,
1216	Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t;
1217
1218#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT         (0x00)
1219#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH           (0x01)
1220#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH         (0x02)
1221#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP          (0x05)
1222#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING      (0x06)
1223#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1           (0x07)
1224#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2           (0x08)
1225#define MPI2_FW_UPLOAD_ITYPE_MEGARAID           (0x09)
1226#define MPI2_FW_UPLOAD_ITYPE_COMPLETE           (0x0A)
1227#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK  (0x0B)
 
 
 
 
 
 
 
 
 
1228
1229/*MPI v2.0 FWUpload TransactionContext Element */
1230typedef struct _MPI2_FW_UPLOAD_TCSGE {
1231	U8 Reserved1;		/*0x00 */
1232	U8 ContextSize;		/*0x01 */
1233	U8 DetailsLength;	/*0x02 */
1234	U8 Flags;		/*0x03 */
1235	U32 Reserved2;		/*0x04 */
1236	U32 ImageOffset;	/*0x08 */
1237	U32 ImageSize;		/*0x0C */
1238} MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE,
1239	Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t;
1240
1241/*MPI v2.5 FWUpload Request message */
1242typedef struct _MPI25_FW_UPLOAD_REQUEST {
1243	U8 ImageType;		/*0x00 */
1244	U8 Reserved1;		/*0x01 */
1245	U8 ChainOffset;		/*0x02 */
1246	U8 Function;		/*0x03 */
1247	U16 Reserved2;		/*0x04 */
1248	U8 Reserved3;		/*0x06 */
1249	U8 MsgFlags;		/*0x07 */
1250	U8 VP_ID;		/*0x08 */
1251	U8 VF_ID;		/*0x09 */
1252	U16 Reserved4;		/*0x0A */
1253	U32 Reserved5;		/*0x0C */
1254	U32 Reserved6;		/*0x10 */
1255	U32 Reserved7;		/*0x14 */
1256	U32 ImageOffset;	/*0x18 */
1257	U32 ImageSize;		/*0x1C */
1258	MPI25_SGE_IO_UNION SGL;	/*0x20 */
1259} MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST,
1260	Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t;
1261
1262/*FWUpload Reply message */
1263typedef struct _MPI2_FW_UPLOAD_REPLY {
1264	U8 ImageType;		/*0x00 */
1265	U8 Reserved1;		/*0x01 */
1266	U8 MsgLength;		/*0x02 */
1267	U8 Function;		/*0x03 */
1268	U16 Reserved2;		/*0x04 */
1269	U8 Reserved3;		/*0x06 */
1270	U8 MsgFlags;		/*0x07 */
1271	U8 VP_ID;		/*0x08 */
1272	U8 VF_ID;		/*0x09 */
1273	U16 Reserved4;		/*0x0A */
1274	U16 Reserved5;		/*0x0C */
1275	U16 IOCStatus;		/*0x0E */
1276	U32 IOCLogInfo;		/*0x10 */
1277	U32 ActualImageSize;	/*0x14 */
1278} MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY,
1279	Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t;
1280
1281/*FW Image Header */
1282typedef struct _MPI2_FW_IMAGE_HEADER {
1283	U32 Signature;		/*0x00 */
1284	U32 Signature0;		/*0x04 */
1285	U32 Signature1;		/*0x08 */
1286	U32 Signature2;		/*0x0C */
1287	MPI2_VERSION_UNION MPIVersion;	/*0x10 */
1288	MPI2_VERSION_UNION FWVersion;	/*0x14 */
1289	MPI2_VERSION_UNION NVDATAVersion;	/*0x18 */
1290	MPI2_VERSION_UNION PackageVersion;	/*0x1C */
1291	U16 VendorID;		/*0x20 */
1292	U16 ProductID;		/*0x22 */
1293	U16 ProtocolFlags;	/*0x24 */
1294	U16 Reserved26;		/*0x26 */
1295	U32 IOCCapabilities;	/*0x28 */
1296	U32 ImageSize;		/*0x2C */
1297	U32 NextImageHeaderOffset;	/*0x30 */
1298	U32 Checksum;		/*0x34 */
1299	U32 Reserved38;		/*0x38 */
1300	U32 Reserved3C;		/*0x3C */
1301	U32 Reserved40;		/*0x40 */
1302	U32 Reserved44;		/*0x44 */
1303	U32 Reserved48;		/*0x48 */
1304	U32 Reserved4C;		/*0x4C */
1305	U32 Reserved50;		/*0x50 */
1306	U32 Reserved54;		/*0x54 */
1307	U32 Reserved58;		/*0x58 */
1308	U32 Reserved5C;		/*0x5C */
1309	U32 Reserved60;		/*0x60 */
1310	U32 FirmwareVersionNameWhat;	/*0x64 */
1311	U8 FirmwareVersionName[32];	/*0x68 */
1312	U32 VendorNameWhat;	/*0x88 */
1313	U8 VendorName[32];	/*0x8C */
1314	U32 PackageNameWhat;	/*0x88 */
1315	U8 PackageName[32];	/*0x8C */
1316	U32 ReservedD0;		/*0xD0 */
1317	U32 ReservedD4;		/*0xD4 */
1318	U32 ReservedD8;		/*0xD8 */
1319	U32 ReservedDC;		/*0xDC */
1320	U32 ReservedE0;		/*0xE0 */
1321	U32 ReservedE4;		/*0xE4 */
1322	U32 ReservedE8;		/*0xE8 */
1323	U32 ReservedEC;		/*0xEC */
1324	U32 ReservedF0;		/*0xF0 */
1325	U32 ReservedF4;		/*0xF4 */
1326	U32 ReservedF8;		/*0xF8 */
1327	U32 ReservedFC;		/*0xFC */
1328} MPI2_FW_IMAGE_HEADER, *PTR_MPI2_FW_IMAGE_HEADER,
1329	Mpi2FWImageHeader_t, *pMpi2FWImageHeader_t;
1330
1331/*Signature field */
1332#define MPI2_FW_HEADER_SIGNATURE_OFFSET         (0x00)
1333#define MPI2_FW_HEADER_SIGNATURE_MASK           (0xFF000000)
1334#define MPI2_FW_HEADER_SIGNATURE                (0xEA000000)
1335
1336/*Signature0 field */
1337#define MPI2_FW_HEADER_SIGNATURE0_OFFSET        (0x04)
1338#define MPI2_FW_HEADER_SIGNATURE0               (0x5AFAA55A)
1339
1340/*Signature1 field */
1341#define MPI2_FW_HEADER_SIGNATURE1_OFFSET        (0x08)
1342#define MPI2_FW_HEADER_SIGNATURE1               (0xA55AFAA5)
1343
1344/*Signature2 field */
1345#define MPI2_FW_HEADER_SIGNATURE2_OFFSET        (0x0C)
1346#define MPI2_FW_HEADER_SIGNATURE2               (0x5AA55AFA)
1347
1348/*defines for using the ProductID field */
1349#define MPI2_FW_HEADER_PID_TYPE_MASK            (0xF000)
1350#define MPI2_FW_HEADER_PID_TYPE_SAS             (0x2000)
1351
1352#define MPI2_FW_HEADER_PID_PROD_MASK                    (0x0F00)
1353#define MPI2_FW_HEADER_PID_PROD_A                       (0x0000)
1354#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI   (0x0200)
1355#define MPI2_FW_HEADER_PID_PROD_IR_SCSI                 (0x0700)
1356
1357#define MPI2_FW_HEADER_PID_FAMILY_MASK          (0x00FF)
1358/*SAS ProductID Family bits */
1359#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS      (0x0013)
1360#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS      (0x0014)
1361#define MPI25_FW_HEADER_PID_FAMILY_3108_SAS     (0x0021)
1362
1363/*use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1364
1365/*use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1366
1367#define MPI2_FW_HEADER_IMAGESIZE_OFFSET         (0x2C)
1368#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET         (0x30)
1369#define MPI2_FW_HEADER_VERNMHWAT_OFFSET         (0x64)
1370
1371#define MPI2_FW_HEADER_WHAT_SIGNATURE           (0x29232840)
1372
1373#define MPI2_FW_HEADER_SIZE                     (0x100)
1374
1375/*Extended Image Header */
1376typedef struct _MPI2_EXT_IMAGE_HEADER {
1377	U8 ImageType;		/*0x00 */
1378	U8 Reserved1;		/*0x01 */
1379	U16 Reserved2;		/*0x02 */
1380	U32 Checksum;		/*0x04 */
1381	U32 ImageSize;		/*0x08 */
1382	U32 NextImageHeaderOffset;	/*0x0C */
1383	U32 PackageVersion;	/*0x10 */
1384	U32 Reserved3;		/*0x14 */
1385	U32 Reserved4;		/*0x18 */
1386	U32 Reserved5;		/*0x1C */
1387	U8 IdentifyString[32];	/*0x20 */
1388} MPI2_EXT_IMAGE_HEADER, *PTR_MPI2_EXT_IMAGE_HEADER,
1389	Mpi2ExtImageHeader_t, *pMpi2ExtImageHeader_t;
1390
1391/*useful offsets */
1392#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET         (0x00)
1393#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET         (0x08)
1394#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET         (0x0C)
1395
1396#define MPI2_EXT_IMAGE_HEADER_SIZE              (0x40)
1397
1398/*defines for the ImageType field */
1399#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED             (0x00)
1400#define MPI2_EXT_IMAGE_TYPE_FW                      (0x01)
1401#define MPI2_EXT_IMAGE_TYPE_NVDATA                  (0x03)
1402#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER              (0x04)
1403#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION          (0x05)
1404#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT            (0x06)
1405#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES       (0x07)
1406#define MPI2_EXT_IMAGE_TYPE_MEGARAID                (0x08)
1407#define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC    (0x80)
1408#define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC    (0xFF)
1409
1410#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC)
1411
1412/*FLASH Layout Extended Image Data */
1413
1414/*
1415 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1416 *one and check RegionsPerLayout at runtime.
1417 */
1418#ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1419#define MPI2_FLASH_NUMBER_OF_REGIONS        (1)
1420#endif
1421
1422/*
1423 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1424 *one and check NumberOfLayouts at runtime.
1425 */
1426#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1427#define MPI2_FLASH_NUMBER_OF_LAYOUTS        (1)
1428#endif
1429
1430typedef struct _MPI2_FLASH_REGION {
1431	U8 RegionType;		/*0x00 */
1432	U8 Reserved1;		/*0x01 */
1433	U16 Reserved2;		/*0x02 */
1434	U32 RegionOffset;	/*0x04 */
1435	U32 RegionSize;		/*0x08 */
1436	U32 Reserved3;		/*0x0C */
1437} MPI2_FLASH_REGION, *PTR_MPI2_FLASH_REGION,
1438	Mpi2FlashRegion_t, *pMpi2FlashRegion_t;
1439
1440typedef struct _MPI2_FLASH_LAYOUT {
1441	U32 FlashSize;		/*0x00 */
1442	U32 Reserved1;		/*0x04 */
1443	U32 Reserved2;		/*0x08 */
1444	U32 Reserved3;		/*0x0C */
1445	MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];	/*0x10 */
1446} MPI2_FLASH_LAYOUT, *PTR_MPI2_FLASH_LAYOUT,
1447	Mpi2FlashLayout_t, *pMpi2FlashLayout_t;
1448
1449typedef struct _MPI2_FLASH_LAYOUT_DATA {
1450	U8 ImageRevision;	/*0x00 */
1451	U8 Reserved1;		/*0x01 */
1452	U8 SizeOfRegion;	/*0x02 */
1453	U8 Reserved2;		/*0x03 */
1454	U16 NumberOfLayouts;	/*0x04 */
1455	U16 RegionsPerLayout;	/*0x06 */
1456	U16 MinimumSectorAlignment;	/*0x08 */
1457	U16 Reserved3;		/*0x0A */
1458	U32 Reserved4;		/*0x0C */
1459	MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];	/*0x10 */
1460} MPI2_FLASH_LAYOUT_DATA, *PTR_MPI2_FLASH_LAYOUT_DATA,
1461	Mpi2FlashLayoutData_t, *pMpi2FlashLayoutData_t;
1462
1463/*defines for the RegionType field */
1464#define MPI2_FLASH_REGION_UNUSED                (0x00)
1465#define MPI2_FLASH_REGION_FIRMWARE              (0x01)
1466#define MPI2_FLASH_REGION_BIOS                  (0x02)
1467#define MPI2_FLASH_REGION_NVDATA                (0x03)
1468#define MPI2_FLASH_REGION_FIRMWARE_BACKUP       (0x05)
1469#define MPI2_FLASH_REGION_MFG_INFORMATION       (0x06)
1470#define MPI2_FLASH_REGION_CONFIG_1              (0x07)
1471#define MPI2_FLASH_REGION_CONFIG_2              (0x08)
1472#define MPI2_FLASH_REGION_MEGARAID              (0x09)
1473#define MPI2_FLASH_REGION_INIT                  (0x0A)
1474
1475/*ImageRevision */
1476#define MPI2_FLASH_LAYOUT_IMAGE_REVISION        (0x00)
1477
1478/*Supported Devices Extended Image Data */
1479
1480/*
1481 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1482 *one and check NumberOfDevices at runtime.
1483 */
1484#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1485#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES    (1)
1486#endif
1487
1488typedef struct _MPI2_SUPPORTED_DEVICE {
1489	U16 DeviceID;		/*0x00 */
1490	U16 VendorID;		/*0x02 */
1491	U16 DeviceIDMask;	/*0x04 */
1492	U16 Reserved1;		/*0x06 */
1493	U8 LowPCIRev;		/*0x08 */
1494	U8 HighPCIRev;		/*0x09 */
1495	U16 Reserved2;		/*0x0A */
1496	U32 Reserved3;		/*0x0C */
1497} MPI2_SUPPORTED_DEVICE, *PTR_MPI2_SUPPORTED_DEVICE,
1498	Mpi2SupportedDevice_t, *pMpi2SupportedDevice_t;
1499
1500typedef struct _MPI2_SUPPORTED_DEVICES_DATA {
1501	U8 ImageRevision;	/*0x00 */
1502	U8 Reserved1;		/*0x01 */
1503	U8 NumberOfDevices;	/*0x02 */
1504	U8 Reserved2;		/*0x03 */
1505	U32 Reserved3;		/*0x04 */
1506	MPI2_SUPPORTED_DEVICE
1507	SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES];/*0x08 */
1508} MPI2_SUPPORTED_DEVICES_DATA, *PTR_MPI2_SUPPORTED_DEVICES_DATA,
1509	Mpi2SupportedDevicesData_t, *pMpi2SupportedDevicesData_t;
1510
1511/*ImageRevision */
1512#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION   (0x00)
1513
1514/*Init Extended Image Data */
1515
1516typedef struct _MPI2_INIT_IMAGE_FOOTER {
1517	U32 BootFlags;		/*0x00 */
1518	U32 ImageSize;		/*0x04 */
1519	U32 Signature0;		/*0x08 */
1520	U32 Signature1;		/*0x0C */
1521	U32 Signature2;		/*0x10 */
1522	U32 ResetVector;	/*0x14 */
1523} MPI2_INIT_IMAGE_FOOTER, *PTR_MPI2_INIT_IMAGE_FOOTER,
1524	Mpi2InitImageFooter_t, *pMpi2InitImageFooter_t;
1525
1526/*defines for the BootFlags field */
1527#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET        (0x00)
1528
1529/*defines for the ImageSize field */
1530#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET        (0x04)
1531
1532/*defines for the Signature0 field */
1533#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET       (0x08)
1534#define MPI2_INIT_IMAGE_SIGNATURE0              (0x5AA55AEA)
1535
1536/*defines for the Signature1 field */
1537#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET       (0x0C)
1538#define MPI2_INIT_IMAGE_SIGNATURE1              (0xA55AEAA5)
1539
1540/*defines for the Signature2 field */
1541#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET       (0x10)
1542#define MPI2_INIT_IMAGE_SIGNATURE2              (0x5AEAA55A)
1543
1544/*Signature fields as individual bytes */
1545#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0        (0xEA)
1546#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1        (0x5A)
1547#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2        (0xA5)
1548#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3        (0x5A)
1549
1550#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4        (0xA5)
1551#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5        (0xEA)
1552#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6        (0x5A)
1553#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7        (0xA5)
1554
1555#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8        (0x5A)
1556#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9        (0xA5)
1557#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A        (0xEA)
1558#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B        (0x5A)
1559
1560/*defines for the ResetVector field */
1561#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET      (0x14)
1562
1563/****************************************************************************
1564* PowerManagementControl message
1565****************************************************************************/
1566
1567/*PowerManagementControl Request message */
1568typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1569	U8 Feature;		/*0x00 */
1570	U8 Reserved1;		/*0x01 */
1571	U8 ChainOffset;		/*0x02 */
1572	U8 Function;		/*0x03 */
1573	U16 Reserved2;		/*0x04 */
1574	U8 Reserved3;		/*0x06 */
1575	U8 MsgFlags;		/*0x07 */
1576	U8 VP_ID;		/*0x08 */
1577	U8 VF_ID;		/*0x09 */
1578	U16 Reserved4;		/*0x0A */
1579	U8 Parameter1;		/*0x0C */
1580	U8 Parameter2;		/*0x0D */
1581	U8 Parameter3;		/*0x0E */
1582	U8 Parameter4;		/*0x0F */
1583	U32 Reserved5;		/*0x10 */
1584	U32 Reserved6;		/*0x14 */
1585} MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1586	Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t;
1587
1588/*defines for the Feature field */
1589#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND       (0x01)
1590#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION   (0x02)
1591#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK               (0x03)	/*obsolete */
1592#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED               (0x04)
1593#define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE    (0x05)
1594#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC    (0x80)
1595#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC    (0xFF)
1596
1597/*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1598/*Parameter1 contains a PHY number */
1599/*Parameter2 indicates power condition action using these defines */
1600#define MPI2_PM_CONTROL_PARAM2_PARTIAL                  (0x01)
1601#define MPI2_PM_CONTROL_PARAM2_SLUMBER                  (0x02)
1602#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT            (0x03)
1603/*Parameter3 and Parameter4 are reserved */
1604
1605/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1606 * Feature */
1607/*Parameter1 contains SAS port width modulation group number */
1608/*Parameter2 indicates IOC action using these defines */
1609#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP        (0x01)
1610#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION        (0x02)
1611#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP     (0x03)
1612/*Parameter3 indicates desired modulation level using these defines */
1613#define MPI2_PM_CONTROL_PARAM3_25_PERCENT               (0x00)
1614#define MPI2_PM_CONTROL_PARAM3_50_PERCENT               (0x01)
1615#define MPI2_PM_CONTROL_PARAM3_75_PERCENT               (0x02)
1616#define MPI2_PM_CONTROL_PARAM3_100_PERCENT              (0x03)
1617/*Parameter4 is reserved */
1618
1619/*this next set (_PCIE_LINK) is obsolete */
1620/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1621/*Parameter1 indicates desired PCIe link speed using these defines */
1622#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS            (0x00)	/*obsolete */
1623#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS            (0x01)	/*obsolete */
1624#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS            (0x02)	/*obsolete */
1625/*Parameter2 indicates desired PCIe link width using these defines */
1626#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1                 (0x01)	/*obsolete */
1627#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2                 (0x02)	/*obsolete */
1628#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4                 (0x04)	/*obsolete */
1629#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8                 (0x08)	/*obsolete */
1630/*Parameter3 and Parameter4 are reserved */
1631
1632/*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1633/*Parameter1 indicates desired IOC hardware clock speed using these defines */
1634#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED           (0x01)
1635#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED           (0x02)
1636#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED        (0x04)
1637#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED         (0x08)
1638/*Parameter2, Parameter3, and Parameter4 are reserved */
1639
1640/*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/
1641/*Parameter1 indicates host action regarding global power management mode */
1642#define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL             (0x01)
1643#define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE       (0x02)
1644#define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL          (0x03)
1645/*Parameter2 indicates the requested global power management mode */
1646#define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF            (0x01)
1647#define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF         (0x08)
1648#define MPI2_PM_CONTROL_PARAM2_STANDBY                  (0x40)
1649/*Parameter3 and Parameter4 are reserved */
1650
1651/*PowerManagementControl Reply message */
1652typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1653	U8 Feature;		/*0x00 */
1654	U8 Reserved1;		/*0x01 */
1655	U8 MsgLength;		/*0x02 */
1656	U8 Function;		/*0x03 */
1657	U16 Reserved2;		/*0x04 */
1658	U8 Reserved3;		/*0x06 */
1659	U8 MsgFlags;		/*0x07 */
1660	U8 VP_ID;		/*0x08 */
1661	U8 VF_ID;		/*0x09 */
1662	U16 Reserved4;		/*0x0A */
1663	U16 Reserved5;		/*0x0C */
1664	U16 IOCStatus;		/*0x0E */
1665	U32 IOCLogInfo;		/*0x10 */
1666} MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1667	Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1668
1669#endif