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1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/reset.h>
13
14#include "dc.h"
15#include "drm.h"
16#include "gem.h"
17
18struct tegra_dc_soc_info {
19 bool supports_interlacing;
20};
21
22struct tegra_plane {
23 struct drm_plane base;
24 unsigned int index;
25};
26
27static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
28{
29 return container_of(plane, struct tegra_plane, base);
30}
31
32static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
33 struct drm_framebuffer *fb, int crtc_x,
34 int crtc_y, unsigned int crtc_w,
35 unsigned int crtc_h, uint32_t src_x,
36 uint32_t src_y, uint32_t src_w, uint32_t src_h)
37{
38 struct tegra_plane *p = to_tegra_plane(plane);
39 struct tegra_dc *dc = to_tegra_dc(crtc);
40 struct tegra_dc_window window;
41 unsigned int i;
42
43 memset(&window, 0, sizeof(window));
44 window.src.x = src_x >> 16;
45 window.src.y = src_y >> 16;
46 window.src.w = src_w >> 16;
47 window.src.h = src_h >> 16;
48 window.dst.x = crtc_x;
49 window.dst.y = crtc_y;
50 window.dst.w = crtc_w;
51 window.dst.h = crtc_h;
52 window.format = tegra_dc_format(fb->pixel_format);
53 window.bits_per_pixel = fb->bits_per_pixel;
54 window.bottom_up = tegra_fb_is_bottom_up(fb);
55 window.tiled = tegra_fb_is_tiled(fb);
56
57 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
58 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
59
60 window.base[i] = bo->paddr + fb->offsets[i];
61
62 /*
63 * Tegra doesn't support different strides for U and V planes
64 * so we display a warning if the user tries to display a
65 * framebuffer with such a configuration.
66 */
67 if (i >= 2) {
68 if (fb->pitches[i] != window.stride[1])
69 DRM_ERROR("unsupported UV-plane configuration\n");
70 } else {
71 window.stride[i] = fb->pitches[i];
72 }
73 }
74
75 return tegra_dc_setup_window(dc, p->index, &window);
76}
77
78static int tegra_plane_disable(struct drm_plane *plane)
79{
80 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
81 struct tegra_plane *p = to_tegra_plane(plane);
82 unsigned long value;
83
84 if (!plane->crtc)
85 return 0;
86
87 value = WINDOW_A_SELECT << p->index;
88 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
89
90 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
91 value &= ~WIN_ENABLE;
92 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
93
94 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
95 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
96
97 return 0;
98}
99
100static void tegra_plane_destroy(struct drm_plane *plane)
101{
102 struct tegra_plane *p = to_tegra_plane(plane);
103
104 tegra_plane_disable(plane);
105 drm_plane_cleanup(plane);
106 kfree(p);
107}
108
109static const struct drm_plane_funcs tegra_plane_funcs = {
110 .update_plane = tegra_plane_update,
111 .disable_plane = tegra_plane_disable,
112 .destroy = tegra_plane_destroy,
113};
114
115static const uint32_t plane_formats[] = {
116 DRM_FORMAT_XBGR8888,
117 DRM_FORMAT_XRGB8888,
118 DRM_FORMAT_RGB565,
119 DRM_FORMAT_UYVY,
120 DRM_FORMAT_YUV420,
121 DRM_FORMAT_YUV422,
122};
123
124static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
125{
126 unsigned int i;
127 int err = 0;
128
129 for (i = 0; i < 2; i++) {
130 struct tegra_plane *plane;
131
132 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
133 if (!plane)
134 return -ENOMEM;
135
136 plane->index = 1 + i;
137
138 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
139 &tegra_plane_funcs, plane_formats,
140 ARRAY_SIZE(plane_formats), false);
141 if (err < 0) {
142 kfree(plane);
143 return err;
144 }
145 }
146
147 return 0;
148}
149
150static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
151 struct drm_framebuffer *fb)
152{
153 unsigned int format = tegra_dc_format(fb->pixel_format);
154 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
155 unsigned int h_offset = 0, v_offset = 0;
156 unsigned long value;
157
158 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
159
160 value = fb->offsets[0] + y * fb->pitches[0] +
161 x * fb->bits_per_pixel / 8;
162
163 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
164 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
165 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
166
167 if (tegra_fb_is_tiled(fb)) {
168 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
169 DC_WIN_BUFFER_ADDR_MODE_TILE;
170 } else {
171 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
172 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
173 }
174
175 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
176
177 /* make sure bottom-up buffers are properly displayed */
178 if (tegra_fb_is_bottom_up(fb)) {
179 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
180 value |= INVERT_V;
181 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
182
183 v_offset += fb->height - 1;
184 } else {
185 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
186 value &= ~INVERT_V;
187 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
188 }
189
190 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
191 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
192
193 value = GENERAL_UPDATE | WIN_A_UPDATE;
194 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
195
196 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
197 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
198
199 return 0;
200}
201
202void tegra_dc_enable_vblank(struct tegra_dc *dc)
203{
204 unsigned long value, flags;
205
206 spin_lock_irqsave(&dc->lock, flags);
207
208 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
209 value |= VBLANK_INT;
210 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
211
212 spin_unlock_irqrestore(&dc->lock, flags);
213}
214
215void tegra_dc_disable_vblank(struct tegra_dc *dc)
216{
217 unsigned long value, flags;
218
219 spin_lock_irqsave(&dc->lock, flags);
220
221 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
222 value &= ~VBLANK_INT;
223 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
224
225 spin_unlock_irqrestore(&dc->lock, flags);
226}
227
228static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
229{
230 struct drm_device *drm = dc->base.dev;
231 struct drm_crtc *crtc = &dc->base;
232 unsigned long flags, base;
233 struct tegra_bo *bo;
234
235 if (!dc->event)
236 return;
237
238 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
239
240 /* check if new start address has been latched */
241 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
242 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
243 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
244
245 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
246 spin_lock_irqsave(&drm->event_lock, flags);
247 drm_send_vblank_event(drm, dc->pipe, dc->event);
248 drm_vblank_put(drm, dc->pipe);
249 dc->event = NULL;
250 spin_unlock_irqrestore(&drm->event_lock, flags);
251 }
252}
253
254void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
255{
256 struct tegra_dc *dc = to_tegra_dc(crtc);
257 struct drm_device *drm = crtc->dev;
258 unsigned long flags;
259
260 spin_lock_irqsave(&drm->event_lock, flags);
261
262 if (dc->event && dc->event->base.file_priv == file) {
263 dc->event->base.destroy(&dc->event->base);
264 drm_vblank_put(drm, dc->pipe);
265 dc->event = NULL;
266 }
267
268 spin_unlock_irqrestore(&drm->event_lock, flags);
269}
270
271static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
272 struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
273{
274 struct tegra_dc *dc = to_tegra_dc(crtc);
275 struct drm_device *drm = crtc->dev;
276
277 if (dc->event)
278 return -EBUSY;
279
280 if (event) {
281 event->pipe = dc->pipe;
282 dc->event = event;
283 drm_vblank_get(drm, dc->pipe);
284 }
285
286 tegra_dc_set_base(dc, 0, 0, fb);
287 crtc->primary->fb = fb;
288
289 return 0;
290}
291
292static void drm_crtc_clear(struct drm_crtc *crtc)
293{
294 memset(crtc, 0, sizeof(*crtc));
295}
296
297static void tegra_dc_destroy(struct drm_crtc *crtc)
298{
299 drm_crtc_cleanup(crtc);
300 drm_crtc_clear(crtc);
301}
302
303static const struct drm_crtc_funcs tegra_crtc_funcs = {
304 .page_flip = tegra_dc_page_flip,
305 .set_config = drm_crtc_helper_set_config,
306 .destroy = tegra_dc_destroy,
307};
308
309static void tegra_crtc_disable(struct drm_crtc *crtc)
310{
311 struct tegra_dc *dc = to_tegra_dc(crtc);
312 struct drm_device *drm = crtc->dev;
313 struct drm_plane *plane;
314
315 drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) {
316 if (plane->crtc == crtc) {
317 tegra_plane_disable(plane);
318 plane->crtc = NULL;
319
320 if (plane->fb) {
321 drm_framebuffer_unreference(plane->fb);
322 plane->fb = NULL;
323 }
324 }
325 }
326
327 drm_vblank_off(drm, dc->pipe);
328}
329
330static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
331 const struct drm_display_mode *mode,
332 struct drm_display_mode *adjusted)
333{
334 return true;
335}
336
337static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
338 unsigned int bpp)
339{
340 fixed20_12 outf = dfixed_init(out);
341 fixed20_12 inf = dfixed_init(in);
342 u32 dda_inc;
343 int max;
344
345 if (v)
346 max = 15;
347 else {
348 switch (bpp) {
349 case 2:
350 max = 8;
351 break;
352
353 default:
354 WARN_ON_ONCE(1);
355 /* fallthrough */
356 case 4:
357 max = 4;
358 break;
359 }
360 }
361
362 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
363 inf.full -= dfixed_const(1);
364
365 dda_inc = dfixed_div(inf, outf);
366 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
367
368 return dda_inc;
369}
370
371static inline u32 compute_initial_dda(unsigned int in)
372{
373 fixed20_12 inf = dfixed_init(in);
374 return dfixed_frac(inf);
375}
376
377static int tegra_dc_set_timings(struct tegra_dc *dc,
378 struct drm_display_mode *mode)
379{
380 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
381 unsigned int h_ref_to_sync = 0;
382 unsigned int v_ref_to_sync = 0;
383 unsigned long value;
384
385 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
386
387 value = (v_ref_to_sync << 16) | h_ref_to_sync;
388 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
389
390 value = ((mode->vsync_end - mode->vsync_start) << 16) |
391 ((mode->hsync_end - mode->hsync_start) << 0);
392 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
393
394 value = ((mode->vtotal - mode->vsync_end) << 16) |
395 ((mode->htotal - mode->hsync_end) << 0);
396 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
397
398 value = ((mode->vsync_start - mode->vdisplay) << 16) |
399 ((mode->hsync_start - mode->hdisplay) << 0);
400 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
401
402 value = (mode->vdisplay << 16) | mode->hdisplay;
403 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
404
405 return 0;
406}
407
408static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
409 struct drm_display_mode *mode,
410 unsigned long *div)
411{
412 unsigned long pclk = mode->clock * 1000, rate;
413 struct tegra_dc *dc = to_tegra_dc(crtc);
414 struct tegra_output *output = NULL;
415 struct drm_encoder *encoder;
416 long err;
417
418 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
419 if (encoder->crtc == crtc) {
420 output = encoder_to_output(encoder);
421 break;
422 }
423
424 if (!output)
425 return -ENODEV;
426
427 /*
428 * This assumes that the display controller will divide its parent
429 * clock by 2 to generate the pixel clock.
430 */
431 err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
432 if (err < 0) {
433 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
434 return err;
435 }
436
437 rate = clk_get_rate(dc->clk);
438 *div = (rate * 2 / pclk) - 2;
439
440 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
441
442 return 0;
443}
444
445static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
446{
447 switch (format) {
448 case WIN_COLOR_DEPTH_YCbCr422:
449 case WIN_COLOR_DEPTH_YUV422:
450 if (planar)
451 *planar = false;
452
453 return true;
454
455 case WIN_COLOR_DEPTH_YCbCr420P:
456 case WIN_COLOR_DEPTH_YUV420P:
457 case WIN_COLOR_DEPTH_YCbCr422P:
458 case WIN_COLOR_DEPTH_YUV422P:
459 case WIN_COLOR_DEPTH_YCbCr422R:
460 case WIN_COLOR_DEPTH_YUV422R:
461 case WIN_COLOR_DEPTH_YCbCr422RA:
462 case WIN_COLOR_DEPTH_YUV422RA:
463 if (planar)
464 *planar = true;
465
466 return true;
467 }
468
469 return false;
470}
471
472int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
473 const struct tegra_dc_window *window)
474{
475 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
476 unsigned long value;
477 bool yuv, planar;
478
479 /*
480 * For YUV planar modes, the number of bytes per pixel takes into
481 * account only the luma component and therefore is 1.
482 */
483 yuv = tegra_dc_format_is_yuv(window->format, &planar);
484 if (!yuv)
485 bpp = window->bits_per_pixel / 8;
486 else
487 bpp = planar ? 1 : 2;
488
489 value = WINDOW_A_SELECT << index;
490 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
491
492 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
493 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
494
495 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
496 tegra_dc_writel(dc, value, DC_WIN_POSITION);
497
498 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
499 tegra_dc_writel(dc, value, DC_WIN_SIZE);
500
501 h_offset = window->src.x * bpp;
502 v_offset = window->src.y;
503 h_size = window->src.w * bpp;
504 v_size = window->src.h;
505
506 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
507 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
508
509 /*
510 * For DDA computations the number of bytes per pixel for YUV planar
511 * modes needs to take into account all Y, U and V components.
512 */
513 if (yuv && planar)
514 bpp = 2;
515
516 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
517 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
518
519 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
520 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
521
522 h_dda = compute_initial_dda(window->src.x);
523 v_dda = compute_initial_dda(window->src.y);
524
525 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
526 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
527
528 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
529 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
530
531 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
532
533 if (yuv && planar) {
534 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
535 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
536 value = window->stride[1] << 16 | window->stride[0];
537 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
538 } else {
539 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
540 }
541
542 if (window->bottom_up)
543 v_offset += window->src.h - 1;
544
545 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
546 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
547
548 if (window->tiled) {
549 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
550 DC_WIN_BUFFER_ADDR_MODE_TILE;
551 } else {
552 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
553 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
554 }
555
556 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
557
558 value = WIN_ENABLE;
559
560 if (yuv) {
561 /* setup default colorspace conversion coefficients */
562 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
563 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
564 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
565 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
566 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
567 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
568 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
569 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
570
571 value |= CSC_ENABLE;
572 } else if (window->bits_per_pixel < 24) {
573 value |= COLOR_EXPAND;
574 }
575
576 if (window->bottom_up)
577 value |= INVERT_V;
578
579 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
580
581 /*
582 * Disable blending and assume Window A is the bottom-most window,
583 * Window C is the top-most window and Window B is in the middle.
584 */
585 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
586 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
587
588 switch (index) {
589 case 0:
590 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
591 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
592 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
593 break;
594
595 case 1:
596 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
597 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
598 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
599 break;
600
601 case 2:
602 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
603 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
604 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
605 break;
606 }
607
608 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
609 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
610
611 return 0;
612}
613
614unsigned int tegra_dc_format(uint32_t format)
615{
616 switch (format) {
617 case DRM_FORMAT_XBGR8888:
618 return WIN_COLOR_DEPTH_R8G8B8A8;
619
620 case DRM_FORMAT_XRGB8888:
621 return WIN_COLOR_DEPTH_B8G8R8A8;
622
623 case DRM_FORMAT_RGB565:
624 return WIN_COLOR_DEPTH_B5G6R5;
625
626 case DRM_FORMAT_UYVY:
627 return WIN_COLOR_DEPTH_YCbCr422;
628
629 case DRM_FORMAT_YUV420:
630 return WIN_COLOR_DEPTH_YCbCr420P;
631
632 case DRM_FORMAT_YUV422:
633 return WIN_COLOR_DEPTH_YCbCr422P;
634
635 default:
636 break;
637 }
638
639 WARN(1, "unsupported pixel format %u, using default\n", format);
640 return WIN_COLOR_DEPTH_B8G8R8A8;
641}
642
643static int tegra_crtc_mode_set(struct drm_crtc *crtc,
644 struct drm_display_mode *mode,
645 struct drm_display_mode *adjusted,
646 int x, int y, struct drm_framebuffer *old_fb)
647{
648 struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0);
649 struct tegra_dc *dc = to_tegra_dc(crtc);
650 struct tegra_dc_window window;
651 unsigned long div, value;
652 int err;
653
654 drm_vblank_pre_modeset(crtc->dev, dc->pipe);
655
656 err = tegra_crtc_setup_clk(crtc, mode, &div);
657 if (err) {
658 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
659 return err;
660 }
661
662 /* program display mode */
663 tegra_dc_set_timings(dc, mode);
664
665 /* interlacing isn't supported yet, so disable it */
666 if (dc->soc->supports_interlacing) {
667 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
668 value &= ~INTERLACE_ENABLE;
669 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
670 }
671
672 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
673 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
674
675 /* setup window parameters */
676 memset(&window, 0, sizeof(window));
677 window.src.x = 0;
678 window.src.y = 0;
679 window.src.w = mode->hdisplay;
680 window.src.h = mode->vdisplay;
681 window.dst.x = 0;
682 window.dst.y = 0;
683 window.dst.w = mode->hdisplay;
684 window.dst.h = mode->vdisplay;
685 window.format = tegra_dc_format(crtc->primary->fb->pixel_format);
686 window.bits_per_pixel = crtc->primary->fb->bits_per_pixel;
687 window.stride[0] = crtc->primary->fb->pitches[0];
688 window.base[0] = bo->paddr;
689
690 err = tegra_dc_setup_window(dc, 0, &window);
691 if (err < 0)
692 dev_err(dc->dev, "failed to enable root plane\n");
693
694 return 0;
695}
696
697static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
698 struct drm_framebuffer *old_fb)
699{
700 struct tegra_dc *dc = to_tegra_dc(crtc);
701
702 return tegra_dc_set_base(dc, x, y, crtc->primary->fb);
703}
704
705static void tegra_crtc_prepare(struct drm_crtc *crtc)
706{
707 struct tegra_dc *dc = to_tegra_dc(crtc);
708 unsigned int syncpt;
709 unsigned long value;
710
711 /* hardware initialization */
712 reset_control_deassert(dc->rst);
713 usleep_range(10000, 20000);
714
715 if (dc->pipe)
716 syncpt = SYNCPT_VBLANK1;
717 else
718 syncpt = SYNCPT_VBLANK0;
719
720 /* initialize display controller */
721 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
722 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
723
724 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
725 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
726
727 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
728 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
729 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
730
731 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
732 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
733 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
734
735 /* initialize timer */
736 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
737 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
738 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
739
740 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
741 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
742 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
743
744 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
745 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
746
747 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
748 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
749}
750
751static void tegra_crtc_commit(struct drm_crtc *crtc)
752{
753 struct tegra_dc *dc = to_tegra_dc(crtc);
754 unsigned long value;
755
756 value = GENERAL_UPDATE | WIN_A_UPDATE;
757 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
758
759 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
760 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
761
762 drm_vblank_post_modeset(crtc->dev, dc->pipe);
763}
764
765static void tegra_crtc_load_lut(struct drm_crtc *crtc)
766{
767}
768
769static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
770 .disable = tegra_crtc_disable,
771 .mode_fixup = tegra_crtc_mode_fixup,
772 .mode_set = tegra_crtc_mode_set,
773 .mode_set_base = tegra_crtc_mode_set_base,
774 .prepare = tegra_crtc_prepare,
775 .commit = tegra_crtc_commit,
776 .load_lut = tegra_crtc_load_lut,
777};
778
779static irqreturn_t tegra_dc_irq(int irq, void *data)
780{
781 struct tegra_dc *dc = data;
782 unsigned long status;
783
784 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
785 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
786
787 if (status & FRAME_END_INT) {
788 /*
789 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
790 */
791 }
792
793 if (status & VBLANK_INT) {
794 /*
795 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
796 */
797 drm_handle_vblank(dc->base.dev, dc->pipe);
798 tegra_dc_finish_page_flip(dc);
799 }
800
801 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
802 /*
803 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
804 */
805 }
806
807 return IRQ_HANDLED;
808}
809
810static int tegra_dc_show_regs(struct seq_file *s, void *data)
811{
812 struct drm_info_node *node = s->private;
813 struct tegra_dc *dc = node->info_ent->data;
814
815#define DUMP_REG(name) \
816 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
817 tegra_dc_readl(dc, name))
818
819 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
820 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
821 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
822 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
823 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
824 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
825 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
826 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
827 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
828 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
829 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
830 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
831 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
832 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
833 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
834 DUMP_REG(DC_CMD_SIGNAL_RAISE);
835 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
836 DUMP_REG(DC_CMD_INT_STATUS);
837 DUMP_REG(DC_CMD_INT_MASK);
838 DUMP_REG(DC_CMD_INT_ENABLE);
839 DUMP_REG(DC_CMD_INT_TYPE);
840 DUMP_REG(DC_CMD_INT_POLARITY);
841 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
842 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
843 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
844 DUMP_REG(DC_CMD_STATE_ACCESS);
845 DUMP_REG(DC_CMD_STATE_CONTROL);
846 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
847 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
848 DUMP_REG(DC_COM_CRC_CONTROL);
849 DUMP_REG(DC_COM_CRC_CHECKSUM);
850 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
851 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
852 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
853 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
854 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
855 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
856 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
857 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
858 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
859 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
860 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
861 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
862 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
863 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
864 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
865 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
866 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
867 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
868 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
869 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
870 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
871 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
872 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
873 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
874 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
875 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
876 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
877 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
878 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
879 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
880 DUMP_REG(DC_COM_SPI_CONTROL);
881 DUMP_REG(DC_COM_SPI_START_BYTE);
882 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
883 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
884 DUMP_REG(DC_COM_HSPI_CS_DC);
885 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
886 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
887 DUMP_REG(DC_COM_GPIO_CTRL);
888 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
889 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
890 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
891 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
892 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
893 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
894 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
895 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
896 DUMP_REG(DC_DISP_REF_TO_SYNC);
897 DUMP_REG(DC_DISP_SYNC_WIDTH);
898 DUMP_REG(DC_DISP_BACK_PORCH);
899 DUMP_REG(DC_DISP_ACTIVE);
900 DUMP_REG(DC_DISP_FRONT_PORCH);
901 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
902 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
903 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
904 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
905 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
906 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
907 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
908 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
909 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
910 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
911 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
912 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
913 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
914 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
915 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
916 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
917 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
918 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
919 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
920 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
921 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
922 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
923 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
924 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
925 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
926 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
927 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
928 DUMP_REG(DC_DISP_M0_CONTROL);
929 DUMP_REG(DC_DISP_M1_CONTROL);
930 DUMP_REG(DC_DISP_DI_CONTROL);
931 DUMP_REG(DC_DISP_PP_CONTROL);
932 DUMP_REG(DC_DISP_PP_SELECT_A);
933 DUMP_REG(DC_DISP_PP_SELECT_B);
934 DUMP_REG(DC_DISP_PP_SELECT_C);
935 DUMP_REG(DC_DISP_PP_SELECT_D);
936 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
937 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
938 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
939 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
940 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
941 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
942 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
943 DUMP_REG(DC_DISP_BORDER_COLOR);
944 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
945 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
946 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
947 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
948 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
949 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
950 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
951 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
952 DUMP_REG(DC_DISP_CURSOR_POSITION);
953 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
954 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
955 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
956 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
957 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
958 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
959 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
960 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
961 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
962 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
963 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
964 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
965 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
966 DUMP_REG(DC_DISP_SD_CONTROL);
967 DUMP_REG(DC_DISP_SD_CSC_COEFF);
968 DUMP_REG(DC_DISP_SD_LUT(0));
969 DUMP_REG(DC_DISP_SD_LUT(1));
970 DUMP_REG(DC_DISP_SD_LUT(2));
971 DUMP_REG(DC_DISP_SD_LUT(3));
972 DUMP_REG(DC_DISP_SD_LUT(4));
973 DUMP_REG(DC_DISP_SD_LUT(5));
974 DUMP_REG(DC_DISP_SD_LUT(6));
975 DUMP_REG(DC_DISP_SD_LUT(7));
976 DUMP_REG(DC_DISP_SD_LUT(8));
977 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
978 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
979 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
980 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
981 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
982 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
983 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
984 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
985 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
986 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
987 DUMP_REG(DC_DISP_SD_BL_TF(0));
988 DUMP_REG(DC_DISP_SD_BL_TF(1));
989 DUMP_REG(DC_DISP_SD_BL_TF(2));
990 DUMP_REG(DC_DISP_SD_BL_TF(3));
991 DUMP_REG(DC_DISP_SD_BL_CONTROL);
992 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
993 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
994 DUMP_REG(DC_WIN_WIN_OPTIONS);
995 DUMP_REG(DC_WIN_BYTE_SWAP);
996 DUMP_REG(DC_WIN_BUFFER_CONTROL);
997 DUMP_REG(DC_WIN_COLOR_DEPTH);
998 DUMP_REG(DC_WIN_POSITION);
999 DUMP_REG(DC_WIN_SIZE);
1000 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1001 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1002 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1003 DUMP_REG(DC_WIN_DDA_INC);
1004 DUMP_REG(DC_WIN_LINE_STRIDE);
1005 DUMP_REG(DC_WIN_BUF_STRIDE);
1006 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1007 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1008 DUMP_REG(DC_WIN_DV_CONTROL);
1009 DUMP_REG(DC_WIN_BLEND_NOKEY);
1010 DUMP_REG(DC_WIN_BLEND_1WIN);
1011 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1012 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1013 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1014 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1015 DUMP_REG(DC_WINBUF_START_ADDR);
1016 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1017 DUMP_REG(DC_WINBUF_START_ADDR_U);
1018 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1019 DUMP_REG(DC_WINBUF_START_ADDR_V);
1020 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1021 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1022 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1023 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1024 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1025 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1026 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1027 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1028 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1029
1030#undef DUMP_REG
1031
1032 return 0;
1033}
1034
1035static struct drm_info_list debugfs_files[] = {
1036 { "regs", tegra_dc_show_regs, 0, NULL },
1037};
1038
1039static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1040{
1041 unsigned int i;
1042 char *name;
1043 int err;
1044
1045 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1046 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1047 kfree(name);
1048
1049 if (!dc->debugfs)
1050 return -ENOMEM;
1051
1052 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1053 GFP_KERNEL);
1054 if (!dc->debugfs_files) {
1055 err = -ENOMEM;
1056 goto remove;
1057 }
1058
1059 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1060 dc->debugfs_files[i].data = dc;
1061
1062 err = drm_debugfs_create_files(dc->debugfs_files,
1063 ARRAY_SIZE(debugfs_files),
1064 dc->debugfs, minor);
1065 if (err < 0)
1066 goto free;
1067
1068 dc->minor = minor;
1069
1070 return 0;
1071
1072free:
1073 kfree(dc->debugfs_files);
1074 dc->debugfs_files = NULL;
1075remove:
1076 debugfs_remove(dc->debugfs);
1077 dc->debugfs = NULL;
1078
1079 return err;
1080}
1081
1082static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1083{
1084 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1085 dc->minor);
1086 dc->minor = NULL;
1087
1088 kfree(dc->debugfs_files);
1089 dc->debugfs_files = NULL;
1090
1091 debugfs_remove(dc->debugfs);
1092 dc->debugfs = NULL;
1093
1094 return 0;
1095}
1096
1097static int tegra_dc_init(struct host1x_client *client)
1098{
1099 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
1100 struct tegra_dc *dc = host1x_client_to_dc(client);
1101 int err;
1102
1103 drm_crtc_init(tegra->drm, &dc->base, &tegra_crtc_funcs);
1104 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1105 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1106
1107 err = tegra_dc_rgb_init(tegra->drm, dc);
1108 if (err < 0 && err != -ENODEV) {
1109 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1110 return err;
1111 }
1112
1113 err = tegra_dc_add_planes(tegra->drm, dc);
1114 if (err < 0)
1115 return err;
1116
1117 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1118 err = tegra_dc_debugfs_init(dc, tegra->drm->primary);
1119 if (err < 0)
1120 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1121 }
1122
1123 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1124 dev_name(dc->dev), dc);
1125 if (err < 0) {
1126 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1127 err);
1128 return err;
1129 }
1130
1131 return 0;
1132}
1133
1134static int tegra_dc_exit(struct host1x_client *client)
1135{
1136 struct tegra_dc *dc = host1x_client_to_dc(client);
1137 int err;
1138
1139 devm_free_irq(dc->dev, dc->irq, dc);
1140
1141 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1142 err = tegra_dc_debugfs_exit(dc);
1143 if (err < 0)
1144 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1145 }
1146
1147 err = tegra_dc_rgb_exit(dc);
1148 if (err) {
1149 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1150 return err;
1151 }
1152
1153 return 0;
1154}
1155
1156static const struct host1x_client_ops dc_client_ops = {
1157 .init = tegra_dc_init,
1158 .exit = tegra_dc_exit,
1159};
1160
1161static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1162 .supports_interlacing = false,
1163};
1164
1165static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1166 .supports_interlacing = false,
1167};
1168
1169static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1170 .supports_interlacing = true,
1171};
1172
1173static const struct of_device_id tegra_dc_of_match[] = {
1174 {
1175 .compatible = "nvidia,tegra124-dc",
1176 .data = &tegra124_dc_soc_info,
1177 }, {
1178 .compatible = "nvidia,tegra30-dc",
1179 .data = &tegra30_dc_soc_info,
1180 }, {
1181 .compatible = "nvidia,tegra20-dc",
1182 .data = &tegra20_dc_soc_info,
1183 }, {
1184 /* sentinel */
1185 }
1186};
1187
1188static int tegra_dc_parse_dt(struct tegra_dc *dc)
1189{
1190 struct device_node *np;
1191 u32 value = 0;
1192 int err;
1193
1194 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1195 if (err < 0) {
1196 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1197
1198 /*
1199 * If the nvidia,head property isn't present, try to find the
1200 * correct head number by looking up the position of this
1201 * display controller's node within the device tree. Assuming
1202 * that the nodes are ordered properly in the DTS file and
1203 * that the translation into a flattened device tree blob
1204 * preserves that ordering this will actually yield the right
1205 * head number.
1206 *
1207 * If those assumptions don't hold, this will still work for
1208 * cases where only a single display controller is used.
1209 */
1210 for_each_matching_node(np, tegra_dc_of_match) {
1211 if (np == dc->dev->of_node)
1212 break;
1213
1214 value++;
1215 }
1216 }
1217
1218 dc->pipe = value;
1219
1220 return 0;
1221}
1222
1223static int tegra_dc_probe(struct platform_device *pdev)
1224{
1225 const struct of_device_id *id;
1226 struct resource *regs;
1227 struct tegra_dc *dc;
1228 int err;
1229
1230 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1231 if (!dc)
1232 return -ENOMEM;
1233
1234 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1235 if (!id)
1236 return -ENODEV;
1237
1238 spin_lock_init(&dc->lock);
1239 INIT_LIST_HEAD(&dc->list);
1240 dc->dev = &pdev->dev;
1241 dc->soc = id->data;
1242
1243 err = tegra_dc_parse_dt(dc);
1244 if (err < 0)
1245 return err;
1246
1247 dc->clk = devm_clk_get(&pdev->dev, NULL);
1248 if (IS_ERR(dc->clk)) {
1249 dev_err(&pdev->dev, "failed to get clock\n");
1250 return PTR_ERR(dc->clk);
1251 }
1252
1253 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1254 if (IS_ERR(dc->rst)) {
1255 dev_err(&pdev->dev, "failed to get reset\n");
1256 return PTR_ERR(dc->rst);
1257 }
1258
1259 err = clk_prepare_enable(dc->clk);
1260 if (err < 0)
1261 return err;
1262
1263 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1264 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1265 if (IS_ERR(dc->regs))
1266 return PTR_ERR(dc->regs);
1267
1268 dc->irq = platform_get_irq(pdev, 0);
1269 if (dc->irq < 0) {
1270 dev_err(&pdev->dev, "failed to get IRQ\n");
1271 return -ENXIO;
1272 }
1273
1274 INIT_LIST_HEAD(&dc->client.list);
1275 dc->client.ops = &dc_client_ops;
1276 dc->client.dev = &pdev->dev;
1277
1278 err = tegra_dc_rgb_probe(dc);
1279 if (err < 0 && err != -ENODEV) {
1280 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1281 return err;
1282 }
1283
1284 err = host1x_client_register(&dc->client);
1285 if (err < 0) {
1286 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1287 err);
1288 return err;
1289 }
1290
1291 platform_set_drvdata(pdev, dc);
1292
1293 return 0;
1294}
1295
1296static int tegra_dc_remove(struct platform_device *pdev)
1297{
1298 struct tegra_dc *dc = platform_get_drvdata(pdev);
1299 int err;
1300
1301 err = host1x_client_unregister(&dc->client);
1302 if (err < 0) {
1303 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1304 err);
1305 return err;
1306 }
1307
1308 err = tegra_dc_rgb_remove(dc);
1309 if (err < 0) {
1310 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
1311 return err;
1312 }
1313
1314 clk_disable_unprepare(dc->clk);
1315
1316 return 0;
1317}
1318
1319struct platform_driver tegra_dc_driver = {
1320 .driver = {
1321 .name = "tegra-dc",
1322 .owner = THIS_MODULE,
1323 .of_match_table = tegra_dc_of_match,
1324 },
1325 .probe = tegra_dc_probe,
1326 .remove = tegra_dc_remove,
1327};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7#include <linux/clk.h>
8#include <linux/debugfs.h>
9#include <linux/delay.h>
10#include <linux/dma-mapping.h>
11#include <linux/iommu.h>
12#include <linux/interconnect.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/pm_domain.h>
16#include <linux/pm_opp.h>
17#include <linux/pm_runtime.h>
18#include <linux/reset.h>
19
20#include <soc/tegra/common.h>
21#include <soc/tegra/pmc.h>
22
23#include <drm/drm_atomic.h>
24#include <drm/drm_atomic_helper.h>
25#include <drm/drm_blend.h>
26#include <drm/drm_debugfs.h>
27#include <drm/drm_fourcc.h>
28#include <drm/drm_framebuffer.h>
29#include <drm/drm_vblank.h>
30
31#include "dc.h"
32#include "drm.h"
33#include "gem.h"
34#include "hub.h"
35#include "plane.h"
36
37static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
38 struct drm_crtc_state *state);
39
40static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
41{
42 stats->frames = 0;
43 stats->vblank = 0;
44 stats->underflow = 0;
45 stats->overflow = 0;
46}
47
48/* Reads the active copy of a register. */
49static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
50{
51 u32 value;
52
53 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
54 value = tegra_dc_readl(dc, offset);
55 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
56
57 return value;
58}
59
60static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
61 unsigned int offset)
62{
63 if (offset >= 0x500 && offset <= 0x638) {
64 offset = 0x000 + (offset - 0x500);
65 return plane->offset + offset;
66 }
67
68 if (offset >= 0x700 && offset <= 0x719) {
69 offset = 0x180 + (offset - 0x700);
70 return plane->offset + offset;
71 }
72
73 if (offset >= 0x800 && offset <= 0x839) {
74 offset = 0x1c0 + (offset - 0x800);
75 return plane->offset + offset;
76 }
77
78 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
79
80 return plane->offset + offset;
81}
82
83static inline u32 tegra_plane_readl(struct tegra_plane *plane,
84 unsigned int offset)
85{
86 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
87}
88
89static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
90 unsigned int offset)
91{
92 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
93}
94
95bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
96{
97 struct device_node *np = dc->dev->of_node;
98 struct of_phandle_iterator it;
99 int err;
100
101 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
102 if (it.node == dev->of_node)
103 return true;
104
105 return false;
106}
107
108/*
109 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
110 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
111 * Latching happens mmediately if the display controller is in STOP mode or
112 * on the next frame boundary otherwise.
113 *
114 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
115 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
116 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
117 * into the ACTIVE copy, either immediately if the display controller is in
118 * STOP mode, or at the next frame boundary otherwise.
119 */
120void tegra_dc_commit(struct tegra_dc *dc)
121{
122 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
123 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
124}
125
126static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
127 unsigned int bpp)
128{
129 fixed20_12 outf = dfixed_init(out);
130 fixed20_12 inf = dfixed_init(in);
131 u32 dda_inc;
132 int max;
133
134 if (v)
135 max = 15;
136 else {
137 switch (bpp) {
138 case 2:
139 max = 8;
140 break;
141
142 default:
143 WARN_ON_ONCE(1);
144 fallthrough;
145 case 4:
146 max = 4;
147 break;
148 }
149 }
150
151 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
152 inf.full -= dfixed_const(1);
153
154 dda_inc = dfixed_div(inf, outf);
155 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
156
157 return dda_inc;
158}
159
160static inline u32 compute_initial_dda(unsigned int in)
161{
162 fixed20_12 inf = dfixed_init(in);
163 return dfixed_frac(inf);
164}
165
166static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
167{
168 u32 background[3] = {
169 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
170 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
171 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
172 };
173 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
174 BLEND_COLOR_KEY_NONE;
175 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
176 struct tegra_plane_state *state;
177 u32 blending[2];
178 unsigned int i;
179
180 /* disable blending for non-overlapping case */
181 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
182 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
183
184 state = to_tegra_plane_state(plane->base.state);
185
186 if (state->opaque) {
187 /*
188 * Since custom fix-weight blending isn't utilized and weight
189 * of top window is set to max, we can enforce dependent
190 * blending which in this case results in transparent bottom
191 * window if top window is opaque and if top window enables
192 * alpha blending, then bottom window is getting alpha value
193 * of 1 minus the sum of alpha components of the overlapping
194 * plane.
195 */
196 background[0] |= BLEND_CONTROL_DEPENDENT;
197 background[1] |= BLEND_CONTROL_DEPENDENT;
198
199 /*
200 * The region where three windows overlap is the intersection
201 * of the two regions where two windows overlap. It contributes
202 * to the area if all of the windows on top of it have an alpha
203 * component.
204 */
205 switch (state->base.normalized_zpos) {
206 case 0:
207 if (state->blending[0].alpha &&
208 state->blending[1].alpha)
209 background[2] |= BLEND_CONTROL_DEPENDENT;
210 break;
211
212 case 1:
213 background[2] |= BLEND_CONTROL_DEPENDENT;
214 break;
215 }
216 } else {
217 /*
218 * Enable alpha blending if pixel format has an alpha
219 * component.
220 */
221 foreground |= BLEND_CONTROL_ALPHA;
222
223 /*
224 * If any of the windows on top of this window is opaque, it
225 * will completely conceal this window within that area. If
226 * top window has an alpha component, it is blended over the
227 * bottom window.
228 */
229 for (i = 0; i < 2; i++) {
230 if (state->blending[i].alpha &&
231 state->blending[i].top)
232 background[i] |= BLEND_CONTROL_DEPENDENT;
233 }
234
235 switch (state->base.normalized_zpos) {
236 case 0:
237 if (state->blending[0].alpha &&
238 state->blending[1].alpha)
239 background[2] |= BLEND_CONTROL_DEPENDENT;
240 break;
241
242 case 1:
243 /*
244 * When both middle and topmost windows have an alpha,
245 * these windows a mixed together and then the result
246 * is blended over the bottom window.
247 */
248 if (state->blending[0].alpha &&
249 state->blending[0].top)
250 background[2] |= BLEND_CONTROL_ALPHA;
251
252 if (state->blending[1].alpha &&
253 state->blending[1].top)
254 background[2] |= BLEND_CONTROL_ALPHA;
255 break;
256 }
257 }
258
259 switch (state->base.normalized_zpos) {
260 case 0:
261 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
262 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
263 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
264 break;
265
266 case 1:
267 /*
268 * If window B / C is topmost, then X / Y registers are
269 * matching the order of blending[...] state indices,
270 * otherwise a swap is required.
271 */
272 if (!state->blending[0].top && state->blending[1].top) {
273 blending[0] = foreground;
274 blending[1] = background[1];
275 } else {
276 blending[0] = background[0];
277 blending[1] = foreground;
278 }
279
280 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
281 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
282 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
283 break;
284
285 case 2:
286 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
287 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
288 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
289 break;
290 }
291}
292
293static void tegra_plane_setup_blending(struct tegra_plane *plane,
294 const struct tegra_dc_window *window)
295{
296 u32 value;
297
298 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
299 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
300 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
301 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
302
303 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
304 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
305 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
306 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
307
308 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
309 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
310}
311
312static bool
313tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
314 const struct tegra_dc_window *window)
315{
316 struct tegra_dc *dc = plane->dc;
317
318 if (window->src.w == window->dst.w)
319 return false;
320
321 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
322 return false;
323
324 return true;
325}
326
327static bool
328tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
329 const struct tegra_dc_window *window)
330{
331 struct tegra_dc *dc = plane->dc;
332
333 if (window->src.h == window->dst.h)
334 return false;
335
336 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
337 return false;
338
339 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
340 return false;
341
342 return true;
343}
344
345static void tegra_dc_setup_window(struct tegra_plane *plane,
346 const struct tegra_dc_window *window)
347{
348 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
349 struct tegra_dc *dc = plane->dc;
350 unsigned int planes;
351 u32 value;
352 bool yuv;
353
354 /*
355 * For YUV planar modes, the number of bytes per pixel takes into
356 * account only the luma component and therefore is 1.
357 */
358 yuv = tegra_plane_format_is_yuv(window->format, &planes, NULL);
359 if (!yuv)
360 bpp = window->bits_per_pixel / 8;
361 else
362 bpp = (planes > 1) ? 1 : 2;
363
364 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
365 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
366
367 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
368 tegra_plane_writel(plane, value, DC_WIN_POSITION);
369
370 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
371 tegra_plane_writel(plane, value, DC_WIN_SIZE);
372
373 h_offset = window->src.x * bpp;
374 v_offset = window->src.y;
375 h_size = window->src.w * bpp;
376 v_size = window->src.h;
377
378 if (window->reflect_x)
379 h_offset += (window->src.w - 1) * bpp;
380
381 if (window->reflect_y)
382 v_offset += window->src.h - 1;
383
384 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
385 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
386
387 /*
388 * For DDA computations the number of bytes per pixel for YUV planar
389 * modes needs to take into account all Y, U and V components.
390 */
391 if (yuv && planes > 1)
392 bpp = 2;
393
394 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
395 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
396
397 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
398 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
399
400 h_dda = compute_initial_dda(window->src.x);
401 v_dda = compute_initial_dda(window->src.y);
402
403 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
404 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
405
406 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
407 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
408
409 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
410
411 if (yuv && planes > 1) {
412 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
413
414 if (planes > 2)
415 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
416
417 value = window->stride[1] << 16 | window->stride[0];
418 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
419 } else {
420 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
421 }
422
423 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
424 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
425
426 if (dc->soc->supports_block_linear) {
427 unsigned long height = window->tiling.value;
428
429 switch (window->tiling.mode) {
430 case TEGRA_BO_TILING_MODE_PITCH:
431 value = DC_WINBUF_SURFACE_KIND_PITCH;
432 break;
433
434 case TEGRA_BO_TILING_MODE_TILED:
435 value = DC_WINBUF_SURFACE_KIND_TILED;
436 break;
437
438 case TEGRA_BO_TILING_MODE_BLOCK:
439 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
440 DC_WINBUF_SURFACE_KIND_BLOCK;
441 break;
442 }
443
444 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
445 } else {
446 switch (window->tiling.mode) {
447 case TEGRA_BO_TILING_MODE_PITCH:
448 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
449 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
450 break;
451
452 case TEGRA_BO_TILING_MODE_TILED:
453 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
454 DC_WIN_BUFFER_ADDR_MODE_TILE;
455 break;
456
457 case TEGRA_BO_TILING_MODE_BLOCK:
458 /*
459 * No need to handle this here because ->atomic_check
460 * will already have filtered it out.
461 */
462 break;
463 }
464
465 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
466 }
467
468 value = WIN_ENABLE;
469
470 if (yuv) {
471 /* setup default colorspace conversion coefficients */
472 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
473 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
474 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
475 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
476 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
477 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
478 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
479 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
480
481 value |= CSC_ENABLE;
482 } else if (window->bits_per_pixel < 24) {
483 value |= COLOR_EXPAND;
484 }
485
486 if (window->reflect_x)
487 value |= H_DIRECTION;
488
489 if (window->reflect_y)
490 value |= V_DIRECTION;
491
492 if (tegra_plane_use_horizontal_filtering(plane, window)) {
493 /*
494 * Enable horizontal 6-tap filter and set filtering
495 * coefficients to the default values defined in TRM.
496 */
497 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
498 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
499 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
500 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
501 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
502 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
503 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
504 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
505 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
506 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
507 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
508 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
509 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
510 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
511 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
512 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
513
514 value |= H_FILTER;
515 }
516
517 if (tegra_plane_use_vertical_filtering(plane, window)) {
518 unsigned int i, k;
519
520 /*
521 * Enable vertical 2-tap filter and set filtering
522 * coefficients to the default values defined in TRM.
523 */
524 for (i = 0, k = 128; i < 16; i++, k -= 8)
525 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
526
527 value |= V_FILTER;
528 }
529
530 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
531
532 if (dc->soc->has_legacy_blending)
533 tegra_plane_setup_blending_legacy(plane);
534 else
535 tegra_plane_setup_blending(plane, window);
536}
537
538static const u32 tegra20_primary_formats[] = {
539 DRM_FORMAT_ARGB4444,
540 DRM_FORMAT_ARGB1555,
541 DRM_FORMAT_RGB565,
542 DRM_FORMAT_RGBA5551,
543 DRM_FORMAT_ABGR8888,
544 DRM_FORMAT_ARGB8888,
545 /* non-native formats */
546 DRM_FORMAT_XRGB1555,
547 DRM_FORMAT_RGBX5551,
548 DRM_FORMAT_XBGR8888,
549 DRM_FORMAT_XRGB8888,
550};
551
552static const u64 tegra20_modifiers[] = {
553 DRM_FORMAT_MOD_LINEAR,
554 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
555 DRM_FORMAT_MOD_INVALID
556};
557
558static const u32 tegra114_primary_formats[] = {
559 DRM_FORMAT_ARGB4444,
560 DRM_FORMAT_ARGB1555,
561 DRM_FORMAT_RGB565,
562 DRM_FORMAT_RGBA5551,
563 DRM_FORMAT_ABGR8888,
564 DRM_FORMAT_ARGB8888,
565 /* new on Tegra114 */
566 DRM_FORMAT_ABGR4444,
567 DRM_FORMAT_ABGR1555,
568 DRM_FORMAT_BGRA5551,
569 DRM_FORMAT_XRGB1555,
570 DRM_FORMAT_RGBX5551,
571 DRM_FORMAT_XBGR1555,
572 DRM_FORMAT_BGRX5551,
573 DRM_FORMAT_BGR565,
574 DRM_FORMAT_BGRA8888,
575 DRM_FORMAT_RGBA8888,
576 DRM_FORMAT_XRGB8888,
577 DRM_FORMAT_XBGR8888,
578};
579
580static const u32 tegra124_primary_formats[] = {
581 DRM_FORMAT_ARGB4444,
582 DRM_FORMAT_ARGB1555,
583 DRM_FORMAT_RGB565,
584 DRM_FORMAT_RGBA5551,
585 DRM_FORMAT_ABGR8888,
586 DRM_FORMAT_ARGB8888,
587 /* new on Tegra114 */
588 DRM_FORMAT_ABGR4444,
589 DRM_FORMAT_ABGR1555,
590 DRM_FORMAT_BGRA5551,
591 DRM_FORMAT_XRGB1555,
592 DRM_FORMAT_RGBX5551,
593 DRM_FORMAT_XBGR1555,
594 DRM_FORMAT_BGRX5551,
595 DRM_FORMAT_BGR565,
596 DRM_FORMAT_BGRA8888,
597 DRM_FORMAT_RGBA8888,
598 DRM_FORMAT_XRGB8888,
599 DRM_FORMAT_XBGR8888,
600 /* new on Tegra124 */
601 DRM_FORMAT_RGBX8888,
602 DRM_FORMAT_BGRX8888,
603};
604
605static const u64 tegra124_modifiers[] = {
606 DRM_FORMAT_MOD_LINEAR,
607 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
608 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
609 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
610 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
611 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
612 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
613 DRM_FORMAT_MOD_INVALID
614};
615
616static int tegra_plane_atomic_check(struct drm_plane *plane,
617 struct drm_atomic_state *state)
618{
619 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
620 plane);
621 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);
622 unsigned int supported_rotation = DRM_MODE_ROTATE_0 |
623 DRM_MODE_REFLECT_X |
624 DRM_MODE_REFLECT_Y;
625 unsigned int rotation = new_plane_state->rotation;
626 struct tegra_bo_tiling *tiling = &plane_state->tiling;
627 struct tegra_plane *tegra = to_tegra_plane(plane);
628 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc);
629 int err;
630
631 plane_state->peak_memory_bandwidth = 0;
632 plane_state->avg_memory_bandwidth = 0;
633
634 /* no need for further checks if the plane is being disabled */
635 if (!new_plane_state->crtc) {
636 plane_state->total_peak_memory_bandwidth = 0;
637 return 0;
638 }
639
640 err = tegra_plane_format(new_plane_state->fb->format->format,
641 &plane_state->format,
642 &plane_state->swap);
643 if (err < 0)
644 return err;
645
646 /*
647 * Tegra20 and Tegra30 are special cases here because they support
648 * only variants of specific formats with an alpha component, but not
649 * the corresponding opaque formats. However, the opaque formats can
650 * be emulated by disabling alpha blending for the plane.
651 */
652 if (dc->soc->has_legacy_blending) {
653 err = tegra_plane_setup_legacy_state(tegra, plane_state);
654 if (err < 0)
655 return err;
656 }
657
658 err = tegra_fb_get_tiling(new_plane_state->fb, tiling);
659 if (err < 0)
660 return err;
661
662 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
663 !dc->soc->supports_block_linear) {
664 DRM_ERROR("hardware doesn't support block linear mode\n");
665 return -EINVAL;
666 }
667
668 /*
669 * Older userspace used custom BO flag in order to specify the Y
670 * reflection, while modern userspace uses the generic DRM rotation
671 * property in order to achieve the same result. The legacy BO flag
672 * duplicates the DRM rotation property when both are set.
673 */
674 if (tegra_fb_is_bottom_up(new_plane_state->fb))
675 rotation |= DRM_MODE_REFLECT_Y;
676
677 rotation = drm_rotation_simplify(rotation, supported_rotation);
678
679 if (rotation & DRM_MODE_REFLECT_X)
680 plane_state->reflect_x = true;
681 else
682 plane_state->reflect_x = false;
683
684 if (rotation & DRM_MODE_REFLECT_Y)
685 plane_state->reflect_y = true;
686 else
687 plane_state->reflect_y = false;
688
689 /*
690 * Tegra doesn't support different strides for U and V planes so we
691 * error out if the user tries to display a framebuffer with such a
692 * configuration.
693 */
694 if (new_plane_state->fb->format->num_planes > 2) {
695 if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) {
696 DRM_ERROR("unsupported UV-plane configuration\n");
697 return -EINVAL;
698 }
699 }
700
701 err = tegra_plane_state_add(tegra, new_plane_state);
702 if (err < 0)
703 return err;
704
705 return 0;
706}
707
708static void tegra_plane_atomic_disable(struct drm_plane *plane,
709 struct drm_atomic_state *state)
710{
711 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
712 plane);
713 struct tegra_plane *p = to_tegra_plane(plane);
714 u32 value;
715
716 /* rien ne va plus */
717 if (!old_state || !old_state->crtc)
718 return;
719
720 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
721 value &= ~WIN_ENABLE;
722 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
723}
724
725static void tegra_plane_atomic_update(struct drm_plane *plane,
726 struct drm_atomic_state *state)
727{
728 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
729 plane);
730 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
731 struct drm_framebuffer *fb = new_state->fb;
732 struct tegra_plane *p = to_tegra_plane(plane);
733 struct tegra_dc_window window;
734 unsigned int i;
735
736 /* rien ne va plus */
737 if (!new_state->crtc || !new_state->fb)
738 return;
739
740 if (!new_state->visible)
741 return tegra_plane_atomic_disable(plane, state);
742
743 memset(&window, 0, sizeof(window));
744 window.src.x = new_state->src.x1 >> 16;
745 window.src.y = new_state->src.y1 >> 16;
746 window.src.w = drm_rect_width(&new_state->src) >> 16;
747 window.src.h = drm_rect_height(&new_state->src) >> 16;
748 window.dst.x = new_state->dst.x1;
749 window.dst.y = new_state->dst.y1;
750 window.dst.w = drm_rect_width(&new_state->dst);
751 window.dst.h = drm_rect_height(&new_state->dst);
752 window.bits_per_pixel = fb->format->cpp[0] * 8;
753 window.reflect_x = tegra_plane_state->reflect_x;
754 window.reflect_y = tegra_plane_state->reflect_y;
755
756 /* copy from state */
757 window.zpos = new_state->normalized_zpos;
758 window.tiling = tegra_plane_state->tiling;
759 window.format = tegra_plane_state->format;
760 window.swap = tegra_plane_state->swap;
761
762 for (i = 0; i < fb->format->num_planes; i++) {
763 window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i];
764
765 /*
766 * Tegra uses a shared stride for UV planes. Framebuffers are
767 * already checked for this in the tegra_plane_atomic_check()
768 * function, so it's safe to ignore the V-plane pitch here.
769 */
770 if (i < 2)
771 window.stride[i] = fb->pitches[i];
772 }
773
774 tegra_dc_setup_window(p, &window);
775}
776
777static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
778 .prepare_fb = tegra_plane_prepare_fb,
779 .cleanup_fb = tegra_plane_cleanup_fb,
780 .atomic_check = tegra_plane_atomic_check,
781 .atomic_disable = tegra_plane_atomic_disable,
782 .atomic_update = tegra_plane_atomic_update,
783};
784
785static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
786{
787 /*
788 * Ideally this would use drm_crtc_mask(), but that would require the
789 * CRTC to already be in the mode_config's list of CRTCs. However, it
790 * will only be added to that list in the drm_crtc_init_with_planes()
791 * (in tegra_dc_init()), which in turn requires registration of these
792 * planes. So we have ourselves a nice little chicken and egg problem
793 * here.
794 *
795 * We work around this by manually creating the mask from the number
796 * of CRTCs that have been registered, and should therefore always be
797 * the same as drm_crtc_index() after registration.
798 */
799 return 1 << drm->mode_config.num_crtc;
800}
801
802static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
803 struct tegra_dc *dc)
804{
805 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
806 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
807 struct tegra_plane *plane;
808 unsigned int num_formats;
809 const u64 *modifiers;
810 const u32 *formats;
811 int err;
812
813 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
814 if (!plane)
815 return ERR_PTR(-ENOMEM);
816
817 /* Always use window A as primary window */
818 plane->offset = 0xa00;
819 plane->index = 0;
820 plane->dc = dc;
821
822 num_formats = dc->soc->num_primary_formats;
823 formats = dc->soc->primary_formats;
824 modifiers = dc->soc->modifiers;
825
826 err = tegra_plane_interconnect_init(plane);
827 if (err) {
828 kfree(plane);
829 return ERR_PTR(err);
830 }
831
832 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
833 &tegra_plane_funcs, formats,
834 num_formats, modifiers, type, NULL);
835 if (err < 0) {
836 kfree(plane);
837 return ERR_PTR(err);
838 }
839
840 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
841 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
842
843 err = drm_plane_create_rotation_property(&plane->base,
844 DRM_MODE_ROTATE_0,
845 DRM_MODE_ROTATE_0 |
846 DRM_MODE_ROTATE_180 |
847 DRM_MODE_REFLECT_X |
848 DRM_MODE_REFLECT_Y);
849 if (err < 0)
850 dev_err(dc->dev, "failed to create rotation property: %d\n",
851 err);
852
853 return &plane->base;
854}
855
856static const u32 tegra_legacy_cursor_plane_formats[] = {
857 DRM_FORMAT_RGBA8888,
858};
859
860static const u32 tegra_cursor_plane_formats[] = {
861 DRM_FORMAT_ARGB8888,
862};
863
864static int tegra_cursor_atomic_check(struct drm_plane *plane,
865 struct drm_atomic_state *state)
866{
867 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
868 plane);
869 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state);
870 struct tegra_plane *tegra = to_tegra_plane(plane);
871 int err;
872
873 plane_state->peak_memory_bandwidth = 0;
874 plane_state->avg_memory_bandwidth = 0;
875
876 /* no need for further checks if the plane is being disabled */
877 if (!new_plane_state->crtc) {
878 plane_state->total_peak_memory_bandwidth = 0;
879 return 0;
880 }
881
882 /* scaling not supported for cursor */
883 if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) ||
884 (new_plane_state->src_h >> 16 != new_plane_state->crtc_h))
885 return -EINVAL;
886
887 /* only square cursors supported */
888 if (new_plane_state->src_w != new_plane_state->src_h)
889 return -EINVAL;
890
891 if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 &&
892 new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256)
893 return -EINVAL;
894
895 err = tegra_plane_state_add(tegra, new_plane_state);
896 if (err < 0)
897 return err;
898
899 return 0;
900}
901
902static void __tegra_cursor_atomic_update(struct drm_plane *plane,
903 struct drm_plane_state *new_state)
904{
905 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state);
906 struct tegra_dc *dc = to_tegra_dc(new_state->crtc);
907 struct tegra_drm *tegra = plane->dev->dev_private;
908#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
909 u64 dma_mask = *dc->dev->dma_mask;
910#endif
911 unsigned int x, y;
912 u32 value = 0;
913
914 /* rien ne va plus */
915 if (!new_state->crtc || !new_state->fb)
916 return;
917
918 /*
919 * Legacy display supports hardware clipping of the cursor, but
920 * nvdisplay relies on software to clip the cursor to the screen.
921 */
922 if (!dc->soc->has_nvdisplay)
923 value |= CURSOR_CLIP_DISPLAY;
924
925 switch (new_state->crtc_w) {
926 case 32:
927 value |= CURSOR_SIZE_32x32;
928 break;
929
930 case 64:
931 value |= CURSOR_SIZE_64x64;
932 break;
933
934 case 128:
935 value |= CURSOR_SIZE_128x128;
936 break;
937
938 case 256:
939 value |= CURSOR_SIZE_256x256;
940 break;
941
942 default:
943 WARN(1, "cursor size %ux%u not supported\n",
944 new_state->crtc_w, new_state->crtc_h);
945 return;
946 }
947
948 value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff;
949 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
950
951#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
952 value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32);
953 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
954#endif
955
956 /* enable cursor and set blend mode */
957 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
958 value |= CURSOR_ENABLE;
959 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
960
961 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
962 value &= ~CURSOR_DST_BLEND_MASK;
963 value &= ~CURSOR_SRC_BLEND_MASK;
964
965 if (dc->soc->has_nvdisplay)
966 value &= ~CURSOR_COMPOSITION_MODE_XOR;
967 else
968 value |= CURSOR_MODE_NORMAL;
969
970 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
971 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
972 value |= CURSOR_ALPHA;
973 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
974
975 /* nvdisplay relies on software for clipping */
976 if (dc->soc->has_nvdisplay) {
977 struct drm_rect src;
978
979 x = new_state->dst.x1;
980 y = new_state->dst.y1;
981
982 drm_rect_fp_to_int(&src, &new_state->src);
983
984 value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask);
985 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR);
986
987 value = (drm_rect_height(&src) & tegra->vmask) << 16 |
988 (drm_rect_width(&src) & tegra->hmask);
989 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR);
990 } else {
991 x = new_state->crtc_x;
992 y = new_state->crtc_y;
993 }
994
995 /* position the cursor */
996 value = ((y & tegra->vmask) << 16) | (x & tegra->hmask);
997 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
998}
999
1000static void tegra_cursor_atomic_update(struct drm_plane *plane,
1001 struct drm_atomic_state *state)
1002{
1003 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1004
1005 __tegra_cursor_atomic_update(plane, new_state);
1006}
1007
1008static void tegra_cursor_atomic_disable(struct drm_plane *plane,
1009 struct drm_atomic_state *state)
1010{
1011 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
1012 plane);
1013 struct tegra_dc *dc;
1014 u32 value;
1015
1016 /* rien ne va plus */
1017 if (!old_state || !old_state->crtc)
1018 return;
1019
1020 dc = to_tegra_dc(old_state->crtc);
1021
1022 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1023 value &= ~CURSOR_ENABLE;
1024 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1025}
1026
1027static int tegra_cursor_atomic_async_check(struct drm_plane *plane, struct drm_atomic_state *state)
1028{
1029 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1030 struct drm_crtc_state *crtc_state;
1031 int min_scale, max_scale;
1032 int err;
1033
1034 crtc_state = drm_atomic_get_existing_crtc_state(state, new_state->crtc);
1035 if (WARN_ON(!crtc_state))
1036 return -EINVAL;
1037
1038 if (!crtc_state->active)
1039 return -EINVAL;
1040
1041 if (plane->state->crtc != new_state->crtc ||
1042 plane->state->src_w != new_state->src_w ||
1043 plane->state->src_h != new_state->src_h ||
1044 plane->state->crtc_w != new_state->crtc_w ||
1045 plane->state->crtc_h != new_state->crtc_h ||
1046 plane->state->fb != new_state->fb ||
1047 plane->state->fb == NULL)
1048 return -EINVAL;
1049
1050 min_scale = (1 << 16) / 8;
1051 max_scale = (8 << 16) / 1;
1052
1053 err = drm_atomic_helper_check_plane_state(new_state, crtc_state, min_scale, max_scale,
1054 true, true);
1055 if (err < 0)
1056 return err;
1057
1058 if (new_state->visible != plane->state->visible)
1059 return -EINVAL;
1060
1061 return 0;
1062}
1063
1064static void tegra_cursor_atomic_async_update(struct drm_plane *plane,
1065 struct drm_atomic_state *state)
1066{
1067 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1068 struct tegra_dc *dc = to_tegra_dc(new_state->crtc);
1069
1070 plane->state->src_x = new_state->src_x;
1071 plane->state->src_y = new_state->src_y;
1072 plane->state->crtc_x = new_state->crtc_x;
1073 plane->state->crtc_y = new_state->crtc_y;
1074
1075 if (new_state->visible) {
1076 struct tegra_plane *p = to_tegra_plane(plane);
1077 u32 value;
1078
1079 __tegra_cursor_atomic_update(plane, new_state);
1080
1081 value = (WIN_A_ACT_REQ << p->index) << 8 | GENERAL_UPDATE;
1082 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1083 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1084
1085 value = (WIN_A_ACT_REQ << p->index) | GENERAL_ACT_REQ;
1086 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1087 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1088 }
1089}
1090
1091static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
1092 .prepare_fb = tegra_plane_prepare_fb,
1093 .cleanup_fb = tegra_plane_cleanup_fb,
1094 .atomic_check = tegra_cursor_atomic_check,
1095 .atomic_update = tegra_cursor_atomic_update,
1096 .atomic_disable = tegra_cursor_atomic_disable,
1097 .atomic_async_check = tegra_cursor_atomic_async_check,
1098 .atomic_async_update = tegra_cursor_atomic_async_update,
1099};
1100
1101static const uint64_t linear_modifiers[] = {
1102 DRM_FORMAT_MOD_LINEAR,
1103 DRM_FORMAT_MOD_INVALID
1104};
1105
1106static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
1107 struct tegra_dc *dc)
1108{
1109 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1110 struct tegra_plane *plane;
1111 unsigned int num_formats;
1112 const u32 *formats;
1113 int err;
1114
1115 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1116 if (!plane)
1117 return ERR_PTR(-ENOMEM);
1118
1119 /*
1120 * This index is kind of fake. The cursor isn't a regular plane, but
1121 * its update and activation request bits in DC_CMD_STATE_CONTROL do
1122 * use the same programming. Setting this fake index here allows the
1123 * code in tegra_add_plane_state() to do the right thing without the
1124 * need to special-casing the cursor plane.
1125 */
1126 plane->index = 6;
1127 plane->dc = dc;
1128
1129 if (!dc->soc->has_nvdisplay) {
1130 num_formats = ARRAY_SIZE(tegra_legacy_cursor_plane_formats);
1131 formats = tegra_legacy_cursor_plane_formats;
1132
1133 err = tegra_plane_interconnect_init(plane);
1134 if (err) {
1135 kfree(plane);
1136 return ERR_PTR(err);
1137 }
1138 } else {
1139 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
1140 formats = tegra_cursor_plane_formats;
1141 }
1142
1143 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1144 &tegra_plane_funcs, formats,
1145 num_formats, linear_modifiers,
1146 DRM_PLANE_TYPE_CURSOR, NULL);
1147 if (err < 0) {
1148 kfree(plane);
1149 return ERR_PTR(err);
1150 }
1151
1152 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
1153 drm_plane_create_zpos_immutable_property(&plane->base, 255);
1154
1155 return &plane->base;
1156}
1157
1158static const u32 tegra20_overlay_formats[] = {
1159 DRM_FORMAT_ARGB4444,
1160 DRM_FORMAT_ARGB1555,
1161 DRM_FORMAT_RGB565,
1162 DRM_FORMAT_RGBA5551,
1163 DRM_FORMAT_ABGR8888,
1164 DRM_FORMAT_ARGB8888,
1165 /* non-native formats */
1166 DRM_FORMAT_XRGB1555,
1167 DRM_FORMAT_RGBX5551,
1168 DRM_FORMAT_XBGR8888,
1169 DRM_FORMAT_XRGB8888,
1170 /* planar formats */
1171 DRM_FORMAT_UYVY,
1172 DRM_FORMAT_YUYV,
1173 DRM_FORMAT_YUV420,
1174 DRM_FORMAT_YUV422,
1175};
1176
1177static const u32 tegra114_overlay_formats[] = {
1178 DRM_FORMAT_ARGB4444,
1179 DRM_FORMAT_ARGB1555,
1180 DRM_FORMAT_RGB565,
1181 DRM_FORMAT_RGBA5551,
1182 DRM_FORMAT_ABGR8888,
1183 DRM_FORMAT_ARGB8888,
1184 /* new on Tegra114 */
1185 DRM_FORMAT_ABGR4444,
1186 DRM_FORMAT_ABGR1555,
1187 DRM_FORMAT_BGRA5551,
1188 DRM_FORMAT_XRGB1555,
1189 DRM_FORMAT_RGBX5551,
1190 DRM_FORMAT_XBGR1555,
1191 DRM_FORMAT_BGRX5551,
1192 DRM_FORMAT_BGR565,
1193 DRM_FORMAT_BGRA8888,
1194 DRM_FORMAT_RGBA8888,
1195 DRM_FORMAT_XRGB8888,
1196 DRM_FORMAT_XBGR8888,
1197 /* planar formats */
1198 DRM_FORMAT_UYVY,
1199 DRM_FORMAT_YUYV,
1200 DRM_FORMAT_YUV420,
1201 DRM_FORMAT_YUV422,
1202 /* semi-planar formats */
1203 DRM_FORMAT_NV12,
1204 DRM_FORMAT_NV21,
1205 DRM_FORMAT_NV16,
1206 DRM_FORMAT_NV61,
1207 DRM_FORMAT_NV24,
1208 DRM_FORMAT_NV42,
1209};
1210
1211static const u32 tegra124_overlay_formats[] = {
1212 DRM_FORMAT_ARGB4444,
1213 DRM_FORMAT_ARGB1555,
1214 DRM_FORMAT_RGB565,
1215 DRM_FORMAT_RGBA5551,
1216 DRM_FORMAT_ABGR8888,
1217 DRM_FORMAT_ARGB8888,
1218 /* new on Tegra114 */
1219 DRM_FORMAT_ABGR4444,
1220 DRM_FORMAT_ABGR1555,
1221 DRM_FORMAT_BGRA5551,
1222 DRM_FORMAT_XRGB1555,
1223 DRM_FORMAT_RGBX5551,
1224 DRM_FORMAT_XBGR1555,
1225 DRM_FORMAT_BGRX5551,
1226 DRM_FORMAT_BGR565,
1227 DRM_FORMAT_BGRA8888,
1228 DRM_FORMAT_RGBA8888,
1229 DRM_FORMAT_XRGB8888,
1230 DRM_FORMAT_XBGR8888,
1231 /* new on Tegra124 */
1232 DRM_FORMAT_RGBX8888,
1233 DRM_FORMAT_BGRX8888,
1234 /* planar formats */
1235 DRM_FORMAT_UYVY,
1236 DRM_FORMAT_YUYV,
1237 DRM_FORMAT_YVYU,
1238 DRM_FORMAT_VYUY,
1239 DRM_FORMAT_YUV420, /* YU12 */
1240 DRM_FORMAT_YUV422, /* YU16 */
1241 DRM_FORMAT_YUV444, /* YU24 */
1242 /* semi-planar formats */
1243 DRM_FORMAT_NV12,
1244 DRM_FORMAT_NV21,
1245 DRM_FORMAT_NV16,
1246 DRM_FORMAT_NV61,
1247 DRM_FORMAT_NV24,
1248 DRM_FORMAT_NV42,
1249};
1250
1251static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
1252 struct tegra_dc *dc,
1253 unsigned int index,
1254 bool cursor)
1255{
1256 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
1257 struct tegra_plane *plane;
1258 unsigned int num_formats;
1259 enum drm_plane_type type;
1260 const u32 *formats;
1261 int err;
1262
1263 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1264 if (!plane)
1265 return ERR_PTR(-ENOMEM);
1266
1267 plane->offset = 0xa00 + 0x200 * index;
1268 plane->index = index;
1269 plane->dc = dc;
1270
1271 num_formats = dc->soc->num_overlay_formats;
1272 formats = dc->soc->overlay_formats;
1273
1274 err = tegra_plane_interconnect_init(plane);
1275 if (err) {
1276 kfree(plane);
1277 return ERR_PTR(err);
1278 }
1279
1280 if (!cursor)
1281 type = DRM_PLANE_TYPE_OVERLAY;
1282 else
1283 type = DRM_PLANE_TYPE_CURSOR;
1284
1285 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1286 &tegra_plane_funcs, formats,
1287 num_formats, linear_modifiers,
1288 type, NULL);
1289 if (err < 0) {
1290 kfree(plane);
1291 return ERR_PTR(err);
1292 }
1293
1294 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1295 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1296
1297 err = drm_plane_create_rotation_property(&plane->base,
1298 DRM_MODE_ROTATE_0,
1299 DRM_MODE_ROTATE_0 |
1300 DRM_MODE_ROTATE_180 |
1301 DRM_MODE_REFLECT_X |
1302 DRM_MODE_REFLECT_Y);
1303 if (err < 0)
1304 dev_err(dc->dev, "failed to create rotation property: %d\n",
1305 err);
1306
1307 return &plane->base;
1308}
1309
1310static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
1311 struct tegra_dc *dc)
1312{
1313 struct drm_plane *plane, *primary = NULL;
1314 unsigned int i, j;
1315
1316 for (i = 0; i < dc->soc->num_wgrps; i++) {
1317 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
1318
1319 if (wgrp->dc == dc->pipe) {
1320 for (j = 0; j < wgrp->num_windows; j++) {
1321 unsigned int index = wgrp->windows[j];
1322
1323 plane = tegra_shared_plane_create(drm, dc,
1324 wgrp->index,
1325 index);
1326 if (IS_ERR(plane))
1327 return plane;
1328
1329 /*
1330 * Choose the first shared plane owned by this
1331 * head as the primary plane.
1332 */
1333 if (!primary) {
1334 plane->type = DRM_PLANE_TYPE_PRIMARY;
1335 primary = plane;
1336 }
1337 }
1338 }
1339 }
1340
1341 return primary;
1342}
1343
1344static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
1345 struct tegra_dc *dc)
1346{
1347 struct drm_plane *planes[2], *primary;
1348 unsigned int planes_num;
1349 unsigned int i;
1350 int err;
1351
1352 primary = tegra_primary_plane_create(drm, dc);
1353 if (IS_ERR(primary))
1354 return primary;
1355
1356 if (dc->soc->supports_cursor)
1357 planes_num = 2;
1358 else
1359 planes_num = 1;
1360
1361 for (i = 0; i < planes_num; i++) {
1362 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i,
1363 false);
1364 if (IS_ERR(planes[i])) {
1365 err = PTR_ERR(planes[i]);
1366
1367 while (i--)
1368 planes[i]->funcs->destroy(planes[i]);
1369
1370 primary->funcs->destroy(primary);
1371 return ERR_PTR(err);
1372 }
1373 }
1374
1375 return primary;
1376}
1377
1378static void tegra_dc_destroy(struct drm_crtc *crtc)
1379{
1380 drm_crtc_cleanup(crtc);
1381}
1382
1383static void tegra_crtc_reset(struct drm_crtc *crtc)
1384{
1385 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
1386
1387 if (crtc->state)
1388 tegra_crtc_atomic_destroy_state(crtc, crtc->state);
1389
1390 __drm_atomic_helper_crtc_reset(crtc, &state->base);
1391}
1392
1393static struct drm_crtc_state *
1394tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1395{
1396 struct tegra_dc_state *state = to_dc_state(crtc->state);
1397 struct tegra_dc_state *copy;
1398
1399 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
1400 if (!copy)
1401 return NULL;
1402
1403 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base);
1404 copy->clk = state->clk;
1405 copy->pclk = state->pclk;
1406 copy->div = state->div;
1407 copy->planes = state->planes;
1408
1409 return ©->base;
1410}
1411
1412static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1413 struct drm_crtc_state *state)
1414{
1415 __drm_atomic_helper_crtc_destroy_state(state);
1416 kfree(state);
1417}
1418
1419#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1420
1421static const struct debugfs_reg32 tegra_dc_regs[] = {
1422 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
1423 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
1424 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
1425 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
1426 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
1427 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
1428 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
1429 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
1430 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
1431 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
1432 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
1433 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
1434 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
1435 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
1436 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
1437 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
1438 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
1439 DEBUGFS_REG32(DC_CMD_INT_STATUS),
1440 DEBUGFS_REG32(DC_CMD_INT_MASK),
1441 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
1442 DEBUGFS_REG32(DC_CMD_INT_TYPE),
1443 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
1444 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
1445 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
1446 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
1447 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
1448 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
1449 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
1450 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
1451 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
1452 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
1453 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
1454 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
1455 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
1456 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
1457 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
1458 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
1459 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
1460 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
1461 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
1462 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
1463 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
1464 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
1465 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
1466 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
1467 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
1468 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
1469 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
1470 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
1471 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
1472 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
1473 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
1474 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
1475 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
1476 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
1477 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
1478 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
1479 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
1480 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
1481 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
1482 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
1483 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
1484 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
1485 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
1486 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
1487 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
1488 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
1489 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
1490 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
1491 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
1492 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
1493 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
1494 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
1495 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
1496 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
1497 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
1498 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
1499 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
1500 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
1501 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
1502 DEBUGFS_REG32(DC_DISP_ACTIVE),
1503 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1504 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1505 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1506 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1507 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1508 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1509 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1510 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1511 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1512 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1513 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1514 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1515 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1516 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1517 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1518 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1519 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1520 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1521 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1522 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1523 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1524 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1525 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1526 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1527 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1528 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1529 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1530 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1531 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1532 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1533 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1534 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1535 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1536 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1537 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1538 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1539 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1540 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1541 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1542 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1543 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1544 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1545 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1546 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1547 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1548 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1549 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1550 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1551 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1552 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1553 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1554 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1555 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1556 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1557 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1558 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1559 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1560 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1561 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1562 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1563 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1564 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1565 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1566 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1567 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1568 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1569 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1570 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1571 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1572 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1573 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1574 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1575 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1576 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1577 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1578 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1579 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1580 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1581 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1582 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1583 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1584 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1585 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1586 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1587 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1588 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1589 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1590 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1591 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1592 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1593 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1594 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1595 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1596 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1597 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1598 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1599 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1600 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1601 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1602 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1603 DEBUGFS_REG32(DC_WIN_POSITION),
1604 DEBUGFS_REG32(DC_WIN_SIZE),
1605 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1606 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1607 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1608 DEBUGFS_REG32(DC_WIN_DDA_INC),
1609 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1610 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1611 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1612 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1613 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1614 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1615 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1616 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1617 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1618 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1619 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1620 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1621 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1622 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1623 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1624 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1625 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1626 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1627 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1628 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1629 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1630 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1631 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1632 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1633 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1634};
1635
1636static int tegra_dc_show_regs(struct seq_file *s, void *data)
1637{
1638 struct drm_info_node *node = s->private;
1639 struct tegra_dc *dc = node->info_ent->data;
1640 unsigned int i;
1641 int err = 0;
1642
1643 drm_modeset_lock(&dc->base.mutex, NULL);
1644
1645 if (!dc->base.state->active) {
1646 err = -EBUSY;
1647 goto unlock;
1648 }
1649
1650 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1651 unsigned int offset = tegra_dc_regs[i].offset;
1652
1653 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1654 offset, tegra_dc_readl(dc, offset));
1655 }
1656
1657unlock:
1658 drm_modeset_unlock(&dc->base.mutex);
1659 return err;
1660}
1661
1662static int tegra_dc_show_crc(struct seq_file *s, void *data)
1663{
1664 struct drm_info_node *node = s->private;
1665 struct tegra_dc *dc = node->info_ent->data;
1666 int err = 0;
1667 u32 value;
1668
1669 drm_modeset_lock(&dc->base.mutex, NULL);
1670
1671 if (!dc->base.state->active) {
1672 err = -EBUSY;
1673 goto unlock;
1674 }
1675
1676 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1677 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1678 tegra_dc_commit(dc);
1679
1680 drm_crtc_wait_one_vblank(&dc->base);
1681 drm_crtc_wait_one_vblank(&dc->base);
1682
1683 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1684 seq_printf(s, "%08x\n", value);
1685
1686 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1687
1688unlock:
1689 drm_modeset_unlock(&dc->base.mutex);
1690 return err;
1691}
1692
1693static int tegra_dc_show_stats(struct seq_file *s, void *data)
1694{
1695 struct drm_info_node *node = s->private;
1696 struct tegra_dc *dc = node->info_ent->data;
1697
1698 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1699 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1700 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1701 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1702
1703 seq_printf(s, "frames total: %lu\n", dc->stats.frames_total);
1704 seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total);
1705 seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total);
1706 seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total);
1707
1708 return 0;
1709}
1710
1711static struct drm_info_list debugfs_files[] = {
1712 { "regs", tegra_dc_show_regs, 0, NULL },
1713 { "crc", tegra_dc_show_crc, 0, NULL },
1714 { "stats", tegra_dc_show_stats, 0, NULL },
1715};
1716
1717static int tegra_dc_late_register(struct drm_crtc *crtc)
1718{
1719 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1720 struct drm_minor *minor = crtc->dev->primary;
1721 struct dentry *root;
1722 struct tegra_dc *dc = to_tegra_dc(crtc);
1723
1724#ifdef CONFIG_DEBUG_FS
1725 root = crtc->debugfs_entry;
1726#else
1727 root = NULL;
1728#endif
1729
1730 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1731 GFP_KERNEL);
1732 if (!dc->debugfs_files)
1733 return -ENOMEM;
1734
1735 for (i = 0; i < count; i++)
1736 dc->debugfs_files[i].data = dc;
1737
1738 drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1739
1740 return 0;
1741}
1742
1743static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1744{
1745 unsigned int count = ARRAY_SIZE(debugfs_files);
1746 struct drm_minor *minor = crtc->dev->primary;
1747 struct tegra_dc *dc = to_tegra_dc(crtc);
1748
1749 drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1750 kfree(dc->debugfs_files);
1751 dc->debugfs_files = NULL;
1752}
1753
1754static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1755{
1756 struct tegra_dc *dc = to_tegra_dc(crtc);
1757
1758 /* XXX vblank syncpoints don't work with nvdisplay yet */
1759 if (dc->syncpt && !dc->soc->has_nvdisplay)
1760 return host1x_syncpt_read(dc->syncpt);
1761
1762 /* fallback to software emulated VBLANK counter */
1763 return (u32)drm_crtc_vblank_count(&dc->base);
1764}
1765
1766static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1767{
1768 struct tegra_dc *dc = to_tegra_dc(crtc);
1769 u32 value;
1770
1771 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1772 value |= VBLANK_INT;
1773 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1774
1775 return 0;
1776}
1777
1778static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1779{
1780 struct tegra_dc *dc = to_tegra_dc(crtc);
1781 u32 value;
1782
1783 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1784 value &= ~VBLANK_INT;
1785 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1786}
1787
1788static const struct drm_crtc_funcs tegra_crtc_funcs = {
1789 .page_flip = drm_atomic_helper_page_flip,
1790 .set_config = drm_atomic_helper_set_config,
1791 .destroy = tegra_dc_destroy,
1792 .reset = tegra_crtc_reset,
1793 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1794 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1795 .late_register = tegra_dc_late_register,
1796 .early_unregister = tegra_dc_early_unregister,
1797 .get_vblank_counter = tegra_dc_get_vblank_counter,
1798 .enable_vblank = tegra_dc_enable_vblank,
1799 .disable_vblank = tegra_dc_disable_vblank,
1800};
1801
1802static int tegra_dc_set_timings(struct tegra_dc *dc,
1803 struct drm_display_mode *mode)
1804{
1805 unsigned int h_ref_to_sync = 1;
1806 unsigned int v_ref_to_sync = 1;
1807 unsigned long value;
1808
1809 if (!dc->soc->has_nvdisplay) {
1810 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1811
1812 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1813 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1814 }
1815
1816 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1817 ((mode->hsync_end - mode->hsync_start) << 0);
1818 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1819
1820 value = ((mode->vtotal - mode->vsync_end) << 16) |
1821 ((mode->htotal - mode->hsync_end) << 0);
1822 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1823
1824 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1825 ((mode->hsync_start - mode->hdisplay) << 0);
1826 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1827
1828 value = (mode->vdisplay << 16) | mode->hdisplay;
1829 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1830
1831 return 0;
1832}
1833
1834/**
1835 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1836 * state
1837 * @dc: display controller
1838 * @crtc_state: CRTC atomic state
1839 * @clk: parent clock for display controller
1840 * @pclk: pixel clock
1841 * @div: shift clock divider
1842 *
1843 * Returns:
1844 * 0 on success or a negative error-code on failure.
1845 */
1846int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1847 struct drm_crtc_state *crtc_state,
1848 struct clk *clk, unsigned long pclk,
1849 unsigned int div)
1850{
1851 struct tegra_dc_state *state = to_dc_state(crtc_state);
1852
1853 if (!clk_has_parent(dc->clk, clk))
1854 return -EINVAL;
1855
1856 state->clk = clk;
1857 state->pclk = pclk;
1858 state->div = div;
1859
1860 return 0;
1861}
1862
1863static void tegra_dc_update_voltage_state(struct tegra_dc *dc,
1864 struct tegra_dc_state *state)
1865{
1866 unsigned long rate, pstate;
1867 struct dev_pm_opp *opp;
1868 int err;
1869
1870 if (!dc->has_opp_table)
1871 return;
1872
1873 /* calculate actual pixel clock rate which depends on internal divider */
1874 rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2);
1875
1876 /* find suitable OPP for the rate */
1877 opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate);
1878
1879 /*
1880 * Very high resolution modes may results in a clock rate that is
1881 * above the characterized maximum. In this case it's okay to fall
1882 * back to the characterized maximum.
1883 */
1884 if (opp == ERR_PTR(-ERANGE))
1885 opp = dev_pm_opp_find_freq_floor(dc->dev, &rate);
1886
1887 if (IS_ERR(opp)) {
1888 dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n",
1889 rate, opp);
1890 return;
1891 }
1892
1893 pstate = dev_pm_opp_get_required_pstate(opp, 0);
1894 dev_pm_opp_put(opp);
1895
1896 /*
1897 * The minimum core voltage depends on the pixel clock rate (which
1898 * depends on internal clock divider of the CRTC) and not on the
1899 * rate of the display controller clock. This is why we're not using
1900 * dev_pm_opp_set_rate() API and instead controlling the power domain
1901 * directly.
1902 */
1903 err = dev_pm_genpd_set_performance_state(dc->dev, pstate);
1904 if (err)
1905 dev_err(dc->dev, "failed to set power domain state to %lu: %d\n",
1906 pstate, err);
1907}
1908
1909static void tegra_dc_set_clock_rate(struct tegra_dc *dc,
1910 struct tegra_dc_state *state)
1911{
1912 int err;
1913
1914 err = clk_set_parent(dc->clk, state->clk);
1915 if (err < 0)
1916 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1917
1918 /*
1919 * Outputs may not want to change the parent clock rate. This is only
1920 * relevant to Tegra20 where only a single display PLL is available.
1921 * Since that PLL would typically be used for HDMI, an internal LVDS
1922 * panel would need to be driven by some other clock such as PLL_P
1923 * which is shared with other peripherals. Changing the clock rate
1924 * should therefore be avoided.
1925 */
1926 if (state->pclk > 0) {
1927 err = clk_set_rate(state->clk, state->pclk);
1928 if (err < 0)
1929 dev_err(dc->dev,
1930 "failed to set clock rate to %lu Hz\n",
1931 state->pclk);
1932
1933 err = clk_set_rate(dc->clk, state->pclk);
1934 if (err < 0)
1935 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1936 dc->clk, state->pclk, err);
1937 }
1938
1939 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1940 state->div);
1941 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1942
1943 tegra_dc_update_voltage_state(dc, state);
1944}
1945
1946static void tegra_dc_stop(struct tegra_dc *dc)
1947{
1948 u32 value;
1949
1950 /* stop the display controller */
1951 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1952 value &= ~DISP_CTRL_MODE_MASK;
1953 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1954
1955 tegra_dc_commit(dc);
1956}
1957
1958static bool tegra_dc_idle(struct tegra_dc *dc)
1959{
1960 u32 value;
1961
1962 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1963
1964 return (value & DISP_CTRL_MODE_MASK) == 0;
1965}
1966
1967static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1968{
1969 timeout = jiffies + msecs_to_jiffies(timeout);
1970
1971 while (time_before(jiffies, timeout)) {
1972 if (tegra_dc_idle(dc))
1973 return 0;
1974
1975 usleep_range(1000, 2000);
1976 }
1977
1978 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1979 return -ETIMEDOUT;
1980}
1981
1982static void
1983tegra_crtc_update_memory_bandwidth(struct drm_crtc *crtc,
1984 struct drm_atomic_state *state,
1985 bool prepare_bandwidth_transition)
1986{
1987 const struct tegra_plane_state *old_tegra_state, *new_tegra_state;
1988 u32 i, new_avg_bw, old_avg_bw, new_peak_bw, old_peak_bw;
1989 const struct drm_plane_state *old_plane_state;
1990 const struct drm_crtc_state *old_crtc_state;
1991 struct tegra_dc_window window, old_window;
1992 struct tegra_dc *dc = to_tegra_dc(crtc);
1993 struct tegra_plane *tegra;
1994 struct drm_plane *plane;
1995
1996 if (dc->soc->has_nvdisplay)
1997 return;
1998
1999 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
2000
2001 if (!crtc->state->active) {
2002 if (!old_crtc_state->active)
2003 return;
2004
2005 /*
2006 * When CRTC is disabled on DPMS, the state of attached planes
2007 * is kept unchanged. Hence we need to enforce removal of the
2008 * bandwidths from the ICC paths.
2009 */
2010 drm_atomic_crtc_for_each_plane(plane, crtc) {
2011 tegra = to_tegra_plane(plane);
2012
2013 icc_set_bw(tegra->icc_mem, 0, 0);
2014 icc_set_bw(tegra->icc_mem_vfilter, 0, 0);
2015 }
2016
2017 return;
2018 }
2019
2020 for_each_old_plane_in_state(old_crtc_state->state, plane,
2021 old_plane_state, i) {
2022 old_tegra_state = to_const_tegra_plane_state(old_plane_state);
2023 new_tegra_state = to_const_tegra_plane_state(plane->state);
2024 tegra = to_tegra_plane(plane);
2025
2026 /*
2027 * We're iterating over the global atomic state and it contains
2028 * planes from another CRTC, hence we need to filter out the
2029 * planes unrelated to this CRTC.
2030 */
2031 if (tegra->dc != dc)
2032 continue;
2033
2034 new_avg_bw = new_tegra_state->avg_memory_bandwidth;
2035 old_avg_bw = old_tegra_state->avg_memory_bandwidth;
2036
2037 new_peak_bw = new_tegra_state->total_peak_memory_bandwidth;
2038 old_peak_bw = old_tegra_state->total_peak_memory_bandwidth;
2039
2040 /*
2041 * See the comment related to !crtc->state->active above,
2042 * which explains why bandwidths need to be updated when
2043 * CRTC is turning ON.
2044 */
2045 if (new_avg_bw == old_avg_bw && new_peak_bw == old_peak_bw &&
2046 old_crtc_state->active)
2047 continue;
2048
2049 window.src.h = drm_rect_height(&plane->state->src) >> 16;
2050 window.dst.h = drm_rect_height(&plane->state->dst);
2051
2052 old_window.src.h = drm_rect_height(&old_plane_state->src) >> 16;
2053 old_window.dst.h = drm_rect_height(&old_plane_state->dst);
2054
2055 /*
2056 * During the preparation phase (atomic_begin), the memory
2057 * freq should go high before the DC changes are committed
2058 * if bandwidth requirement goes up, otherwise memory freq
2059 * should to stay high if BW requirement goes down. The
2060 * opposite applies to the completion phase (post_commit).
2061 */
2062 if (prepare_bandwidth_transition) {
2063 new_avg_bw = max(old_avg_bw, new_avg_bw);
2064 new_peak_bw = max(old_peak_bw, new_peak_bw);
2065
2066 if (tegra_plane_use_vertical_filtering(tegra, &old_window))
2067 window = old_window;
2068 }
2069
2070 icc_set_bw(tegra->icc_mem, new_avg_bw, new_peak_bw);
2071
2072 if (tegra_plane_use_vertical_filtering(tegra, &window))
2073 icc_set_bw(tegra->icc_mem_vfilter, new_avg_bw, new_peak_bw);
2074 else
2075 icc_set_bw(tegra->icc_mem_vfilter, 0, 0);
2076 }
2077}
2078
2079static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
2080 struct drm_atomic_state *state)
2081{
2082 struct tegra_dc *dc = to_tegra_dc(crtc);
2083 u32 value;
2084 int err;
2085
2086 if (!tegra_dc_idle(dc)) {
2087 tegra_dc_stop(dc);
2088
2089 /*
2090 * Ignore the return value, there isn't anything useful to do
2091 * in case this fails.
2092 */
2093 tegra_dc_wait_idle(dc, 100);
2094 }
2095
2096 /*
2097 * This should really be part of the RGB encoder driver, but clearing
2098 * these bits has the side-effect of stopping the display controller.
2099 * When that happens no VBLANK interrupts will be raised. At the same
2100 * time the encoder is disabled before the display controller, so the
2101 * above code is always going to timeout waiting for the controller
2102 * to go idle.
2103 *
2104 * Given the close coupling between the RGB encoder and the display
2105 * controller doing it here is still kind of okay. None of the other
2106 * encoder drivers require these bits to be cleared.
2107 *
2108 * XXX: Perhaps given that the display controller is switched off at
2109 * this point anyway maybe clearing these bits isn't even useful for
2110 * the RGB encoder?
2111 */
2112 if (dc->rgb) {
2113 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
2114 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
2115 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
2116 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
2117 }
2118
2119 tegra_dc_stats_reset(&dc->stats);
2120 drm_crtc_vblank_off(crtc);
2121
2122 spin_lock_irq(&crtc->dev->event_lock);
2123
2124 if (crtc->state->event) {
2125 drm_crtc_send_vblank_event(crtc, crtc->state->event);
2126 crtc->state->event = NULL;
2127 }
2128
2129 spin_unlock_irq(&crtc->dev->event_lock);
2130
2131 err = host1x_client_suspend(&dc->client);
2132 if (err < 0)
2133 dev_err(dc->dev, "failed to suspend: %d\n", err);
2134
2135 if (dc->has_opp_table) {
2136 err = dev_pm_genpd_set_performance_state(dc->dev, 0);
2137 if (err)
2138 dev_err(dc->dev,
2139 "failed to clear power domain state: %d\n", err);
2140 }
2141}
2142
2143static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
2144 struct drm_atomic_state *state)
2145{
2146 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2147 struct tegra_dc_state *crtc_state = to_dc_state(crtc->state);
2148 struct tegra_dc *dc = to_tegra_dc(crtc);
2149 u32 value;
2150 int err;
2151
2152 /* apply PLL changes */
2153 tegra_dc_set_clock_rate(dc, crtc_state);
2154
2155 err = host1x_client_resume(&dc->client);
2156 if (err < 0) {
2157 dev_err(dc->dev, "failed to resume: %d\n", err);
2158 return;
2159 }
2160
2161 /* initialize display controller */
2162 if (dc->syncpt) {
2163 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
2164
2165 if (dc->soc->has_nvdisplay)
2166 enable = 1 << 31;
2167 else
2168 enable = 1 << 8;
2169
2170 value = SYNCPT_CNTRL_NO_STALL;
2171 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2172
2173 value = enable | syncpt;
2174 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
2175 }
2176
2177 if (dc->soc->has_nvdisplay) {
2178 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
2179 DSC_OBUF_UF_INT;
2180 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
2181
2182 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
2183 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
2184 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
2185 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
2186 VBLANK_INT | FRAME_END_INT;
2187 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
2188
2189 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
2190 FRAME_END_INT;
2191 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
2192
2193 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
2194 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
2195
2196 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
2197 } else {
2198 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2199 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2200 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
2201
2202 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2203 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2204 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
2205
2206 /* initialize timer */
2207 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
2208 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
2209 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
2210
2211 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
2212 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
2213 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
2214
2215 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2216 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2217 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
2218
2219 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
2220 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
2221 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
2222 }
2223
2224 if (dc->soc->supports_background_color)
2225 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
2226 else
2227 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
2228
2229 /* apply pixel clock changes */
2230 if (!dc->soc->has_nvdisplay) {
2231 value = SHIFT_CLK_DIVIDER(crtc_state->div) | PIXEL_CLK_DIVIDER_PCD1;
2232 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
2233 }
2234
2235 /* program display mode */
2236 tegra_dc_set_timings(dc, mode);
2237
2238 /* interlacing isn't supported yet, so disable it */
2239 if (dc->soc->supports_interlacing) {
2240 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
2241 value &= ~INTERLACE_ENABLE;
2242 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
2243 }
2244
2245 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
2246 value &= ~DISP_CTRL_MODE_MASK;
2247 value |= DISP_CTRL_MODE_C_DISPLAY;
2248 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
2249
2250 if (!dc->soc->has_nvdisplay) {
2251 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
2252 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
2253 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
2254 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
2255 }
2256
2257 /* enable underflow reporting and display red for missing pixels */
2258 if (dc->soc->has_nvdisplay) {
2259 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
2260 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
2261 }
2262
2263 if (dc->rgb) {
2264 /* XXX: parameterize? */
2265 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
2266 tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
2267 }
2268
2269 tegra_dc_commit(dc);
2270
2271 drm_crtc_vblank_on(crtc);
2272}
2273
2274static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
2275 struct drm_atomic_state *state)
2276{
2277 unsigned long flags;
2278
2279 tegra_crtc_update_memory_bandwidth(crtc, state, true);
2280
2281 if (crtc->state->event) {
2282 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2283
2284 if (drm_crtc_vblank_get(crtc) != 0)
2285 drm_crtc_send_vblank_event(crtc, crtc->state->event);
2286 else
2287 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
2288
2289 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2290
2291 crtc->state->event = NULL;
2292 }
2293}
2294
2295static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
2296 struct drm_atomic_state *state)
2297{
2298 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
2299 crtc);
2300 struct tegra_dc_state *dc_state = to_dc_state(crtc_state);
2301 struct tegra_dc *dc = to_tegra_dc(crtc);
2302 u32 value;
2303
2304 value = dc_state->planes << 8 | GENERAL_UPDATE;
2305 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
2306 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2307
2308 value = dc_state->planes | GENERAL_ACT_REQ;
2309 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
2310 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2311}
2312
2313static bool tegra_plane_is_cursor(const struct drm_plane_state *state)
2314{
2315 const struct tegra_dc_soc_info *soc = to_tegra_dc(state->crtc)->soc;
2316 const struct drm_format_info *fmt = state->fb->format;
2317 unsigned int src_w = drm_rect_width(&state->src) >> 16;
2318 unsigned int dst_w = drm_rect_width(&state->dst);
2319
2320 if (state->plane->type != DRM_PLANE_TYPE_CURSOR)
2321 return false;
2322
2323 if (soc->supports_cursor)
2324 return true;
2325
2326 if (src_w != dst_w || fmt->num_planes != 1 || src_w * fmt->cpp[0] > 256)
2327 return false;
2328
2329 return true;
2330}
2331
2332static unsigned long
2333tegra_plane_overlap_mask(struct drm_crtc_state *state,
2334 const struct drm_plane_state *plane_state)
2335{
2336 const struct drm_plane_state *other_state;
2337 const struct tegra_plane *tegra;
2338 unsigned long overlap_mask = 0;
2339 struct drm_plane *plane;
2340 struct drm_rect rect;
2341
2342 if (!plane_state->visible || !plane_state->fb)
2343 return 0;
2344
2345 /*
2346 * Data-prefetch FIFO will easily help to overcome temporal memory
2347 * pressure if other plane overlaps with the cursor plane.
2348 */
2349 if (tegra_plane_is_cursor(plane_state))
2350 return 0;
2351
2352 drm_atomic_crtc_state_for_each_plane_state(plane, other_state, state) {
2353 rect = plane_state->dst;
2354
2355 tegra = to_tegra_plane(other_state->plane);
2356
2357 if (!other_state->visible || !other_state->fb)
2358 continue;
2359
2360 /*
2361 * Ignore cursor plane overlaps because it's not practical to
2362 * assume that it contributes to the bandwidth in overlapping
2363 * area if window width is small.
2364 */
2365 if (tegra_plane_is_cursor(other_state))
2366 continue;
2367
2368 if (drm_rect_intersect(&rect, &other_state->dst))
2369 overlap_mask |= BIT(tegra->index);
2370 }
2371
2372 return overlap_mask;
2373}
2374
2375static int tegra_crtc_calculate_memory_bandwidth(struct drm_crtc *crtc,
2376 struct drm_atomic_state *state)
2377{
2378 ulong overlap_mask[TEGRA_DC_LEGACY_PLANES_NUM] = {}, mask;
2379 u32 plane_peak_bw[TEGRA_DC_LEGACY_PLANES_NUM] = {};
2380 bool all_planes_overlap_simultaneously = true;
2381 const struct tegra_plane_state *tegra_state;
2382 const struct drm_plane_state *plane_state;
2383 struct tegra_dc *dc = to_tegra_dc(crtc);
2384 const struct drm_crtc_state *old_state;
2385 struct drm_crtc_state *new_state;
2386 struct tegra_plane *tegra;
2387 struct drm_plane *plane;
2388
2389 /*
2390 * The nv-display uses shared planes. The algorithm below assumes
2391 * maximum 3 planes per-CRTC, this assumption isn't applicable to
2392 * the nv-display. Note that T124 support has additional windows,
2393 * but currently they aren't supported by the driver.
2394 */
2395 if (dc->soc->has_nvdisplay)
2396 return 0;
2397
2398 new_state = drm_atomic_get_new_crtc_state(state, crtc);
2399 old_state = drm_atomic_get_old_crtc_state(state, crtc);
2400
2401 /*
2402 * For overlapping planes pixel's data is fetched for each plane at
2403 * the same time, hence bandwidths are accumulated in this case.
2404 * This needs to be taken into account for calculating total bandwidth
2405 * consumed by all planes.
2406 *
2407 * Here we get the overlapping state of each plane, which is a
2408 * bitmask of plane indices telling with what planes there is an
2409 * overlap. Note that bitmask[plane] includes BIT(plane) in order
2410 * to make further code nicer and simpler.
2411 */
2412 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {
2413 tegra_state = to_const_tegra_plane_state(plane_state);
2414 tegra = to_tegra_plane(plane);
2415
2416 if (WARN_ON_ONCE(tegra->index >= TEGRA_DC_LEGACY_PLANES_NUM))
2417 return -EINVAL;
2418
2419 plane_peak_bw[tegra->index] = tegra_state->peak_memory_bandwidth;
2420 mask = tegra_plane_overlap_mask(new_state, plane_state);
2421 overlap_mask[tegra->index] = mask;
2422
2423 if (hweight_long(mask) != 3)
2424 all_planes_overlap_simultaneously = false;
2425 }
2426
2427 /*
2428 * Then we calculate maximum bandwidth of each plane state.
2429 * The bandwidth includes the plane BW + BW of the "simultaneously"
2430 * overlapping planes, where "simultaneously" means areas where DC
2431 * fetches from the planes simultaneously during of scan-out process.
2432 *
2433 * For example, if plane A overlaps with planes B and C, but B and C
2434 * don't overlap, then the peak bandwidth will be either in area where
2435 * A-and-B or A-and-C planes overlap.
2436 *
2437 * The plane_peak_bw[] contains peak memory bandwidth values of
2438 * each plane, this information is needed by interconnect provider
2439 * in order to set up latency allowance based on the peak BW, see
2440 * tegra_crtc_update_memory_bandwidth().
2441 */
2442 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {
2443 u32 i, old_peak_bw, new_peak_bw, overlap_bw = 0;
2444
2445 /*
2446 * Note that plane's atomic check doesn't touch the
2447 * total_peak_memory_bandwidth of enabled plane, hence the
2448 * current state contains the old bandwidth state from the
2449 * previous CRTC commit.
2450 */
2451 tegra_state = to_const_tegra_plane_state(plane_state);
2452 tegra = to_tegra_plane(plane);
2453
2454 for_each_set_bit(i, &overlap_mask[tegra->index], 3) {
2455 if (i == tegra->index)
2456 continue;
2457
2458 if (all_planes_overlap_simultaneously)
2459 overlap_bw += plane_peak_bw[i];
2460 else
2461 overlap_bw = max(overlap_bw, plane_peak_bw[i]);
2462 }
2463
2464 new_peak_bw = plane_peak_bw[tegra->index] + overlap_bw;
2465 old_peak_bw = tegra_state->total_peak_memory_bandwidth;
2466
2467 /*
2468 * If plane's peak bandwidth changed (for example plane isn't
2469 * overlapped anymore) and plane isn't in the atomic state,
2470 * then add plane to the state in order to have the bandwidth
2471 * updated.
2472 */
2473 if (old_peak_bw != new_peak_bw) {
2474 struct tegra_plane_state *new_tegra_state;
2475 struct drm_plane_state *new_plane_state;
2476
2477 new_plane_state = drm_atomic_get_plane_state(state, plane);
2478 if (IS_ERR(new_plane_state))
2479 return PTR_ERR(new_plane_state);
2480
2481 new_tegra_state = to_tegra_plane_state(new_plane_state);
2482 new_tegra_state->total_peak_memory_bandwidth = new_peak_bw;
2483 }
2484 }
2485
2486 return 0;
2487}
2488
2489static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
2490 struct drm_atomic_state *state)
2491{
2492 int err;
2493
2494 err = tegra_crtc_calculate_memory_bandwidth(crtc, state);
2495 if (err)
2496 return err;
2497
2498 return 0;
2499}
2500
2501void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc,
2502 struct drm_atomic_state *state)
2503{
2504 /*
2505 * Display bandwidth is allowed to go down only once hardware state
2506 * is known to be armed, i.e. state was committed and VBLANK event
2507 * received.
2508 */
2509 tegra_crtc_update_memory_bandwidth(crtc, state, false);
2510}
2511
2512static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
2513 .atomic_check = tegra_crtc_atomic_check,
2514 .atomic_begin = tegra_crtc_atomic_begin,
2515 .atomic_flush = tegra_crtc_atomic_flush,
2516 .atomic_enable = tegra_crtc_atomic_enable,
2517 .atomic_disable = tegra_crtc_atomic_disable,
2518};
2519
2520static irqreturn_t tegra_dc_irq(int irq, void *data)
2521{
2522 struct tegra_dc *dc = data;
2523 unsigned long status;
2524
2525 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2526 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2527
2528 if (status & FRAME_END_INT) {
2529 /*
2530 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
2531 */
2532 dc->stats.frames_total++;
2533 dc->stats.frames++;
2534 }
2535
2536 if (status & VBLANK_INT) {
2537 /*
2538 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
2539 */
2540 drm_crtc_handle_vblank(&dc->base);
2541 dc->stats.vblank_total++;
2542 dc->stats.vblank++;
2543 }
2544
2545 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
2546 /*
2547 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
2548 */
2549 dc->stats.underflow_total++;
2550 dc->stats.underflow++;
2551 }
2552
2553 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
2554 /*
2555 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
2556 */
2557 dc->stats.overflow_total++;
2558 dc->stats.overflow++;
2559 }
2560
2561 if (status & HEAD_UF_INT) {
2562 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
2563 dc->stats.underflow_total++;
2564 dc->stats.underflow++;
2565 }
2566
2567 return IRQ_HANDLED;
2568}
2569
2570static bool tegra_dc_has_window_groups(struct tegra_dc *dc)
2571{
2572 unsigned int i;
2573
2574 if (!dc->soc->wgrps)
2575 return true;
2576
2577 for (i = 0; i < dc->soc->num_wgrps; i++) {
2578 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
2579
2580 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0)
2581 return true;
2582 }
2583
2584 return false;
2585}
2586
2587static int tegra_dc_early_init(struct host1x_client *client)
2588{
2589 struct drm_device *drm = dev_get_drvdata(client->host);
2590 struct tegra_drm *tegra = drm->dev_private;
2591
2592 tegra->num_crtcs++;
2593
2594 return 0;
2595}
2596
2597static int tegra_dc_init(struct host1x_client *client)
2598{
2599 struct drm_device *drm = dev_get_drvdata(client->host);
2600 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
2601 struct tegra_dc *dc = host1x_client_to_dc(client);
2602 struct tegra_drm *tegra = drm->dev_private;
2603 struct drm_plane *primary = NULL;
2604 struct drm_plane *cursor = NULL;
2605 int err;
2606
2607 /*
2608 * DC has been reset by now, so VBLANK syncpoint can be released
2609 * for general use.
2610 */
2611 host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe);
2612
2613 /*
2614 * XXX do not register DCs with no window groups because we cannot
2615 * assign a primary plane to them, which in turn will cause KMS to
2616 * crash.
2617 */
2618 if (!tegra_dc_has_window_groups(dc))
2619 return 0;
2620
2621 /*
2622 * Set the display hub as the host1x client parent for the display
2623 * controller. This is needed for the runtime reference counting that
2624 * ensures the display hub is always powered when any of the display
2625 * controllers are.
2626 */
2627 if (dc->soc->has_nvdisplay)
2628 client->parent = &tegra->hub->client;
2629
2630 dc->syncpt = host1x_syncpt_request(client, flags);
2631 if (!dc->syncpt)
2632 dev_warn(dc->dev, "failed to allocate syncpoint\n");
2633
2634 err = host1x_client_iommu_attach(client);
2635 if (err < 0 && err != -ENODEV) {
2636 dev_err(client->dev, "failed to attach to domain: %d\n", err);
2637 return err;
2638 }
2639
2640 if (dc->soc->wgrps)
2641 primary = tegra_dc_add_shared_planes(drm, dc);
2642 else
2643 primary = tegra_dc_add_planes(drm, dc);
2644
2645 if (IS_ERR(primary)) {
2646 err = PTR_ERR(primary);
2647 goto cleanup;
2648 }
2649
2650 if (dc->soc->supports_cursor) {
2651 cursor = tegra_dc_cursor_plane_create(drm, dc);
2652 if (IS_ERR(cursor)) {
2653 err = PTR_ERR(cursor);
2654 goto cleanup;
2655 }
2656 } else {
2657 /* dedicate one overlay to mouse cursor */
2658 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true);
2659 if (IS_ERR(cursor)) {
2660 err = PTR_ERR(cursor);
2661 goto cleanup;
2662 }
2663 }
2664
2665 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
2666 &tegra_crtc_funcs, NULL);
2667 if (err < 0)
2668 goto cleanup;
2669
2670 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
2671
2672 /*
2673 * Keep track of the minimum pitch alignment across all display
2674 * controllers.
2675 */
2676 if (dc->soc->pitch_align > tegra->pitch_align)
2677 tegra->pitch_align = dc->soc->pitch_align;
2678
2679 /* track maximum resolution */
2680 if (dc->soc->has_nvdisplay)
2681 drm->mode_config.max_width = drm->mode_config.max_height = 16384;
2682 else
2683 drm->mode_config.max_width = drm->mode_config.max_height = 4096;
2684
2685 err = tegra_dc_rgb_init(drm, dc);
2686 if (err < 0 && err != -ENODEV) {
2687 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
2688 goto cleanup;
2689 }
2690
2691 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
2692 dev_name(dc->dev), dc);
2693 if (err < 0) {
2694 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
2695 err);
2696 goto cleanup;
2697 }
2698
2699 /*
2700 * Inherit the DMA parameters (such as maximum segment size) from the
2701 * parent host1x device.
2702 */
2703 client->dev->dma_parms = client->host->dma_parms;
2704
2705 return 0;
2706
2707cleanup:
2708 if (!IS_ERR_OR_NULL(cursor))
2709 drm_plane_cleanup(cursor);
2710
2711 if (!IS_ERR(primary))
2712 drm_plane_cleanup(primary);
2713
2714 host1x_client_iommu_detach(client);
2715 host1x_syncpt_put(dc->syncpt);
2716
2717 return err;
2718}
2719
2720static int tegra_dc_exit(struct host1x_client *client)
2721{
2722 struct tegra_dc *dc = host1x_client_to_dc(client);
2723 int err;
2724
2725 if (!tegra_dc_has_window_groups(dc))
2726 return 0;
2727
2728 /* avoid a dangling pointer just in case this disappears */
2729 client->dev->dma_parms = NULL;
2730
2731 devm_free_irq(dc->dev, dc->irq, dc);
2732
2733 err = tegra_dc_rgb_exit(dc);
2734 if (err) {
2735 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
2736 return err;
2737 }
2738
2739 host1x_client_iommu_detach(client);
2740 host1x_syncpt_put(dc->syncpt);
2741
2742 return 0;
2743}
2744
2745static int tegra_dc_late_exit(struct host1x_client *client)
2746{
2747 struct drm_device *drm = dev_get_drvdata(client->host);
2748 struct tegra_drm *tegra = drm->dev_private;
2749
2750 tegra->num_crtcs--;
2751
2752 return 0;
2753}
2754
2755static int tegra_dc_runtime_suspend(struct host1x_client *client)
2756{
2757 struct tegra_dc *dc = host1x_client_to_dc(client);
2758 struct device *dev = client->dev;
2759 int err;
2760
2761 err = reset_control_assert(dc->rst);
2762 if (err < 0) {
2763 dev_err(dev, "failed to assert reset: %d\n", err);
2764 return err;
2765 }
2766
2767 if (dc->soc->has_powergate)
2768 tegra_powergate_power_off(dc->powergate);
2769
2770 clk_disable_unprepare(dc->clk);
2771 pm_runtime_put_sync(dev);
2772
2773 return 0;
2774}
2775
2776static int tegra_dc_runtime_resume(struct host1x_client *client)
2777{
2778 struct tegra_dc *dc = host1x_client_to_dc(client);
2779 struct device *dev = client->dev;
2780 int err;
2781
2782 err = pm_runtime_resume_and_get(dev);
2783 if (err < 0) {
2784 dev_err(dev, "failed to get runtime PM: %d\n", err);
2785 return err;
2786 }
2787
2788 if (dc->soc->has_powergate) {
2789 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2790 dc->rst);
2791 if (err < 0) {
2792 dev_err(dev, "failed to power partition: %d\n", err);
2793 goto put_rpm;
2794 }
2795 } else {
2796 err = clk_prepare_enable(dc->clk);
2797 if (err < 0) {
2798 dev_err(dev, "failed to enable clock: %d\n", err);
2799 goto put_rpm;
2800 }
2801
2802 err = reset_control_deassert(dc->rst);
2803 if (err < 0) {
2804 dev_err(dev, "failed to deassert reset: %d\n", err);
2805 goto disable_clk;
2806 }
2807 }
2808
2809 return 0;
2810
2811disable_clk:
2812 clk_disable_unprepare(dc->clk);
2813put_rpm:
2814 pm_runtime_put_sync(dev);
2815 return err;
2816}
2817
2818static const struct host1x_client_ops dc_client_ops = {
2819 .early_init = tegra_dc_early_init,
2820 .init = tegra_dc_init,
2821 .exit = tegra_dc_exit,
2822 .late_exit = tegra_dc_late_exit,
2823 .suspend = tegra_dc_runtime_suspend,
2824 .resume = tegra_dc_runtime_resume,
2825};
2826
2827static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
2828 .supports_background_color = false,
2829 .supports_interlacing = false,
2830 .supports_cursor = false,
2831 .supports_block_linear = false,
2832 .supports_sector_layout = false,
2833 .has_legacy_blending = true,
2834 .pitch_align = 8,
2835 .has_powergate = false,
2836 .coupled_pm = true,
2837 .has_nvdisplay = false,
2838 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2839 .primary_formats = tegra20_primary_formats,
2840 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2841 .overlay_formats = tegra20_overlay_formats,
2842 .modifiers = tegra20_modifiers,
2843 .has_win_a_without_filters = true,
2844 .has_win_b_vfilter_mem_client = true,
2845 .has_win_c_without_vert_filter = true,
2846 .plane_tiled_memory_bandwidth_x2 = false,
2847 .has_pll_d2_out0 = false,
2848};
2849
2850static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
2851 .supports_background_color = false,
2852 .supports_interlacing = false,
2853 .supports_cursor = false,
2854 .supports_block_linear = false,
2855 .supports_sector_layout = false,
2856 .has_legacy_blending = true,
2857 .pitch_align = 8,
2858 .has_powergate = false,
2859 .coupled_pm = false,
2860 .has_nvdisplay = false,
2861 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
2862 .primary_formats = tegra20_primary_formats,
2863 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
2864 .overlay_formats = tegra20_overlay_formats,
2865 .modifiers = tegra20_modifiers,
2866 .has_win_a_without_filters = false,
2867 .has_win_b_vfilter_mem_client = true,
2868 .has_win_c_without_vert_filter = false,
2869 .plane_tiled_memory_bandwidth_x2 = true,
2870 .has_pll_d2_out0 = true,
2871};
2872
2873static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
2874 .supports_background_color = false,
2875 .supports_interlacing = false,
2876 .supports_cursor = false,
2877 .supports_block_linear = false,
2878 .supports_sector_layout = false,
2879 .has_legacy_blending = true,
2880 .pitch_align = 64,
2881 .has_powergate = true,
2882 .coupled_pm = false,
2883 .has_nvdisplay = false,
2884 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2885 .primary_formats = tegra114_primary_formats,
2886 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2887 .overlay_formats = tegra114_overlay_formats,
2888 .modifiers = tegra20_modifiers,
2889 .has_win_a_without_filters = false,
2890 .has_win_b_vfilter_mem_client = false,
2891 .has_win_c_without_vert_filter = false,
2892 .plane_tiled_memory_bandwidth_x2 = true,
2893 .has_pll_d2_out0 = true,
2894};
2895
2896static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
2897 .supports_background_color = true,
2898 .supports_interlacing = true,
2899 .supports_cursor = true,
2900 .supports_block_linear = true,
2901 .supports_sector_layout = false,
2902 .has_legacy_blending = false,
2903 .pitch_align = 64,
2904 .has_powergate = true,
2905 .coupled_pm = false,
2906 .has_nvdisplay = false,
2907 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
2908 .primary_formats = tegra124_primary_formats,
2909 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
2910 .overlay_formats = tegra124_overlay_formats,
2911 .modifiers = tegra124_modifiers,
2912 .has_win_a_without_filters = false,
2913 .has_win_b_vfilter_mem_client = false,
2914 .has_win_c_without_vert_filter = false,
2915 .plane_tiled_memory_bandwidth_x2 = false,
2916 .has_pll_d2_out0 = true,
2917};
2918
2919static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
2920 .supports_background_color = true,
2921 .supports_interlacing = true,
2922 .supports_cursor = true,
2923 .supports_block_linear = true,
2924 .supports_sector_layout = false,
2925 .has_legacy_blending = false,
2926 .pitch_align = 64,
2927 .has_powergate = true,
2928 .coupled_pm = false,
2929 .has_nvdisplay = false,
2930 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
2931 .primary_formats = tegra114_primary_formats,
2932 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
2933 .overlay_formats = tegra114_overlay_formats,
2934 .modifiers = tegra124_modifiers,
2935 .has_win_a_without_filters = false,
2936 .has_win_b_vfilter_mem_client = false,
2937 .has_win_c_without_vert_filter = false,
2938 .plane_tiled_memory_bandwidth_x2 = false,
2939 .has_pll_d2_out0 = true,
2940};
2941
2942static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
2943 {
2944 .index = 0,
2945 .dc = 0,
2946 .windows = (const unsigned int[]) { 0 },
2947 .num_windows = 1,
2948 }, {
2949 .index = 1,
2950 .dc = 1,
2951 .windows = (const unsigned int[]) { 1 },
2952 .num_windows = 1,
2953 }, {
2954 .index = 2,
2955 .dc = 1,
2956 .windows = (const unsigned int[]) { 2 },
2957 .num_windows = 1,
2958 }, {
2959 .index = 3,
2960 .dc = 2,
2961 .windows = (const unsigned int[]) { 3 },
2962 .num_windows = 1,
2963 }, {
2964 .index = 4,
2965 .dc = 2,
2966 .windows = (const unsigned int[]) { 4 },
2967 .num_windows = 1,
2968 }, {
2969 .index = 5,
2970 .dc = 2,
2971 .windows = (const unsigned int[]) { 5 },
2972 .num_windows = 1,
2973 },
2974};
2975
2976static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
2977 .supports_background_color = true,
2978 .supports_interlacing = true,
2979 .supports_cursor = true,
2980 .supports_block_linear = true,
2981 .supports_sector_layout = false,
2982 .has_legacy_blending = false,
2983 .pitch_align = 64,
2984 .has_powergate = false,
2985 .coupled_pm = false,
2986 .has_nvdisplay = true,
2987 .wgrps = tegra186_dc_wgrps,
2988 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
2989 .plane_tiled_memory_bandwidth_x2 = false,
2990 .has_pll_d2_out0 = false,
2991};
2992
2993static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = {
2994 {
2995 .index = 0,
2996 .dc = 0,
2997 .windows = (const unsigned int[]) { 0 },
2998 .num_windows = 1,
2999 }, {
3000 .index = 1,
3001 .dc = 1,
3002 .windows = (const unsigned int[]) { 1 },
3003 .num_windows = 1,
3004 }, {
3005 .index = 2,
3006 .dc = 1,
3007 .windows = (const unsigned int[]) { 2 },
3008 .num_windows = 1,
3009 }, {
3010 .index = 3,
3011 .dc = 2,
3012 .windows = (const unsigned int[]) { 3 },
3013 .num_windows = 1,
3014 }, {
3015 .index = 4,
3016 .dc = 2,
3017 .windows = (const unsigned int[]) { 4 },
3018 .num_windows = 1,
3019 }, {
3020 .index = 5,
3021 .dc = 2,
3022 .windows = (const unsigned int[]) { 5 },
3023 .num_windows = 1,
3024 },
3025};
3026
3027static const struct tegra_dc_soc_info tegra194_dc_soc_info = {
3028 .supports_background_color = true,
3029 .supports_interlacing = true,
3030 .supports_cursor = true,
3031 .supports_block_linear = true,
3032 .supports_sector_layout = true,
3033 .has_legacy_blending = false,
3034 .pitch_align = 64,
3035 .has_powergate = false,
3036 .coupled_pm = false,
3037 .has_nvdisplay = true,
3038 .wgrps = tegra194_dc_wgrps,
3039 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps),
3040 .plane_tiled_memory_bandwidth_x2 = false,
3041 .has_pll_d2_out0 = false,
3042};
3043
3044static const struct of_device_id tegra_dc_of_match[] = {
3045 {
3046 .compatible = "nvidia,tegra194-dc",
3047 .data = &tegra194_dc_soc_info,
3048 }, {
3049 .compatible = "nvidia,tegra186-dc",
3050 .data = &tegra186_dc_soc_info,
3051 }, {
3052 .compatible = "nvidia,tegra210-dc",
3053 .data = &tegra210_dc_soc_info,
3054 }, {
3055 .compatible = "nvidia,tegra124-dc",
3056 .data = &tegra124_dc_soc_info,
3057 }, {
3058 .compatible = "nvidia,tegra114-dc",
3059 .data = &tegra114_dc_soc_info,
3060 }, {
3061 .compatible = "nvidia,tegra30-dc",
3062 .data = &tegra30_dc_soc_info,
3063 }, {
3064 .compatible = "nvidia,tegra20-dc",
3065 .data = &tegra20_dc_soc_info,
3066 }, {
3067 /* sentinel */
3068 }
3069};
3070MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
3071
3072static int tegra_dc_parse_dt(struct tegra_dc *dc)
3073{
3074 struct device_node *np;
3075 u32 value = 0;
3076 int err;
3077
3078 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
3079 if (err < 0) {
3080 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
3081
3082 /*
3083 * If the nvidia,head property isn't present, try to find the
3084 * correct head number by looking up the position of this
3085 * display controller's node within the device tree. Assuming
3086 * that the nodes are ordered properly in the DTS file and
3087 * that the translation into a flattened device tree blob
3088 * preserves that ordering this will actually yield the right
3089 * head number.
3090 *
3091 * If those assumptions don't hold, this will still work for
3092 * cases where only a single display controller is used.
3093 */
3094 for_each_matching_node(np, tegra_dc_of_match) {
3095 if (np == dc->dev->of_node) {
3096 of_node_put(np);
3097 break;
3098 }
3099
3100 value++;
3101 }
3102 }
3103
3104 dc->pipe = value;
3105
3106 return 0;
3107}
3108
3109static int tegra_dc_match_by_pipe(struct device *dev, const void *data)
3110{
3111 struct tegra_dc *dc = dev_get_drvdata(dev);
3112 unsigned int pipe = (unsigned long)(void *)data;
3113
3114 return dc->pipe == pipe;
3115}
3116
3117static int tegra_dc_couple(struct tegra_dc *dc)
3118{
3119 /*
3120 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to
3121 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND /
3122 * POWER_CONTROL registers during CRTC enabling.
3123 */
3124 if (dc->soc->coupled_pm && dc->pipe == 1) {
3125 struct device *companion;
3126 struct tegra_dc *parent;
3127
3128 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0,
3129 tegra_dc_match_by_pipe);
3130 if (!companion)
3131 return -EPROBE_DEFER;
3132
3133 parent = dev_get_drvdata(companion);
3134 dc->client.parent = &parent->client;
3135
3136 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion));
3137 }
3138
3139 return 0;
3140}
3141
3142static int tegra_dc_init_opp_table(struct tegra_dc *dc)
3143{
3144 struct tegra_core_opp_params opp_params = {};
3145 int err;
3146
3147 err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params);
3148 if (err && err != -ENODEV)
3149 return err;
3150
3151 if (err)
3152 dc->has_opp_table = false;
3153 else
3154 dc->has_opp_table = true;
3155
3156 return 0;
3157}
3158
3159static int tegra_dc_probe(struct platform_device *pdev)
3160{
3161 u64 dma_mask = dma_get_mask(pdev->dev.parent);
3162 struct tegra_dc *dc;
3163 int err;
3164
3165 err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask);
3166 if (err < 0) {
3167 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
3168 return err;
3169 }
3170
3171 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
3172 if (!dc)
3173 return -ENOMEM;
3174
3175 dc->soc = of_device_get_match_data(&pdev->dev);
3176
3177 INIT_LIST_HEAD(&dc->list);
3178 dc->dev = &pdev->dev;
3179
3180 err = tegra_dc_parse_dt(dc);
3181 if (err < 0)
3182 return err;
3183
3184 err = tegra_dc_couple(dc);
3185 if (err < 0)
3186 return err;
3187
3188 dc->clk = devm_clk_get(&pdev->dev, NULL);
3189 if (IS_ERR(dc->clk)) {
3190 dev_err(&pdev->dev, "failed to get clock\n");
3191 return PTR_ERR(dc->clk);
3192 }
3193
3194 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
3195 if (IS_ERR(dc->rst)) {
3196 dev_err(&pdev->dev, "failed to get reset\n");
3197 return PTR_ERR(dc->rst);
3198 }
3199
3200 /* assert reset and disable clock */
3201 err = clk_prepare_enable(dc->clk);
3202 if (err < 0)
3203 return err;
3204
3205 usleep_range(2000, 4000);
3206
3207 err = reset_control_assert(dc->rst);
3208 if (err < 0) {
3209 clk_disable_unprepare(dc->clk);
3210 return err;
3211 }
3212
3213 usleep_range(2000, 4000);
3214
3215 clk_disable_unprepare(dc->clk);
3216
3217 if (dc->soc->has_powergate) {
3218 if (dc->pipe == 0)
3219 dc->powergate = TEGRA_POWERGATE_DIS;
3220 else
3221 dc->powergate = TEGRA_POWERGATE_DISB;
3222
3223 tegra_powergate_power_off(dc->powergate);
3224 }
3225
3226 err = tegra_dc_init_opp_table(dc);
3227 if (err < 0)
3228 return err;
3229
3230 dc->regs = devm_platform_ioremap_resource(pdev, 0);
3231 if (IS_ERR(dc->regs))
3232 return PTR_ERR(dc->regs);
3233
3234 dc->irq = platform_get_irq(pdev, 0);
3235 if (dc->irq < 0)
3236 return -ENXIO;
3237
3238 err = tegra_dc_rgb_probe(dc);
3239 if (err < 0 && err != -ENODEV)
3240 return dev_err_probe(&pdev->dev, err,
3241 "failed to probe RGB output\n");
3242
3243 platform_set_drvdata(pdev, dc);
3244 pm_runtime_enable(&pdev->dev);
3245
3246 INIT_LIST_HEAD(&dc->client.list);
3247 dc->client.ops = &dc_client_ops;
3248 dc->client.dev = &pdev->dev;
3249
3250 err = host1x_client_register(&dc->client);
3251 if (err < 0) {
3252 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3253 err);
3254 goto disable_pm;
3255 }
3256
3257 return 0;
3258
3259disable_pm:
3260 pm_runtime_disable(&pdev->dev);
3261 tegra_dc_rgb_remove(dc);
3262
3263 return err;
3264}
3265
3266static int tegra_dc_remove(struct platform_device *pdev)
3267{
3268 struct tegra_dc *dc = platform_get_drvdata(pdev);
3269 int err;
3270
3271 err = host1x_client_unregister(&dc->client);
3272 if (err < 0) {
3273 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
3274 err);
3275 return err;
3276 }
3277
3278 err = tegra_dc_rgb_remove(dc);
3279 if (err < 0) {
3280 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
3281 return err;
3282 }
3283
3284 pm_runtime_disable(&pdev->dev);
3285
3286 return 0;
3287}
3288
3289struct platform_driver tegra_dc_driver = {
3290 .driver = {
3291 .name = "tegra-dc",
3292 .of_match_table = tegra_dc_of_match,
3293 },
3294 .probe = tegra_dc_probe,
3295 .remove = tegra_dc_remove,
3296};