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1/*
2 * linux/arch/arm/mach-pxa/pxa27x.c
3 *
4 * Author: Nicolas Pitre
5 * Created: Nov 05, 2002
6 * Copyright: MontaVista Software Inc.
7 *
8 * Code specific to PXA27x aka Bulverde.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/gpio.h>
15#include <linux/gpio-pxa.h>
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/suspend.h>
20#include <linux/platform_device.h>
21#include <linux/syscore_ops.h>
22#include <linux/io.h>
23#include <linux/irq.h>
24#include <linux/i2c/pxa-i2c.h>
25
26#include <asm/mach/map.h>
27#include <mach/hardware.h>
28#include <asm/irq.h>
29#include <asm/suspend.h>
30#include <mach/irqs.h>
31#include <mach/pxa27x.h>
32#include <mach/reset.h>
33#include <linux/platform_data/usb-ohci-pxa27x.h>
34#include <mach/pm.h>
35#include <mach/dma.h>
36#include <mach/smemc.h>
37
38#include "generic.h"
39#include "devices.h"
40#include "clock.h"
41
42void pxa27x_clear_otgph(void)
43{
44 if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
45 PSSR |= PSSR_OTGPH;
46}
47EXPORT_SYMBOL(pxa27x_clear_otgph);
48
49static unsigned long ac97_reset_config[] = {
50 GPIO113_AC97_nRESET_GPIO_HIGH,
51 GPIO113_AC97_nRESET,
52 GPIO95_AC97_nRESET_GPIO_HIGH,
53 GPIO95_AC97_nRESET,
54};
55
56void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
57{
58 /*
59 * This helper function is used to work around a bug in the pxa27x's
60 * ac97 controller during a warm reset. The configuration of the
61 * reset_gpio is changed as follows:
62 * to_gpio == true: configured to generic output gpio and driven high
63 * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET
64 */
65
66 if (reset_gpio == 113)
67 pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] :
68 &ac97_reset_config[1], 1);
69
70 if (reset_gpio == 95)
71 pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] :
72 &ac97_reset_config[3], 1);
73}
74EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
75
76/* Crystal clock: 13MHz */
77#define BASE_CLK 13000000
78
79/*
80 * Get the clock frequency as reflected by CCSR and the turbo flag.
81 * We assume these values have been applied via a fcs.
82 * If info is not 0 we also display the current settings.
83 */
84unsigned int pxa27x_get_clk_frequency_khz(int info)
85{
86 unsigned long ccsr, clkcfg;
87 unsigned int l, L, m, M, n2, N, S;
88 int cccr_a, t, ht, b;
89
90 ccsr = CCSR;
91 cccr_a = CCCR & (1 << 25);
92
93 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
94 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
95 t = clkcfg & (1 << 0);
96 ht = clkcfg & (1 << 2);
97 b = clkcfg & (1 << 3);
98
99 l = ccsr & 0x1f;
100 n2 = (ccsr>>7) & 0xf;
101 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
102
103 L = l * BASE_CLK;
104 N = (L * n2) / 2;
105 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
106 S = (b) ? L : (L/2);
107
108 if (info) {
109 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
110 L / 1000000, (L % 1000000) / 10000, l );
111 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
112 N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
113 (t) ? "" : "in" );
114 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
115 M / 1000000, (M % 1000000) / 10000, m );
116 printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
117 S / 1000000, (S % 1000000) / 10000 );
118 }
119
120 return (t) ? (N/1000) : (L/1000);
121}
122
123/*
124 * Return the current mem clock frequency as reflected by CCCR[A], B, and L
125 */
126static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
127{
128 unsigned long ccsr, clkcfg;
129 unsigned int l, L, m, M;
130 int cccr_a, b;
131
132 ccsr = CCSR;
133 cccr_a = CCCR & (1 << 25);
134
135 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
136 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
137 b = clkcfg & (1 << 3);
138
139 l = ccsr & 0x1f;
140 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
141
142 L = l * BASE_CLK;
143 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
144
145 return M;
146}
147
148static const struct clkops clk_pxa27x_mem_ops = {
149 .enable = clk_dummy_enable,
150 .disable = clk_dummy_disable,
151 .getrate = clk_pxa27x_mem_getrate,
152};
153
154/*
155 * Return the current LCD clock frequency in units of 10kHz as
156 */
157static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
158{
159 unsigned long ccsr;
160 unsigned int l, L, k, K;
161
162 ccsr = CCSR;
163
164 l = ccsr & 0x1f;
165 k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
166
167 L = l * BASE_CLK;
168 K = L / k;
169
170 return (K / 10000);
171}
172
173static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
174{
175 return pxa27x_get_lcdclk_frequency_10khz() * 10000;
176}
177
178static const struct clkops clk_pxa27x_lcd_ops = {
179 .enable = clk_pxa2xx_cken_enable,
180 .disable = clk_pxa2xx_cken_disable,
181 .getrate = clk_pxa27x_lcd_getrate,
182};
183
184static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
185static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
186static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
187static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
188static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
189static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
190static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
191static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
192static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
193static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
194static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
195static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
196static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
197static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
198static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
199static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
200static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
201static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
202static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
203static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
204static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
205static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
206static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
207
208static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
209static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
210static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
211
212static struct clk_lookup pxa27x_clkregs[] = {
213 INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
214 INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
215 INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
216 INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
217 INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
218 INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
219 INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
220 INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
221 INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
222 INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
223 INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
224 INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
225 INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
226 INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
227 INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
228 INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
229 INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
230 INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
231 INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
232 INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
233 INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
234 INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
235 INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
236 INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
237 INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
238 INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
239 INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
240 INIT_CLKREG(&clk_dummy, "pxa27x-gpio", NULL),
241 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
242};
243
244#ifdef CONFIG_PM
245
246#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
247#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
248
249/*
250 * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
251 */
252static unsigned int pwrmode = PWRMODE_SLEEP;
253
254int __init pxa27x_set_pwrmode(unsigned int mode)
255{
256 switch (mode) {
257 case PWRMODE_SLEEP:
258 case PWRMODE_DEEPSLEEP:
259 pwrmode = mode;
260 return 0;
261 }
262
263 return -EINVAL;
264}
265
266/*
267 * List of global PXA peripheral registers to preserve.
268 * More ones like CP and general purpose register values are preserved
269 * with the stack pointer in sleep.S.
270 */
271enum {
272 SLEEP_SAVE_PSTR,
273 SLEEP_SAVE_MDREFR,
274 SLEEP_SAVE_PCFR,
275 SLEEP_SAVE_COUNT
276};
277
278void pxa27x_cpu_pm_save(unsigned long *sleep_save)
279{
280 sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
281 SAVE(PCFR);
282
283 SAVE(PSTR);
284}
285
286void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
287{
288 __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
289 RESTORE(PCFR);
290
291 PSSR = PSSR_RDH | PSSR_PH;
292
293 RESTORE(PSTR);
294}
295
296void pxa27x_cpu_pm_enter(suspend_state_t state)
297{
298 extern void pxa_cpu_standby(void);
299#ifndef CONFIG_IWMMXT
300 u64 acc0;
301
302 asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
303#endif
304
305 /* ensure voltage-change sequencer not initiated, which hangs */
306 PCFR &= ~PCFR_FVC;
307
308 /* Clear edge-detect status register. */
309 PEDR = 0xDF12FE1B;
310
311 /* Clear reset status */
312 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
313
314 switch (state) {
315 case PM_SUSPEND_STANDBY:
316 pxa_cpu_standby();
317 break;
318 case PM_SUSPEND_MEM:
319 cpu_suspend(pwrmode, pxa27x_finish_suspend);
320#ifndef CONFIG_IWMMXT
321 asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
322#endif
323 break;
324 }
325}
326
327static int pxa27x_cpu_pm_valid(suspend_state_t state)
328{
329 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
330}
331
332static int pxa27x_cpu_pm_prepare(void)
333{
334 /* set resume return address */
335 PSPR = virt_to_phys(cpu_resume);
336 return 0;
337}
338
339static void pxa27x_cpu_pm_finish(void)
340{
341 /* ensure not to come back here if it wasn't intended */
342 PSPR = 0;
343}
344
345static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
346 .save_count = SLEEP_SAVE_COUNT,
347 .save = pxa27x_cpu_pm_save,
348 .restore = pxa27x_cpu_pm_restore,
349 .valid = pxa27x_cpu_pm_valid,
350 .enter = pxa27x_cpu_pm_enter,
351 .prepare = pxa27x_cpu_pm_prepare,
352 .finish = pxa27x_cpu_pm_finish,
353};
354
355static void __init pxa27x_init_pm(void)
356{
357 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
358}
359#else
360static inline void pxa27x_init_pm(void) {}
361#endif
362
363/* PXA27x: Various gpios can issue wakeup events. This logic only
364 * handles the simple cases, not the WEMUX2 and WEMUX3 options
365 */
366static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
367{
368 int gpio = pxa_irq_to_gpio(d->irq);
369 uint32_t mask;
370
371 if (gpio >= 0 && gpio < 128)
372 return gpio_set_wake(gpio, on);
373
374 if (d->irq == IRQ_KEYPAD)
375 return keypad_set_wake(on);
376
377 switch (d->irq) {
378 case IRQ_RTCAlrm:
379 mask = PWER_RTC;
380 break;
381 case IRQ_USB:
382 mask = 1u << 26;
383 break;
384 default:
385 return -EINVAL;
386 }
387
388 if (on)
389 PWER |= mask;
390 else
391 PWER &=~mask;
392
393 return 0;
394}
395
396void __init pxa27x_init_irq(void)
397{
398 pxa_init_irq(34, pxa27x_set_wake);
399}
400
401static struct map_desc pxa27x_io_desc[] __initdata = {
402 { /* Mem Ctl */
403 .virtual = (unsigned long)SMEMC_VIRT,
404 .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
405 .length = 0x00200000,
406 .type = MT_DEVICE
407 }, { /* IMem ctl */
408 .virtual = 0xfe000000,
409 .pfn = __phys_to_pfn(0x58000000),
410 .length = 0x00100000,
411 .type = MT_DEVICE
412 },
413};
414
415void __init pxa27x_map_io(void)
416{
417 pxa_map_io();
418 iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
419 pxa27x_get_clk_frequency_khz(1);
420}
421
422/*
423 * device registration specific to PXA27x.
424 */
425void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
426{
427 local_irq_disable();
428 PCFR |= PCFR_PI2CEN;
429 local_irq_enable();
430 pxa_register_device(&pxa27x_device_i2c_power, info);
431}
432
433static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
434 .irq_base = PXA_GPIO_TO_IRQ(0),
435 .gpio_set_wake = gpio_set_wake,
436};
437
438static struct platform_device *devices[] __initdata = {
439 &pxa27x_device_udc,
440 &pxa_device_pmu,
441 &pxa_device_i2s,
442 &pxa_device_asoc_ssp1,
443 &pxa_device_asoc_ssp2,
444 &pxa_device_asoc_ssp3,
445 &pxa_device_asoc_platform,
446 &sa1100_device_rtc,
447 &pxa_device_rtc,
448 &pxa27x_device_ssp1,
449 &pxa27x_device_ssp2,
450 &pxa27x_device_ssp3,
451 &pxa27x_device_pwm0,
452 &pxa27x_device_pwm1,
453};
454
455static int __init pxa27x_init(void)
456{
457 int ret = 0;
458
459 if (cpu_is_pxa27x()) {
460
461 reset_status = RCSR;
462
463 clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
464
465 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
466 return ret;
467
468 pxa27x_init_pm();
469
470 register_syscore_ops(&pxa_irq_syscore_ops);
471 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
472 register_syscore_ops(&pxa2xx_clock_syscore_ops);
473
474 pxa_register_device(&pxa27x_device_gpio, &pxa27x_gpio_info);
475 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
476 }
477
478 return ret;
479}
480
481postcore_initcall(pxa27x_init);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-pxa/pxa27x.c
4 *
5 * Author: Nicolas Pitre
6 * Created: Nov 05, 2002
7 * Copyright: MontaVista Software Inc.
8 *
9 * Code specific to PXA27x aka Bulverde.
10 */
11#include <linux/dmaengine.h>
12#include <linux/dma/pxa-dma.h>
13#include <linux/gpio.h>
14#include <linux/gpio-pxa.h>
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/irqchip.h>
19#include <linux/suspend.h>
20#include <linux/platform_device.h>
21#include <linux/syscore_ops.h>
22#include <linux/io.h>
23#include <linux/irq.h>
24#include <linux/platform_data/i2c-pxa.h>
25#include <linux/platform_data/mmp_dma.h>
26#include <linux/soc/pxa/cpu.h>
27
28#include <asm/mach/map.h>
29#include <asm/irq.h>
30#include <asm/suspend.h>
31#include "irqs.h"
32#include "pxa27x.h"
33#include "reset.h"
34#include <linux/platform_data/usb-ohci-pxa27x.h>
35#include "pm.h"
36#include "addr-map.h"
37#include "smemc.h"
38
39#include "generic.h"
40#include "devices.h"
41#include <linux/clk-provider.h>
42#include <linux/clkdev.h>
43
44void pxa27x_clear_otgph(void)
45{
46 if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
47 PSSR |= PSSR_OTGPH;
48}
49EXPORT_SYMBOL(pxa27x_clear_otgph);
50
51static unsigned long ac97_reset_config[] = {
52 GPIO113_AC97_nRESET_GPIO_HIGH,
53 GPIO113_AC97_nRESET,
54 GPIO95_AC97_nRESET_GPIO_HIGH,
55 GPIO95_AC97_nRESET,
56};
57
58void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
59{
60 /*
61 * This helper function is used to work around a bug in the pxa27x's
62 * ac97 controller during a warm reset. The configuration of the
63 * reset_gpio is changed as follows:
64 * to_gpio == true: configured to generic output gpio and driven high
65 * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET
66 */
67
68 if (reset_gpio == 113)
69 pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] :
70 &ac97_reset_config[1], 1);
71
72 if (reset_gpio == 95)
73 pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] :
74 &ac97_reset_config[3], 1);
75}
76EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
77
78#ifdef CONFIG_PM
79
80#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
81#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
82
83/*
84 * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
85 */
86static unsigned int pwrmode = PWRMODE_SLEEP;
87
88int pxa27x_set_pwrmode(unsigned int mode)
89{
90 switch (mode) {
91 case PWRMODE_SLEEP:
92 case PWRMODE_DEEPSLEEP:
93 pwrmode = mode;
94 return 0;
95 }
96
97 return -EINVAL;
98}
99
100/*
101 * List of global PXA peripheral registers to preserve.
102 * More ones like CP and general purpose register values are preserved
103 * with the stack pointer in sleep.S.
104 */
105enum {
106 SLEEP_SAVE_PSTR,
107 SLEEP_SAVE_MDREFR,
108 SLEEP_SAVE_PCFR,
109 SLEEP_SAVE_COUNT
110};
111
112void pxa27x_cpu_pm_save(unsigned long *sleep_save)
113{
114 sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
115 SAVE(PCFR);
116
117 SAVE(PSTR);
118}
119
120void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
121{
122 __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
123 RESTORE(PCFR);
124
125 PSSR = PSSR_RDH | PSSR_PH;
126
127 RESTORE(PSTR);
128}
129
130void pxa27x_cpu_pm_enter(suspend_state_t state)
131{
132 extern void pxa_cpu_standby(void);
133#ifndef CONFIG_IWMMXT
134 u64 acc0;
135
136#ifndef CONFIG_AS_IS_LLVM
137 asm volatile(".arch_extension xscale\n\t"
138 "mra %Q0, %R0, acc0" : "=r" (acc0));
139#else
140 asm volatile("mrrc p0, 0, %Q0, %R0, c0" : "=r" (acc0));
141#endif
142#endif
143
144 /* ensure voltage-change sequencer not initiated, which hangs */
145 PCFR &= ~PCFR_FVC;
146
147 /* Clear edge-detect status register. */
148 PEDR = 0xDF12FE1B;
149
150 /* Clear reset status */
151 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
152
153 switch (state) {
154 case PM_SUSPEND_STANDBY:
155 pxa_cpu_standby();
156 break;
157 case PM_SUSPEND_MEM:
158 cpu_suspend(pwrmode, pxa27x_finish_suspend);
159#ifndef CONFIG_IWMMXT
160#ifndef CONFIG_AS_IS_LLVM
161 asm volatile(".arch_extension xscale\n\t"
162 "mar acc0, %Q0, %R0" : "=r" (acc0));
163#else
164 asm volatile("mcrr p0, 0, %Q0, %R0, c0" :: "r" (acc0));
165#endif
166#endif
167 break;
168 }
169}
170
171static int pxa27x_cpu_pm_valid(suspend_state_t state)
172{
173 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
174}
175
176static int pxa27x_cpu_pm_prepare(void)
177{
178 /* set resume return address */
179 PSPR = __pa_symbol(cpu_resume);
180 return 0;
181}
182
183static void pxa27x_cpu_pm_finish(void)
184{
185 /* ensure not to come back here if it wasn't intended */
186 PSPR = 0;
187}
188
189static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
190 .save_count = SLEEP_SAVE_COUNT,
191 .save = pxa27x_cpu_pm_save,
192 .restore = pxa27x_cpu_pm_restore,
193 .valid = pxa27x_cpu_pm_valid,
194 .enter = pxa27x_cpu_pm_enter,
195 .prepare = pxa27x_cpu_pm_prepare,
196 .finish = pxa27x_cpu_pm_finish,
197};
198
199static void __init pxa27x_init_pm(void)
200{
201 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
202}
203#else
204static inline void pxa27x_init_pm(void) {}
205#endif
206
207/* PXA27x: Various gpios can issue wakeup events. This logic only
208 * handles the simple cases, not the WEMUX2 and WEMUX3 options
209 */
210static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
211{
212 int gpio = pxa_irq_to_gpio(d->irq);
213 uint32_t mask;
214
215 if (gpio >= 0 && gpio < 128)
216 return gpio_set_wake(gpio, on);
217
218 if (d->irq == IRQ_KEYPAD)
219 return keypad_set_wake(on);
220
221 switch (d->irq) {
222 case IRQ_RTCAlrm:
223 mask = PWER_RTC;
224 break;
225 case IRQ_USB:
226 mask = 1u << 26;
227 break;
228 default:
229 return -EINVAL;
230 }
231
232 if (on)
233 PWER |= mask;
234 else
235 PWER &=~mask;
236
237 return 0;
238}
239
240void __init pxa27x_init_irq(void)
241{
242 pxa_init_irq(34, pxa27x_set_wake);
243}
244
245static int __init
246pxa27x_dt_init_irq(struct device_node *node, struct device_node *parent)
247{
248 pxa_dt_irq_init(pxa27x_set_wake);
249 set_handle_irq(ichp_handle_irq);
250
251 return 0;
252}
253IRQCHIP_DECLARE(pxa27x_intc, "marvell,pxa-intc", pxa27x_dt_init_irq);
254
255static struct map_desc pxa27x_io_desc[] __initdata = {
256 { /* Mem Ctl */
257 .virtual = (unsigned long)SMEMC_VIRT,
258 .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
259 .length = SMEMC_SIZE,
260 .type = MT_DEVICE
261 }, { /* UNCACHED_PHYS_0 */
262 .virtual = UNCACHED_PHYS_0,
263 .pfn = __phys_to_pfn(0x00000000),
264 .length = UNCACHED_PHYS_0_SIZE,
265 .type = MT_DEVICE
266 },
267};
268
269void __init pxa27x_map_io(void)
270{
271 pxa_map_io();
272 iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
273 pxa27x_get_clk_frequency_khz(1);
274}
275
276/*
277 * device registration specific to PXA27x.
278 */
279void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
280{
281 local_irq_disable();
282 PCFR |= PCFR_PI2CEN;
283 local_irq_enable();
284 pxa_register_device(&pxa27x_device_i2c_power, info);
285}
286
287static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
288 .irq_base = PXA_GPIO_TO_IRQ(0),
289 .gpio_set_wake = gpio_set_wake,
290};
291
292static struct platform_device *devices[] __initdata = {
293 &pxa27x_device_udc,
294 &pxa_device_pmu,
295 &pxa_device_i2s,
296 &pxa_device_asoc_ssp1,
297 &pxa_device_asoc_ssp2,
298 &pxa_device_asoc_ssp3,
299 &pxa_device_asoc_platform,
300 &pxa_device_rtc,
301 &pxa27x_device_ssp1,
302 &pxa27x_device_ssp2,
303 &pxa27x_device_ssp3,
304 &pxa27x_device_pwm0,
305 &pxa27x_device_pwm1,
306};
307
308static const struct dma_slave_map pxa27x_slave_map[] = {
309 /* PXA25x, PXA27x and PXA3xx common entries */
310 { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
311 { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
312 { "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
313 PDMA_FILTER_PARAM(LOWEST, 10) },
314 { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
315 { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
316 { "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
317 { "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
318 { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
319 { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
320 { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
321 { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
322 { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
323 { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
324 { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) },
325 { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) },
326
327 /* PXA27x specific map */
328 { "pxa2xx-i2s", "rx", PDMA_FILTER_PARAM(LOWEST, 2) },
329 { "pxa2xx-i2s", "tx", PDMA_FILTER_PARAM(LOWEST, 3) },
330 { "pxa27x-camera.0", "CI_Y", PDMA_FILTER_PARAM(HIGHEST, 68) },
331 { "pxa27x-camera.0", "CI_U", PDMA_FILTER_PARAM(HIGHEST, 69) },
332 { "pxa27x-camera.0", "CI_V", PDMA_FILTER_PARAM(HIGHEST, 70) },
333};
334
335static struct mmp_dma_platdata pxa27x_dma_pdata = {
336 .dma_channels = 32,
337 .nb_requestors = 75,
338 .slave_map = pxa27x_slave_map,
339 .slave_map_cnt = ARRAY_SIZE(pxa27x_slave_map),
340};
341
342static int __init pxa27x_init(void)
343{
344 int ret = 0;
345
346 if (cpu_is_pxa27x()) {
347
348 pxa_register_wdt(RCSR);
349
350 pxa27x_init_pm();
351
352 register_syscore_ops(&pxa_irq_syscore_ops);
353 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
354
355 if (!of_have_populated_dt()) {
356 pxa_register_device(&pxa27x_device_gpio,
357 &pxa27x_gpio_info);
358 pxa2xx_set_dmac_info(&pxa27x_dma_pdata);
359 ret = platform_add_devices(devices,
360 ARRAY_SIZE(devices));
361 }
362 }
363
364 return ret;
365}
366
367postcore_initcall(pxa27x_init);