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1/*
2 * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
13 */
14#include <asm/sizes.h>
15
16#include "omap_hwmod.h"
17#include "l3_2xxx.h"
18#include "l4_2xxx.h"
19#include "serial.h"
20
21#include "omap_hwmod_common_data.h"
22
23/*
24 * Common interconnect data
25 */
26
27/* L3 -> L4_CORE interface */
28struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
29 .master = &omap2xxx_l3_main_hwmod,
30 .slave = &omap2xxx_l4_core_hwmod,
31 .user = OCP_USER_MPU | OCP_USER_SDMA,
32};
33
34/* MPU -> L3 interface */
35struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
36 .master = &omap2xxx_mpu_hwmod,
37 .slave = &omap2xxx_l3_main_hwmod,
38 .user = OCP_USER_MPU,
39};
40
41/* DSS -> l3 */
42struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
43 .master = &omap2xxx_dss_core_hwmod,
44 .slave = &omap2xxx_l3_main_hwmod,
45 .fw = {
46 .omap2 = {
47 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
48 .flags = OMAP_FIREWALL_L3,
49 },
50 },
51 .user = OCP_USER_MPU | OCP_USER_SDMA,
52};
53
54/* L4_CORE -> L4_WKUP interface */
55struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
56 .master = &omap2xxx_l4_core_hwmod,
57 .slave = &omap2xxx_l4_wkup_hwmod,
58 .user = OCP_USER_MPU | OCP_USER_SDMA,
59};
60
61/* L4 CORE -> UART1 interface */
62struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
63 .master = &omap2xxx_l4_core_hwmod,
64 .slave = &omap2xxx_uart1_hwmod,
65 .clk = "uart1_ick",
66 .user = OCP_USER_MPU | OCP_USER_SDMA,
67};
68
69/* L4 CORE -> UART2 interface */
70struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
71 .master = &omap2xxx_l4_core_hwmod,
72 .slave = &omap2xxx_uart2_hwmod,
73 .clk = "uart2_ick",
74 .user = OCP_USER_MPU | OCP_USER_SDMA,
75};
76
77/* L4 PER -> UART3 interface */
78struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
79 .master = &omap2xxx_l4_core_hwmod,
80 .slave = &omap2xxx_uart3_hwmod,
81 .clk = "uart3_ick",
82 .user = OCP_USER_MPU | OCP_USER_SDMA,
83};
84
85/* l4 core -> mcspi1 interface */
86struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
87 .master = &omap2xxx_l4_core_hwmod,
88 .slave = &omap2xxx_mcspi1_hwmod,
89 .clk = "mcspi1_ick",
90 .user = OCP_USER_MPU | OCP_USER_SDMA,
91};
92
93/* l4 core -> mcspi2 interface */
94struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
95 .master = &omap2xxx_l4_core_hwmod,
96 .slave = &omap2xxx_mcspi2_hwmod,
97 .clk = "mcspi2_ick",
98 .user = OCP_USER_MPU | OCP_USER_SDMA,
99};
100
101/* l4_core -> timer2 */
102struct omap_hwmod_ocp_if omap2xxx_l4_core__timer2 = {
103 .master = &omap2xxx_l4_core_hwmod,
104 .slave = &omap2xxx_timer2_hwmod,
105 .clk = "gpt2_ick",
106 .user = OCP_USER_MPU | OCP_USER_SDMA,
107};
108
109/* l4_core -> timer3 */
110struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
111 .master = &omap2xxx_l4_core_hwmod,
112 .slave = &omap2xxx_timer3_hwmod,
113 .clk = "gpt3_ick",
114 .user = OCP_USER_MPU | OCP_USER_SDMA,
115};
116
117/* l4_core -> timer4 */
118struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
119 .master = &omap2xxx_l4_core_hwmod,
120 .slave = &omap2xxx_timer4_hwmod,
121 .clk = "gpt4_ick",
122 .user = OCP_USER_MPU | OCP_USER_SDMA,
123};
124
125/* l4_core -> timer5 */
126struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
127 .master = &omap2xxx_l4_core_hwmod,
128 .slave = &omap2xxx_timer5_hwmod,
129 .clk = "gpt5_ick",
130 .user = OCP_USER_MPU | OCP_USER_SDMA,
131};
132
133/* l4_core -> timer6 */
134struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
135 .master = &omap2xxx_l4_core_hwmod,
136 .slave = &omap2xxx_timer6_hwmod,
137 .clk = "gpt6_ick",
138 .user = OCP_USER_MPU | OCP_USER_SDMA,
139};
140
141/* l4_core -> timer7 */
142struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
143 .master = &omap2xxx_l4_core_hwmod,
144 .slave = &omap2xxx_timer7_hwmod,
145 .clk = "gpt7_ick",
146 .user = OCP_USER_MPU | OCP_USER_SDMA,
147};
148
149/* l4_core -> timer8 */
150struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
151 .master = &omap2xxx_l4_core_hwmod,
152 .slave = &omap2xxx_timer8_hwmod,
153 .clk = "gpt8_ick",
154 .user = OCP_USER_MPU | OCP_USER_SDMA,
155};
156
157/* l4_core -> timer9 */
158struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
159 .master = &omap2xxx_l4_core_hwmod,
160 .slave = &omap2xxx_timer9_hwmod,
161 .clk = "gpt9_ick",
162 .user = OCP_USER_MPU | OCP_USER_SDMA,
163};
164
165/* l4_core -> timer10 */
166struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
167 .master = &omap2xxx_l4_core_hwmod,
168 .slave = &omap2xxx_timer10_hwmod,
169 .clk = "gpt10_ick",
170 .user = OCP_USER_MPU | OCP_USER_SDMA,
171};
172
173/* l4_core -> timer11 */
174struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
175 .master = &omap2xxx_l4_core_hwmod,
176 .slave = &omap2xxx_timer11_hwmod,
177 .clk = "gpt11_ick",
178 .user = OCP_USER_MPU | OCP_USER_SDMA,
179};
180
181/* l4_core -> timer12 */
182struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
183 .master = &omap2xxx_l4_core_hwmod,
184 .slave = &omap2xxx_timer12_hwmod,
185 .clk = "gpt12_ick",
186 .user = OCP_USER_MPU | OCP_USER_SDMA,
187};
188
189/* l4_core -> dss */
190struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
191 .master = &omap2xxx_l4_core_hwmod,
192 .slave = &omap2xxx_dss_core_hwmod,
193 .clk = "dss_ick",
194 .addr = omap2_dss_addrs,
195 .fw = {
196 .omap2 = {
197 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
198 .flags = OMAP_FIREWALL_L4,
199 },
200 },
201 .user = OCP_USER_MPU | OCP_USER_SDMA,
202};
203
204/* l4_core -> dss_dispc */
205struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
206 .master = &omap2xxx_l4_core_hwmod,
207 .slave = &omap2xxx_dss_dispc_hwmod,
208 .clk = "dss_ick",
209 .addr = omap2_dss_dispc_addrs,
210 .fw = {
211 .omap2 = {
212 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
213 .flags = OMAP_FIREWALL_L4,
214 },
215 },
216 .user = OCP_USER_MPU | OCP_USER_SDMA,
217};
218
219/* l4_core -> dss_rfbi */
220struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
221 .master = &omap2xxx_l4_core_hwmod,
222 .slave = &omap2xxx_dss_rfbi_hwmod,
223 .clk = "dss_ick",
224 .addr = omap2_dss_rfbi_addrs,
225 .fw = {
226 .omap2 = {
227 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
228 .flags = OMAP_FIREWALL_L4,
229 },
230 },
231 .user = OCP_USER_MPU | OCP_USER_SDMA,
232};
233
234/* l4_core -> dss_venc */
235struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
236 .master = &omap2xxx_l4_core_hwmod,
237 .slave = &omap2xxx_dss_venc_hwmod,
238 .clk = "dss_ick",
239 .addr = omap2_dss_venc_addrs,
240 .fw = {
241 .omap2 = {
242 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
243 .flags = OMAP_FIREWALL_L4,
244 },
245 },
246 .flags = OCPIF_SWSUP_IDLE,
247 .user = OCP_USER_MPU | OCP_USER_SDMA,
248};
249
250/* l4_core -> rng */
251struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
252 .master = &omap2xxx_l4_core_hwmod,
253 .slave = &omap2xxx_rng_hwmod,
254 .clk = "rng_ick",
255 .user = OCP_USER_MPU | OCP_USER_SDMA,
256};
257
258/* l4 core -> sham interface */
259struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
260 .master = &omap2xxx_l4_core_hwmod,
261 .slave = &omap2xxx_sham_hwmod,
262 .clk = "sha_ick",
263 .user = OCP_USER_MPU | OCP_USER_SDMA,
264};
265
266/* l4 core -> aes interface */
267struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
268 .master = &omap2xxx_l4_core_hwmod,
269 .slave = &omap2xxx_aes_hwmod,
270 .clk = "aes_ick",
271 .user = OCP_USER_MPU | OCP_USER_SDMA,
272};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
4 *
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Paul Walmsley
7 *
8 * XXX handle crossbar/shared link difference for L3?
9 * XXX these should be marked initdata for multi-OMAP kernels
10 */
11#include <linux/sizes.h>
12
13#include "omap_hwmod.h"
14#include "l3_2xxx.h"
15#include "l4_2xxx.h"
16#include "serial.h"
17
18#include "omap_hwmod_common_data.h"
19
20/*
21 * Common interconnect data
22 */
23
24/* L3 -> L4_CORE interface */
25struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core = {
26 .master = &omap2xxx_l3_main_hwmod,
27 .slave = &omap2xxx_l4_core_hwmod,
28 .user = OCP_USER_MPU | OCP_USER_SDMA,
29};
30
31/* MPU -> L3 interface */
32struct omap_hwmod_ocp_if omap2xxx_mpu__l3_main = {
33 .master = &omap2xxx_mpu_hwmod,
34 .slave = &omap2xxx_l3_main_hwmod,
35 .user = OCP_USER_MPU,
36};
37
38/* DSS -> l3 */
39struct omap_hwmod_ocp_if omap2xxx_dss__l3 = {
40 .master = &omap2xxx_dss_core_hwmod,
41 .slave = &omap2xxx_l3_main_hwmod,
42 .fw = {
43 .omap2 = {
44 .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS,
45 .flags = OMAP_FIREWALL_L3,
46 },
47 },
48 .user = OCP_USER_MPU | OCP_USER_SDMA,
49};
50
51/* L4_CORE -> L4_WKUP interface */
52struct omap_hwmod_ocp_if omap2xxx_l4_core__l4_wkup = {
53 .master = &omap2xxx_l4_core_hwmod,
54 .slave = &omap2xxx_l4_wkup_hwmod,
55 .user = OCP_USER_MPU | OCP_USER_SDMA,
56};
57
58/* L4 CORE -> UART1 interface */
59struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
60 .master = &omap2xxx_l4_core_hwmod,
61 .slave = &omap2xxx_uart1_hwmod,
62 .clk = "uart1_ick",
63 .user = OCP_USER_MPU | OCP_USER_SDMA,
64};
65
66/* L4 CORE -> UART2 interface */
67struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
68 .master = &omap2xxx_l4_core_hwmod,
69 .slave = &omap2xxx_uart2_hwmod,
70 .clk = "uart2_ick",
71 .user = OCP_USER_MPU | OCP_USER_SDMA,
72};
73
74/* L4 PER -> UART3 interface */
75struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
76 .master = &omap2xxx_l4_core_hwmod,
77 .slave = &omap2xxx_uart3_hwmod,
78 .clk = "uart3_ick",
79 .user = OCP_USER_MPU | OCP_USER_SDMA,
80};
81
82/* l4 core -> mcspi1 interface */
83struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi1 = {
84 .master = &omap2xxx_l4_core_hwmod,
85 .slave = &omap2xxx_mcspi1_hwmod,
86 .clk = "mcspi1_ick",
87 .user = OCP_USER_MPU | OCP_USER_SDMA,
88};
89
90/* l4 core -> mcspi2 interface */
91struct omap_hwmod_ocp_if omap2xxx_l4_core__mcspi2 = {
92 .master = &omap2xxx_l4_core_hwmod,
93 .slave = &omap2xxx_mcspi2_hwmod,
94 .clk = "mcspi2_ick",
95 .user = OCP_USER_MPU | OCP_USER_SDMA,
96};
97
98/* l4_core -> timer3 */
99struct omap_hwmod_ocp_if omap2xxx_l4_core__timer3 = {
100 .master = &omap2xxx_l4_core_hwmod,
101 .slave = &omap2xxx_timer3_hwmod,
102 .clk = "gpt3_ick",
103 .user = OCP_USER_MPU | OCP_USER_SDMA,
104};
105
106/* l4_core -> timer4 */
107struct omap_hwmod_ocp_if omap2xxx_l4_core__timer4 = {
108 .master = &omap2xxx_l4_core_hwmod,
109 .slave = &omap2xxx_timer4_hwmod,
110 .clk = "gpt4_ick",
111 .user = OCP_USER_MPU | OCP_USER_SDMA,
112};
113
114/* l4_core -> timer5 */
115struct omap_hwmod_ocp_if omap2xxx_l4_core__timer5 = {
116 .master = &omap2xxx_l4_core_hwmod,
117 .slave = &omap2xxx_timer5_hwmod,
118 .clk = "gpt5_ick",
119 .user = OCP_USER_MPU | OCP_USER_SDMA,
120};
121
122/* l4_core -> timer6 */
123struct omap_hwmod_ocp_if omap2xxx_l4_core__timer6 = {
124 .master = &omap2xxx_l4_core_hwmod,
125 .slave = &omap2xxx_timer6_hwmod,
126 .clk = "gpt6_ick",
127 .user = OCP_USER_MPU | OCP_USER_SDMA,
128};
129
130/* l4_core -> timer7 */
131struct omap_hwmod_ocp_if omap2xxx_l4_core__timer7 = {
132 .master = &omap2xxx_l4_core_hwmod,
133 .slave = &omap2xxx_timer7_hwmod,
134 .clk = "gpt7_ick",
135 .user = OCP_USER_MPU | OCP_USER_SDMA,
136};
137
138/* l4_core -> timer8 */
139struct omap_hwmod_ocp_if omap2xxx_l4_core__timer8 = {
140 .master = &omap2xxx_l4_core_hwmod,
141 .slave = &omap2xxx_timer8_hwmod,
142 .clk = "gpt8_ick",
143 .user = OCP_USER_MPU | OCP_USER_SDMA,
144};
145
146/* l4_core -> timer9 */
147struct omap_hwmod_ocp_if omap2xxx_l4_core__timer9 = {
148 .master = &omap2xxx_l4_core_hwmod,
149 .slave = &omap2xxx_timer9_hwmod,
150 .clk = "gpt9_ick",
151 .user = OCP_USER_MPU | OCP_USER_SDMA,
152};
153
154/* l4_core -> timer10 */
155struct omap_hwmod_ocp_if omap2xxx_l4_core__timer10 = {
156 .master = &omap2xxx_l4_core_hwmod,
157 .slave = &omap2xxx_timer10_hwmod,
158 .clk = "gpt10_ick",
159 .user = OCP_USER_MPU | OCP_USER_SDMA,
160};
161
162/* l4_core -> timer11 */
163struct omap_hwmod_ocp_if omap2xxx_l4_core__timer11 = {
164 .master = &omap2xxx_l4_core_hwmod,
165 .slave = &omap2xxx_timer11_hwmod,
166 .clk = "gpt11_ick",
167 .user = OCP_USER_MPU | OCP_USER_SDMA,
168};
169
170/* l4_core -> timer12 */
171struct omap_hwmod_ocp_if omap2xxx_l4_core__timer12 = {
172 .master = &omap2xxx_l4_core_hwmod,
173 .slave = &omap2xxx_timer12_hwmod,
174 .clk = "gpt12_ick",
175 .user = OCP_USER_MPU | OCP_USER_SDMA,
176};
177
178/* l4_core -> dss */
179struct omap_hwmod_ocp_if omap2xxx_l4_core__dss = {
180 .master = &omap2xxx_l4_core_hwmod,
181 .slave = &omap2xxx_dss_core_hwmod,
182 .clk = "dss_ick",
183 .fw = {
184 .omap2 = {
185 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
186 .flags = OMAP_FIREWALL_L4,
187 },
188 },
189 .user = OCP_USER_MPU | OCP_USER_SDMA,
190};
191
192/* l4_core -> dss_dispc */
193struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc = {
194 .master = &omap2xxx_l4_core_hwmod,
195 .slave = &omap2xxx_dss_dispc_hwmod,
196 .clk = "dss_ick",
197 .fw = {
198 .omap2 = {
199 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
200 .flags = OMAP_FIREWALL_L4,
201 },
202 },
203 .user = OCP_USER_MPU | OCP_USER_SDMA,
204};
205
206/* l4_core -> dss_rfbi */
207struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi = {
208 .master = &omap2xxx_l4_core_hwmod,
209 .slave = &omap2xxx_dss_rfbi_hwmod,
210 .clk = "dss_ick",
211 .fw = {
212 .omap2 = {
213 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
214 .flags = OMAP_FIREWALL_L4,
215 },
216 },
217 .user = OCP_USER_MPU | OCP_USER_SDMA,
218};
219
220/* l4_core -> dss_venc */
221struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
222 .master = &omap2xxx_l4_core_hwmod,
223 .slave = &omap2xxx_dss_venc_hwmod,
224 .clk = "dss_ick",
225 .fw = {
226 .omap2 = {
227 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
228 .flags = OMAP_FIREWALL_L4,
229 },
230 },
231 .flags = OCPIF_SWSUP_IDLE,
232 .user = OCP_USER_MPU | OCP_USER_SDMA,
233};
234
235/* l4_core -> rng */
236struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
237 .master = &omap2xxx_l4_core_hwmod,
238 .slave = &omap2xxx_rng_hwmod,
239 .clk = "rng_ick",
240 .user = OCP_USER_MPU | OCP_USER_SDMA,
241};
242
243/* l4 core -> sham interface */
244struct omap_hwmod_ocp_if omap2xxx_l4_core__sham = {
245 .master = &omap2xxx_l4_core_hwmod,
246 .slave = &omap2xxx_sham_hwmod,
247 .clk = "sha_ick",
248 .user = OCP_USER_MPU | OCP_USER_SDMA,
249};
250
251/* l4 core -> aes interface */
252struct omap_hwmod_ocp_if omap2xxx_l4_core__aes = {
253 .master = &omap2xxx_l4_core_hwmod,
254 .slave = &omap2xxx_aes_hwmod,
255 .clk = "aes_ick",
256 .user = OCP_USER_MPU | OCP_USER_SDMA,
257};