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1/*
2 * Copyright (c) 2012 Linaro Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/init.h>
20#include <linux/linkage.h>
21#include <asm/assembler.h>
22#include <asm/virt.h>
23
24#ifndef ZIMAGE
25/*
26 * For the kernel proper, we need to find out the CPU boot mode long after
27 * boot, so we need to store it in a writable variable.
28 *
29 * This is not in .bss, because we set it sufficiently early that the boot-time
30 * zeroing of .bss would clobber it.
31 */
32.data
33ENTRY(__boot_cpu_mode)
34 .long 0
35.text
36
37 /*
38 * Save the primary CPU boot mode. Requires 3 scratch registers.
39 */
40 .macro store_primary_cpu_mode reg1, reg2, reg3
41 mrs \reg1, cpsr
42 and \reg1, \reg1, #MODE_MASK
43 adr \reg2, .L__boot_cpu_mode_offset
44 ldr \reg3, [\reg2]
45 str \reg1, [\reg2, \reg3]
46 .endm
47
48 /*
49 * Compare the current mode with the one saved on the primary CPU.
50 * If they don't match, record that fact. The Z bit indicates
51 * if there's a match or not.
52 * Requires 3 additionnal scratch registers.
53 */
54 .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3
55 adr \reg2, .L__boot_cpu_mode_offset
56 ldr \reg3, [\reg2]
57 ldr \reg1, [\reg2, \reg3]
58 cmp \mode, \reg1 @ matches primary CPU boot mode?
59 orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
60 strne \reg1, [\reg2, \reg3] @ record what happened and give up
61 .endm
62
63#else /* ZIMAGE */
64
65 .macro store_primary_cpu_mode reg1:req, reg2:req, reg3:req
66 .endm
67
68/*
69 * The zImage loader only runs on one CPU, so we don't bother with mult-CPU
70 * consistency checking:
71 */
72 .macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3
73 cmp \mode, \mode
74 .endm
75
76#endif /* ZIMAGE */
77
78/*
79 * Hypervisor stub installation functions.
80 *
81 * These must be called with the MMU and D-cache off.
82 * They are not ABI compliant and are only intended to be called from the kernel
83 * entry points in head.S.
84 */
85@ Call this from the primary CPU
86ENTRY(__hyp_stub_install)
87 store_primary_cpu_mode r4, r5, r6
88ENDPROC(__hyp_stub_install)
89
90 @ fall through...
91
92@ Secondary CPUs should call here
93ENTRY(__hyp_stub_install_secondary)
94 mrs r4, cpsr
95 and r4, r4, #MODE_MASK
96
97 /*
98 * If the secondary has booted with a different mode, give up
99 * immediately.
100 */
101 compare_cpu_mode_with_primary r4, r5, r6, r7
102 movne pc, lr
103
104 /*
105 * Once we have given up on one CPU, we do not try to install the
106 * stub hypervisor on the remaining ones: because the saved boot mode
107 * is modified, it can't compare equal to the CPSR mode field any
108 * more.
109 *
110 * Otherwise...
111 */
112
113 cmp r4, #HYP_MODE
114 movne pc, lr @ give up if the CPU is not in HYP mode
115
116/*
117 * Configure HSCTLR to set correct exception endianness/instruction set
118 * state etc.
119 * Turn off all traps
120 * Eventually, CPU-specific code might be needed -- assume not for now
121 *
122 * This code relies on the "eret" instruction to synchronize the
123 * various coprocessor accesses. This is done when we switch to SVC
124 * (see safe_svcmode_maskall).
125 */
126 @ Now install the hypervisor stub:
127 adr r7, __hyp_stub_vectors
128 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
129
130 @ Disable all traps, so we don't get any nasty surprise
131 mov r7, #0
132 mcr p15, 4, r7, c1, c1, 0 @ HCR
133 mcr p15, 4, r7, c1, c1, 2 @ HCPTR
134 mcr p15, 4, r7, c1, c1, 3 @ HSTR
135
136THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
137#ifdef CONFIG_CPU_BIG_ENDIAN
138 orr r7, #(1 << 9) @ HSCTLR.EE
139#endif
140 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
141
142 mrc p15, 4, r7, c1, c1, 1 @ HDCR
143 and r7, #0x1f @ Preserve HPMN
144 mcr p15, 4, r7, c1, c1, 1 @ HDCR
145
146#if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER)
147 @ make CNTP_* and CNTPCT accessible from PL1
148 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
149 lsr r7, #16
150 and r7, #0xf
151 cmp r7, #1
152 bne 1f
153 mrc p15, 4, r7, c14, c1, 0 @ CNTHCTL
154 orr r7, r7, #3 @ PL1PCEN | PL1PCTEN
155 mcr p15, 4, r7, c14, c1, 0 @ CNTHCTL
156 mov r7, #0
157 mcrr p15, 4, r7, r7, c14 @ CNTVOFF
158
159 @ Disable virtual timer in case it was counting
160 mrc p15, 0, r7, c14, c3, 1 @ CNTV_CTL
161 bic r7, #1 @ Clear ENABLE
162 mcr p15, 0, r7, c14, c3, 1 @ CNTV_CTL
1631:
164#endif
165
166 bx lr @ The boot CPU mode is left in r4.
167ENDPROC(__hyp_stub_install_secondary)
168
169__hyp_stub_do_trap:
170 cmp r0, #-1
171 mrceq p15, 4, r0, c12, c0, 0 @ get HVBAR
172 mcrne p15, 4, r0, c12, c0, 0 @ set HVBAR
173 __ERET
174ENDPROC(__hyp_stub_do_trap)
175
176/*
177 * __hyp_set_vectors: Call this after boot to set the initial hypervisor
178 * vectors as part of hypervisor installation. On an SMP system, this should
179 * be called on each CPU.
180 *
181 * r0 must be the physical address of the new vector table (which must lie in
182 * the bottom 4GB of physical address space.
183 *
184 * r0 must be 32-byte aligned.
185 *
186 * Before calling this, you must check that the stub hypervisor is installed
187 * everywhere, by waiting for any secondary CPUs to be brought up and then
188 * checking that BOOT_CPU_MODE_HAVE_HYP(__boot_cpu_mode) is true.
189 *
190 * If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
191 * something else went wrong... in such cases, trying to install a new
192 * hypervisor is unlikely to work as desired.
193 *
194 * When you call into your shiny new hypervisor, sp_hyp will contain junk,
195 * so you will need to set that to something sensible at the new hypervisor's
196 * initialisation entry point.
197 */
198ENTRY(__hyp_get_vectors)
199 mov r0, #-1
200ENDPROC(__hyp_get_vectors)
201 @ fall through
202ENTRY(__hyp_set_vectors)
203 __HVC(0)
204 mov pc, lr
205ENDPROC(__hyp_set_vectors)
206
207#ifndef ZIMAGE
208.align 2
209.L__boot_cpu_mode_offset:
210 .long __boot_cpu_mode - .
211#endif
212
213.align 5
214__hyp_stub_vectors:
215__hyp_stub_reset: W(b) .
216__hyp_stub_und: W(b) .
217__hyp_stub_svc: W(b) .
218__hyp_stub_pabort: W(b) .
219__hyp_stub_dabort: W(b) .
220__hyp_stub_trap: W(b) __hyp_stub_do_trap
221__hyp_stub_irq: W(b) .
222__hyp_stub_fiq: W(b) .
223ENDPROC(__hyp_stub_vectors)
224
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (c) 2012 Linaro Limited.
4 */
5
6#include <linux/init.h>
7#include <linux/irqchip/arm-gic-v3.h>
8#include <linux/linkage.h>
9#include <asm/assembler.h>
10#include <asm/virt.h>
11
12.arch armv7-a
13
14#ifndef ZIMAGE
15/*
16 * For the kernel proper, we need to find out the CPU boot mode long after
17 * boot, so we need to store it in a writable variable.
18 *
19 * This is not in .bss, because we set it sufficiently early that the boot-time
20 * zeroing of .bss would clobber it.
21 */
22.data
23 .align 2
24ENTRY(__boot_cpu_mode)
25 .long 0
26.text
27
28 /*
29 * Save the primary CPU boot mode. Requires 2 scratch registers.
30 */
31 .macro store_primary_cpu_mode reg1, reg2
32 mrs \reg1, cpsr
33 and \reg1, \reg1, #MODE_MASK
34 str_l \reg1, __boot_cpu_mode, \reg2
35 .endm
36
37 /*
38 * Compare the current mode with the one saved on the primary CPU.
39 * If they don't match, record that fact. The Z bit indicates
40 * if there's a match or not.
41 * Requires 2 additional scratch registers.
42 */
43 .macro compare_cpu_mode_with_primary mode, reg1, reg2
44 adr_l \reg2, __boot_cpu_mode
45 ldr \reg1, [\reg2]
46 cmp \mode, \reg1 @ matches primary CPU boot mode?
47 orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
48 strne \reg1, [\reg2] @ record what happened and give up
49 .endm
50
51#else /* ZIMAGE */
52
53 .macro store_primary_cpu_mode reg1:req, reg2:req
54 .endm
55
56/*
57 * The zImage loader only runs on one CPU, so we don't bother with mult-CPU
58 * consistency checking:
59 */
60 .macro compare_cpu_mode_with_primary mode, reg1, reg2
61 cmp \mode, \mode
62 .endm
63
64#endif /* ZIMAGE */
65
66/*
67 * Hypervisor stub installation functions.
68 *
69 * These must be called with the MMU and D-cache off.
70 * They are not ABI compliant and are only intended to be called from the kernel
71 * entry points in head.S.
72 */
73@ Call this from the primary CPU
74ENTRY(__hyp_stub_install)
75 store_primary_cpu_mode r4, r5
76ENDPROC(__hyp_stub_install)
77
78 @ fall through...
79
80@ Secondary CPUs should call here
81ENTRY(__hyp_stub_install_secondary)
82 mrs r4, cpsr
83 and r4, r4, #MODE_MASK
84
85 /*
86 * If the secondary has booted with a different mode, give up
87 * immediately.
88 */
89 compare_cpu_mode_with_primary r4, r5, r6
90 retne lr
91
92 /*
93 * Once we have given up on one CPU, we do not try to install the
94 * stub hypervisor on the remaining ones: because the saved boot mode
95 * is modified, it can't compare equal to the CPSR mode field any
96 * more.
97 *
98 * Otherwise...
99 */
100
101 cmp r4, #HYP_MODE
102 retne lr @ give up if the CPU is not in HYP mode
103
104/*
105 * Configure HSCTLR to set correct exception endianness/instruction set
106 * state etc.
107 * Turn off all traps
108 * Eventually, CPU-specific code might be needed -- assume not for now
109 *
110 * This code relies on the "eret" instruction to synchronize the
111 * various coprocessor accesses. This is done when we switch to SVC
112 * (see safe_svcmode_maskall).
113 */
114 @ Now install the hypervisor stub:
115 W(adr) r7, __hyp_stub_vectors
116 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
117
118 @ Disable all traps, so we don't get any nasty surprise
119 mov r7, #0
120 mcr p15, 4, r7, c1, c1, 0 @ HCR
121 mcr p15, 4, r7, c1, c1, 2 @ HCPTR
122 mcr p15, 4, r7, c1, c1, 3 @ HSTR
123
124THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
125ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE
126 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
127
128 mrc p15, 4, r7, c1, c1, 1 @ HDCR
129 and r7, #0x1f @ Preserve HPMN
130 mcr p15, 4, r7, c1, c1, 1 @ HDCR
131
132 @ Make sure NS-SVC is initialised appropriately
133 mrc p15, 0, r7, c1, c0, 0 @ SCTLR
134 orr r7, #(1 << 5) @ CP15 barriers enabled
135 bic r7, #(3 << 7) @ Clear SED/ITD for v8 (RES0 for v7)
136 bic r7, #(3 << 19) @ WXN and UWXN disabled
137 mcr p15, 0, r7, c1, c0, 0 @ SCTLR
138
139 mrc p15, 0, r7, c0, c0, 0 @ MIDR
140 mcr p15, 4, r7, c0, c0, 0 @ VPIDR
141
142 mrc p15, 0, r7, c0, c0, 5 @ MPIDR
143 mcr p15, 4, r7, c0, c0, 5 @ VMPIDR
144
145#if !defined(ZIMAGE) && defined(CONFIG_ARM_ARCH_TIMER)
146 @ make CNTP_* and CNTPCT accessible from PL1
147 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
148 ubfx r7, r7, #16, #4
149 teq r7, #0
150 beq 1f
151 mrc p15, 4, r7, c14, c1, 0 @ CNTHCTL
152 orr r7, r7, #3 @ PL1PCEN | PL1PCTEN
153 mcr p15, 4, r7, c14, c1, 0 @ CNTHCTL
154 mov r7, #0
155 mcrr p15, 4, r7, r7, c14 @ CNTVOFF
156
157 @ Disable virtual timer in case it was counting
158 mrc p15, 0, r7, c14, c3, 1 @ CNTV_CTL
159 bic r7, #1 @ Clear ENABLE
160 mcr p15, 0, r7, c14, c3, 1 @ CNTV_CTL
1611:
162#endif
163
164#ifdef CONFIG_ARM_GIC_V3
165 @ Check whether GICv3 system registers are available
166 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1
167 ubfx r7, r7, #28, #4
168 teq r7, #0
169 beq 2f
170
171 @ Enable system register accesses
172 mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
173 orr r7, r7, #(ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE)
174 mcr p15, 4, r7, c12, c9, 5 @ ICC_HSRE
175 isb
176
177 @ SRE bit could be forced to 0 by firmware.
178 @ Check whether it sticks before accessing any other sysreg
179 mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
180 tst r7, #ICC_SRE_EL2_SRE
181 beq 2f
182 mov r7, #0
183 mcr p15, 4, r7, c12, c11, 0 @ ICH_HCR
1842:
185#endif
186
187 bx lr @ The boot CPU mode is left in r4.
188ENDPROC(__hyp_stub_install_secondary)
189
190__hyp_stub_do_trap:
191#ifdef ZIMAGE
192 teq r0, #HVC_SET_VECTORS
193 bne 1f
194 /* Only the ZIMAGE stubs can change the HYP vectors */
195 mcr p15, 4, r1, c12, c0, 0 @ set HVBAR
196 b __hyp_stub_exit
197#endif
198
1991: teq r0, #HVC_SOFT_RESTART
200 bne 2f
201 bx r1
202
2032: ldr r0, =HVC_STUB_ERR
204 __ERET
205
206__hyp_stub_exit:
207 mov r0, #0
208 __ERET
209ENDPROC(__hyp_stub_do_trap)
210
211/*
212 * __hyp_set_vectors is only used when ZIMAGE must bounce between HYP
213 * and SVC. For the kernel itself, the vectors are set once and for
214 * all by the stubs.
215 */
216ENTRY(__hyp_set_vectors)
217 mov r1, r0
218 mov r0, #HVC_SET_VECTORS
219 __HVC(0)
220 ret lr
221ENDPROC(__hyp_set_vectors)
222
223ENTRY(__hyp_soft_restart)
224 mov r1, r0
225 mov r0, #HVC_SOFT_RESTART
226 __HVC(0)
227 ret lr
228ENDPROC(__hyp_soft_restart)
229
230.align 5
231ENTRY(__hyp_stub_vectors)
232__hyp_stub_reset: W(b) .
233__hyp_stub_und: W(b) .
234__hyp_stub_svc: W(b) .
235__hyp_stub_pabort: W(b) .
236__hyp_stub_dabort: W(b) .
237__hyp_stub_trap: W(b) __hyp_stub_do_trap
238__hyp_stub_irq: W(b) .
239__hyp_stub_fiq: W(b) .
240ENDPROC(__hyp_stub_vectors)
241