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1/*
2 * Xtensa built-in interrupt controller
3 *
4 * Copyright (C) 2002 - 2013 Tensilica, Inc.
5 * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 *
11 * Chris Zankel <chris@zankel.net>
12 * Kevin Chea
13 */
14
15#include <linux/interrupt.h>
16#include <linux/irqdomain.h>
17#include <linux/irq.h>
18#include <linux/of.h>
19
20#include "irqchip.h"
21
22unsigned int cached_irq_mask;
23
24/*
25 * Device Tree IRQ specifier translation function which works with one or
26 * two cell bindings. First cell value maps directly to the hwirq number.
27 * Second cell if present specifies whether hwirq number is external (1) or
28 * internal (0).
29 */
30static int xtensa_pic_irq_domain_xlate(struct irq_domain *d,
31 struct device_node *ctrlr,
32 const u32 *intspec, unsigned int intsize,
33 unsigned long *out_hwirq, unsigned int *out_type)
34{
35 return xtensa_irq_domain_xlate(intspec, intsize,
36 intspec[0], intspec[0],
37 out_hwirq, out_type);
38}
39
40static const struct irq_domain_ops xtensa_irq_domain_ops = {
41 .xlate = xtensa_pic_irq_domain_xlate,
42 .map = xtensa_irq_map,
43};
44
45static void xtensa_irq_mask(struct irq_data *d)
46{
47 cached_irq_mask &= ~(1 << d->hwirq);
48 set_sr(cached_irq_mask, intenable);
49}
50
51static void xtensa_irq_unmask(struct irq_data *d)
52{
53 cached_irq_mask |= 1 << d->hwirq;
54 set_sr(cached_irq_mask, intenable);
55}
56
57static void xtensa_irq_enable(struct irq_data *d)
58{
59 variant_irq_enable(d->hwirq);
60 xtensa_irq_unmask(d);
61}
62
63static void xtensa_irq_disable(struct irq_data *d)
64{
65 xtensa_irq_mask(d);
66 variant_irq_disable(d->hwirq);
67}
68
69static void xtensa_irq_ack(struct irq_data *d)
70{
71 set_sr(1 << d->hwirq, intclear);
72}
73
74static int xtensa_irq_retrigger(struct irq_data *d)
75{
76 set_sr(1 << d->hwirq, intset);
77 return 1;
78}
79
80static struct irq_chip xtensa_irq_chip = {
81 .name = "xtensa",
82 .irq_enable = xtensa_irq_enable,
83 .irq_disable = xtensa_irq_disable,
84 .irq_mask = xtensa_irq_mask,
85 .irq_unmask = xtensa_irq_unmask,
86 .irq_ack = xtensa_irq_ack,
87 .irq_retrigger = xtensa_irq_retrigger,
88};
89
90int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent)
91{
92 struct irq_domain *root_domain =
93 irq_domain_add_legacy(NULL, NR_IRQS, 0, 0,
94 &xtensa_irq_domain_ops, &xtensa_irq_chip);
95 irq_set_default_host(root_domain);
96 return 0;
97}
98
99static int __init xtensa_pic_init(struct device_node *np,
100 struct device_node *interrupt_parent)
101{
102 struct irq_domain *root_domain =
103 irq_domain_add_linear(np, NR_IRQS, &xtensa_irq_domain_ops,
104 &xtensa_irq_chip);
105 irq_set_default_host(root_domain);
106 return 0;
107}
108IRQCHIP_DECLARE(xtensa_irq_chip, "cdns,xtensa-pic", xtensa_pic_init);
1/*
2 * Xtensa built-in interrupt controller
3 *
4 * Copyright (C) 2002 - 2013 Tensilica, Inc.
5 * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 *
11 * Chris Zankel <chris@zankel.net>
12 * Kevin Chea
13 */
14
15#include <linux/bits.h>
16#include <linux/interrupt.h>
17#include <linux/irqdomain.h>
18#include <linux/irq.h>
19#include <linux/irqchip.h>
20#include <linux/irqchip/xtensa-pic.h>
21#include <linux/of.h>
22
23/*
24 * Device Tree IRQ specifier translation function which works with one or
25 * two cell bindings. First cell value maps directly to the hwirq number.
26 * Second cell if present specifies whether hwirq number is external (1) or
27 * internal (0).
28 */
29static int xtensa_pic_irq_domain_xlate(struct irq_domain *d,
30 struct device_node *ctrlr,
31 const u32 *intspec, unsigned int intsize,
32 unsigned long *out_hwirq, unsigned int *out_type)
33{
34 return xtensa_irq_domain_xlate(intspec, intsize,
35 intspec[0], intspec[0],
36 out_hwirq, out_type);
37}
38
39static const struct irq_domain_ops xtensa_irq_domain_ops = {
40 .xlate = xtensa_pic_irq_domain_xlate,
41 .map = xtensa_irq_map,
42};
43
44static void xtensa_irq_mask(struct irq_data *d)
45{
46 u32 irq_mask;
47
48 irq_mask = xtensa_get_sr(intenable);
49 irq_mask &= ~BIT(d->hwirq);
50 xtensa_set_sr(irq_mask, intenable);
51}
52
53static void xtensa_irq_unmask(struct irq_data *d)
54{
55 u32 irq_mask;
56
57 irq_mask = xtensa_get_sr(intenable);
58 irq_mask |= BIT(d->hwirq);
59 xtensa_set_sr(irq_mask, intenable);
60}
61
62static void xtensa_irq_ack(struct irq_data *d)
63{
64 xtensa_set_sr(BIT(d->hwirq), intclear);
65}
66
67static int xtensa_irq_retrigger(struct irq_data *d)
68{
69 unsigned int mask = BIT(d->hwirq);
70
71 if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
72 return 0;
73 xtensa_set_sr(mask, intset);
74 return 1;
75}
76
77static struct irq_chip xtensa_irq_chip = {
78 .name = "xtensa",
79 .irq_mask = xtensa_irq_mask,
80 .irq_unmask = xtensa_irq_unmask,
81 .irq_ack = xtensa_irq_ack,
82 .irq_retrigger = xtensa_irq_retrigger,
83};
84
85int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent)
86{
87 struct irq_domain *root_domain =
88 irq_domain_add_legacy(NULL, NR_IRQS - 1, 1, 0,
89 &xtensa_irq_domain_ops, &xtensa_irq_chip);
90 irq_set_default_host(root_domain);
91 return 0;
92}
93
94static int __init xtensa_pic_init(struct device_node *np,
95 struct device_node *interrupt_parent)
96{
97 struct irq_domain *root_domain =
98 irq_domain_add_linear(np, NR_IRQS, &xtensa_irq_domain_ops,
99 &xtensa_irq_chip);
100 irq_set_default_host(root_domain);
101 return 0;
102}
103IRQCHIP_DECLARE(xtensa_irq_chip, "cdns,xtensa-pic", xtensa_pic_init);