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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * drivers/dma/fsl-edma.c
4 *
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 *
7 * Driver for the Freescale eDMA engine with flexible channel multiplexing
8 * capability for DMA request sources. The eDMA block can be found on some
9 * Vybrid and Layerscape SoCs.
10 */
11
12#include <dt-bindings/dma/fsl-edma.h>
13#include <linux/bitfield.h>
14#include <linux/module.h>
15#include <linux/interrupt.h>
16#include <linux/clk.h>
17#include <linux/of.h>
18#include <linux/of_dma.h>
19#include <linux/dma-mapping.h>
20#include <linux/pm_runtime.h>
21#include <linux/pm_domain.h>
22#include <linux/property.h>
23
24#include "fsl-edma-common.h"
25
26static void fsl_edma_synchronize(struct dma_chan *chan)
27{
28 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
29
30 vchan_synchronize(&fsl_chan->vchan);
31}
32
33static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
34{
35 struct fsl_edma_engine *fsl_edma = dev_id;
36 unsigned int intr, ch;
37 struct edma_regs *regs = &fsl_edma->regs;
38
39 intr = edma_readl(fsl_edma, regs->intl);
40 if (!intr)
41 return IRQ_NONE;
42
43 for (ch = 0; ch < fsl_edma->n_chans; ch++) {
44 if (intr & (0x1 << ch)) {
45 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
46 fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]);
47 }
48 }
49 return IRQ_HANDLED;
50}
51
52static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id)
53{
54 struct fsl_edma_chan *fsl_chan = dev_id;
55 unsigned int intr;
56
57 intr = edma_readl_chreg(fsl_chan, ch_int);
58 if (!intr)
59 return IRQ_HANDLED;
60
61 edma_writel_chreg(fsl_chan, 1, ch_int);
62
63 fsl_edma_tx_chan_handler(fsl_chan);
64
65 return IRQ_HANDLED;
66}
67
68static irqreturn_t fsl_edma2_tx_handler(int irq, void *devi_id)
69{
70 struct fsl_edma_chan *fsl_chan = devi_id;
71
72 return fsl_edma_tx_handler(irq, fsl_chan->edma);
73}
74
75static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
76{
77 struct fsl_edma_engine *fsl_edma = dev_id;
78 unsigned int err, ch;
79 struct edma_regs *regs = &fsl_edma->regs;
80
81 err = edma_readl(fsl_edma, regs->errl);
82 if (!err)
83 return IRQ_NONE;
84
85 for (ch = 0; ch < fsl_edma->n_chans; ch++) {
86 if (err & (0x1 << ch)) {
87 fsl_edma_disable_request(&fsl_edma->chans[ch]);
88 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
89 fsl_edma_err_chan_handler(&fsl_edma->chans[ch]);
90 }
91 }
92 return IRQ_HANDLED;
93}
94
95static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id)
96{
97 if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED)
98 return IRQ_HANDLED;
99
100 return fsl_edma_err_handler(irq, dev_id);
101}
102
103static bool fsl_edma_srcid_in_use(struct fsl_edma_engine *fsl_edma, u32 srcid)
104{
105 struct fsl_edma_chan *fsl_chan;
106 int i;
107
108 for (i = 0; i < fsl_edma->n_chans; i++) {
109 fsl_chan = &fsl_edma->chans[i];
110
111 if (fsl_chan->srcid && srcid == fsl_chan->srcid) {
112 dev_err(&fsl_chan->pdev->dev, "The srcid is in use, can't use!");
113 return true;
114 }
115 }
116 return false;
117}
118
119static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
120 struct of_dma *ofdma)
121{
122 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
123 struct dma_chan *chan, *_chan;
124 struct fsl_edma_chan *fsl_chan;
125 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs;
126 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr;
127
128 if (dma_spec->args_count != 2)
129 return NULL;
130
131 guard(mutex)(&fsl_edma->fsl_edma_mutex);
132
133 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
134 if (chan->client_count)
135 continue;
136
137 if (fsl_edma_srcid_in_use(fsl_edma, dma_spec->args[1]))
138 return NULL;
139
140 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) {
141 chan = dma_get_slave_channel(chan);
142 if (chan) {
143 chan->device->privatecnt++;
144 fsl_chan = to_fsl_edma_chan(chan);
145 fsl_chan->srcid = dma_spec->args[1];
146
147 if (!fsl_chan->srcid) {
148 dev_err(&fsl_chan->pdev->dev, "Invalidate srcid %d\n",
149 fsl_chan->srcid);
150 return NULL;
151 }
152
153 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid,
154 true);
155 return chan;
156 }
157 }
158 }
159 return NULL;
160}
161
162static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,
163 struct of_dma *ofdma)
164{
165 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
166 struct dma_chan *chan, *_chan;
167 struct fsl_edma_chan *fsl_chan;
168 bool b_chmux;
169 int i;
170
171 if (dma_spec->args_count != 3)
172 return NULL;
173
174 b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX);
175
176 guard(mutex)(&fsl_edma->fsl_edma_mutex);
177 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels,
178 device_node) {
179
180 if (chan->client_count)
181 continue;
182
183 fsl_chan = to_fsl_edma_chan(chan);
184 if (fsl_edma_srcid_in_use(fsl_edma, dma_spec->args[0]))
185 return NULL;
186 i = fsl_chan - fsl_edma->chans;
187
188 fsl_chan->priority = dma_spec->args[1];
189 fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX;
190 fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE;
191 fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO;
192
193 if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1))
194 continue;
195
196 if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1))
197 continue;
198
199 if (!b_chmux && i == dma_spec->args[0]) {
200 chan = dma_get_slave_channel(chan);
201 chan->device->privatecnt++;
202 return chan;
203 } else if (b_chmux && !fsl_chan->srcid) {
204 /* if controller support channel mux, choose a free channel */
205 chan = dma_get_slave_channel(chan);
206 chan->device->privatecnt++;
207 fsl_chan->srcid = dma_spec->args[0];
208 return chan;
209 }
210 }
211 return NULL;
212}
213
214static int
215fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
216{
217 int ret;
218
219 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
220
221 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
222 if (fsl_edma->txirq < 0)
223 return fsl_edma->txirq;
224
225 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
226 if (fsl_edma->errirq < 0)
227 return fsl_edma->errirq;
228
229 if (fsl_edma->txirq == fsl_edma->errirq) {
230 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
231 fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
232 if (ret) {
233 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
234 return ret;
235 }
236 } else {
237 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
238 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
239 if (ret) {
240 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
241 return ret;
242 }
243
244 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
245 fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
246 if (ret) {
247 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
248 return ret;
249 }
250 }
251
252 return 0;
253}
254
255static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
256{
257 int i;
258
259 for (i = 0; i < fsl_edma->n_chans; i++) {
260
261 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
262
263 if (fsl_edma->chan_masked & BIT(i))
264 continue;
265
266 /* request channel irq */
267 fsl_chan->txirq = platform_get_irq(pdev, i);
268 if (fsl_chan->txirq < 0)
269 return -EINVAL;
270
271 fsl_chan->irq_handler = fsl_edma3_tx_handler;
272 }
273
274 return 0;
275}
276
277static int
278fsl_edma2_irq_init(struct platform_device *pdev,
279 struct fsl_edma_engine *fsl_edma)
280{
281 int i, ret, irq;
282 int count;
283
284 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
285
286 count = platform_irq_count(pdev);
287 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
288 if (count <= 2) {
289 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n");
290 return -EINVAL;
291 }
292 /*
293 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp.
294 * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17...
295 * For now, just simply request irq without IRQF_SHARED flag, since 16
296 * channels are enough on i.mx7ulp whose M4 domain own some peripherals.
297 */
298 for (i = 0; i < count; i++) {
299 irq = platform_get_irq(pdev, i);
300 ret = 0;
301 if (irq < 0)
302 return -ENXIO;
303
304 /* The last IRQ is for eDMA err */
305 if (i == count - 1) {
306 ret = devm_request_irq(&pdev->dev, irq,
307 fsl_edma_err_handler,
308 0, "eDMA2-ERR", fsl_edma);
309 } else {
310 fsl_edma->chans[i].txirq = irq;
311 fsl_edma->chans[i].irq_handler = fsl_edma2_tx_handler;
312 }
313
314 if (ret)
315 return ret;
316 }
317
318 return 0;
319}
320
321static void fsl_edma_irq_exit(
322 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
323{
324 if (fsl_edma->txirq == fsl_edma->errirq) {
325 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
326 } else {
327 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
328 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
329 }
330}
331
332static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
333{
334 int i;
335
336 for (i = 0; i < nr_clocks; i++)
337 clk_disable_unprepare(fsl_edma->muxclk[i]);
338}
339
340static struct fsl_edma_drvdata vf610_data = {
341 .dmamuxs = DMAMUX_NR,
342 .flags = FSL_EDMA_DRV_WRAP_IO,
343 .chreg_off = EDMA_TCD,
344 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
345 .setup_irq = fsl_edma_irq_init,
346};
347
348static struct fsl_edma_drvdata ls1028a_data = {
349 .dmamuxs = DMAMUX_NR,
350 .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO,
351 .chreg_off = EDMA_TCD,
352 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
353 .setup_irq = fsl_edma_irq_init,
354};
355
356static struct fsl_edma_drvdata imx7ulp_data = {
357 .dmamuxs = 1,
358 .chreg_off = EDMA_TCD,
359 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
360 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32,
361 .setup_irq = fsl_edma2_irq_init,
362};
363
364static struct fsl_edma_drvdata imx8qm_data = {
365 .flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_MEM_REMOTE,
366 .chreg_space_sz = 0x10000,
367 .chreg_off = 0x10000,
368 .setup_irq = fsl_edma3_irq_init,
369};
370
371static struct fsl_edma_drvdata imx8ulp_data = {
372 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_CHCLK | FSL_EDMA_DRV_HAS_DMACLK |
373 FSL_EDMA_DRV_EDMA3,
374 .chreg_space_sz = 0x10000,
375 .chreg_off = 0x10000,
376 .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux),
377 .mux_skip = 0x10000,
378 .setup_irq = fsl_edma3_irq_init,
379};
380
381static struct fsl_edma_drvdata imx93_data3 = {
382 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3,
383 .chreg_space_sz = 0x10000,
384 .chreg_off = 0x10000,
385 .setup_irq = fsl_edma3_irq_init,
386};
387
388static struct fsl_edma_drvdata imx93_data4 = {
389 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4,
390 .chreg_space_sz = 0x8000,
391 .chreg_off = 0x10000,
392 .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux),
393 .mux_skip = 0x8000,
394 .setup_irq = fsl_edma3_irq_init,
395};
396
397static struct fsl_edma_drvdata imx95_data5 = {
398 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4 |
399 FSL_EDMA_DRV_TCD64,
400 .chreg_space_sz = 0x8000,
401 .chreg_off = 0x10000,
402 .mux_off = 0x200,
403 .mux_skip = sizeof(u32),
404 .setup_irq = fsl_edma3_irq_init,
405};
406
407static const struct of_device_id fsl_edma_dt_ids[] = {
408 { .compatible = "fsl,vf610-edma", .data = &vf610_data},
409 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
410 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
411 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data},
412 { .compatible = "fsl,imx8ulp-edma", .data = &imx8ulp_data},
413 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3},
414 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4},
415 { .compatible = "fsl,imx95-edma5", .data = &imx95_data5},
416 { /* sentinel */ }
417};
418MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
419
420static void fsl_edma3_detach_pd(struct fsl_edma_engine *fsl_edma)
421{
422 struct fsl_edma_chan *fsl_chan;
423 int i;
424
425 for (i = 0; i < fsl_edma->n_chans; i++) {
426 if (fsl_edma->chan_masked & BIT(i))
427 continue;
428 fsl_chan = &fsl_edma->chans[i];
429 if (fsl_chan->pd_dev_link)
430 device_link_del(fsl_chan->pd_dev_link);
431 if (fsl_chan->pd_dev) {
432 dev_pm_domain_detach(fsl_chan->pd_dev, false);
433 pm_runtime_dont_use_autosuspend(fsl_chan->pd_dev);
434 pm_runtime_set_suspended(fsl_chan->pd_dev);
435 }
436 }
437}
438
439static void devm_fsl_edma3_detach_pd(void *data)
440{
441 fsl_edma3_detach_pd(data);
442}
443
444static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
445{
446 struct fsl_edma_chan *fsl_chan;
447 struct device *pd_chan;
448 struct device *dev;
449 int i;
450
451 dev = &pdev->dev;
452
453 for (i = 0; i < fsl_edma->n_chans; i++) {
454 if (fsl_edma->chan_masked & BIT(i))
455 continue;
456
457 fsl_chan = &fsl_edma->chans[i];
458
459 pd_chan = dev_pm_domain_attach_by_id(dev, i);
460 if (IS_ERR_OR_NULL(pd_chan)) {
461 dev_err(dev, "Failed attach pd %d\n", i);
462 goto detach;
463 }
464
465 fsl_chan->pd_dev_link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS |
466 DL_FLAG_PM_RUNTIME |
467 DL_FLAG_RPM_ACTIVE);
468 if (!fsl_chan->pd_dev_link) {
469 dev_err(dev, "Failed to add device_link to %d\n", i);
470 dev_pm_domain_detach(pd_chan, false);
471 goto detach;
472 }
473
474 fsl_chan->pd_dev = pd_chan;
475
476 pm_runtime_use_autosuspend(fsl_chan->pd_dev);
477 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200);
478 pm_runtime_set_active(fsl_chan->pd_dev);
479 }
480
481 return 0;
482
483detach:
484 fsl_edma3_detach_pd(fsl_edma);
485 return -EINVAL;
486}
487
488static int fsl_edma_probe(struct platform_device *pdev)
489{
490 struct device_node *np = pdev->dev.of_node;
491 struct fsl_edma_engine *fsl_edma;
492 const struct fsl_edma_drvdata *drvdata = NULL;
493 u32 chan_mask[2] = {0, 0};
494 char clk_name[36];
495 struct edma_regs *regs;
496 int chans;
497 int ret, i;
498
499 drvdata = device_get_match_data(&pdev->dev);
500 if (!drvdata) {
501 dev_err(&pdev->dev, "unable to find driver data\n");
502 return -EINVAL;
503 }
504
505 ret = of_property_read_u32(np, "dma-channels", &chans);
506 if (ret) {
507 dev_err(&pdev->dev, "Can't get dma-channels.\n");
508 return ret;
509 }
510
511 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans),
512 GFP_KERNEL);
513 if (!fsl_edma)
514 return -ENOMEM;
515
516 fsl_edma->drvdata = drvdata;
517 fsl_edma->n_chans = chans;
518 mutex_init(&fsl_edma->fsl_edma_mutex);
519
520 fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0);
521 if (IS_ERR(fsl_edma->membase))
522 return PTR_ERR(fsl_edma->membase);
523
524 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) {
525 fsl_edma_setup_regs(fsl_edma);
526 regs = &fsl_edma->regs;
527 }
528
529 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) {
530 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma");
531 if (IS_ERR(fsl_edma->dmaclk)) {
532 dev_err(&pdev->dev, "Missing DMA block clock.\n");
533 return PTR_ERR(fsl_edma->dmaclk);
534 }
535 }
536
537 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2);
538
539 if (ret > 0) {
540 fsl_edma->chan_masked = chan_mask[1];
541 fsl_edma->chan_masked <<= 32;
542 fsl_edma->chan_masked |= chan_mask[0];
543 }
544
545 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
546 char clkname[32];
547
548 /* eDMAv3 mux register move to TCD area if ch_mux exist */
549 if (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)
550 break;
551
552 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev,
553 1 + i);
554 if (IS_ERR(fsl_edma->muxbase[i])) {
555 /* on error: disable all previously enabled clks */
556 fsl_disable_clocks(fsl_edma, i);
557 return PTR_ERR(fsl_edma->muxbase[i]);
558 }
559
560 sprintf(clkname, "dmamux%d", i);
561 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname);
562 if (IS_ERR(fsl_edma->muxclk[i])) {
563 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
564 /* on error: disable all previously enabled clks */
565 return PTR_ERR(fsl_edma->muxclk[i]);
566 }
567 }
568
569 fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
570
571 if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) {
572 ret = fsl_edma3_attach_pd(pdev, fsl_edma);
573 if (ret)
574 return ret;
575 ret = devm_add_action_or_reset(&pdev->dev, devm_fsl_edma3_detach_pd, fsl_edma);
576 if (ret)
577 return ret;
578 }
579
580 if (drvdata->flags & FSL_EDMA_DRV_TCD64)
581 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
582
583 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
584 for (i = 0; i < fsl_edma->n_chans; i++) {
585 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
586 int len;
587
588 if (fsl_edma->chan_masked & BIT(i))
589 continue;
590
591 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d",
592 dev_name(&pdev->dev), i);
593
594 fsl_chan->edma = fsl_edma;
595 fsl_chan->pm_state = RUNNING;
596 fsl_chan->srcid = 0;
597 fsl_chan->dma_dir = DMA_NONE;
598 fsl_chan->vchan.desc_free = fsl_edma_free_desc;
599
600 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ?
601 offsetof(struct fsl_edma3_ch_reg, tcd) : 0;
602 fsl_chan->tcd = fsl_edma->membase
603 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len;
604 fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip;
605
606 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) {
607 snprintf(clk_name, sizeof(clk_name), "ch%02d", i);
608 fsl_chan->clk = devm_clk_get_enabled(&pdev->dev,
609 (const char *)clk_name);
610
611 if (IS_ERR(fsl_chan->clk))
612 return PTR_ERR(fsl_chan->clk);
613 }
614 fsl_chan->pdev = pdev;
615 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
616
617 edma_write_tcdreg(fsl_chan, cpu_to_le32(0), csr);
618 fsl_edma_chan_mux(fsl_chan, 0, false);
619 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK)
620 clk_disable_unprepare(fsl_chan->clk);
621 }
622
623 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
624 if (ret)
625 return ret;
626
627 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
628 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
629 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
630 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask);
631
632 fsl_edma->dma_dev.dev = &pdev->dev;
633 fsl_edma->dma_dev.device_alloc_chan_resources
634 = fsl_edma_alloc_chan_resources;
635 fsl_edma->dma_dev.device_free_chan_resources
636 = fsl_edma_free_chan_resources;
637 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
638 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
639 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
640 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy;
641 fsl_edma->dma_dev.device_config = fsl_edma_slave_config;
642 fsl_edma->dma_dev.device_pause = fsl_edma_pause;
643 fsl_edma->dma_dev.device_resume = fsl_edma_resume;
644 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
645 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize;
646 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
647
648 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
649 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
650
651 if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) {
652 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
653 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
654 }
655
656 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
657 if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV)
658 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV);
659
660 fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ?
661 DMAENGINE_ALIGN_64_BYTES :
662 DMAENGINE_ALIGN_32_BYTES;
663
664 /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */
665 dma_set_max_seg_size(fsl_edma->dma_dev.dev,
666 FIELD_GET(EDMA_TCD_ITER_MASK, EDMA_TCD_ITER_MASK));
667
668 fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
669
670 platform_set_drvdata(pdev, fsl_edma);
671
672 ret = dma_async_device_register(&fsl_edma->dma_dev);
673 if (ret) {
674 dev_err(&pdev->dev,
675 "Can't register Freescale eDMA engine. (%d)\n", ret);
676 return ret;
677 }
678
679 ret = of_dma_controller_register(np,
680 drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate : fsl_edma_xlate,
681 fsl_edma);
682 if (ret) {
683 dev_err(&pdev->dev,
684 "Can't register Freescale eDMA of_dma. (%d)\n", ret);
685 dma_async_device_unregister(&fsl_edma->dma_dev);
686 return ret;
687 }
688
689 /* enable round robin arbitration */
690 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
691 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
692
693 return 0;
694}
695
696static void fsl_edma_remove(struct platform_device *pdev)
697{
698 struct device_node *np = pdev->dev.of_node;
699 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
700
701 fsl_edma_irq_exit(pdev, fsl_edma);
702 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
703 of_dma_controller_free(np);
704 dma_async_device_unregister(&fsl_edma->dma_dev);
705 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
706}
707
708static int fsl_edma_suspend_late(struct device *dev)
709{
710 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
711 struct fsl_edma_chan *fsl_chan;
712 unsigned long flags;
713 int i;
714
715 for (i = 0; i < fsl_edma->n_chans; i++) {
716 fsl_chan = &fsl_edma->chans[i];
717 if (fsl_edma->chan_masked & BIT(i))
718 continue;
719 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
720 /* Make sure chan is idle or will force disable. */
721 if (unlikely(fsl_chan->status == DMA_IN_PROGRESS)) {
722 dev_warn(dev, "WARN: There is non-idle channel.");
723 fsl_edma_disable_request(fsl_chan);
724 fsl_edma_chan_mux(fsl_chan, 0, false);
725 }
726
727 fsl_chan->pm_state = SUSPENDED;
728 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
729 }
730
731 return 0;
732}
733
734static int fsl_edma_resume_early(struct device *dev)
735{
736 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
737 struct fsl_edma_chan *fsl_chan;
738 struct edma_regs *regs = &fsl_edma->regs;
739 int i;
740
741 for (i = 0; i < fsl_edma->n_chans; i++) {
742 fsl_chan = &fsl_edma->chans[i];
743 if (fsl_edma->chan_masked & BIT(i))
744 continue;
745 fsl_chan->pm_state = RUNNING;
746 edma_write_tcdreg(fsl_chan, 0, csr);
747 if (fsl_chan->srcid != 0)
748 fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, true);
749 }
750
751 if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
752 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
753
754 return 0;
755}
756
757/*
758 * eDMA provides the service to others, so it should be suspend late
759 * and resume early. When eDMA suspend, all of the clients should stop
760 * the DMA data transmission and let the channel idle.
761 */
762static const struct dev_pm_ops fsl_edma_pm_ops = {
763 .suspend_late = fsl_edma_suspend_late,
764 .resume_early = fsl_edma_resume_early,
765};
766
767static struct platform_driver fsl_edma_driver = {
768 .driver = {
769 .name = "fsl-edma",
770 .of_match_table = fsl_edma_dt_ids,
771 .pm = &fsl_edma_pm_ops,
772 },
773 .probe = fsl_edma_probe,
774 .remove = fsl_edma_remove,
775};
776
777static int __init fsl_edma_init(void)
778{
779 return platform_driver_register(&fsl_edma_driver);
780}
781subsys_initcall(fsl_edma_init);
782
783static void __exit fsl_edma_exit(void)
784{
785 platform_driver_unregister(&fsl_edma_driver);
786}
787module_exit(fsl_edma_exit);
788
789MODULE_ALIAS("platform:fsl-edma");
790MODULE_DESCRIPTION("Freescale eDMA engine driver");
791MODULE_LICENSE("GPL v2");