1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Amlogic Meson-G12A Clock Controller Driver
   4 *
   5 * Copyright (c) 2016 Baylibre SAS.
   6 * Author: Michael Turquette <mturquette@baylibre.com>
   7 *
   8 * Copyright (c) 2018 Amlogic, inc.
   9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
  10 * Author: Jian Hu <jian.hu@amlogic.com>
  11 */
  12
  13#include <linux/clk-provider.h>
  14#include <linux/init.h>
  15#include <linux/of.h>
  16#include <linux/platform_device.h>
  17#include <linux/clk.h>
  18#include <linux/module.h>
  19
  20#include "clk-mpll.h"
  21#include "clk-pll.h"
  22#include "clk-regmap.h"
  23#include "clk-cpu-dyndiv.h"
  24#include "vid-pll-div.h"
  25#include "vclk.h"
  26#include "meson-eeclk.h"
  27#include "g12a.h"
  28
  29#include <dt-bindings/clock/g12a-clkc.h>
  30
  31static struct clk_regmap g12a_fixed_pll_dco = {
  32	.data = &(struct meson_clk_pll_data){
  33		.en = {
  34			.reg_off = HHI_FIX_PLL_CNTL0,
  35			.shift   = 28,
  36			.width   = 1,
  37		},
  38		.m = {
  39			.reg_off = HHI_FIX_PLL_CNTL0,
  40			.shift   = 0,
  41			.width   = 8,
  42		},
  43		.n = {
  44			.reg_off = HHI_FIX_PLL_CNTL0,
  45			.shift   = 10,
  46			.width   = 5,
  47		},
  48		.frac = {
  49			.reg_off = HHI_FIX_PLL_CNTL1,
  50			.shift   = 0,
  51			.width   = 17,
  52		},
  53		.l = {
  54			.reg_off = HHI_FIX_PLL_CNTL0,
  55			.shift   = 31,
  56			.width   = 1,
  57		},
  58		.rst = {
  59			.reg_off = HHI_FIX_PLL_CNTL0,
  60			.shift   = 29,
  61			.width   = 1,
  62		},
  63	},
  64	.hw.init = &(struct clk_init_data){
  65		.name = "fixed_pll_dco",
  66		.ops = &meson_clk_pll_ro_ops,
  67		.parent_data = &(const struct clk_parent_data) {
  68			.fw_name = "xtal",
  69		},
  70		.num_parents = 1,
  71	},
  72};
  73
  74static struct clk_regmap g12a_fixed_pll = {
  75	.data = &(struct clk_regmap_div_data){
  76		.offset = HHI_FIX_PLL_CNTL0,
  77		.shift = 16,
  78		.width = 2,
  79		.flags = CLK_DIVIDER_POWER_OF_TWO,
  80	},
  81	.hw.init = &(struct clk_init_data){
  82		.name = "fixed_pll",
  83		.ops = &clk_regmap_divider_ro_ops,
  84		.parent_hws = (const struct clk_hw *[]) {
  85			&g12a_fixed_pll_dco.hw
  86		},
  87		.num_parents = 1,
  88		/*
  89		 * This clock won't ever change at runtime so
  90		 * CLK_SET_RATE_PARENT is not required
  91		 */
  92	},
  93};
  94
  95static const struct pll_mult_range g12a_sys_pll_mult_range = {
  96	.min = 128,
  97	.max = 250,
  98};
  99
 100static struct clk_regmap g12a_sys_pll_dco = {
 101	.data = &(struct meson_clk_pll_data){
 102		.en = {
 103			.reg_off = HHI_SYS_PLL_CNTL0,
 104			.shift   = 28,
 105			.width   = 1,
 106		},
 107		.m = {
 108			.reg_off = HHI_SYS_PLL_CNTL0,
 109			.shift   = 0,
 110			.width   = 8,
 111		},
 112		.n = {
 113			.reg_off = HHI_SYS_PLL_CNTL0,
 114			.shift   = 10,
 115			.width   = 5,
 116		},
 117		.l = {
 118			.reg_off = HHI_SYS_PLL_CNTL0,
 119			.shift   = 31,
 120			.width   = 1,
 121		},
 122		.rst = {
 123			.reg_off = HHI_SYS_PLL_CNTL0,
 124			.shift   = 29,
 125			.width   = 1,
 126		},
 127		.range = &g12a_sys_pll_mult_range,
 128	},
 129	.hw.init = &(struct clk_init_data){
 130		.name = "sys_pll_dco",
 131		.ops = &meson_clk_pll_ops,
 132		.parent_data = &(const struct clk_parent_data) {
 133			.fw_name = "xtal",
 134		},
 135		.num_parents = 1,
 136		/* This clock feeds the CPU, avoid disabling it */
 137		.flags = CLK_IS_CRITICAL,
 138	},
 139};
 140
 141static struct clk_regmap g12a_sys_pll = {
 142	.data = &(struct clk_regmap_div_data){
 143		.offset = HHI_SYS_PLL_CNTL0,
 144		.shift = 16,
 145		.width = 3,
 146		.flags = CLK_DIVIDER_POWER_OF_TWO,
 147	},
 148	.hw.init = &(struct clk_init_data){
 149		.name = "sys_pll",
 150		.ops = &clk_regmap_divider_ops,
 151		.parent_hws = (const struct clk_hw *[]) {
 152			&g12a_sys_pll_dco.hw
 153		},
 154		.num_parents = 1,
 155		.flags = CLK_SET_RATE_PARENT,
 156	},
 157};
 158
 159static struct clk_regmap g12b_sys1_pll_dco = {
 160	.data = &(struct meson_clk_pll_data){
 161		.en = {
 162			.reg_off = HHI_SYS1_PLL_CNTL0,
 163			.shift   = 28,
 164			.width   = 1,
 165		},
 166		.m = {
 167			.reg_off = HHI_SYS1_PLL_CNTL0,
 168			.shift   = 0,
 169			.width   = 8,
 170		},
 171		.n = {
 172			.reg_off = HHI_SYS1_PLL_CNTL0,
 173			.shift   = 10,
 174			.width   = 5,
 175		},
 176		.l = {
 177			.reg_off = HHI_SYS1_PLL_CNTL0,
 178			.shift   = 31,
 179			.width   = 1,
 180		},
 181		.rst = {
 182			.reg_off = HHI_SYS1_PLL_CNTL0,
 183			.shift   = 29,
 184			.width   = 1,
 185		},
 186		.range = &g12a_sys_pll_mult_range,
 187	},
 188	.hw.init = &(struct clk_init_data){
 189		.name = "sys1_pll_dco",
 190		.ops = &meson_clk_pll_ops,
 191		.parent_data = &(const struct clk_parent_data) {
 192			.fw_name = "xtal",
 193		},
 194		.num_parents = 1,
 195		/* This clock feeds the CPU, avoid disabling it */
 196		.flags = CLK_IS_CRITICAL,
 197	},
 198};
 199
 200static struct clk_regmap g12b_sys1_pll = {
 201	.data = &(struct clk_regmap_div_data){
 202		.offset = HHI_SYS1_PLL_CNTL0,
 203		.shift = 16,
 204		.width = 3,
 205		.flags = CLK_DIVIDER_POWER_OF_TWO,
 206	},
 207	.hw.init = &(struct clk_init_data){
 208		.name = "sys1_pll",
 209		.ops = &clk_regmap_divider_ops,
 210		.parent_hws = (const struct clk_hw *[]) {
 211			&g12b_sys1_pll_dco.hw
 212		},
 213		.num_parents = 1,
 214		.flags = CLK_SET_RATE_PARENT,
 215	},
 216};
 217
 218static struct clk_regmap g12a_sys_pll_div16_en = {
 219	.data = &(struct clk_regmap_gate_data){
 220		.offset = HHI_SYS_CPU_CLK_CNTL1,
 221		.bit_idx = 24,
 222	},
 223	.hw.init = &(struct clk_init_data) {
 224		.name = "sys_pll_div16_en",
 225		.ops = &clk_regmap_gate_ro_ops,
 226		.parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
 227		.num_parents = 1,
 228		/*
 229		 * This clock is used to debug the sys_pll range
 230		 * Linux should not change it at runtime
 231		 */
 232	},
 233};
 234
 235static struct clk_regmap g12b_sys1_pll_div16_en = {
 236	.data = &(struct clk_regmap_gate_data){
 237		.offset = HHI_SYS_CPUB_CLK_CNTL1,
 238		.bit_idx = 24,
 239	},
 240	.hw.init = &(struct clk_init_data) {
 241		.name = "sys1_pll_div16_en",
 242		.ops = &clk_regmap_gate_ro_ops,
 243		.parent_hws = (const struct clk_hw *[]) {
 244			&g12b_sys1_pll.hw
 245		},
 246		.num_parents = 1,
 247		/*
 248		 * This clock is used to debug the sys_pll range
 249		 * Linux should not change it at runtime
 250		 */
 251	},
 252};
 253
 254static struct clk_fixed_factor g12a_sys_pll_div16 = {
 255	.mult = 1,
 256	.div = 16,
 257	.hw.init = &(struct clk_init_data){
 258		.name = "sys_pll_div16",
 259		.ops = &clk_fixed_factor_ops,
 260		.parent_hws = (const struct clk_hw *[]) {
 261			&g12a_sys_pll_div16_en.hw
 262		},
 263		.num_parents = 1,
 264	},
 265};
 266
 267static struct clk_fixed_factor g12b_sys1_pll_div16 = {
 268	.mult = 1,
 269	.div = 16,
 270	.hw.init = &(struct clk_init_data){
 271		.name = "sys1_pll_div16",
 272		.ops = &clk_fixed_factor_ops,
 273		.parent_hws = (const struct clk_hw *[]) {
 274			&g12b_sys1_pll_div16_en.hw
 275		},
 276		.num_parents = 1,
 277	},
 278};
 279
 280static struct clk_fixed_factor g12a_fclk_div2_div = {
 281	.mult = 1,
 282	.div = 2,
 283	.hw.init = &(struct clk_init_data){
 284		.name = "fclk_div2_div",
 285		.ops = &clk_fixed_factor_ops,
 286		.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
 287		.num_parents = 1,
 288	},
 289};
 290
 291static struct clk_regmap g12a_fclk_div2 = {
 292	.data = &(struct clk_regmap_gate_data){
 293		.offset = HHI_FIX_PLL_CNTL1,
 294		.bit_idx = 24,
 295	},
 296	.hw.init = &(struct clk_init_data){
 297		.name = "fclk_div2",
 298		.ops = &clk_regmap_gate_ops,
 299		.parent_hws = (const struct clk_hw *[]) {
 300			&g12a_fclk_div2_div.hw
 301		},
 302		.num_parents = 1,
 303		/*
 304		 * Similar to fclk_div3, it seems that this clock is used by
 305		 * the resident firmware and is required by the platform to
 306		 * operate correctly.
 307		 * Until the following condition are met, we need this clock to
 308		 * be marked as critical:
 309		 * a) Mark the clock used by a firmware resource, if possible
 310		 * b) CCF has a clock hand-off mechanism to make the sure the
 311		 *    clock stays on until the proper driver comes along
 312		 */
 313		.flags = CLK_IS_CRITICAL,
 314	},
 315};
 316
 317static struct clk_fixed_factor g12a_fclk_div3_div = {
 318	.mult = 1,
 319	.div = 3,
 320	.hw.init = &(struct clk_init_data){
 321		.name = "fclk_div3_div",
 322		.ops = &clk_fixed_factor_ops,
 323		.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
 324		.num_parents = 1,
 325	},
 326};
 327
 328static struct clk_regmap g12a_fclk_div3 = {
 329	.data = &(struct clk_regmap_gate_data){
 330		.offset = HHI_FIX_PLL_CNTL1,
 331		.bit_idx = 20,
 332	},
 333	.hw.init = &(struct clk_init_data){
 334		.name = "fclk_div3",
 335		.ops = &clk_regmap_gate_ops,
 336		.parent_hws = (const struct clk_hw *[]) {
 337			&g12a_fclk_div3_div.hw
 338		},
 339		.num_parents = 1,
 340		/*
 341		 * This clock is used by the resident firmware and is required
 342		 * by the platform to operate correctly.
 343		 * Until the following condition are met, we need this clock to
 344		 * be marked as critical:
 345		 * a) Mark the clock used by a firmware resource, if possible
 346		 * b) CCF has a clock hand-off mechanism to make the sure the
 347		 *    clock stays on until the proper driver comes along
 348		 */
 349		.flags = CLK_IS_CRITICAL,
 350	},
 351};
 352
 353/* Datasheet names this field as "premux0" */
 354static struct clk_regmap g12a_cpu_clk_premux0 = {
 355	.data = &(struct clk_regmap_mux_data){
 356		.offset = HHI_SYS_CPU_CLK_CNTL0,
 357		.mask = 0x3,
 358		.shift = 0,
 359		.flags = CLK_MUX_ROUND_CLOSEST,
 360	},
 361	.hw.init = &(struct clk_init_data){
 362		.name = "cpu_clk_dyn0_sel",
 363		.ops = &clk_regmap_mux_ops,
 364		.parent_data = (const struct clk_parent_data []) {
 365			{ .fw_name = "xtal", },
 366			{ .hw = &g12a_fclk_div2.hw },
 367			{ .hw = &g12a_fclk_div3.hw },
 368		},
 369		.num_parents = 3,
 370		.flags = CLK_SET_RATE_PARENT,
 371	},
 372};
 373
 374/* Datasheet names this field as "premux1" */
 375static struct clk_regmap g12a_cpu_clk_premux1 = {
 376	.data = &(struct clk_regmap_mux_data){
 377		.offset = HHI_SYS_CPU_CLK_CNTL0,
 378		.mask = 0x3,
 379		.shift = 16,
 380	},
 381	.hw.init = &(struct clk_init_data){
 382		.name = "cpu_clk_dyn1_sel",
 383		.ops = &clk_regmap_mux_ops,
 384		.parent_data = (const struct clk_parent_data []) {
 385			{ .fw_name = "xtal", },
 386			{ .hw = &g12a_fclk_div2.hw },
 387			{ .hw = &g12a_fclk_div3.hw },
 388		},
 389		.num_parents = 3,
 390		/* This sub-tree is used a parking clock */
 391		.flags = CLK_SET_RATE_NO_REPARENT
 392	},
 393};
 394
 395/* Datasheet names this field as "mux0_divn_tcnt" */
 396static struct clk_regmap g12a_cpu_clk_mux0_div = {
 397	.data = &(struct meson_clk_cpu_dyndiv_data){
 398		.div = {
 399			.reg_off = HHI_SYS_CPU_CLK_CNTL0,
 400			.shift = 4,
 401			.width = 6,
 402		},
 403		.dyn = {
 404			.reg_off = HHI_SYS_CPU_CLK_CNTL0,
 405			.shift = 26,
 406			.width = 1,
 407		},
 408	},
 409	.hw.init = &(struct clk_init_data){
 410		.name = "cpu_clk_dyn0_div",
 411		.ops = &meson_clk_cpu_dyndiv_ops,
 412		.parent_hws = (const struct clk_hw *[]) {
 413			&g12a_cpu_clk_premux0.hw
 414		},
 415		.num_parents = 1,
 416		.flags = CLK_SET_RATE_PARENT,
 417	},
 418};
 419
 420/* Datasheet names this field as "postmux0" */
 421static struct clk_regmap g12a_cpu_clk_postmux0 = {
 422	.data = &(struct clk_regmap_mux_data){
 423		.offset = HHI_SYS_CPU_CLK_CNTL0,
 424		.mask = 0x1,
 425		.shift = 2,
 426		.flags = CLK_MUX_ROUND_CLOSEST,
 427	},
 428	.hw.init = &(struct clk_init_data){
 429		.name = "cpu_clk_dyn0",
 430		.ops = &clk_regmap_mux_ops,
 431		.parent_hws = (const struct clk_hw *[]) {
 432			&g12a_cpu_clk_premux0.hw,
 433			&g12a_cpu_clk_mux0_div.hw,
 434		},
 435		.num_parents = 2,
 436		.flags = CLK_SET_RATE_PARENT,
 437	},
 438};
 439
 440/* Datasheet names this field as "Mux1_divn_tcnt" */
 441static struct clk_regmap g12a_cpu_clk_mux1_div = {
 442	.data = &(struct clk_regmap_div_data){
 443		.offset = HHI_SYS_CPU_CLK_CNTL0,
 444		.shift = 20,
 445		.width = 6,
 446	},
 447	.hw.init = &(struct clk_init_data){
 448		.name = "cpu_clk_dyn1_div",
 449		.ops = &clk_regmap_divider_ro_ops,
 450		.parent_hws = (const struct clk_hw *[]) {
 451			&g12a_cpu_clk_premux1.hw
 452		},
 453		.num_parents = 1,
 454	},
 455};
 456
 457/* Datasheet names this field as "postmux1" */
 458static struct clk_regmap g12a_cpu_clk_postmux1 = {
 459	.data = &(struct clk_regmap_mux_data){
 460		.offset = HHI_SYS_CPU_CLK_CNTL0,
 461		.mask = 0x1,
 462		.shift = 18,
 463	},
 464	.hw.init = &(struct clk_init_data){
 465		.name = "cpu_clk_dyn1",
 466		.ops = &clk_regmap_mux_ops,
 467		.parent_hws = (const struct clk_hw *[]) {
 468			&g12a_cpu_clk_premux1.hw,
 469			&g12a_cpu_clk_mux1_div.hw,
 470		},
 471		.num_parents = 2,
 472		/* This sub-tree is used a parking clock */
 473		.flags = CLK_SET_RATE_NO_REPARENT,
 474	},
 475};
 476
 477/* Datasheet names this field as "Final_dyn_mux_sel" */
 478static struct clk_regmap g12a_cpu_clk_dyn = {
 479	.data = &(struct clk_regmap_mux_data){
 480		.offset = HHI_SYS_CPU_CLK_CNTL0,
 481		.mask = 0x1,
 482		.shift = 10,
 483		.flags = CLK_MUX_ROUND_CLOSEST,
 484	},
 485	.hw.init = &(struct clk_init_data){
 486		.name = "cpu_clk_dyn",
 487		.ops = &clk_regmap_mux_ops,
 488		.parent_hws = (const struct clk_hw *[]) {
 489			&g12a_cpu_clk_postmux0.hw,
 490			&g12a_cpu_clk_postmux1.hw,
 491		},
 492		.num_parents = 2,
 493		.flags = CLK_SET_RATE_PARENT,
 494	},
 495};
 496
 497/* Datasheet names this field as "Final_mux_sel" */
 498static struct clk_regmap g12a_cpu_clk = {
 499	.data = &(struct clk_regmap_mux_data){
 500		.offset = HHI_SYS_CPU_CLK_CNTL0,
 501		.mask = 0x1,
 502		.shift = 11,
 503		.flags = CLK_MUX_ROUND_CLOSEST,
 504	},
 505	.hw.init = &(struct clk_init_data){
 506		.name = "cpu_clk",
 507		.ops = &clk_regmap_mux_ops,
 508		.parent_hws = (const struct clk_hw *[]) {
 509			&g12a_cpu_clk_dyn.hw,
 510			&g12a_sys_pll.hw,
 511		},
 512		.num_parents = 2,
 513		.flags = CLK_SET_RATE_PARENT,
 514	},
 515};
 516
 517/* Datasheet names this field as "Final_mux_sel" */
 518static struct clk_regmap g12b_cpu_clk = {
 519	.data = &(struct clk_regmap_mux_data){
 520		.offset = HHI_SYS_CPU_CLK_CNTL0,
 521		.mask = 0x1,
 522		.shift = 11,
 523		.flags = CLK_MUX_ROUND_CLOSEST,
 524	},
 525	.hw.init = &(struct clk_init_data){
 526		.name = "cpu_clk",
 527		.ops = &clk_regmap_mux_ops,
 528		.parent_hws = (const struct clk_hw *[]) {
 529			&g12a_cpu_clk_dyn.hw,
 530			&g12b_sys1_pll.hw
 531		},
 532		.num_parents = 2,
 533		.flags = CLK_SET_RATE_PARENT,
 534	},
 535};
 536
 537/* Datasheet names this field as "premux0" */
 538static struct clk_regmap g12b_cpub_clk_premux0 = {
 539	.data = &(struct clk_regmap_mux_data){
 540		.offset = HHI_SYS_CPUB_CLK_CNTL,
 541		.mask = 0x3,
 542		.shift = 0,
 543		.flags = CLK_MUX_ROUND_CLOSEST,
 544	},
 545	.hw.init = &(struct clk_init_data){
 546		.name = "cpub_clk_dyn0_sel",
 547		.ops = &clk_regmap_mux_ops,
 548		.parent_data = (const struct clk_parent_data []) {
 549			{ .fw_name = "xtal", },
 550			{ .hw = &g12a_fclk_div2.hw },
 551			{ .hw = &g12a_fclk_div3.hw },
 552		},
 553		.num_parents = 3,
 554		.flags = CLK_SET_RATE_PARENT,
 555	},
 556};
 557
 558/* Datasheet names this field as "mux0_divn_tcnt" */
 559static struct clk_regmap g12b_cpub_clk_mux0_div = {
 560	.data = &(struct meson_clk_cpu_dyndiv_data){
 561		.div = {
 562			.reg_off = HHI_SYS_CPUB_CLK_CNTL,
 563			.shift = 4,
 564			.width = 6,
 565		},
 566		.dyn = {
 567			.reg_off = HHI_SYS_CPUB_CLK_CNTL,
 568			.shift = 26,
 569			.width = 1,
 570		},
 571	},
 572	.hw.init = &(struct clk_init_data){
 573		.name = "cpub_clk_dyn0_div",
 574		.ops = &meson_clk_cpu_dyndiv_ops,
 575		.parent_hws = (const struct clk_hw *[]) {
 576			&g12b_cpub_clk_premux0.hw
 577		},
 578		.num_parents = 1,
 579		.flags = CLK_SET_RATE_PARENT,
 580	},
 581};
 582
 583/* Datasheet names this field as "postmux0" */
 584static struct clk_regmap g12b_cpub_clk_postmux0 = {
 585	.data = &(struct clk_regmap_mux_data){
 586		.offset = HHI_SYS_CPUB_CLK_CNTL,
 587		.mask = 0x1,
 588		.shift = 2,
 589		.flags = CLK_MUX_ROUND_CLOSEST,
 590	},
 591	.hw.init = &(struct clk_init_data){
 592		.name = "cpub_clk_dyn0",
 593		.ops = &clk_regmap_mux_ops,
 594		.parent_hws = (const struct clk_hw *[]) {
 595			&g12b_cpub_clk_premux0.hw,
 596			&g12b_cpub_clk_mux0_div.hw
 597		},
 598		.num_parents = 2,
 599		.flags = CLK_SET_RATE_PARENT,
 600	},
 601};
 602
 603/* Datasheet names this field as "premux1" */
 604static struct clk_regmap g12b_cpub_clk_premux1 = {
 605	.data = &(struct clk_regmap_mux_data){
 606		.offset = HHI_SYS_CPUB_CLK_CNTL,
 607		.mask = 0x3,
 608		.shift = 16,
 609	},
 610	.hw.init = &(struct clk_init_data){
 611		.name = "cpub_clk_dyn1_sel",
 612		.ops = &clk_regmap_mux_ops,
 613		.parent_data = (const struct clk_parent_data []) {
 614			{ .fw_name = "xtal", },
 615			{ .hw = &g12a_fclk_div2.hw },
 616			{ .hw = &g12a_fclk_div3.hw },
 617		},
 618		.num_parents = 3,
 619		/* This sub-tree is used a parking clock */
 620		.flags = CLK_SET_RATE_NO_REPARENT,
 621	},
 622};
 623
 624/* Datasheet names this field as "Mux1_divn_tcnt" */
 625static struct clk_regmap g12b_cpub_clk_mux1_div = {
 626	.data = &(struct clk_regmap_div_data){
 627		.offset = HHI_SYS_CPUB_CLK_CNTL,
 628		.shift = 20,
 629		.width = 6,
 630	},
 631	.hw.init = &(struct clk_init_data){
 632		.name = "cpub_clk_dyn1_div",
 633		.ops = &clk_regmap_divider_ro_ops,
 634		.parent_hws = (const struct clk_hw *[]) {
 635			&g12b_cpub_clk_premux1.hw
 636		},
 637		.num_parents = 1,
 638	},
 639};
 640
 641/* Datasheet names this field as "postmux1" */
 642static struct clk_regmap g12b_cpub_clk_postmux1 = {
 643	.data = &(struct clk_regmap_mux_data){
 644		.offset = HHI_SYS_CPUB_CLK_CNTL,
 645		.mask = 0x1,
 646		.shift = 18,
 647	},
 648	.hw.init = &(struct clk_init_data){
 649		.name = "cpub_clk_dyn1",
 650		.ops = &clk_regmap_mux_ops,
 651		.parent_hws = (const struct clk_hw *[]) {
 652			&g12b_cpub_clk_premux1.hw,
 653			&g12b_cpub_clk_mux1_div.hw
 654		},
 655		.num_parents = 2,
 656		/* This sub-tree is used a parking clock */
 657		.flags = CLK_SET_RATE_NO_REPARENT,
 658	},
 659};
 660
 661/* Datasheet names this field as "Final_dyn_mux_sel" */
 662static struct clk_regmap g12b_cpub_clk_dyn = {
 663	.data = &(struct clk_regmap_mux_data){
 664		.offset = HHI_SYS_CPUB_CLK_CNTL,
 665		.mask = 0x1,
 666		.shift = 10,
 667		.flags = CLK_MUX_ROUND_CLOSEST,
 668	},
 669	.hw.init = &(struct clk_init_data){
 670		.name = "cpub_clk_dyn",
 671		.ops = &clk_regmap_mux_ops,
 672		.parent_hws = (const struct clk_hw *[]) {
 673			&g12b_cpub_clk_postmux0.hw,
 674			&g12b_cpub_clk_postmux1.hw
 675		},
 676		.num_parents = 2,
 677		.flags = CLK_SET_RATE_PARENT,
 678	},
 679};
 680
 681/* Datasheet names this field as "Final_mux_sel" */
 682static struct clk_regmap g12b_cpub_clk = {
 683	.data = &(struct clk_regmap_mux_data){
 684		.offset = HHI_SYS_CPUB_CLK_CNTL,
 685		.mask = 0x1,
 686		.shift = 11,
 687		.flags = CLK_MUX_ROUND_CLOSEST,
 688	},
 689	.hw.init = &(struct clk_init_data){
 690		.name = "cpub_clk",
 691		.ops = &clk_regmap_mux_ops,
 692		.parent_hws = (const struct clk_hw *[]) {
 693			&g12b_cpub_clk_dyn.hw,
 694			&g12a_sys_pll.hw
 695		},
 696		.num_parents = 2,
 697		.flags = CLK_SET_RATE_PARENT,
 698	},
 699};
 700
 701static struct clk_regmap sm1_gp1_pll;
 702
 703/* Datasheet names this field as "premux0" */
 704static struct clk_regmap sm1_dsu_clk_premux0 = {
 705	.data = &(struct clk_regmap_mux_data){
 706		.offset = HHI_SYS_CPU_CLK_CNTL5,
 707		.mask = 0x3,
 708		.shift = 0,
 709	},
 710	.hw.init = &(struct clk_init_data){
 711		.name = "dsu_clk_dyn0_sel",
 712		.ops = &clk_regmap_mux_ro_ops,
 713		.parent_data = (const struct clk_parent_data []) {
 714			{ .fw_name = "xtal", },
 715			{ .hw = &g12a_fclk_div2.hw },
 716			{ .hw = &g12a_fclk_div3.hw },
 717			{ .hw = &sm1_gp1_pll.hw },
 718		},
 719		.num_parents = 4,
 720	},
 721};
 722
 723/* Datasheet names this field as "premux1" */
 724static struct clk_regmap sm1_dsu_clk_premux1 = {
 725	.data = &(struct clk_regmap_mux_data){
 726		.offset = HHI_SYS_CPU_CLK_CNTL5,
 727		.mask = 0x3,
 728		.shift = 16,
 729	},
 730	.hw.init = &(struct clk_init_data){
 731		.name = "dsu_clk_dyn1_sel",
 732		.ops = &clk_regmap_mux_ro_ops,
 733		.parent_data = (const struct clk_parent_data []) {
 734			{ .fw_name = "xtal", },
 735			{ .hw = &g12a_fclk_div2.hw },
 736			{ .hw = &g12a_fclk_div3.hw },
 737			{ .hw = &sm1_gp1_pll.hw },
 738		},
 739		.num_parents = 4,
 740	},
 741};
 742
 743/* Datasheet names this field as "Mux0_divn_tcnt" */
 744static struct clk_regmap sm1_dsu_clk_mux0_div = {
 745	.data = &(struct clk_regmap_div_data){
 746		.offset = HHI_SYS_CPU_CLK_CNTL5,
 747		.shift = 4,
 748		.width = 6,
 749	},
 750	.hw.init = &(struct clk_init_data){
 751		.name = "dsu_clk_dyn0_div",
 752		.ops = &clk_regmap_divider_ro_ops,
 753		.parent_hws = (const struct clk_hw *[]) {
 754			&sm1_dsu_clk_premux0.hw
 755		},
 756		.num_parents = 1,
 757	},
 758};
 759
 760/* Datasheet names this field as "postmux0" */
 761static struct clk_regmap sm1_dsu_clk_postmux0 = {
 762	.data = &(struct clk_regmap_mux_data){
 763		.offset = HHI_SYS_CPU_CLK_CNTL5,
 764		.mask = 0x1,
 765		.shift = 2,
 766	},
 767	.hw.init = &(struct clk_init_data){
 768		.name = "dsu_clk_dyn0",
 769		.ops = &clk_regmap_mux_ro_ops,
 770		.parent_hws = (const struct clk_hw *[]) {
 771			&sm1_dsu_clk_premux0.hw,
 772			&sm1_dsu_clk_mux0_div.hw,
 773		},
 774		.num_parents = 2,
 775	},
 776};
 777
 778/* Datasheet names this field as "Mux1_divn_tcnt" */
 779static struct clk_regmap sm1_dsu_clk_mux1_div = {
 780	.data = &(struct clk_regmap_div_data){
 781		.offset = HHI_SYS_CPU_CLK_CNTL5,
 782		.shift = 20,
 783		.width = 6,
 784	},
 785	.hw.init = &(struct clk_init_data){
 786		.name = "dsu_clk_dyn1_div",
 787		.ops = &clk_regmap_divider_ro_ops,
 788		.parent_hws = (const struct clk_hw *[]) {
 789			&sm1_dsu_clk_premux1.hw
 790		},
 791		.num_parents = 1,
 792	},
 793};
 794
 795/* Datasheet names this field as "postmux1" */
 796static struct clk_regmap sm1_dsu_clk_postmux1 = {
 797	.data = &(struct clk_regmap_mux_data){
 798		.offset = HHI_SYS_CPU_CLK_CNTL5,
 799		.mask = 0x1,
 800		.shift = 18,
 801	},
 802	.hw.init = &(struct clk_init_data){
 803		.name = "dsu_clk_dyn1",
 804		.ops = &clk_regmap_mux_ro_ops,
 805		.parent_hws = (const struct clk_hw *[]) {
 806			&sm1_dsu_clk_premux1.hw,
 807			&sm1_dsu_clk_mux1_div.hw,
 808		},
 809		.num_parents = 2,
 810	},
 811};
 812
 813/* Datasheet names this field as "Final_dyn_mux_sel" */
 814static struct clk_regmap sm1_dsu_clk_dyn = {
 815	.data = &(struct clk_regmap_mux_data){
 816		.offset = HHI_SYS_CPU_CLK_CNTL5,
 817		.mask = 0x1,
 818		.shift = 10,
 819	},
 820	.hw.init = &(struct clk_init_data){
 821		.name = "dsu_clk_dyn",
 822		.ops = &clk_regmap_mux_ro_ops,
 823		.parent_hws = (const struct clk_hw *[]) {
 824			&sm1_dsu_clk_postmux0.hw,
 825			&sm1_dsu_clk_postmux1.hw,
 826		},
 827		.num_parents = 2,
 828	},
 829};
 830
 831/* Datasheet names this field as "Final_mux_sel" */
 832static struct clk_regmap sm1_dsu_final_clk = {
 833	.data = &(struct clk_regmap_mux_data){
 834		.offset = HHI_SYS_CPU_CLK_CNTL5,
 835		.mask = 0x1,
 836		.shift = 11,
 837	},
 838	.hw.init = &(struct clk_init_data){
 839		.name = "dsu_clk_final",
 840		.ops = &clk_regmap_mux_ro_ops,
 841		.parent_hws = (const struct clk_hw *[]) {
 842			&sm1_dsu_clk_dyn.hw,
 843			&g12a_sys_pll.hw,
 844		},
 845		.num_parents = 2,
 846	},
 847};
 848
 849/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */
 850static struct clk_regmap sm1_cpu1_clk = {
 851	.data = &(struct clk_regmap_mux_data){
 852		.offset = HHI_SYS_CPU_CLK_CNTL6,
 853		.mask = 0x1,
 854		.shift = 24,
 855	},
 856	.hw.init = &(struct clk_init_data){
 857		.name = "cpu1_clk",
 858		.ops = &clk_regmap_mux_ro_ops,
 859		.parent_hws = (const struct clk_hw *[]) {
 860			&g12a_cpu_clk.hw,
 861			/* This CPU also have a dedicated clock tree */
 862		},
 863		.num_parents = 1,
 864	},
 865};
 866
 867/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */
 868static struct clk_regmap sm1_cpu2_clk = {
 869	.data = &(struct clk_regmap_mux_data){
 870		.offset = HHI_SYS_CPU_CLK_CNTL6,
 871		.mask = 0x1,
 872		.shift = 25,
 873	},
 874	.hw.init = &(struct clk_init_data){
 875		.name = "cpu2_clk",
 876		.ops = &clk_regmap_mux_ro_ops,
 877		.parent_hws = (const struct clk_hw *[]) {
 878			&g12a_cpu_clk.hw,
 879			/* This CPU also have a dedicated clock tree */
 880		},
 881		.num_parents = 1,
 882	},
 883};
 884
 885/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */
 886static struct clk_regmap sm1_cpu3_clk = {
 887	.data = &(struct clk_regmap_mux_data){
 888		.offset = HHI_SYS_CPU_CLK_CNTL6,
 889		.mask = 0x1,
 890		.shift = 26,
 891	},
 892	.hw.init = &(struct clk_init_data){
 893		.name = "cpu3_clk",
 894		.ops = &clk_regmap_mux_ro_ops,
 895		.parent_hws = (const struct clk_hw *[]) {
 896			&g12a_cpu_clk.hw,
 897			/* This CPU also have a dedicated clock tree */
 898		},
 899		.num_parents = 1,
 900	},
 901};
 902
 903/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
 904static struct clk_regmap sm1_dsu_clk = {
 905	.data = &(struct clk_regmap_mux_data){
 906		.offset = HHI_SYS_CPU_CLK_CNTL6,
 907		.mask = 0x1,
 908		.shift = 27,
 909	},
 910	.hw.init = &(struct clk_init_data){
 911		.name = "dsu_clk",
 912		.ops = &clk_regmap_mux_ro_ops,
 913		.parent_hws = (const struct clk_hw *[]) {
 914			&g12a_cpu_clk.hw,
 915			&sm1_dsu_final_clk.hw,
 916		},
 917		.num_parents = 2,
 918	},
 919};
 920
 921static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
 922					unsigned long event, void *data)
 923{
 924	if (event == POST_RATE_CHANGE || event == PRE_RATE_CHANGE) {
 925		/* Wait for clock propagation before/after changing the mux */
 926		udelay(100);
 927		return NOTIFY_OK;
 928	}
 929
 930	return NOTIFY_DONE;
 931}
 932
 933static struct notifier_block g12a_cpu_clk_mux_nb = {
 934	.notifier_call = g12a_cpu_clk_mux_notifier_cb,
 935};
 936
 937struct g12a_cpu_clk_postmux_nb_data {
 938	struct notifier_block nb;
 939	struct clk_hw *xtal;
 940	struct clk_hw *cpu_clk_dyn;
 941	struct clk_hw *cpu_clk_postmux0;
 942	struct clk_hw *cpu_clk_postmux1;
 943	struct clk_hw *cpu_clk_premux1;
 944};
 945
 946static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb,
 947					    unsigned long event, void *data)
 948{
 949	struct g12a_cpu_clk_postmux_nb_data *nb_data =
 950		container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb);
 951
 952	switch (event) {
 953	case PRE_RATE_CHANGE:
 954		/*
 955		 * This notifier means cpu_clk_postmux0 clock will be changed
 956		 * to feed cpu_clk, this is the current path :
 957		 * cpu_clk
 958		 *    \- cpu_clk_dyn
 959		 *          \- cpu_clk_postmux0
 960		 *                \- cpu_clk_muxX_div
 961		 *                      \- cpu_clk_premux0
 962		 *				\- fclk_div3 or fclk_div2
 963		 *		OR
 964		 *                \- cpu_clk_premux0
 965		 *			\- fclk_div3 or fclk_div2
 966		 */
 967
 968		/* Setup cpu_clk_premux1 to xtal */
 969		clk_hw_set_parent(nb_data->cpu_clk_premux1,
 970				  nb_data->xtal);
 971
 972		/* Setup cpu_clk_postmux1 to bypass divider */
 973		clk_hw_set_parent(nb_data->cpu_clk_postmux1,
 974				  nb_data->cpu_clk_premux1);
 975
 976		/* Switch to parking clk on cpu_clk_postmux1 */
 977		clk_hw_set_parent(nb_data->cpu_clk_dyn,
 978				  nb_data->cpu_clk_postmux1);
 979
 980		/*
 981		 * Now, cpu_clk is 24MHz in the current path :
 982		 * cpu_clk
 983		 *    \- cpu_clk_dyn
 984		 *          \- cpu_clk_postmux1
 985		 *                \- cpu_clk_premux1
 986		 *                      \- xtal
 987		 */
 988
 989		udelay(100);
 990
 991		return NOTIFY_OK;
 992
 993	case POST_RATE_CHANGE:
 994		/*
 995		 * The cpu_clk_postmux0 has ben updated, now switch back
 996		 * cpu_clk_dyn to cpu_clk_postmux0 and take the changes
 997		 * in account.
 998		 */
 999
1000		/* Configure cpu_clk_dyn back to cpu_clk_postmux0 */
1001		clk_hw_set_parent(nb_data->cpu_clk_dyn,
1002				  nb_data->cpu_clk_postmux0);
1003
1004		/*
1005		 * new path :
1006		 * cpu_clk
1007		 *    \- cpu_clk_dyn
1008		 *          \- cpu_clk_postmux0
1009		 *                \- cpu_clk_muxX_div
1010		 *                      \- cpu_clk_premux0
1011		 *				\- fclk_div3 or fclk_div2
1012		 *		OR
1013		 *                \- cpu_clk_premux0
1014		 *			\- fclk_div3 or fclk_div2
1015		 */
1016
1017		udelay(100);
1018
1019		return NOTIFY_OK;
1020
1021	default:
1022		return NOTIFY_DONE;
1023	}
1024}
1025
1026static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = {
1027	.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1028	.cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
1029	.cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
1030	.cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
1031	.nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1032};
1033
1034static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = {
1035	.cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1036	.cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
1037	.cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
1038	.cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
1039	.nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1040};
1041
1042struct g12a_sys_pll_nb_data {
1043	struct notifier_block nb;
1044	struct clk_hw *sys_pll;
1045	struct clk_hw *cpu_clk;
1046	struct clk_hw *cpu_clk_dyn;
1047};
1048
1049static int g12a_sys_pll_notifier_cb(struct notifier_block *nb,
1050				    unsigned long event, void *data)
1051{
1052	struct g12a_sys_pll_nb_data *nb_data =
1053		container_of(nb, struct g12a_sys_pll_nb_data, nb);
1054
1055	switch (event) {
1056	case PRE_RATE_CHANGE:
1057		/*
1058		 * This notifier means sys_pll clock will be changed
1059		 * to feed cpu_clk, this the current path :
1060		 * cpu_clk
1061		 *    \- sys_pll
1062		 *          \- sys_pll_dco
1063		 */
1064
1065		/* Configure cpu_clk to use cpu_clk_dyn */
1066		clk_hw_set_parent(nb_data->cpu_clk,
1067				  nb_data->cpu_clk_dyn);
1068
1069		/*
1070		 * Now, cpu_clk uses the dyn path
1071		 * cpu_clk
1072		 *    \- cpu_clk_dyn
1073		 *          \- cpu_clk_dynX
1074		 *                \- cpu_clk_dynX_sel
1075		 *		     \- cpu_clk_dynX_div
1076		 *                      \- xtal/fclk_div2/fclk_div3
1077		 *                   \- xtal/fclk_div2/fclk_div3
1078		 */
1079
1080		udelay(100);
1081
1082		return NOTIFY_OK;
1083
1084	case POST_RATE_CHANGE:
1085		/*
1086		 * The sys_pll has ben updated, now switch back cpu_clk to
1087		 * sys_pll
1088		 */
1089
1090		/* Configure cpu_clk to use sys_pll */
1091		clk_hw_set_parent(nb_data->cpu_clk,
1092				  nb_data->sys_pll);
1093
1094		udelay(100);
1095
1096		/* new path :
1097		 * cpu_clk
1098		 *    \- sys_pll
1099		 *          \- sys_pll_dco
1100		 */
1101
1102		return NOTIFY_OK;
1103
1104	default:
1105		return NOTIFY_DONE;
1106	}
1107}
1108
1109static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = {
1110	.sys_pll = &g12a_sys_pll.hw,
1111	.cpu_clk = &g12a_cpu_clk.hw,
1112	.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1113	.nb.notifier_call = g12a_sys_pll_notifier_cb,
1114};
1115
1116/* G12B first CPU cluster uses sys1_pll */
1117static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = {
1118	.sys_pll = &g12b_sys1_pll.hw,
1119	.cpu_clk = &g12b_cpu_clk.hw,
1120	.cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1121	.nb.notifier_call = g12a_sys_pll_notifier_cb,
1122};
1123
1124/* G12B second CPU cluster uses sys_pll */
1125static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = {
1126	.sys_pll = &g12a_sys_pll.hw,
1127	.cpu_clk = &g12b_cpub_clk.hw,
1128	.cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1129	.nb.notifier_call = g12a_sys_pll_notifier_cb,
1130};
1131
1132static struct clk_regmap g12a_cpu_clk_div16_en = {
1133	.data = &(struct clk_regmap_gate_data){
1134		.offset = HHI_SYS_CPU_CLK_CNTL1,
1135		.bit_idx = 1,
1136	},
1137	.hw.init = &(struct clk_init_data) {
1138		.name = "cpu_clk_div16_en",
1139		.ops = &clk_regmap_gate_ro_ops,
1140		.parent_hws = (const struct clk_hw *[]) {
1141			&g12a_cpu_clk.hw
1142		},
1143		.num_parents = 1,
1144		/*
1145		 * This clock is used to debug the cpu_clk range
1146		 * Linux should not change it at runtime
1147		 */
1148	},
1149};
1150
1151static struct clk_regmap g12b_cpub_clk_div16_en = {
1152	.data = &(struct clk_regmap_gate_data){
1153		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1154		.bit_idx = 1,
1155	},
1156	.hw.init = &(struct clk_init_data) {
1157		.name = "cpub_clk_div16_en",
1158		.ops = &clk_regmap_gate_ro_ops,
1159		.parent_hws = (const struct clk_hw *[]) {
1160			&g12b_cpub_clk.hw
1161		},
1162		.num_parents = 1,
1163		/*
1164		 * This clock is used to debug the cpu_clk range
1165		 * Linux should not change it at runtime
1166		 */
1167	},
1168};
1169
1170static struct clk_fixed_factor g12a_cpu_clk_div16 = {
1171	.mult = 1,
1172	.div = 16,
1173	.hw.init = &(struct clk_init_data){
1174		.name = "cpu_clk_div16",
1175		.ops = &clk_fixed_factor_ops,
1176		.parent_hws = (const struct clk_hw *[]) {
1177			&g12a_cpu_clk_div16_en.hw
1178		},
1179		.num_parents = 1,
1180	},
1181};
1182
1183static struct clk_fixed_factor g12b_cpub_clk_div16 = {
1184	.mult = 1,
1185	.div = 16,
1186	.hw.init = &(struct clk_init_data){
1187		.name = "cpub_clk_div16",
1188		.ops = &clk_fixed_factor_ops,
1189		.parent_hws = (const struct clk_hw *[]) {
1190			&g12b_cpub_clk_div16_en.hw
1191		},
1192		.num_parents = 1,
1193	},
1194};
1195
1196static struct clk_regmap g12a_cpu_clk_apb_div = {
1197	.data = &(struct clk_regmap_div_data){
1198		.offset = HHI_SYS_CPU_CLK_CNTL1,
1199		.shift = 3,
1200		.width = 3,
1201		.flags = CLK_DIVIDER_POWER_OF_TWO,
1202	},
1203	.hw.init = &(struct clk_init_data){
1204		.name = "cpu_clk_apb_div",
1205		.ops = &clk_regmap_divider_ro_ops,
1206		.parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1207		.num_parents = 1,
1208	},
1209};
1210
1211static struct clk_regmap g12a_cpu_clk_apb = {
1212	.data = &(struct clk_regmap_gate_data){
1213		.offset = HHI_SYS_CPU_CLK_CNTL1,
1214		.bit_idx = 1,
1215	},
1216	.hw.init = &(struct clk_init_data) {
1217		.name = "cpu_clk_apb",
1218		.ops = &clk_regmap_gate_ro_ops,
1219		.parent_hws = (const struct clk_hw *[]) {
1220			&g12a_cpu_clk_apb_div.hw
1221		},
1222		.num_parents = 1,
1223		/*
1224		 * This clock is set by the ROM monitor code,
1225		 * Linux should not change it at runtime
1226		 */
1227	},
1228};
1229
1230static struct clk_regmap g12a_cpu_clk_atb_div = {
1231	.data = &(struct clk_regmap_div_data){
1232		.offset = HHI_SYS_CPU_CLK_CNTL1,
1233		.shift = 6,
1234		.width = 3,
1235		.flags = CLK_DIVIDER_POWER_OF_TWO,
1236	},
1237	.hw.init = &(struct clk_init_data){
1238		.name = "cpu_clk_atb_div",
1239		.ops = &clk_regmap_divider_ro_ops,
1240		.parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1241		.num_parents = 1,
1242	},
1243};
1244
1245static struct clk_regmap g12a_cpu_clk_atb = {
1246	.data = &(struct clk_regmap_gate_data){
1247		.offset = HHI_SYS_CPU_CLK_CNTL1,
1248		.bit_idx = 17,
1249	},
1250	.hw.init = &(struct clk_init_data) {
1251		.name = "cpu_clk_atb",
1252		.ops = &clk_regmap_gate_ro_ops,
1253		.parent_hws = (const struct clk_hw *[]) {
1254			&g12a_cpu_clk_atb_div.hw
1255		},
1256		.num_parents = 1,
1257		/*
1258		 * This clock is set by the ROM monitor code,
1259		 * Linux should not change it at runtime
1260		 */
1261	},
1262};
1263
1264static struct clk_regmap g12a_cpu_clk_axi_div = {
1265	.data = &(struct clk_regmap_div_data){
1266		.offset = HHI_SYS_CPU_CLK_CNTL1,
1267		.shift = 9,
1268		.width = 3,
1269		.flags = CLK_DIVIDER_POWER_OF_TWO,
1270	},
1271	.hw.init = &(struct clk_init_data){
1272		.name = "cpu_clk_axi_div",
1273		.ops = &clk_regmap_divider_ro_ops,
1274		.parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
1275		.num_parents = 1,
1276	},
1277};
1278
1279static struct clk_regmap g12a_cpu_clk_axi = {
1280	.data = &(struct clk_regmap_gate_data){
1281		.offset = HHI_SYS_CPU_CLK_CNTL1,
1282		.bit_idx = 18,
1283	},
1284	.hw.init = &(struct clk_init_data) {
1285		.name = "cpu_clk_axi",
1286		.ops = &clk_regmap_gate_ro_ops,
1287		.parent_hws = (const struct clk_hw *[]) {
1288			&g12a_cpu_clk_axi_div.hw
1289		},
1290		.num_parents = 1,
1291		/*
1292		 * This clock is set by the ROM monitor code,
1293		 * Linux should not change it at runtime
1294		 */
1295	},
1296};
1297
1298static struct clk_regmap g12a_cpu_clk_trace_div = {
1299	.data = &(struct clk_regmap_div_data){
1300		.offset = HHI_SYS_CPU_CLK_CNTL1,
1301		.shift = 20,
1302		.width = 3,
1303		.flags = CLK_DIVIDER_POWER_OF_TWO,
1304	},
1305	.hw.init = &(struct clk_init_data){
1306		.name = "cpu_clk_trace_div",
1307		.ops = &clk_regmap_divider_ro_ops,
1308		.parent_data = &(const struct clk_parent_data) {
1309			/*
1310			 * Note:
1311			 * G12A and G12B have different cpu_clks (with
1312			 * different struct clk_hw). We fallback to the global
1313			 * naming string mechanism so cpu_clk_trace_div picks
1314			 * up the appropriate one.
1315			 */
1316			.name = "cpu_clk",
1317			.index = -1,
1318		},
1319		.num_parents = 1,
1320	},
1321};
1322
1323static struct clk_regmap g12a_cpu_clk_trace = {
1324	.data = &(struct clk_regmap_gate_data){
1325		.offset = HHI_SYS_CPU_CLK_CNTL1,
1326		.bit_idx = 23,
1327	},
1328	.hw.init = &(struct clk_init_data) {
1329		.name = "cpu_clk_trace",
1330		.ops = &clk_regmap_gate_ro_ops,
1331		.parent_hws = (const struct clk_hw *[]) {
1332			&g12a_cpu_clk_trace_div.hw
1333		},
1334		.num_parents = 1,
1335		/*
1336		 * This clock is set by the ROM monitor code,
1337		 * Linux should not change it at runtime
1338		 */
1339	},
1340};
1341
1342static struct clk_fixed_factor g12b_cpub_clk_div2 = {
1343	.mult = 1,
1344	.div = 2,
1345	.hw.init = &(struct clk_init_data){
1346		.name = "cpub_clk_div2",
1347		.ops = &clk_fixed_factor_ops,
1348		.parent_hws = (const struct clk_hw *[]) {
1349			&g12b_cpub_clk.hw
1350		},
1351		.num_parents = 1,
1352	},
1353};
1354
1355static struct clk_fixed_factor g12b_cpub_clk_div3 = {
1356	.mult = 1,
1357	.div = 3,
1358	.hw.init = &(struct clk_init_data){
1359		.name = "cpub_clk_div3",
1360		.ops = &clk_fixed_factor_ops,
1361		.parent_hws = (const struct clk_hw *[]) {
1362			&g12b_cpub_clk.hw
1363		},
1364		.num_parents = 1,
1365	},
1366};
1367
1368static struct clk_fixed_factor g12b_cpub_clk_div4 = {
1369	.mult = 1,
1370	.div = 4,
1371	.hw.init = &(struct clk_init_data){
1372		.name = "cpub_clk_div4",
1373		.ops = &clk_fixed_factor_ops,
1374		.parent_hws = (const struct clk_hw *[]) {
1375			&g12b_cpub_clk.hw
1376		},
1377		.num_parents = 1,
1378	},
1379};
1380
1381static struct clk_fixed_factor g12b_cpub_clk_div5 = {
1382	.mult = 1,
1383	.div = 5,
1384	.hw.init = &(struct clk_init_data){
1385		.name = "cpub_clk_div5",
1386		.ops = &clk_fixed_factor_ops,
1387		.parent_hws = (const struct clk_hw *[]) {
1388			&g12b_cpub_clk.hw
1389		},
1390		.num_parents = 1,
1391	},
1392};
1393
1394static struct clk_fixed_factor g12b_cpub_clk_div6 = {
1395	.mult = 1,
1396	.div = 6,
1397	.hw.init = &(struct clk_init_data){
1398		.name = "cpub_clk_div6",
1399		.ops = &clk_fixed_factor_ops,
1400		.parent_hws = (const struct clk_hw *[]) {
1401			&g12b_cpub_clk.hw
1402		},
1403		.num_parents = 1,
1404	},
1405};
1406
1407static struct clk_fixed_factor g12b_cpub_clk_div7 = {
1408	.mult = 1,
1409	.div = 7,
1410	.hw.init = &(struct clk_init_data){
1411		.name = "cpub_clk_div7",
1412		.ops = &clk_fixed_factor_ops,
1413		.parent_hws = (const struct clk_hw *[]) {
1414			&g12b_cpub_clk.hw
1415		},
1416		.num_parents = 1,
1417	},
1418};
1419
1420static struct clk_fixed_factor g12b_cpub_clk_div8 = {
1421	.mult = 1,
1422	.div = 8,
1423	.hw.init = &(struct clk_init_data){
1424		.name = "cpub_clk_div8",
1425		.ops = &clk_fixed_factor_ops,
1426		.parent_hws = (const struct clk_hw *[]) {
1427			&g12b_cpub_clk.hw
1428		},
1429		.num_parents = 1,
1430	},
1431};
1432
1433static u32 mux_table_cpub[] = { 1, 2, 3, 4, 5, 6, 7 };
1434static struct clk_regmap g12b_cpub_clk_apb_sel = {
1435	.data = &(struct clk_regmap_mux_data){
1436		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1437		.mask = 7,
1438		.shift = 3,
1439		.table = mux_table_cpub,
1440	},
1441	.hw.init = &(struct clk_init_data){
1442		.name = "cpub_clk_apb_sel",
1443		.ops = &clk_regmap_mux_ro_ops,
1444		.parent_hws = (const struct clk_hw *[]) {
1445			&g12b_cpub_clk_div2.hw,
1446			&g12b_cpub_clk_div3.hw,
1447			&g12b_cpub_clk_div4.hw,
1448			&g12b_cpub_clk_div5.hw,
1449			&g12b_cpub_clk_div6.hw,
1450			&g12b_cpub_clk_div7.hw,
1451			&g12b_cpub_clk_div8.hw
1452		},
1453		.num_parents = 7,
1454	},
1455};
1456
1457static struct clk_regmap g12b_cpub_clk_apb = {
1458	.data = &(struct clk_regmap_gate_data){
1459		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1460		.bit_idx = 16,
1461		.flags = CLK_GATE_SET_TO_DISABLE,
1462	},
1463	.hw.init = &(struct clk_init_data) {
1464		.name = "cpub_clk_apb",
1465		.ops = &clk_regmap_gate_ro_ops,
1466		.parent_hws = (const struct clk_hw *[]) {
1467			&g12b_cpub_clk_apb_sel.hw
1468		},
1469		.num_parents = 1,
1470		/*
1471		 * This clock is set by the ROM monitor code,
1472		 * Linux should not change it at runtime
1473		 */
1474	},
1475};
1476
1477static struct clk_regmap g12b_cpub_clk_atb_sel = {
1478	.data = &(struct clk_regmap_mux_data){
1479		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1480		.mask = 7,
1481		.shift = 6,
1482		.table = mux_table_cpub,
1483	},
1484	.hw.init = &(struct clk_init_data){
1485		.name = "cpub_clk_atb_sel",
1486		.ops = &clk_regmap_mux_ro_ops,
1487		.parent_hws = (const struct clk_hw *[]) {
1488			&g12b_cpub_clk_div2.hw,
1489			&g12b_cpub_clk_div3.hw,
1490			&g12b_cpub_clk_div4.hw,
1491			&g12b_cpub_clk_div5.hw,
1492			&g12b_cpub_clk_div6.hw,
1493			&g12b_cpub_clk_div7.hw,
1494			&g12b_cpub_clk_div8.hw
1495		},
1496		.num_parents = 7,
1497	},
1498};
1499
1500static struct clk_regmap g12b_cpub_clk_atb = {
1501	.data = &(struct clk_regmap_gate_data){
1502		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1503		.bit_idx = 17,
1504		.flags = CLK_GATE_SET_TO_DISABLE,
1505	},
1506	.hw.init = &(struct clk_init_data) {
1507		.name = "cpub_clk_atb",
1508		.ops = &clk_regmap_gate_ro_ops,
1509		.parent_hws = (const struct clk_hw *[]) {
1510			&g12b_cpub_clk_atb_sel.hw
1511		},
1512		.num_parents = 1,
1513		/*
1514		 * This clock is set by the ROM monitor code,
1515		 * Linux should not change it at runtime
1516		 */
1517	},
1518};
1519
1520static struct clk_regmap g12b_cpub_clk_axi_sel = {
1521	.data = &(struct clk_regmap_mux_data){
1522		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1523		.mask = 7,
1524		.shift = 9,
1525		.table = mux_table_cpub,
1526	},
1527	.hw.init = &(struct clk_init_data){
1528		.name = "cpub_clk_axi_sel",
1529		.ops = &clk_regmap_mux_ro_ops,
1530		.parent_hws = (const struct clk_hw *[]) {
1531			&g12b_cpub_clk_div2.hw,
1532			&g12b_cpub_clk_div3.hw,
1533			&g12b_cpub_clk_div4.hw,
1534			&g12b_cpub_clk_div5.hw,
1535			&g12b_cpub_clk_div6.hw,
1536			&g12b_cpub_clk_div7.hw,
1537			&g12b_cpub_clk_div8.hw
1538		},
1539		.num_parents = 7,
1540	},
1541};
1542
1543static struct clk_regmap g12b_cpub_clk_axi = {
1544	.data = &(struct clk_regmap_gate_data){
1545		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1546		.bit_idx = 18,
1547		.flags = CLK_GATE_SET_TO_DISABLE,
1548	},
1549	.hw.init = &(struct clk_init_data) {
1550		.name = "cpub_clk_axi",
1551		.ops = &clk_regmap_gate_ro_ops,
1552		.parent_hws = (const struct clk_hw *[]) {
1553			&g12b_cpub_clk_axi_sel.hw
1554		},
1555		.num_parents = 1,
1556		/*
1557		 * This clock is set by the ROM monitor code,
1558		 * Linux should not change it at runtime
1559		 */
1560	},
1561};
1562
1563static struct clk_regmap g12b_cpub_clk_trace_sel = {
1564	.data = &(struct clk_regmap_mux_data){
1565		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1566		.mask = 7,
1567		.shift = 20,
1568		.table = mux_table_cpub,
1569	},
1570	.hw.init = &(struct clk_init_data){
1571		.name = "cpub_clk_trace_sel",
1572		.ops = &clk_regmap_mux_ro_ops,
1573		.parent_hws = (const struct clk_hw *[]) {
1574			&g12b_cpub_clk_div2.hw,
1575			&g12b_cpub_clk_div3.hw,
1576			&g12b_cpub_clk_div4.hw,
1577			&g12b_cpub_clk_div5.hw,
1578			&g12b_cpub_clk_div6.hw,
1579			&g12b_cpub_clk_div7.hw,
1580			&g12b_cpub_clk_div8.hw
1581		},
1582		.num_parents = 7,
1583	},
1584};
1585
1586static struct clk_regmap g12b_cpub_clk_trace = {
1587	.data = &(struct clk_regmap_gate_data){
1588		.offset = HHI_SYS_CPUB_CLK_CNTL1,
1589		.bit_idx = 23,
1590		.flags = CLK_GATE_SET_TO_DISABLE,
1591	},
1592	.hw.init = &(struct clk_init_data) {
1593		.name = "cpub_clk_trace",
1594		.ops = &clk_regmap_gate_ro_ops,
1595		.parent_hws = (const struct clk_hw *[]) {
1596			&g12b_cpub_clk_trace_sel.hw
1597		},
1598		.num_parents = 1,
1599		/*
1600		 * This clock is set by the ROM monitor code,
1601		 * Linux should not change it at runtime
1602		 */
1603	},
1604};
1605
1606static const struct pll_mult_range g12a_gp0_pll_mult_range = {
1607	.min = 125,
1608	.max = 255,
1609};
1610
1611/*
1612 * Internal gp0 pll emulation configuration parameters
1613 */
1614static const struct reg_sequence g12a_gp0_init_regs[] = {
1615	{ .reg = HHI_GP0_PLL_CNTL1,	.def = 0x00000000 },
1616	{ .reg = HHI_GP0_PLL_CNTL2,	.def = 0x00000000 },
1617	{ .reg = HHI_GP0_PLL_CNTL3,	.def = 0x48681c00 },
1618	{ .reg = HHI_GP0_PLL_CNTL4,	.def = 0x33771290 },
1619	{ .reg = HHI_GP0_PLL_CNTL5,	.def = 0x39272000 },
1620	{ .reg = HHI_GP0_PLL_CNTL6,	.def = 0x56540000 },
1621};
1622
1623static struct clk_regmap g12a_gp0_pll_dco = {
1624	.data = &(struct meson_clk_pll_data){
1625		.en = {
1626			.reg_off = HHI_GP0_PLL_CNTL0,
1627			.shift   = 28,
1628			.width   = 1,
1629		},
1630		.m = {
1631			.reg_off = HHI_GP0_PLL_CNTL0,
1632			.shift   = 0,
1633			.width   = 8,
1634		},
1635		.n = {
1636			.reg_off = HHI_GP0_PLL_CNTL0,
1637			.shift   = 10,
1638			.width   = 5,
1639		},
1640		.frac = {
1641			.reg_off = HHI_GP0_PLL_CNTL1,
1642			.shift   = 0,
1643			.width   = 17,
1644		},
1645		.l = {
1646			.reg_off = HHI_GP0_PLL_CNTL0,
1647			.shift   = 31,
1648			.width   = 1,
1649		},
1650		.rst = {
1651			.reg_off = HHI_GP0_PLL_CNTL0,
1652			.shift   = 29,
1653			.width   = 1,
1654		},
1655		.range = &g12a_gp0_pll_mult_range,
1656		.init_regs = g12a_gp0_init_regs,
1657		.init_count = ARRAY_SIZE(g12a_gp0_init_regs),
1658	},
1659	.hw.init = &(struct clk_init_data){
1660		.name = "gp0_pll_dco",
1661		.ops = &meson_clk_pll_ops,
1662		.parent_data = &(const struct clk_parent_data) {
1663			.fw_name = "xtal",
1664		},
1665		.num_parents = 1,
1666	},
1667};
1668
1669static struct clk_regmap g12a_gp0_pll = {
1670	.data = &(struct clk_regmap_div_data){
1671		.offset = HHI_GP0_PLL_CNTL0,
1672		.shift = 16,
1673		.width = 3,
1674		.flags = (CLK_DIVIDER_POWER_OF_TWO |
1675			  CLK_DIVIDER_ROUND_CLOSEST),
1676	},
1677	.hw.init = &(struct clk_init_data){
1678		.name = "gp0_pll",
1679		.ops = &clk_regmap_divider_ops,
1680		.parent_hws = (const struct clk_hw *[]) {
1681			&g12a_gp0_pll_dco.hw
1682		},
1683		.num_parents = 1,
1684		.flags = CLK_SET_RATE_PARENT,
1685	},
1686};
1687
1688static struct clk_regmap sm1_gp1_pll_dco = {
1689	.data = &(struct meson_clk_pll_data){
1690		.en = {
1691			.reg_off = HHI_GP1_PLL_CNTL0,
1692			.shift   = 28,
1693			.width   = 1,
1694		},
1695		.m = {
1696			.reg_off = HHI_GP1_PLL_CNTL0,
1697			.shift   = 0,
1698			.width   = 8,
1699		},
1700		.n = {
1701			.reg_off = HHI_GP1_PLL_CNTL0,
1702			.shift   = 10,
1703			.width   = 5,
1704		},
1705		.frac = {
1706			.reg_off = HHI_GP1_PLL_CNTL1,
1707			.shift   = 0,
1708			.width   = 17,
1709		},
1710		.l = {
1711			.reg_off = HHI_GP1_PLL_CNTL0,
1712			.shift   = 31,
1713			.width   = 1,
1714		},
1715		.rst = {
1716			.reg_off = HHI_GP1_PLL_CNTL0,
1717			.shift   = 29,
1718			.width   = 1,
1719		},
1720	},
1721	.hw.init = &(struct clk_init_data){
1722		.name = "gp1_pll_dco",
1723		.ops = &meson_clk_pll_ro_ops,
1724		.parent_data = &(const struct clk_parent_data) {
1725			.fw_name = "xtal",
1726		},
1727		.num_parents = 1,
1728		/* This clock feeds the DSU, avoid disabling it */
1729		.flags = CLK_IS_CRITICAL,
1730	},
1731};
1732
1733static struct clk_regmap sm1_gp1_pll = {
1734	.data = &(struct clk_regmap_div_data){
1735		.offset = HHI_GP1_PLL_CNTL0,
1736		.shift = 16,
1737		.width = 3,
1738		.flags = (CLK_DIVIDER_POWER_OF_TWO |
1739			  CLK_DIVIDER_ROUND_CLOSEST),
1740	},
1741	.hw.init = &(struct clk_init_data){
1742		.name = "gp1_pll",
1743		.ops = &clk_regmap_divider_ro_ops,
1744		.parent_hws = (const struct clk_hw *[]) {
1745			&sm1_gp1_pll_dco.hw
1746		},
1747		.num_parents = 1,
1748	},
1749};
1750
1751/*
1752 * Internal hifi pll emulation configuration parameters
1753 */
1754static const struct reg_sequence g12a_hifi_init_regs[] = {
1755	{ .reg = HHI_HIFI_PLL_CNTL1,	.def = 0x00000000 },
1756	{ .reg = HHI_HIFI_PLL_CNTL2,	.def = 0x00000000 },
1757	{ .reg = HHI_HIFI_PLL_CNTL3,	.def = 0x6a285c00 },
1758	{ .reg = HHI_HIFI_PLL_CNTL4,	.def = 0x65771290 },
1759	{ .reg = HHI_HIFI_PLL_CNTL5,	.def = 0x39272000 },
1760	{ .reg = HHI_HIFI_PLL_CNTL6,	.def = 0x56540000 },
1761};
1762
1763static struct clk_regmap g12a_hifi_pll_dco = {
1764	.data = &(struct meson_clk_pll_data){
1765		.en = {
1766			.reg_off = HHI_HIFI_PLL_CNTL0,
1767			.shift   = 28,
1768			.width   = 1,
1769		},
1770		.m = {
1771			.reg_off = HHI_HIFI_PLL_CNTL0,
1772			.shift   = 0,
1773			.width   = 8,
1774		},
1775		.n = {
1776			.reg_off = HHI_HIFI_PLL_CNTL0,
1777			.shift   = 10,
1778			.width   = 5,
1779		},
1780		.frac = {
1781			.reg_off = HHI_HIFI_PLL_CNTL1,
1782			.shift   = 0,
1783			.width   = 17,
1784		},
1785		.l = {
1786			.reg_off = HHI_HIFI_PLL_CNTL0,
1787			.shift   = 31,
1788			.width   = 1,
1789		},
1790		.rst = {
1791			.reg_off = HHI_HIFI_PLL_CNTL0,
1792			.shift   = 29,
1793			.width   = 1,
1794		},
1795		.range = &g12a_gp0_pll_mult_range,
1796		.init_regs = g12a_hifi_init_regs,
1797		.init_count = ARRAY_SIZE(g12a_hifi_init_regs),
1798		.flags = CLK_MESON_PLL_ROUND_CLOSEST,
1799	},
1800	.hw.init = &(struct clk_init_data){
1801		.name = "hifi_pll_dco",
1802		.ops = &meson_clk_pll_ops,
1803		.parent_data = &(const struct clk_parent_data) {
1804			.fw_name = "xtal",
1805		},
1806		.num_parents = 1,
1807	},
1808};
1809
1810static struct clk_regmap g12a_hifi_pll = {
1811	.data = &(struct clk_regmap_div_data){
1812		.offset = HHI_HIFI_PLL_CNTL0,
1813		.shift = 16,
1814		.width = 2,
1815		.flags = (CLK_DIVIDER_POWER_OF_TWO |
1816			  CLK_DIVIDER_ROUND_CLOSEST),
1817	},
1818	.hw.init = &(struct clk_init_data){
1819		.name = "hifi_pll",
1820		.ops = &clk_regmap_divider_ops,
1821		.parent_hws = (const struct clk_hw *[]) {
1822			&g12a_hifi_pll_dco.hw
1823		},
1824		.num_parents = 1,
1825		.flags = CLK_SET_RATE_PARENT,
1826	},
1827};
1828
1829/*
1830 * The Meson G12A PCIE PLL is fined tuned to deliver a very precise
1831 * 100MHz reference clock for the PCIe Analog PHY, and thus requires
1832 * a strict register sequence to enable the PLL.
1833 */
1834static const struct reg_sequence g12a_pcie_pll_init_regs[] = {
1835	{ .reg = HHI_PCIE_PLL_CNTL0,	.def = 0x20090496 },
1836	{ .reg = HHI_PCIE_PLL_CNTL0,	.def = 0x30090496 },
1837	{ .reg = HHI_PCIE_PLL_CNTL1,	.def = 0x00000000 },
1838	{ .reg = HHI_PCIE_PLL_CNTL2,	.def = 0x00001100 },
1839	{ .reg = HHI_PCIE_PLL_CNTL3,	.def = 0x10058e00 },
1840	{ .reg = HHI_PCIE_PLL_CNTL4,	.def = 0x000100c0 },
1841	{ .reg = HHI_PCIE_PLL_CNTL5,	.def = 0x68000048 },
1842	{ .reg = HHI_PCIE_PLL_CNTL5,	.def = 0x68000068, .delay_us = 20 },
1843	{ .reg = HHI_PCIE_PLL_CNTL4,	.def = 0x008100c0, .delay_us = 10 },
1844	{ .reg = HHI_PCIE_PLL_CNTL0,	.def = 0x34090496 },
1845	{ .reg = HHI_PCIE_PLL_CNTL0,	.def = 0x14090496, .delay_us = 10 },
1846	{ .reg = HHI_PCIE_PLL_CNTL2,	.def = 0x00001000 },
1847};
1848
1849/* Keep a single entry table for recalc/round_rate() ops */
1850static const struct pll_params_table g12a_pcie_pll_table[] = {
1851	PLL_PARAMS(150, 1),
1852	{0, 0},
1853};
1854
1855static struct clk_regmap g12a_pcie_pll_dco = {
1856	.data = &(struct meson_clk_pll_data){
1857		.en = {
1858			.reg_off = HHI_PCIE_PLL_CNTL0,
1859			.shift   = 28,
1860			.width   = 1,
1861		},
1862		.m = {
1863			.reg_off = HHI_PCIE_PLL_CNTL0,
1864			.shift   = 0,
1865			.width   = 8,
1866		},
1867		.n = {
1868			.reg_off = HHI_PCIE_PLL_CNTL0,
1869			.shift   = 10,
1870			.width   = 5,
1871		},
1872		.frac = {
1873			.reg_off = HHI_PCIE_PLL_CNTL1,
1874			.shift   = 0,
1875			.width   = 12,
1876		},
1877		.l = {
1878			.reg_off = HHI_PCIE_PLL_CNTL0,
1879			.shift   = 31,
1880			.width   = 1,
1881		},
1882		.rst = {
1883			.reg_off = HHI_PCIE_PLL_CNTL0,
1884			.shift   = 29,
1885			.width   = 1,
1886		},
1887		.table = g12a_pcie_pll_table,
1888		.init_regs = g12a_pcie_pll_init_regs,
1889		.init_count = ARRAY_SIZE(g12a_pcie_pll_init_regs),
1890	},
1891	.hw.init = &(struct clk_init_data){
1892		.name = "pcie_pll_dco",
1893		.ops = &meson_clk_pcie_pll_ops,
1894		.parent_data = &(const struct clk_parent_data) {
1895			.fw_name = "xtal",
1896		},
1897		.num_parents = 1,
1898	},
1899};
1900
1901static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
1902	.mult = 1,
1903	.div = 2,
1904	.hw.init = &(struct clk_init_data){
1905		.name = "pcie_pll_dco_div2",
1906		.ops = &clk_fixed_factor_ops,
1907		.parent_hws = (const struct clk_hw *[]) {
1908			&g12a_pcie_pll_dco.hw
1909		},
1910		.num_parents = 1,
1911		.flags = CLK_SET_RATE_PARENT,
1912	},
1913};
1914
1915static struct clk_regmap g12a_pcie_pll_od = {
1916	.data = &(struct clk_regmap_div_data){
1917		.offset = HHI_PCIE_PLL_CNTL0,
1918		.shift = 16,
1919		.width = 5,
1920		.flags = CLK_DIVIDER_ROUND_CLOSEST |
1921			 CLK_DIVIDER_ONE_BASED |
1922			 CLK_DIVIDER_ALLOW_ZERO,
1923	},
1924	.hw.init = &(struct clk_init_data){
1925		.name = "pcie_pll_od",
1926		.ops = &clk_regmap_divider_ops,
1927		.parent_hws = (const struct clk_hw *[]) {
1928			&g12a_pcie_pll_dco_div2.hw
1929		},
1930		.num_parents = 1,
1931		.flags = CLK_SET_RATE_PARENT,
1932	},
1933};
1934
1935static struct clk_fixed_factor g12a_pcie_pll = {
1936	.mult = 1,
1937	.div = 2,
1938	.hw.init = &(struct clk_init_data){
1939		.name = "pcie_pll_pll",
1940		.ops = &clk_fixed_factor_ops,
1941		.parent_hws = (const struct clk_hw *[]) {
1942			&g12a_pcie_pll_od.hw
1943		},
1944		.num_parents = 1,
1945		.flags = CLK_SET_RATE_PARENT,
1946	},
1947};
1948
1949static struct clk_regmap g12a_hdmi_pll_dco = {
1950	.data = &(struct meson_clk_pll_data){
1951		.en = {
1952			.reg_off = HHI_HDMI_PLL_CNTL0,
1953			.shift   = 28,
1954			.width   = 1,
1955		},
1956		.m = {
1957			.reg_off = HHI_HDMI_PLL_CNTL0,
1958			.shift   = 0,
1959			.width   = 8,
1960		},
1961		.n = {
1962			.reg_off = HHI_HDMI_PLL_CNTL0,
1963			.shift   = 10,
1964			.width   = 5,
1965		},
1966		.frac = {
1967			.reg_off = HHI_HDMI_PLL_CNTL1,
1968			.shift   = 0,
1969			.width   = 16,
1970		},
1971		.l = {
1972			.reg_off = HHI_HDMI_PLL_CNTL0,
1973			.shift   = 30,
1974			.width   = 1,
1975		},
1976		.rst = {
1977			.reg_off = HHI_HDMI_PLL_CNTL0,
1978			.shift   = 29,
1979			.width   = 1,
1980		},
1981	},
1982	.hw.init = &(struct clk_init_data){
1983		.name = "hdmi_pll_dco",
1984		.ops = &meson_clk_pll_ro_ops,
1985		.parent_data = &(const struct clk_parent_data) {
1986			.fw_name = "xtal",
1987		},
1988		.num_parents = 1,
1989		/*
1990		 * Display directly handle hdmi pll registers ATM, we need
1991		 * NOCACHE to keep our view of the clock as accurate as possible
1992		 */
1993		.flags = CLK_GET_RATE_NOCACHE,
1994	},
1995};
1996
1997static struct clk_regmap g12a_hdmi_pll_od = {
1998	.data = &(struct clk_regmap_div_data){
1999		.offset = HHI_HDMI_PLL_CNTL0,
2000		.shift = 16,
2001		.width = 2,
2002		.flags = CLK_DIVIDER_POWER_OF_TWO,
2003	},
2004	.hw.init = &(struct clk_init_data){
2005		.name = "hdmi_pll_od",
2006		.ops = &clk_regmap_divider_ro_ops,
2007		.parent_hws = (const struct clk_hw *[]) {
2008			&g12a_hdmi_pll_dco.hw
2009		},
2010		.num_parents = 1,
2011		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2012	},
2013};
2014
2015static struct clk_regmap g12a_hdmi_pll_od2 = {
2016	.data = &(struct clk_regmap_div_data){
2017		.offset = HHI_HDMI_PLL_CNTL0,
2018		.shift = 18,
2019		.width = 2,
2020		.flags = CLK_DIVIDER_POWER_OF_TWO,
2021	},
2022	.hw.init = &(struct clk_init_data){
2023		.name = "hdmi_pll_od2",
2024		.ops = &clk_regmap_divider_ro_ops,
2025		.parent_hws = (const struct clk_hw *[]) {
2026			&g12a_hdmi_pll_od.hw
2027		},
2028		.num_parents = 1,
2029		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2030	},
2031};
2032
2033static struct clk_regmap g12a_hdmi_pll = {
2034	.data = &(struct clk_regmap_div_data){
2035		.offset = HHI_HDMI_PLL_CNTL0,
2036		.shift = 20,
2037		.width = 2,
2038		.flags = CLK_DIVIDER_POWER_OF_TWO,
2039	},
2040	.hw.init = &(struct clk_init_data){
2041		.name = "hdmi_pll",
2042		.ops = &clk_regmap_divider_ro_ops,
2043		.parent_hws = (const struct clk_hw *[]) {
2044			&g12a_hdmi_pll_od2.hw
2045		},
2046		.num_parents = 1,
2047		.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
2048	},
2049};
2050
2051static struct clk_fixed_factor g12a_fclk_div4_div = {
2052	.mult = 1,
2053	.div = 4,
2054	.hw.init = &(struct clk_init_data){
2055		.name = "fclk_div4_div",
2056		.ops = &clk_fixed_factor_ops,
2057		.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2058		.num_parents = 1,
2059	},
2060};
2061
2062static struct clk_regmap g12a_fclk_div4 = {
2063	.data = &(struct clk_regmap_gate_data){
2064		.offset = HHI_FIX_PLL_CNTL1,
2065		.bit_idx = 21,
2066	},
2067	.hw.init = &(struct clk_init_data){
2068		.name = "fclk_div4",
2069		.ops = &clk_regmap_gate_ops,
2070		.parent_hws = (const struct clk_hw *[]) {
2071			&g12a_fclk_div4_div.hw
2072		},
2073		.num_parents = 1,
2074	},
2075};
2076
2077static struct clk_fixed_factor g12a_fclk_div5_div = {
2078	.mult = 1,
2079	.div = 5,
2080	.hw.init = &(struct clk_init_data){
2081		.name = "fclk_div5_div",
2082		.ops = &clk_fixed_factor_ops,
2083		.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2084		.num_parents = 1,
2085	},
2086};
2087
2088static struct clk_regmap g12a_fclk_div5 = {
2089	.data = &(struct clk_regmap_gate_data){
2090		.offset = HHI_FIX_PLL_CNTL1,
2091		.bit_idx = 22,
2092	},
2093	.hw.init = &(struct clk_init_data){
2094		.name = "fclk_div5",
2095		.ops = &clk_regmap_gate_ops,
2096		.parent_hws = (const struct clk_hw *[]) {
2097			&g12a_fclk_div5_div.hw
2098		},
2099		.num_parents = 1,
2100	},
2101};
2102
2103static struct clk_fixed_factor g12a_fclk_div7_div = {
2104	.mult = 1,
2105	.div = 7,
2106	.hw.init = &(struct clk_init_data){
2107		.name = "fclk_div7_div",
2108		.ops = &clk_fixed_factor_ops,
2109		.parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
2110		.num_parents = 1,
2111	},
2112};
2113
2114static struct clk_regmap g12a_fclk_div7 = {
2115	.data = &(struct clk_regmap_gate_data){
2116		.offset = HHI_FIX_PLL_CNTL1,
2117		.bit_idx = 23,
2118	},
2119	.hw.init = &(struct clk_init_data){
2120		.name = "fclk_div7",
2121		.ops = &clk_regmap_gate_ops,
2122		.parent_hws = (const struct clk_hw *[]) {
2123			&g12a_fclk_div7_div.hw
2124		},
2125		.num_parents = 1,
2126	},
2127};
2128
2129static struct clk_fixed_factor g12a_fclk_div2p5_div = {
2130	.mult = 1,
2131	.div = 5,
2132	.hw.init = &(struct clk_init_data){
2133		.name = "fclk_div2p5_div",
2134		.ops = &clk_fixed_factor_ops,
2135		.parent_hws = (const struct clk_hw *[]) {
2136			&g12a_fixed_pll_dco.hw
2137		},
2138		.num_parents = 1,
2139	},
2140};
2141
2142static struct clk_regmap g12a_fclk_div2p5 = {
2143	.data = &(struct clk_regmap_gate_data){
2144		.offset = HHI_FIX_PLL_CNTL1,
2145		.bit_idx = 25,
2146	},
2147	.hw.init = &(struct clk_init_data){
2148		.name = "fclk_div2p5",
2149		.ops = &clk_regmap_gate_ops,
2150		.parent_hws = (const struct clk_hw *[]) {
2151			&g12a_fclk_div2p5_div.hw
2152		},
2153		.num_parents = 1,
2154	},
2155};
2156
2157static struct clk_fixed_factor g12a_mpll_50m_div = {
2158	.mult = 1,
2159	.div = 80,
2160	.hw.init = &(struct clk_init_data){
2161		.name = "mpll_50m_div",
2162		.ops = &clk_fixed_factor_ops,
2163		.parent_hws = (const struct clk_hw *[]) {
2164			&g12a_fixed_pll_dco.hw
2165		},
2166		.num_parents = 1,
2167	},
2168};
2169
2170static struct clk_regmap g12a_mpll_50m = {
2171	.data = &(struct clk_regmap_mux_data){
2172		.offset = HHI_FIX_PLL_CNTL3,
2173		.mask = 0x1,
2174		.shift = 5,
2175	},
2176	.hw.init = &(struct clk_init_data){
2177		.name = "mpll_50m",
2178		.ops = &clk_regmap_mux_ro_ops,
2179		.parent_data = (const struct clk_parent_data []) {
2180			{ .fw_name = "xtal", },
2181			{ .hw = &g12a_mpll_50m_div.hw },
2182		},
2183		.num_parents = 2,
2184	},
2185};
2186
2187static struct clk_fixed_factor g12a_mpll_prediv = {
2188	.mult = 1,
2189	.div = 2,
2190	.hw.init = &(struct clk_init_data){
2191		.name = "mpll_prediv",
2192		.ops = &clk_fixed_factor_ops,
2193		.parent_hws = (const struct clk_hw *[]) {
2194			&g12a_fixed_pll_dco.hw
2195		},
2196		.num_parents = 1,
2197	},
2198};
2199
2200static const struct reg_sequence g12a_mpll0_init_regs[] = {
2201	{ .reg = HHI_MPLL_CNTL2,	.def = 0x40000033 },
2202};
2203
2204static struct clk_regmap g12a_mpll0_div = {
2205	.data = &(struct meson_clk_mpll_data){
2206		.sdm = {
2207			.reg_off = HHI_MPLL_CNTL1,
2208			.shift   = 0,
2209			.width   = 14,
2210		},
2211		.sdm_en = {
2212			.reg_off = HHI_MPLL_CNTL1,
2213			.shift   = 30,
2214			.width	 = 1,
2215		},
2216		.n2 = {
2217			.reg_off = HHI_MPLL_CNTL1,
2218			.shift   = 20,
2219			.width   = 9,
2220		},
2221		.ssen = {
2222			.reg_off = HHI_MPLL_CNTL1,
2223			.shift   = 29,
2224			.width	 = 1,
2225		},
2226		.init_regs = g12a_mpll0_init_regs,
2227		.init_count = ARRAY_SIZE(g12a_mpll0_init_regs),
2228	},
2229	.hw.init = &(struct clk_init_data){
2230		.name = "mpll0_div",
2231		.ops = &meson_clk_mpll_ops,
2232		.parent_hws = (const struct clk_hw *[]) {
2233			&g12a_mpll_prediv.hw
2234		},
2235		.num_parents = 1,
2236	},
2237};
2238
2239static struct clk_regmap g12a_mpll0 = {
2240	.data = &(struct clk_regmap_gate_data){
2241		.offset = HHI_MPLL_CNTL1,
2242		.bit_idx = 31,
2243	},
2244	.hw.init = &(struct clk_init_data){
2245		.name = "mpll0",
2246		.ops = &clk_regmap_gate_ops,
2247		.parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
2248		.num_parents = 1,
2249		.flags = CLK_SET_RATE_PARENT,
2250	},
2251};
2252
2253static const struct reg_sequence g12a_mpll1_init_regs[] = {
2254	{ .reg = HHI_MPLL_CNTL4,	.def = 0x40000033 },
2255};
2256
2257static struct clk_regmap g12a_mpll1_div = {
2258	.data = &(struct meson_clk_mpll_data){
2259		.sdm = {
2260			.reg_off = HHI_MPLL_CNTL3,
2261			.shift   = 0,
2262			.width   = 14,
2263		},
2264		.sdm_en = {
2265			.reg_off = HHI_MPLL_CNTL3,
2266			.shift   = 30,
2267			.width	 = 1,
2268		},
2269		.n2 = {
2270			.reg_off = HHI_MPLL_CNTL3,
2271			.shift   = 20,
2272			.width   = 9,
2273		},
2274		.ssen = {
2275			.reg_off = HHI_MPLL_CNTL3,
2276			.shift   = 29,
2277			.width	 = 1,
2278		},
2279		.init_regs = g12a_mpll1_init_regs,
2280		.init_count = ARRAY_SIZE(g12a_mpll1_init_regs),
2281	},
2282	.hw.init = &(struct clk_init_data){
2283		.name = "mpll1_div",
2284		.ops = &meson_clk_mpll_ops,
2285		.parent_hws = (const struct clk_hw *[]) {
2286			&g12a_mpll_prediv.hw
2287		},
2288		.num_parents = 1,
2289	},
2290};
2291
2292static struct clk_regmap g12a_mpll1 = {
2293	.data = &(struct clk_regmap_gate_data){
2294		.offset = HHI_MPLL_CNTL3,
2295		.bit_idx = 31,
2296	},
2297	.hw.init = &(struct clk_init_data){
2298		.name = "mpll1",
2299		.ops = &clk_regmap_gate_ops,
2300		.parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
2301		.num_parents = 1,
2302		.flags = CLK_SET_RATE_PARENT,
2303	},
2304};
2305
2306static const struct reg_sequence g12a_mpll2_init_regs[] = {
2307	{ .reg = HHI_MPLL_CNTL6,	.def = 0x40000033 },
2308};
2309
2310static struct clk_regmap g12a_mpll2_div = {
2311	.data = &(struct meson_clk_mpll_data){
2312		.sdm = {
2313			.reg_off = HHI_MPLL_CNTL5,
2314			.shift   = 0,
2315			.width   = 14,
2316		},
2317		.sdm_en = {
2318			.reg_off = HHI_MPLL_CNTL5,
2319			.shift   = 30,
2320			.width	 = 1,
2321		},
2322		.n2 = {
2323			.reg_off = HHI_MPLL_CNTL5,
2324			.shift   = 20,
2325			.width   = 9,
2326		},
2327		.ssen = {
2328			.reg_off = HHI_MPLL_CNTL5,
2329			.shift   = 29,
2330			.width	 = 1,
2331		},
2332		.init_regs = g12a_mpll2_init_regs,
2333		.init_count = ARRAY_SIZE(g12a_mpll2_init_regs),
2334	},
2335	.hw.init = &(struct clk_init_data){
2336		.name = "mpll2_div",
2337		.ops = &meson_clk_mpll_ops,
2338		.parent_hws = (const struct clk_hw *[]) {
2339			&g12a_mpll_prediv.hw
2340		},
2341		.num_parents = 1,
2342	},
2343};
2344
2345static struct clk_regmap g12a_mpll2 = {
2346	.data = &(struct clk_regmap_gate_data){
2347		.offset = HHI_MPLL_CNTL5,
2348		.bit_idx = 31,
2349	},
2350	.hw.init = &(struct clk_init_data){
2351		.name = "mpll2",
2352		.ops = &clk_regmap_gate_ops,
2353		.parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
2354		.num_parents = 1,
2355		.flags = CLK_SET_RATE_PARENT,
2356	},
2357};
2358
2359static const struct reg_sequence g12a_mpll3_init_regs[] = {
2360	{ .reg = HHI_MPLL_CNTL8,	.def = 0x40000033 },
2361};
2362
2363static struct clk_regmap g12a_mpll3_div = {
2364	.data = &(struct meson_clk_mpll_data){
2365		.sdm = {
2366			.reg_off = HHI_MPLL_CNTL7,
2367			.shift   = 0,
2368			.width   = 14,
2369		},
2370		.sdm_en = {
2371			.reg_off = HHI_MPLL_CNTL7,
2372			.shift   = 30,
2373			.width	 = 1,
2374		},
2375		.n2 = {
2376			.reg_off = HHI_MPLL_CNTL7,
2377			.shift   = 20,
2378			.width   = 9,
2379		},
2380		.ssen = {
2381			.reg_off = HHI_MPLL_CNTL7,
2382			.shift   = 29,
2383			.width	 = 1,
2384		},
2385		.init_regs = g12a_mpll3_init_regs,
2386		.init_count = ARRAY_SIZE(g12a_mpll3_init_regs),
2387	},
2388	.hw.init = &(struct clk_init_data){
2389		.name = "mpll3_div",
2390		.ops = &meson_clk_mpll_ops,
2391		.parent_hws = (const struct clk_hw *[]) {
2392			&g12a_mpll_prediv.hw
2393		},
2394		.num_parents = 1,
2395	},
2396};
2397
2398static struct clk_regmap g12a_mpll3 = {
2399	.data = &(struct clk_regmap_gate_data){
2400		.offset = HHI_MPLL_CNTL7,
2401		.bit_idx = 31,
2402	},
2403	.hw.init = &(struct clk_init_data){
2404		.name = "mpll3",
2405		.ops = &clk_regmap_gate_ops,
2406		.parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
2407		.num_parents = 1,
2408		.flags = CLK_SET_RATE_PARENT,
2409	},
2410};
2411
2412static u32 mux_table_clk81[]	= { 0, 2, 3, 4, 5, 6, 7 };
2413static const struct clk_parent_data clk81_parent_data[] = {
2414	{ .fw_name = "xtal", },
2415	{ .hw = &g12a_fclk_div7.hw },
2416	{ .hw = &g12a_mpll1.hw },
2417	{ .hw = &g12a_mpll2.hw },
2418	{ .hw = &g12a_fclk_div4.hw },
2419	{ .hw = &g12a_fclk_div3.hw },
2420	{ .hw = &g12a_fclk_div5.hw },
2421};
2422
2423static struct clk_regmap g12a_mpeg_clk_sel = {
2424	.data = &(struct clk_regmap_mux_data){
2425		.offset = HHI_MPEG_CLK_CNTL,
2426		.mask = 0x7,
2427		.shift = 12,
2428		.table = mux_table_clk81,
2429	},
2430	.hw.init = &(struct clk_init_data){
2431		.name = "mpeg_clk_sel",
2432		.ops = &clk_regmap_mux_ro_ops,
2433		.parent_data = clk81_parent_data,
2434		.num_parents = ARRAY_SIZE(clk81_parent_data),
2435	},
2436};
2437
2438static struct clk_regmap g12a_mpeg_clk_div = {
2439	.data = &(struct clk_regmap_div_data){
2440		.offset = HHI_MPEG_CLK_CNTL,
2441		.shift = 0,
2442		.width = 7,
2443	},
2444	.hw.init = &(struct clk_init_data){
2445		.name = "mpeg_clk_div",
2446		.ops = &clk_regmap_divider_ops,
2447		.parent_hws = (const struct clk_hw *[]) {
2448			&g12a_mpeg_clk_sel.hw
2449		},
2450		.num_parents = 1,
2451		.flags = CLK_SET_RATE_PARENT,
2452	},
2453};
2454
2455static struct clk_regmap g12a_clk81 = {
2456	.data = &(struct clk_regmap_gate_data){
2457		.offset = HHI_MPEG_CLK_CNTL,
2458		.bit_idx = 7,
2459	},
2460	.hw.init = &(struct clk_init_data){
2461		.name = "clk81",
2462		.ops = &clk_regmap_gate_ops,
2463		.parent_hws = (const struct clk_hw *[]) {
2464			&g12a_mpeg_clk_div.hw
2465		},
2466		.num_parents = 1,
2467		.flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
2468	},
2469};
2470
2471static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = {
2472	{ .fw_name = "xtal", },
2473	{ .hw = &g12a_fclk_div2.hw },
2474	{ .hw = &g12a_fclk_div3.hw },
2475	{ .hw = &g12a_fclk_div5.hw },
2476	{ .hw = &g12a_fclk_div7.hw },
2477	/*
2478	 * Following these parent clocks, we should also have had mpll2, mpll3
2479	 * and gp0_pll but these clocks are too precious to be used here. All
2480	 * the necessary rates for MMC and NAND operation can be acheived using
2481	 * g12a_ee_core or fclk_div clocks
2482	 */
2483};
2484
2485/* SDIO clock */
2486static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
2487	.data = &(struct clk_regmap_mux_data){
2488		.offset = HHI_SD_EMMC_CLK_CNTL,
2489		.mask = 0x7,
2490		.shift = 9,
2491	},
2492	.hw.init = &(struct clk_init_data) {
2493		.name = "sd_emmc_a_clk0_sel",
2494		.ops = &clk_regmap_mux_ops,
2495		.parent_data = g12a_sd_emmc_clk0_parent_data,
2496		.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2497		.flags = CLK_SET_RATE_PARENT,
2498	},
2499};
2500
2501static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
2502	.data = &(struct clk_regmap_div_data){
2503		.offset = HHI_SD_EMMC_CLK_CNTL,
2504		.shift = 0,
2505		.width = 7,
2506	},
2507	.hw.init = &(struct clk_init_data) {
2508		.name = "sd_emmc_a_clk0_div",
2509		.ops = &clk_regmap_divider_ops,
2510		.parent_hws = (const struct clk_hw *[]) {
2511			&g12a_sd_emmc_a_clk0_sel.hw
2512		},
2513		.num_parents = 1,
2514		.flags = CLK_SET_RATE_PARENT,
2515	},
2516};
2517
2518static struct clk_regmap g12a_sd_emmc_a_clk0 = {
2519	.data = &(struct clk_regmap_gate_data){
2520		.offset = HHI_SD_EMMC_CLK_CNTL,
2521		.bit_idx = 7,
2522	},
2523	.hw.init = &(struct clk_init_data){
2524		.name = "sd_emmc_a_clk0",
2525		.ops = &clk_regmap_gate_ops,
2526		.parent_hws = (const struct clk_hw *[]) {
2527			&g12a_sd_emmc_a_clk0_div.hw
2528		},
2529		.num_parents = 1,
2530		.flags = CLK_SET_RATE_PARENT,
2531	},
2532};
2533
2534/* SDcard clock */
2535static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
2536	.data = &(struct clk_regmap_mux_data){
2537		.offset = HHI_SD_EMMC_CLK_CNTL,
2538		.mask = 0x7,
2539		.shift = 25,
2540	},
2541	.hw.init = &(struct clk_init_data) {
2542		.name = "sd_emmc_b_clk0_sel",
2543		.ops = &clk_regmap_mux_ops,
2544		.parent_data = g12a_sd_emmc_clk0_parent_data,
2545		.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2546		.flags = CLK_SET_RATE_PARENT,
2547	},
2548};
2549
2550static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
2551	.data = &(struct clk_regmap_div_data){
2552		.offset = HHI_SD_EMMC_CLK_CNTL,
2553		.shift = 16,
2554		.width = 7,
2555	},
2556	.hw.init = &(struct clk_init_data) {
2557		.name = "sd_emmc_b_clk0_div",
2558		.ops = &clk_regmap_divider_ops,
2559		.parent_hws = (const struct clk_hw *[]) {
2560			&g12a_sd_emmc_b_clk0_sel.hw
2561		},
2562		.num_parents = 1,
2563		.flags = CLK_SET_RATE_PARENT,
2564	},
2565};
2566
2567static struct clk_regmap g12a_sd_emmc_b_clk0 = {
2568	.data = &(struct clk_regmap_gate_data){
2569		.offset = HHI_SD_EMMC_CLK_CNTL,
2570		.bit_idx = 23,
2571	},
2572	.hw.init = &(struct clk_init_data){
2573		.name = "sd_emmc_b_clk0",
2574		.ops = &clk_regmap_gate_ops,
2575		.parent_hws = (const struct clk_hw *[]) {
2576			&g12a_sd_emmc_b_clk0_div.hw
2577		},
2578		.num_parents = 1,
2579		.flags = CLK_SET_RATE_PARENT,
2580	},
2581};
2582
2583/* EMMC/NAND clock */
2584static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
2585	.data = &(struct clk_regmap_mux_data){
2586		.offset = HHI_NAND_CLK_CNTL,
2587		.mask = 0x7,
2588		.shift = 9,
2589	},
2590	.hw.init = &(struct clk_init_data) {
2591		.name = "sd_emmc_c_clk0_sel",
2592		.ops = &clk_regmap_mux_ops,
2593		.parent_data = g12a_sd_emmc_clk0_parent_data,
2594		.num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
2595		.flags = CLK_SET_RATE_PARENT,
2596	},
2597};
2598
2599static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
2600	.data = &(struct clk_regmap_div_data){
2601		.offset = HHI_NAND_CLK_CNTL,
2602		.shift = 0,
2603		.width = 7,
2604	},
2605	.hw.init = &(struct clk_init_data) {
2606		.name = "sd_emmc_c_clk0_div",
2607		.ops = &clk_regmap_divider_ops,
2608		.parent_hws = (const struct clk_hw *[]) {
2609			&g12a_sd_emmc_c_clk0_sel.hw
2610		},
2611		.num_parents = 1,
2612		.flags = CLK_SET_RATE_PARENT,
2613	},
2614};
2615
2616static struct clk_regmap g12a_sd_emmc_c_clk0 = {
2617	.data = &(struct clk_regmap_gate_data){
2618		.offset = HHI_NAND_CLK_CNTL,
2619		.bit_idx = 7,
2620	},
2621	.hw.init = &(struct clk_init_data){
2622		.name = "sd_emmc_c_clk0",
2623		.ops = &clk_regmap_gate_ops,
2624		.parent_hws = (const struct clk_hw *[]) {
2625			&g12a_sd_emmc_c_clk0_div.hw
2626		},
2627		.num_parents = 1,
2628		.flags = CLK_SET_RATE_PARENT,
2629	},
2630};
2631
2632/* Video Clocks */
2633
2634static struct clk_regmap g12a_vid_pll_div = {
2635	.data = &(struct meson_vid_pll_div_data){
2636		.val = {
2637			.reg_off = HHI_VID_PLL_CLK_DIV,
2638			.shift   = 0,
2639			.width   = 15,
2640		},
2641		.sel = {
2642			.reg_off = HHI_VID_PLL_CLK_DIV,
2643			.shift   = 16,
2644			.width   = 2,
2645		},
2646	},
2647	.hw.init = &(struct clk_init_data) {
2648		.name = "vid_pll_div",
2649		.ops = &meson_vid_pll_div_ro_ops,
2650		.parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2651		.num_parents = 1,
2652		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2653	},
2654};
2655
2656static const struct clk_hw *g12a_vid_pll_parent_hws[] = {
2657	&g12a_vid_pll_div.hw,
2658	&g12a_hdmi_pll.hw,
2659};
2660
2661static struct clk_regmap g12a_vid_pll_sel = {
2662	.data = &(struct clk_regmap_mux_data){
2663		.offset = HHI_VID_PLL_CLK_DIV,
2664		.mask = 0x1,
2665		.shift = 18,
2666	},
2667	.hw.init = &(struct clk_init_data){
2668		.name = "vid_pll_sel",
2669		.ops = &clk_regmap_mux_ops,
2670		/*
2671		 * bit 18 selects from 2 possible parents:
2672		 * vid_pll_div or hdmi_pll
2673		 */
2674		.parent_hws = g12a_vid_pll_parent_hws,
2675		.num_parents = ARRAY_SIZE(g12a_vid_pll_parent_hws),
2676		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2677	},
2678};
2679
2680static struct clk_regmap g12a_vid_pll = {
2681	.data = &(struct clk_regmap_gate_data){
2682		.offset = HHI_VID_PLL_CLK_DIV,
2683		.bit_idx = 19,
2684	},
2685	.hw.init = &(struct clk_init_data) {
2686		.name = "vid_pll",
2687		.ops = &clk_regmap_gate_ops,
2688		.parent_hws = (const struct clk_hw *[]) {
2689			&g12a_vid_pll_sel.hw
2690		},
2691		.num_parents = 1,
2692		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2693	},
2694};
2695
2696/* VPU Clock */
2697
2698static const struct clk_hw *g12a_vpu_parent_hws[] = {
2699	&g12a_fclk_div3.hw,
2700	&g12a_fclk_div4.hw,
2701	&g12a_fclk_div5.hw,
2702	&g12a_fclk_div7.hw,
2703	&g12a_mpll1.hw,
2704	&g12a_vid_pll.hw,
2705	&g12a_hifi_pll.hw,
2706	&g12a_gp0_pll.hw,
2707};
2708
2709static struct clk_regmap g12a_vpu_0_sel = {
2710	.data = &(struct clk_regmap_mux_data){
2711		.offset = HHI_VPU_CLK_CNTL,
2712		.mask = 0x7,
2713		.shift = 9,
2714	},
2715	.hw.init = &(struct clk_init_data){
2716		.name = "vpu_0_sel",
2717		.ops = &clk_regmap_mux_ops,
2718		.parent_hws = g12a_vpu_parent_hws,
2719		.num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2720		.flags = CLK_SET_RATE_NO_REPARENT,
2721	},
2722};
2723
2724static struct clk_regmap g12a_vpu_0_div = {
2725	.data = &(struct clk_regmap_div_data){
2726		.offset = HHI_VPU_CLK_CNTL,
2727		.shift = 0,
2728		.width = 7,
2729	},
2730	.hw.init = &(struct clk_init_data){
2731		.name = "vpu_0_div",
2732		.ops = &clk_regmap_divider_ops,
2733		.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
2734		.num_parents = 1,
2735		.flags = CLK_SET_RATE_PARENT,
2736	},
2737};
2738
2739static struct clk_regmap g12a_vpu_0 = {
2740	.data = &(struct clk_regmap_gate_data){
2741		.offset = HHI_VPU_CLK_CNTL,
2742		.bit_idx = 8,
2743	},
2744	.hw.init = &(struct clk_init_data) {
2745		.name = "vpu_0",
2746		.ops = &clk_regmap_gate_ops,
2747		.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
2748		.num_parents = 1,
2749		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2750	},
2751};
2752
2753static struct clk_regmap g12a_vpu_1_sel = {
2754	.data = &(struct clk_regmap_mux_data){
2755		.offset = HHI_VPU_CLK_CNTL,
2756		.mask = 0x7,
2757		.shift = 25,
2758	},
2759	.hw.init = &(struct clk_init_data){
2760		.name = "vpu_1_sel",
2761		.ops = &clk_regmap_mux_ops,
2762		.parent_hws = g12a_vpu_parent_hws,
2763		.num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
2764		.flags = CLK_SET_RATE_NO_REPARENT,
2765	},
2766};
2767
2768static struct clk_regmap g12a_vpu_1_div = {
2769	.data = &(struct clk_regmap_div_data){
2770		.offset = HHI_VPU_CLK_CNTL,
2771		.shift = 16,
2772		.width = 7,
2773	},
2774	.hw.init = &(struct clk_init_data){
2775		.name = "vpu_1_div",
2776		.ops = &clk_regmap_divider_ops,
2777		.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
2778		.num_parents = 1,
2779		.flags = CLK_SET_RATE_PARENT,
2780	},
2781};
2782
2783static struct clk_regmap g12a_vpu_1 = {
2784	.data = &(struct clk_regmap_gate_data){
2785		.offset = HHI_VPU_CLK_CNTL,
2786		.bit_idx = 24,
2787	},
2788	.hw.init = &(struct clk_init_data) {
2789		.name = "vpu_1",
2790		.ops = &clk_regmap_gate_ops,
2791		.parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
2792		.num_parents = 1,
2793		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2794	},
2795};
2796
2797static struct clk_regmap g12a_vpu = {
2798	.data = &(struct clk_regmap_mux_data){
2799		.offset = HHI_VPU_CLK_CNTL,
2800		.mask = 1,
2801		.shift = 31,
2802	},
2803	.hw.init = &(struct clk_init_data){
2804		.name = "vpu",
2805		.ops = &clk_regmap_mux_ops,
2806		/*
2807		 * bit 31 selects from 2 possible parents:
2808		 * vpu_0 or vpu_1
2809		 */
2810		.parent_hws = (const struct clk_hw *[]) {
2811			&g12a_vpu_0.hw,
2812			&g12a_vpu_1.hw,
2813		},
2814		.num_parents = 2,
2815		.flags = CLK_SET_RATE_NO_REPARENT,
2816	},
2817};
2818
2819/* VDEC clocks */
2820
2821static const struct clk_hw *g12a_vdec_parent_hws[] = {
2822	&g12a_fclk_div2p5.hw,
2823	&g12a_fclk_div3.hw,
2824	&g12a_fclk_div4.hw,
2825	&g12a_fclk_div5.hw,
2826	&g12a_fclk_div7.hw,
2827	&g12a_hifi_pll.hw,
2828	&g12a_gp0_pll.hw,
2829};
2830
2831static struct clk_regmap g12a_vdec_1_sel = {
2832	.data = &(struct clk_regmap_mux_data){
2833		.offset = HHI_VDEC_CLK_CNTL,
2834		.mask = 0x7,
2835		.shift = 9,
2836		.flags = CLK_MUX_ROUND_CLOSEST,
2837	},
2838	.hw.init = &(struct clk_init_data){
2839		.name = "vdec_1_sel",
2840		.ops = &clk_regmap_mux_ops,
2841		.parent_hws = g12a_vdec_parent_hws,
2842		.num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2843		.flags = CLK_SET_RATE_PARENT,
2844	},
2845};
2846
2847static struct clk_regmap g12a_vdec_1_div = {
2848	.data = &(struct clk_regmap_div_data){
2849		.offset = HHI_VDEC_CLK_CNTL,
2850		.shift = 0,
2851		.width = 7,
2852		.flags = CLK_DIVIDER_ROUND_CLOSEST,
2853	},
2854	.hw.init = &(struct clk_init_data){
2855		.name = "vdec_1_div",
2856		.ops = &clk_regmap_divider_ops,
2857		.parent_hws = (const struct clk_hw *[]) {
2858			&g12a_vdec_1_sel.hw
2859		},
2860		.num_parents = 1,
2861		.flags = CLK_SET_RATE_PARENT,
2862	},
2863};
2864
2865static struct clk_regmap g12a_vdec_1 = {
2866	.data = &(struct clk_regmap_gate_data){
2867		.offset = HHI_VDEC_CLK_CNTL,
2868		.bit_idx = 8,
2869	},
2870	.hw.init = &(struct clk_init_data) {
2871		.name = "vdec_1",
2872		.ops = &clk_regmap_gate_ops,
2873		.parent_hws = (const struct clk_hw *[]) {
2874			&g12a_vdec_1_div.hw
2875		},
2876		.num_parents = 1,
2877		.flags = CLK_SET_RATE_PARENT,
2878	},
2879};
2880
2881static struct clk_regmap g12a_vdec_hevcf_sel = {
2882	.data = &(struct clk_regmap_mux_data){
2883		.offset = HHI_VDEC2_CLK_CNTL,
2884		.mask = 0x7,
2885		.shift = 9,
2886		.flags = CLK_MUX_ROUND_CLOSEST,
2887	},
2888	.hw.init = &(struct clk_init_data){
2889		.name = "vdec_hevcf_sel",
2890		.ops = &clk_regmap_mux_ops,
2891		.parent_hws = g12a_vdec_parent_hws,
2892		.num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2893		.flags = CLK_SET_RATE_PARENT,
2894	},
2895};
2896
2897static struct clk_regmap g12a_vdec_hevcf_div = {
2898	.data = &(struct clk_regmap_div_data){
2899		.offset = HHI_VDEC2_CLK_CNTL,
2900		.shift = 0,
2901		.width = 7,
2902		.flags = CLK_DIVIDER_ROUND_CLOSEST,
2903	},
2904	.hw.init = &(struct clk_init_data){
2905		.name = "vdec_hevcf_div",
2906		.ops = &clk_regmap_divider_ops,
2907		.parent_hws = (const struct clk_hw *[]) {
2908			&g12a_vdec_hevcf_sel.hw
2909		},
2910		.num_parents = 1,
2911		.flags = CLK_SET_RATE_PARENT,
2912	},
2913};
2914
2915static struct clk_regmap g12a_vdec_hevcf = {
2916	.data = &(struct clk_regmap_gate_data){
2917		.offset = HHI_VDEC2_CLK_CNTL,
2918		.bit_idx = 8,
2919	},
2920	.hw.init = &(struct clk_init_data) {
2921		.name = "vdec_hevcf",
2922		.ops = &clk_regmap_gate_ops,
2923		.parent_hws = (const struct clk_hw *[]) {
2924			&g12a_vdec_hevcf_div.hw
2925		},
2926		.num_parents = 1,
2927		.flags = CLK_SET_RATE_PARENT,
2928	},
2929};
2930
2931static struct clk_regmap g12a_vdec_hevc_sel = {
2932	.data = &(struct clk_regmap_mux_data){
2933		.offset = HHI_VDEC2_CLK_CNTL,
2934		.mask = 0x7,
2935		.shift = 25,
2936		.flags = CLK_MUX_ROUND_CLOSEST,
2937	},
2938	.hw.init = &(struct clk_init_data){
2939		.name = "vdec_hevc_sel",
2940		.ops = &clk_regmap_mux_ops,
2941		.parent_hws = g12a_vdec_parent_hws,
2942		.num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2943		.flags = CLK_SET_RATE_PARENT,
2944	},
2945};
2946
2947static struct clk_regmap g12a_vdec_hevc_div = {
2948	.data = &(struct clk_regmap_div_data){
2949		.offset = HHI_VDEC2_CLK_CNTL,
2950		.shift = 16,
2951		.width = 7,
2952		.flags = CLK_DIVIDER_ROUND_CLOSEST,
2953	},
2954	.hw.init = &(struct clk_init_data){
2955		.name = "vdec_hevc_div",
2956		.ops = &clk_regmap_divider_ops,
2957		.parent_hws = (const struct clk_hw *[]) {
2958			&g12a_vdec_hevc_sel.hw
2959		},
2960		.num_parents = 1,
2961		.flags = CLK_SET_RATE_PARENT,
2962	},
2963};
2964
2965static struct clk_regmap g12a_vdec_hevc = {
2966	.data = &(struct clk_regmap_gate_data){
2967		.offset = HHI_VDEC2_CLK_CNTL,
2968		.bit_idx = 24,
2969	},
2970	.hw.init = &(struct clk_init_data) {
2971		.name = "vdec_hevc",
2972		.ops = &clk_regmap_gate_ops,
2973		.parent_hws = (const struct clk_hw *[]) {
2974			&g12a_vdec_hevc_div.hw
2975		},
2976		.num_parents = 1,
2977		.flags = CLK_SET_RATE_PARENT,
2978	},
2979};
2980
2981/* VAPB Clock */
2982
2983static const struct clk_hw *g12a_vapb_parent_hws[] = {
2984	&g12a_fclk_div4.hw,
2985	&g12a_fclk_div3.hw,
2986	&g12a_fclk_div5.hw,
2987	&g12a_fclk_div7.hw,
2988	&g12a_mpll1.hw,
2989	&g12a_vid_pll.hw,
2990	&g12a_mpll2.hw,
2991	&g12a_fclk_div2p5.hw,
2992};
2993
2994static struct clk_regmap g12a_vapb_0_sel = {
2995	.data = &(struct clk_regmap_mux_data){
2996		.offset = HHI_VAPBCLK_CNTL,
2997		.mask = 0x3,
2998		.shift = 9,
2999	},
3000	.hw.init = &(struct clk_init_data){
3001		.name = "vapb_0_sel",
3002		.ops = &clk_regmap_mux_ops,
3003		.parent_hws = g12a_vapb_parent_hws,
3004		.num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
3005		.flags = CLK_SET_RATE_NO_REPARENT,
3006	},
3007};
3008
3009static struct clk_regmap g12a_vapb_0_div = {
3010	.data = &(struct clk_regmap_div_data){
3011		.offset = HHI_VAPBCLK_CNTL,
3012		.shift = 0,
3013		.width = 7,
3014	},
3015	.hw.init = &(struct clk_init_data){
3016		.name = "vapb_0_div",
3017		.ops = &clk_regmap_divider_ops,
3018		.parent_hws = (const struct clk_hw *[]) {
3019			&g12a_vapb_0_sel.hw
3020		},
3021		.num_parents = 1,
3022		.flags = CLK_SET_RATE_PARENT,
3023	},
3024};
3025
3026static struct clk_regmap g12a_vapb_0 = {
3027	.data = &(struct clk_regmap_gate_data){
3028		.offset = HHI_VAPBCLK_CNTL,
3029		.bit_idx = 8,
3030	},
3031	.hw.init = &(struct clk_init_data) {
3032		.name = "vapb_0",
3033		.ops = &clk_regmap_gate_ops,
3034		.parent_hws = (const struct clk_hw *[]) {
3035			&g12a_vapb_0_div.hw
3036		},
3037		.num_parents = 1,
3038		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3039	},
3040};
3041
3042static struct clk_regmap g12a_vapb_1_sel = {
3043	.data = &(struct clk_regmap_mux_data){
3044		.offset = HHI_VAPBCLK_CNTL,
3045		.mask = 0x3,
3046		.shift = 25,
3047	},
3048	.hw.init = &(struct clk_init_data){
3049		.name = "vapb_1_sel",
3050		.ops = &clk_regmap_mux_ops,
3051		.parent_hws = g12a_vapb_parent_hws,
3052		.num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
3053		.flags = CLK_SET_RATE_NO_REPARENT,
3054	},
3055};
3056
3057static struct clk_regmap g12a_vapb_1_div = {
3058	.data = &(struct clk_regmap_div_data){
3059		.offset = HHI_VAPBCLK_CNTL,
3060		.shift = 16,
3061		.width = 7,
3062	},
3063	.hw.init = &(struct clk_init_data){
3064		.name = "vapb_1_div",
3065		.ops = &clk_regmap_divider_ops,
3066		.parent_hws = (const struct clk_hw *[]) {
3067			&g12a_vapb_1_sel.hw
3068		},
3069		.num_parents = 1,
3070		.flags = CLK_SET_RATE_PARENT,
3071	},
3072};
3073
3074static struct clk_regmap g12a_vapb_1 = {
3075	.data = &(struct clk_regmap_gate_data){
3076		.offset = HHI_VAPBCLK_CNTL,
3077		.bit_idx = 24,
3078	},
3079	.hw.init = &(struct clk_init_data) {
3080		.name = "vapb_1",
3081		.ops = &clk_regmap_gate_ops,
3082		.parent_hws = (const struct clk_hw *[]) {
3083			&g12a_vapb_1_div.hw
3084		},
3085		.num_parents = 1,
3086		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3087	},
3088};
3089
3090static struct clk_regmap g12a_vapb_sel = {
3091	.data = &(struct clk_regmap_mux_data){
3092		.offset = HHI_VAPBCLK_CNTL,
3093		.mask = 1,
3094		.shift = 31,
3095	},
3096	.hw.init = &(struct clk_init_data){
3097		.name = "vapb_sel",
3098		.ops = &clk_regmap_mux_ops,
3099		/*
3100		 * bit 31 selects from 2 possible parents:
3101		 * vapb_0 or vapb_1
3102		 */
3103		.parent_hws = (const struct clk_hw *[]) {
3104			&g12a_vapb_0.hw,
3105			&g12a_vapb_1.hw,
3106		},
3107		.num_parents = 2,
3108		.flags = CLK_SET_RATE_NO_REPARENT,
3109	},
3110};
3111
3112static struct clk_regmap g12a_vapb = {
3113	.data = &(struct clk_regmap_gate_data){
3114		.offset = HHI_VAPBCLK_CNTL,
3115		.bit_idx = 30,
3116	},
3117	.hw.init = &(struct clk_init_data) {
3118		.name = "vapb",
3119		.ops = &clk_regmap_gate_ops,
3120		.parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
3121		.num_parents = 1,
3122		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3123	},
3124};
3125
3126static const struct clk_hw *g12a_vclk_parent_hws[] = {
3127	&g12a_vid_pll.hw,
3128	&g12a_gp0_pll.hw,
3129	&g12a_hifi_pll.hw,
3130	&g12a_mpll1.hw,
3131	&g12a_fclk_div3.hw,
3132	&g12a_fclk_div4.hw,
3133	&g12a_fclk_div5.hw,
3134	&g12a_fclk_div7.hw,
3135};
3136
3137static struct clk_regmap g12a_vclk_sel = {
3138	.data = &(struct clk_regmap_mux_data){
3139		.offset = HHI_VID_CLK_CNTL,
3140		.mask = 0x7,
3141		.shift = 16,
3142	},
3143	.hw.init = &(struct clk_init_data){
3144		.name = "vclk_sel",
3145		.ops = &clk_regmap_mux_ops,
3146		.parent_hws = g12a_vclk_parent_hws,
3147		.num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
3148		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3149	},
3150};
3151
3152static struct clk_regmap g12a_vclk2_sel = {
3153	.data = &(struct clk_regmap_mux_data){
3154		.offset = HHI_VIID_CLK_CNTL,
3155		.mask = 0x7,
3156		.shift = 16,
3157	},
3158	.hw.init = &(struct clk_init_data){
3159		.name = "vclk2_sel",
3160		.ops = &clk_regmap_mux_ops,
3161		.parent_hws = g12a_vclk_parent_hws,
3162		.num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
3163		.flags = CLK_SET_RATE_NO_REPARENT,
3164	},
3165};
3166
3167static struct clk_regmap g12a_vclk_input = {
3168	.data = &(struct clk_regmap_gate_data){
3169		.offset = HHI_VID_CLK_DIV,
3170		.bit_idx = 16,
3171	},
3172	.hw.init = &(struct clk_init_data) {
3173		.name = "vclk_input",
3174		.ops = &clk_regmap_gate_ops,
3175		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
3176		.num_parents = 1,
3177		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3178	},
3179};
3180
3181static struct clk_regmap g12a_vclk2_input = {
3182	.data = &(struct clk_regmap_gate_data){
3183		.offset = HHI_VIID_CLK_DIV,
3184		.bit_idx = 16,
3185	},
3186	.hw.init = &(struct clk_init_data) {
3187		.name = "vclk2_input",
3188		.ops = &clk_regmap_gate_ops,
3189		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
3190		.num_parents = 1,
3191	},
3192};
3193
3194static struct clk_regmap g12a_vclk_div = {
3195	.data = &(struct clk_regmap_div_data){
3196		.offset = HHI_VID_CLK_DIV,
3197		.shift = 0,
3198		.width = 8,
3199	},
3200	.hw.init = &(struct clk_init_data){
3201		.name = "vclk_div",
3202		.ops = &clk_regmap_divider_ops,
3203		.parent_hws = (const struct clk_hw *[]) {
3204			&g12a_vclk_input.hw
3205		},
3206		.num_parents = 1,
3207		.flags = CLK_GET_RATE_NOCACHE,
3208	},
3209};
3210
3211static struct clk_regmap g12a_vclk2_div = {
3212	.data = &(struct meson_vclk_div_data){
3213		.div = {
3214			.reg_off = HHI_VIID_CLK_DIV,
3215			.shift   = 0,
3216			.width   = 8,
3217		},
3218		.enable = {
3219			.reg_off = HHI_VIID_CLK_DIV,
3220			.shift   = 16,
3221			.width   = 1,
3222		},
3223		.reset = {
3224			.reg_off = HHI_VIID_CLK_DIV,
3225			.shift   = 17,
3226			.width   = 1,
3227		},
3228		.flags = CLK_DIVIDER_ROUND_CLOSEST,
3229	},
3230	.hw.init = &(struct clk_init_data){
3231		.name = "vclk2_div",
3232		.ops = &meson_vclk_div_ops,
3233		.parent_hws = (const struct clk_hw *[]) {
3234			&g12a_vclk2_input.hw
3235		},
3236		.num_parents = 1,
3237		.flags = CLK_SET_RATE_GATE,
3238	},
3239};
3240
3241static struct clk_regmap g12a_vclk = {
3242	.data = &(struct clk_regmap_gate_data){
3243		.offset = HHI_VID_CLK_CNTL,
3244		.bit_idx = 19,
3245	},
3246	.hw.init = &(struct clk_init_data) {
3247		.name = "vclk",
3248		.ops = &clk_regmap_gate_ops,
3249		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
3250		.num_parents = 1,
3251		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3252	},
3253};
3254
3255static struct clk_regmap g12a_vclk2 = {
3256	.data = &(struct meson_vclk_gate_data){
3257		.enable = {
3258			.reg_off = HHI_VIID_CLK_CNTL,
3259			.shift   = 19,
3260			.width   = 1,
3261		},
3262		.reset = {
3263			.reg_off = HHI_VIID_CLK_CNTL,
3264			.shift   = 15,
3265			.width   = 1,
3266		},
3267	},
3268	.hw.init = &(struct clk_init_data) {
3269		.name = "vclk2",
3270		.ops = &meson_vclk_gate_ops,
3271		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
3272		.num_parents = 1,
3273		.flags = CLK_SET_RATE_PARENT,
3274	},
3275};
3276
3277static struct clk_regmap g12a_vclk_div1 = {
3278	.data = &(struct clk_regmap_gate_data){
3279		.offset = HHI_VID_CLK_CNTL,
3280		.bit_idx = 0,
3281	},
3282	.hw.init = &(struct clk_init_data) {
3283		.name = "vclk_div1",
3284		.ops = &clk_regmap_gate_ops,
3285		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3286		.num_parents = 1,
3287		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3288	},
3289};
3290
3291static struct clk_regmap g12a_vclk_div2_en = {
3292	.data = &(struct clk_regmap_gate_data){
3293		.offset = HHI_VID_CLK_CNTL,
3294		.bit_idx = 1,
3295	},
3296	.hw.init = &(struct clk_init_data) {
3297		.name = "vclk_div2_en",
3298		.ops = &clk_regmap_gate_ops,
3299		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3300		.num_parents = 1,
3301		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3302	},
3303};
3304
3305static struct clk_regmap g12a_vclk_div4_en = {
3306	.data = &(struct clk_regmap_gate_data){
3307		.offset = HHI_VID_CLK_CNTL,
3308		.bit_idx = 2,
3309	},
3310	.hw.init = &(struct clk_init_data) {
3311		.name = "vclk_div4_en",
3312		.ops = &clk_regmap_gate_ops,
3313		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3314		.num_parents = 1,
3315		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3316	},
3317};
3318
3319static struct clk_regmap g12a_vclk_div6_en = {
3320	.data = &(struct clk_regmap_gate_data){
3321		.offset = HHI_VID_CLK_CNTL,
3322		.bit_idx = 3,
3323	},
3324	.hw.init = &(struct clk_init_data) {
3325		.name = "vclk_div6_en",
3326		.ops = &clk_regmap_gate_ops,
3327		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3328		.num_parents = 1,
3329		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3330	},
3331};
3332
3333static struct clk_regmap g12a_vclk_div12_en = {
3334	.data = &(struct clk_regmap_gate_data){
3335		.offset = HHI_VID_CLK_CNTL,
3336		.bit_idx = 4,
3337	},
3338	.hw.init = &(struct clk_init_data) {
3339		.name = "vclk_div12_en",
3340		.ops = &clk_regmap_gate_ops,
3341		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
3342		.num_parents = 1,
3343		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3344	},
3345};
3346
3347static struct clk_regmap g12a_vclk2_div1 = {
3348	.data = &(struct clk_regmap_gate_data){
3349		.offset = HHI_VIID_CLK_CNTL,
3350		.bit_idx = 0,
3351	},
3352	.hw.init = &(struct clk_init_data) {
3353		.name = "vclk2_div1",
3354		.ops = &clk_regmap_gate_ops,
3355		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3356		.num_parents = 1,
3357		.flags = CLK_SET_RATE_PARENT,
3358	},
3359};
3360
3361static struct clk_regmap g12a_vclk2_div2_en = {
3362	.data = &(struct clk_regmap_gate_data){
3363		.offset = HHI_VIID_CLK_CNTL,
3364		.bit_idx = 1,
3365	},
3366	.hw.init = &(struct clk_init_data) {
3367		.name = "vclk2_div2_en",
3368		.ops = &clk_regmap_gate_ops,
3369		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3370		.num_parents = 1,
3371		.flags = CLK_SET_RATE_PARENT,
3372	},
3373};
3374
3375static struct clk_regmap g12a_vclk2_div4_en = {
3376	.data = &(struct clk_regmap_gate_data){
3377		.offset = HHI_VIID_CLK_CNTL,
3378		.bit_idx = 2,
3379	},
3380	.hw.init = &(struct clk_init_data) {
3381		.name = "vclk2_div4_en",
3382		.ops = &clk_regmap_gate_ops,
3383		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3384		.num_parents = 1,
3385		.flags = CLK_SET_RATE_PARENT,
3386	},
3387};
3388
3389static struct clk_regmap g12a_vclk2_div6_en = {
3390	.data = &(struct clk_regmap_gate_data){
3391		.offset = HHI_VIID_CLK_CNTL,
3392		.bit_idx = 3,
3393	},
3394	.hw.init = &(struct clk_init_data) {
3395		.name = "vclk2_div6_en",
3396		.ops = &clk_regmap_gate_ops,
3397		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3398		.num_parents = 1,
3399		.flags = CLK_SET_RATE_PARENT,
3400	},
3401};
3402
3403static struct clk_regmap g12a_vclk2_div12_en = {
3404	.data = &(struct clk_regmap_gate_data){
3405		.offset = HHI_VIID_CLK_CNTL,
3406		.bit_idx = 4,
3407	},
3408	.hw.init = &(struct clk_init_data) {
3409		.name = "vclk2_div12_en",
3410		.ops = &clk_regmap_gate_ops,
3411		.parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
3412		.num_parents = 1,
3413		.flags = CLK_SET_RATE_PARENT,
3414	},
3415};
3416
3417static struct clk_fixed_factor g12a_vclk_div2 = {
3418	.mult = 1,
3419	.div = 2,
3420	.hw.init = &(struct clk_init_data){
3421		.name = "vclk_div2",
3422		.ops = &clk_fixed_factor_ops,
3423		.parent_hws = (const struct clk_hw *[]) {
3424			&g12a_vclk_div2_en.hw
3425		},
3426		.num_parents = 1,
3427	},
3428};
3429
3430static struct clk_fixed_factor g12a_vclk_div4 = {
3431	.mult = 1,
3432	.div = 4,
3433	.hw.init = &(struct clk_init_data){
3434		.name = "vclk_div4",
3435		.ops = &clk_fixed_factor_ops,
3436		.parent_hws = (const struct clk_hw *[]) {
3437			&g12a_vclk_div4_en.hw
3438		},
3439		.num_parents = 1,
3440	},
3441};
3442
3443static struct clk_fixed_factor g12a_vclk_div6 = {
3444	.mult = 1,
3445	.div = 6,
3446	.hw.init = &(struct clk_init_data){
3447		.name = "vclk_div6",
3448		.ops = &clk_fixed_factor_ops,
3449		.parent_hws = (const struct clk_hw *[]) {
3450			&g12a_vclk_div6_en.hw
3451		},
3452		.num_parents = 1,
3453	},
3454};
3455
3456static struct clk_fixed_factor g12a_vclk_div12 = {
3457	.mult = 1,
3458	.div = 12,
3459	.hw.init = &(struct clk_init_data){
3460		.name = "vclk_div12",
3461		.ops = &clk_fixed_factor_ops,
3462		.parent_hws = (const struct clk_hw *[]) {
3463			&g12a_vclk_div12_en.hw
3464		},
3465		.num_parents = 1,
3466	},
3467};
3468
3469static struct clk_fixed_factor g12a_vclk2_div2 = {
3470	.mult = 1,
3471	.div = 2,
3472	.hw.init = &(struct clk_init_data){
3473		.name = "vclk2_div2",
3474		.ops = &clk_fixed_factor_ops,
3475		.parent_hws = (const struct clk_hw *[]) {
3476			&g12a_vclk2_div2_en.hw
3477		},
3478		.num_parents = 1,
3479		.flags = CLK_SET_RATE_PARENT,
3480	},
3481};
3482
3483static struct clk_fixed_factor g12a_vclk2_div4 = {
3484	.mult = 1,
3485	.div = 4,
3486	.hw.init = &(struct clk_init_data){
3487		.name = "vclk2_div4",
3488		.ops = &clk_fixed_factor_ops,
3489		.parent_hws = (const struct clk_hw *[]) {
3490			&g12a_vclk2_div4_en.hw
3491		},
3492		.num_parents = 1,
3493		.flags = CLK_SET_RATE_PARENT,
3494	},
3495};
3496
3497static struct clk_fixed_factor g12a_vclk2_div6 = {
3498	.mult = 1,
3499	.div = 6,
3500	.hw.init = &(struct clk_init_data){
3501		.name = "vclk2_div6",
3502		.ops = &clk_fixed_factor_ops,
3503		.parent_hws = (const struct clk_hw *[]) {
3504			&g12a_vclk2_div6_en.hw
3505		},
3506		.num_parents = 1,
3507		.flags = CLK_SET_RATE_PARENT,
3508	},
3509};
3510
3511static struct clk_fixed_factor g12a_vclk2_div12 = {
3512	.mult = 1,
3513	.div = 12,
3514	.hw.init = &(struct clk_init_data){
3515		.name = "vclk2_div12",
3516		.ops = &clk_fixed_factor_ops,
3517		.parent_hws = (const struct clk_hw *[]) {
3518			&g12a_vclk2_div12_en.hw
3519		},
3520		.num_parents = 1,
3521		.flags = CLK_SET_RATE_PARENT,
3522	},
3523};
3524
3525static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3526static const struct clk_hw *g12a_cts_parent_hws[] = {
3527	&g12a_vclk_div1.hw,
3528	&g12a_vclk_div2.hw,
3529	&g12a_vclk_div4.hw,
3530	&g12a_vclk_div6.hw,
3531	&g12a_vclk_div12.hw,
3532	&g12a_vclk2_div1.hw,
3533	&g12a_vclk2_div2.hw,
3534	&g12a_vclk2_div4.hw,
3535	&g12a_vclk2_div6.hw,
3536	&g12a_vclk2_div12.hw,
3537};
3538
3539static struct clk_regmap g12a_cts_enci_sel = {
3540	.data = &(struct clk_regmap_mux_data){
3541		.offset = HHI_VID_CLK_DIV,
3542		.mask = 0xf,
3543		.shift = 28,
3544		.table = mux_table_cts_sel,
3545	},
3546	.hw.init = &(struct clk_init_data){
3547		.name = "cts_enci_sel",
3548		.ops = &clk_regmap_mux_ops,
3549		.parent_hws = g12a_cts_parent_hws,
3550		.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3551		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3552	},
3553};
3554
3555static struct clk_regmap g12a_cts_encp_sel = {
3556	.data = &(struct clk_regmap_mux_data){
3557		.offset = HHI_VID_CLK_DIV,
3558		.mask = 0xf,
3559		.shift = 20,
3560		.table = mux_table_cts_sel,
3561	},
3562	.hw.init = &(struct clk_init_data){
3563		.name = "cts_encp_sel",
3564		.ops = &clk_regmap_mux_ops,
3565		.parent_hws = g12a_cts_parent_hws,
3566		.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3567		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3568	},
3569};
3570
3571static struct clk_regmap g12a_cts_encl_sel = {
3572	.data = &(struct clk_regmap_mux_data){
3573		.offset = HHI_VIID_CLK_DIV,
3574		.mask = 0xf,
3575		.shift = 12,
3576		.table = mux_table_cts_sel,
3577	},
3578	.hw.init = &(struct clk_init_data){
3579		.name = "cts_encl_sel",
3580		.ops = &clk_regmap_mux_ops,
3581		.parent_hws = g12a_cts_parent_hws,
3582		.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3583		.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
3584	},
3585};
3586
3587static struct clk_regmap g12a_cts_vdac_sel = {
3588	.data = &(struct clk_regmap_mux_data){
3589		.offset = HHI_VIID_CLK_DIV,
3590		.mask = 0xf,
3591		.shift = 28,
3592		.table = mux_table_cts_sel,
3593	},
3594	.hw.init = &(struct clk_init_data){
3595		.name = "cts_vdac_sel",
3596		.ops = &clk_regmap_mux_ops,
3597		.parent_hws = g12a_cts_parent_hws,
3598		.num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
3599		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3600	},
3601};
3602
3603/* TOFIX: add support for cts_tcon */
3604static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
3605static const struct clk_hw *g12a_cts_hdmi_tx_parent_hws[] = {
3606	&g12a_vclk_div1.hw,
3607	&g12a_vclk_div2.hw,
3608	&g12a_vclk_div4.hw,
3609	&g12a_vclk_div6.hw,
3610	&g12a_vclk_div12.hw,
3611	&g12a_vclk2_div1.hw,
3612	&g12a_vclk2_div2.hw,
3613	&g12a_vclk2_div4.hw,
3614	&g12a_vclk2_div6.hw,
3615	&g12a_vclk2_div12.hw,
3616};
3617
3618static struct clk_regmap g12a_hdmi_tx_sel = {
3619	.data = &(struct clk_regmap_mux_data){
3620		.offset = HHI_HDMI_CLK_CNTL,
3621		.mask = 0xf,
3622		.shift = 16,
3623		.table = mux_table_hdmi_tx_sel,
3624	},
3625	.hw.init = &(struct clk_init_data){
3626		.name = "hdmi_tx_sel",
3627		.ops = &clk_regmap_mux_ops,
3628		.parent_hws = g12a_cts_hdmi_tx_parent_hws,
3629		.num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_hws),
3630		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3631	},
3632};
3633
3634static struct clk_regmap g12a_cts_enci = {
3635	.data = &(struct clk_regmap_gate_data){
3636		.offset = HHI_VID_CLK_CNTL2,
3637		.bit_idx = 0,
3638	},
3639	.hw.init = &(struct clk_init_data) {
3640		.name = "cts_enci",
3641		.ops = &clk_regmap_gate_ops,
3642		.parent_hws = (const struct clk_hw *[]) {
3643			&g12a_cts_enci_sel.hw
3644		},
3645		.num_parents = 1,
3646		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3647	},
3648};
3649
3650static struct clk_regmap g12a_cts_encp = {
3651	.data = &(struct clk_regmap_gate_data){
3652		.offset = HHI_VID_CLK_CNTL2,
3653		.bit_idx = 2,
3654	},
3655	.hw.init = &(struct clk_init_data) {
3656		.name = "cts_encp",
3657		.ops = &clk_regmap_gate_ops,
3658		.parent_hws = (const struct clk_hw *[]) {
3659			&g12a_cts_encp_sel.hw
3660		},
3661		.num_parents = 1,
3662		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3663	},
3664};
3665
3666static struct clk_regmap g12a_cts_encl = {
3667	.data = &(struct clk_regmap_gate_data){
3668		.offset = HHI_VID_CLK_CNTL2,
3669		.bit_idx = 3,
3670	},
3671	.hw.init = &(struct clk_init_data) {
3672		.name = "cts_encl",
3673		.ops = &clk_regmap_gate_ops,
3674		.parent_hws = (const struct clk_hw *[]) {
3675			&g12a_cts_encl_sel.hw
3676		},
3677		.num_parents = 1,
3678		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3679	},
3680};
3681
3682static struct clk_regmap g12a_cts_vdac = {
3683	.data = &(struct clk_regmap_gate_data){
3684		.offset = HHI_VID_CLK_CNTL2,
3685		.bit_idx = 4,
3686	},
3687	.hw.init = &(struct clk_init_data) {
3688		.name = "cts_vdac",
3689		.ops = &clk_regmap_gate_ops,
3690		.parent_hws = (const struct clk_hw *[]) {
3691			&g12a_cts_vdac_sel.hw
3692		},
3693		.num_parents = 1,
3694		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3695	},
3696};
3697
3698static struct clk_regmap g12a_hdmi_tx = {
3699	.data = &(struct clk_regmap_gate_data){
3700		.offset = HHI_VID_CLK_CNTL2,
3701		.bit_idx = 5,
3702	},
3703	.hw.init = &(struct clk_init_data) {
3704		.name = "hdmi_tx",
3705		.ops = &clk_regmap_gate_ops,
3706		.parent_hws = (const struct clk_hw *[]) {
3707			&g12a_hdmi_tx_sel.hw
3708		},
3709		.num_parents = 1,
3710		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3711	},
3712};
3713
3714/* MIPI DSI Host Clocks */
3715
3716static const struct clk_hw *g12a_mipi_dsi_pxclk_parent_hws[] = {
3717	&g12a_vid_pll.hw,
3718	&g12a_gp0_pll.hw,
3719	&g12a_hifi_pll.hw,
3720	&g12a_mpll1.hw,
3721	&g12a_fclk_div2.hw,
3722	&g12a_fclk_div2p5.hw,
3723	&g12a_fclk_div3.hw,
3724	&g12a_fclk_div7.hw,
3725};
3726
3727static struct clk_regmap g12a_mipi_dsi_pxclk_sel = {
3728	.data = &(struct clk_regmap_mux_data){
3729		.offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3730		.mask = 0x7,
3731		.shift = 12,
3732		.flags = CLK_MUX_ROUND_CLOSEST,
3733	},
3734	.hw.init = &(struct clk_init_data){
3735		.name = "mipi_dsi_pxclk_sel",
3736		.ops = &clk_regmap_mux_ops,
3737		.parent_hws = g12a_mipi_dsi_pxclk_parent_hws,
3738		.num_parents = ARRAY_SIZE(g12a_mipi_dsi_pxclk_parent_hws),
3739		.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
3740	},
3741};
3742
3743/*
3744 * FIXME: Force as bypass by forcing a single /1 table entry, and doensn't on boot value
3745 * when setting a clock whith this node in the clock path, but doesn't garantee the divider
3746 * is at /1 at boot until a rate is set.
3747 */
3748static const struct clk_div_table g12a_mipi_dsi_pxclk_div_table[] = {
3749	{ .val = 0, .div = 1 },
3750	{ /* sentinel */ },
3751};
3752
3753static struct clk_regmap g12a_mipi_dsi_pxclk_div = {
3754	.data = &(struct clk_regmap_div_data){
3755		.offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3756		.shift = 0,
3757		.width = 7,
3758		.table = g12a_mipi_dsi_pxclk_div_table,
3759	},
3760	.hw.init = &(struct clk_init_data){
3761		.name = "mipi_dsi_pxclk_div",
3762		.ops = &clk_regmap_divider_ops,
3763		.parent_hws = (const struct clk_hw *[]) {
3764			&g12a_mipi_dsi_pxclk_sel.hw
3765		},
3766		.num_parents = 1,
3767		.flags = CLK_SET_RATE_PARENT,
3768	},
3769};
3770
3771static struct clk_regmap g12a_mipi_dsi_pxclk = {
3772	.data = &(struct clk_regmap_gate_data){
3773		.offset = HHI_MIPIDSI_PHY_CLK_CNTL,
3774		.bit_idx = 8,
3775	},
3776	.hw.init = &(struct clk_init_data) {
3777		.name = "mipi_dsi_pxclk",
3778		.ops = &clk_regmap_gate_ops,
3779		.parent_hws = (const struct clk_hw *[]) {
3780			&g12a_mipi_dsi_pxclk_div.hw
3781		},
3782		.num_parents = 1,
3783		.flags = CLK_SET_RATE_PARENT,
3784	},
3785};
3786
3787/* MIPI ISP Clocks */
3788
3789static const struct clk_parent_data g12b_mipi_isp_parent_data[] = {
3790	{ .fw_name = "xtal", },
3791	{ .hw = &g12a_gp0_pll.hw },
3792	{ .hw = &g12a_hifi_pll.hw },
3793	{ .hw = &g12a_fclk_div2p5.hw },
3794	{ .hw = &g12a_fclk_div3.hw },
3795	{ .hw = &g12a_fclk_div4.hw },
3796	{ .hw = &g12a_fclk_div5.hw },
3797	{ .hw = &g12a_fclk_div7.hw },
3798};
3799
3800static struct clk_regmap g12b_mipi_isp_sel = {
3801	.data = &(struct clk_regmap_mux_data){
3802		.offset = HHI_ISP_CLK_CNTL,
3803		.mask = 7,
3804		.shift = 9,
3805	},
3806	.hw.init = &(struct clk_init_data){
3807		.name = "mipi_isp_sel",
3808		.ops = &clk_regmap_mux_ops,
3809		.parent_data = g12b_mipi_isp_parent_data,
3810		.num_parents = ARRAY_SIZE(g12b_mipi_isp_parent_data),
3811	},
3812};
3813
3814static struct clk_regmap g12b_mipi_isp_div = {
3815	.data = &(struct clk_regmap_div_data){
3816		.offset = HHI_ISP_CLK_CNTL,
3817		.shift = 0,
3818		.width = 7,
3819	},
3820	.hw.init = &(struct clk_init_data){
3821		.name = "mipi_isp_div",
3822		.ops = &clk_regmap_divider_ops,
3823		.parent_hws = (const struct clk_hw *[]) {
3824			&g12b_mipi_isp_sel.hw
3825		},
3826		.num_parents = 1,
3827		.flags = CLK_SET_RATE_PARENT,
3828	},
3829};
3830
3831static struct clk_regmap g12b_mipi_isp = {
3832	.data = &(struct clk_regmap_gate_data){
3833		.offset = HHI_ISP_CLK_CNTL,
3834		.bit_idx = 8,
3835	},
3836	.hw.init = &(struct clk_init_data) {
3837		.name = "mipi_isp",
3838		.ops = &clk_regmap_gate_ops,
3839		.parent_hws = (const struct clk_hw *[]) {
3840			&g12b_mipi_isp_div.hw
3841		},
3842		.num_parents = 1,
3843		.flags = CLK_SET_RATE_PARENT,
3844	},
3845};
3846
3847/* HDMI Clocks */
3848
3849static const struct clk_parent_data g12a_hdmi_parent_data[] = {
3850	{ .fw_name = "xtal", },
3851	{ .hw = &g12a_fclk_div4.hw },
3852	{ .hw = &g12a_fclk_div3.hw },
3853	{ .hw = &g12a_fclk_div5.hw },
3854};
3855
3856static struct clk_regmap g12a_hdmi_sel = {
3857	.data = &(struct clk_regmap_mux_data){
3858		.offset = HHI_HDMI_CLK_CNTL,
3859		.mask = 0x3,
3860		.shift = 9,
3861		.flags = CLK_MUX_ROUND_CLOSEST,
3862	},
3863	.hw.init = &(struct clk_init_data){
3864		.name = "hdmi_sel",
3865		.ops = &clk_regmap_mux_ops,
3866		.parent_data = g12a_hdmi_parent_data,
3867		.num_parents = ARRAY_SIZE(g12a_hdmi_parent_data),
3868		.flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
3869	},
3870};
3871
3872static struct clk_regmap g12a_hdmi_div = {
3873	.data = &(struct clk_regmap_div_data){
3874		.offset = HHI_HDMI_CLK_CNTL,
3875		.shift = 0,
3876		.width = 7,
3877	},
3878	.hw.init = &(struct clk_init_data){
3879		.name = "hdmi_div",
3880		.ops = &clk_regmap_divider_ops,
3881		.parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
3882		.num_parents = 1,
3883		.flags = CLK_GET_RATE_NOCACHE,
3884	},
3885};
3886
3887static struct clk_regmap g12a_hdmi = {
3888	.data = &(struct clk_regmap_gate_data){
3889		.offset = HHI_HDMI_CLK_CNTL,
3890		.bit_idx = 8,
3891	},
3892	.hw.init = &(struct clk_init_data) {
3893		.name = "hdmi",
3894		.ops = &clk_regmap_gate_ops,
3895		.parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
3896		.num_parents = 1,
3897		.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
3898	},
3899};
3900
3901/*
3902 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
3903 * muxed by a glitch-free switch. The CCF can manage this glitch-free
3904 * mux because it does top-to-bottom updates the each clock tree and
3905 * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
3906 */
3907static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {
3908	{ .fw_name = "xtal", },
3909	{ .hw = &g12a_gp0_pll.hw },
3910	{ .hw = &g12a_hifi_pll.hw },
3911	{ .hw = &g12a_fclk_div2p5.hw },
3912	{ .hw = &g12a_fclk_div3.hw },
3913	{ .hw = &g12a_fclk_div4.hw },
3914	{ .hw = &g12a_fclk_div5.hw },
3915	{ .hw = &g12a_fclk_div7.hw },
3916};
3917
3918static struct clk_regmap g12a_mali_0_sel = {
3919	.data = &(struct clk_regmap_mux_data){
3920		.offset = HHI_MALI_CLK_CNTL,
3921		.mask = 0x7,
3922		.shift = 9,
3923	},
3924	.hw.init = &(struct clk_init_data){
3925		.name = "mali_0_sel",
3926		.ops = &clk_regmap_mux_ops,
3927		.parent_data = g12a_mali_0_1_parent_data,
3928		.num_parents = 8,
3929		/*
3930		 * Don't request the parent to change the rate because
3931		 * all GPU frequencies can be derived from the fclk_*
3932		 * clocks and one special GP0_PLL setting. This is
3933		 * important because we need the MPLL clocks for audio.
3934		 */
3935		.flags = 0,
3936	},
3937};
3938
3939static struct clk_regmap g12a_mali_0_div = {
3940	.data = &(struct clk_regmap_div_data){
3941		.offset = HHI_MALI_CLK_CNTL,
3942		.shift = 0,
3943		.width = 7,
3944	},
3945	.hw.init = &(struct clk_init_data){
3946		.name = "mali_0_div",
3947		.ops = &clk_regmap_divider_ops,
3948		.parent_hws = (const struct clk_hw *[]) {
3949			&g12a_mali_0_sel.hw
3950		},
3951		.num_parents = 1,
3952		.flags = CLK_SET_RATE_PARENT,
3953	},
3954};
3955
3956static struct clk_regmap g12a_mali_0 = {
3957	.data = &(struct clk_regmap_gate_data){
3958		.offset = HHI_MALI_CLK_CNTL,
3959		.bit_idx = 8,
3960	},
3961	.hw.init = &(struct clk_init_data){
3962		.name = "mali_0",
3963		.ops = &clk_regmap_gate_ops,
3964		.parent_hws = (const struct clk_hw *[]) {
3965			&g12a_mali_0_div.hw
3966		},
3967		.num_parents = 1,
3968		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
3969	},
3970};
3971
3972static struct clk_regmap g12a_mali_1_sel = {
3973	.data = &(struct clk_regmap_mux_data){
3974		.offset = HHI_MALI_CLK_CNTL,
3975		.mask = 0x7,
3976		.shift = 25,
3977	},
3978	.hw.init = &(struct clk_init_data){
3979		.name = "mali_1_sel",
3980		.ops = &clk_regmap_mux_ops,
3981		.parent_data = g12a_mali_0_1_parent_data,
3982		.num_parents = 8,
3983		/*
3984		 * Don't request the parent to change the rate because
3985		 * all GPU frequencies can be derived from the fclk_*
3986		 * clocks and one special GP0_PLL setting. This is
3987		 * important because we need the MPLL clocks for audio.
3988		 */
3989		.flags = 0,
3990	},
3991};
3992
3993static struct clk_regmap g12a_mali_1_div = {
3994	.data = &(struct clk_regmap_div_data){
3995		.offset = HHI_MALI_CLK_CNTL,
3996		.shift = 16,
3997		.width = 7,
3998	},
3999	.hw.init = &(struct clk_init_data){
4000		.name = "mali_1_div",
4001		.ops = &clk_regmap_divider_ops,
4002		.parent_hws = (const struct clk_hw *[]) {
4003			&g12a_mali_1_sel.hw
4004		},
4005		.num_parents = 1,
4006		.flags = CLK_SET_RATE_PARENT,
4007	},
4008};
4009
4010static struct clk_regmap g12a_mali_1 = {
4011	.data = &(struct clk_regmap_gate_data){
4012		.offset = HHI_MALI_CLK_CNTL,
4013		.bit_idx = 24,
4014	},
4015	.hw.init = &(struct clk_init_data){
4016		.name = "mali_1",
4017		.ops = &clk_regmap_gate_ops,
4018		.parent_hws = (const struct clk_hw *[]) {
4019			&g12a_mali_1_div.hw
4020		},
4021		.num_parents = 1,
4022		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
4023	},
4024};
4025
4026static const struct clk_hw *g12a_mali_parent_hws[] = {
4027	&g12a_mali_0.hw,
4028	&g12a_mali_1.hw,
4029};
4030
4031static struct clk_regmap g12a_mali = {
4032	.data = &(struct clk_regmap_mux_data){
4033		.offset = HHI_MALI_CLK_CNTL,
4034		.mask = 1,
4035		.shift = 31,
4036	},
4037	.hw.init = &(struct clk_init_data){
4038		.name = "mali",
4039		.ops = &clk_regmap_mux_ops,
4040		.parent_hws = g12a_mali_parent_hws,
4041		.num_parents = 2,
4042		.flags = CLK_SET_RATE_PARENT,
4043	},
4044};
4045
4046static struct clk_regmap g12a_ts_div = {
4047	.data = &(struct clk_regmap_div_data){
4048		.offset = HHI_TS_CLK_CNTL,
4049		.shift = 0,
4050		.width = 8,
4051	},
4052	.hw.init = &(struct clk_init_data){
4053		.name = "ts_div",
4054		.ops = &clk_regmap_divider_ro_ops,
4055		.parent_data = &(const struct clk_parent_data) {
4056			.fw_name = "xtal",
4057		},
4058		.num_parents = 1,
4059	},
4060};
4061
4062static struct clk_regmap g12a_ts = {
4063	.data = &(struct clk_regmap_gate_data){
4064		.offset = HHI_TS_CLK_CNTL,
4065		.bit_idx = 8,
4066	},
4067	.hw.init = &(struct clk_init_data){
4068		.name = "ts",
4069		.ops = &clk_regmap_gate_ops,
4070		.parent_hws = (const struct clk_hw *[]) {
4071			&g12a_ts_div.hw
4072		},
4073		.num_parents = 1,
4074	},
4075};
4076
4077/* SPICC SCLK source clock */
4078
4079static const struct clk_parent_data spicc_sclk_parent_data[] = {
4080	{ .fw_name = "xtal", },
4081	{ .hw = &g12a_clk81.hw },
4082	{ .hw = &g12a_fclk_div4.hw },
4083	{ .hw = &g12a_fclk_div3.hw },
4084	{ .hw = &g12a_fclk_div5.hw },
4085	{ .hw = &g12a_fclk_div7.hw },
4086};
4087
4088static struct clk_regmap g12a_spicc0_sclk_sel = {
4089	.data = &(struct clk_regmap_mux_data){
4090		.offset = HHI_SPICC_CLK_CNTL,
4091		.mask = 7,
4092		.shift = 7,
4093	},
4094	.hw.init = &(struct clk_init_data){
4095		.name = "spicc0_sclk_sel",
4096		.ops = &clk_regmap_mux_ops,
4097		.parent_data = spicc_sclk_parent_data,
4098		.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
4099	},
4100};
4101
4102static struct clk_regmap g12a_spicc0_sclk_div = {
4103	.data = &(struct clk_regmap_div_data){
4104		.offset = HHI_SPICC_CLK_CNTL,
4105		.shift = 0,
4106		.width = 6,
4107	},
4108	.hw.init = &(struct clk_init_data){
4109		.name = "spicc0_sclk_div",
4110		.ops = &clk_regmap_divider_ops,
4111		.parent_hws = (const struct clk_hw *[]) {
4112			&g12a_spicc0_sclk_sel.hw
4113		},
4114		.num_parents = 1,
4115		.flags = CLK_SET_RATE_PARENT,
4116	},
4117};
4118
4119static struct clk_regmap g12a_spicc0_sclk = {
4120	.data = &(struct clk_regmap_gate_data){
4121		.offset = HHI_SPICC_CLK_CNTL,
4122		.bit_idx = 6,
4123	},
4124	.hw.init = &(struct clk_init_data){
4125		.name = "spicc0_sclk",
4126		.ops = &clk_regmap_gate_ops,
4127		.parent_hws = (const struct clk_hw *[]) {
4128			&g12a_spicc0_sclk_div.hw
4129		},
4130		.num_parents = 1,
4131		.flags = CLK_SET_RATE_PARENT,
4132	},
4133};
4134
4135static struct clk_regmap g12a_spicc1_sclk_sel = {
4136	.data = &(struct clk_regmap_mux_data){
4137		.offset = HHI_SPICC_CLK_CNTL,
4138		.mask = 7,
4139		.shift = 23,
4140	},
4141	.hw.init = &(struct clk_init_data){
4142		.name = "spicc1_sclk_sel",
4143		.ops = &clk_regmap_mux_ops,
4144		.parent_data = spicc_sclk_parent_data,
4145		.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
4146	},
4147};
4148
4149static struct clk_regmap g12a_spicc1_sclk_div = {
4150	.data = &(struct clk_regmap_div_data){
4151		.offset = HHI_SPICC_CLK_CNTL,
4152		.shift = 16,
4153		.width = 6,
4154	},
4155	.hw.init = &(struct clk_init_data){
4156		.name = "spicc1_sclk_div",
4157		.ops = &clk_regmap_divider_ops,
4158		.parent_hws = (const struct clk_hw *[]) {
4159			&g12a_spicc1_sclk_sel.hw
4160		},
4161		.num_parents = 1,
4162		.flags = CLK_SET_RATE_PARENT,
4163	},
4164};
4165
4166static struct clk_regmap g12a_spicc1_sclk = {
4167	.data = &(struct clk_regmap_gate_data){
4168		.offset = HHI_SPICC_CLK_CNTL,
4169		.bit_idx = 22,
4170	},
4171	.hw.init = &(struct clk_init_data){
4172		.name = "spicc1_sclk",
4173		.ops = &clk_regmap_gate_ops,
4174		.parent_hws = (const struct clk_hw *[]) {
4175			&g12a_spicc1_sclk_div.hw
4176		},
4177		.num_parents = 1,
4178		.flags = CLK_SET_RATE_PARENT,
4179	},
4180};
4181
4182/* Neural Network Accelerator source clock */
4183
4184static const struct clk_parent_data nna_clk_parent_data[] = {
4185	{ .fw_name = "xtal", },
4186	{ .hw = &g12a_gp0_pll.hw, },
4187	{ .hw = &g12a_hifi_pll.hw, },
4188	{ .hw = &g12a_fclk_div2p5.hw, },
4189	{ .hw = &g12a_fclk_div3.hw, },
4190	{ .hw = &g12a_fclk_div4.hw, },
4191	{ .hw = &g12a_fclk_div5.hw, },
4192	{ .hw = &g12a_fclk_div7.hw },
4193};
4194
4195static struct clk_regmap sm1_nna_axi_clk_sel = {
4196	.data = &(struct clk_regmap_mux_data){
4197		.offset = HHI_NNA_CLK_CNTL,
4198		.mask = 7,
4199		.shift = 9,
4200	},
4201	.hw.init = &(struct clk_init_data){
4202		.name = "nna_axi_clk_sel",
4203		.ops = &clk_regmap_mux_ops,
4204		.parent_data = nna_clk_parent_data,
4205		.num_parents = ARRAY_SIZE(nna_clk_parent_data),
4206	},
4207};
4208
4209static struct clk_regmap sm1_nna_axi_clk_div = {
4210	.data = &(struct clk_regmap_div_data){
4211		.offset = HHI_NNA_CLK_CNTL,
4212		.shift = 0,
4213		.width = 7,
4214	},
4215	.hw.init = &(struct clk_init_data){
4216		.name = "nna_axi_clk_div",
4217		.ops = &clk_regmap_divider_ops,
4218		.parent_hws = (const struct clk_hw *[]) {
4219			&sm1_nna_axi_clk_sel.hw
4220		},
4221		.num_parents = 1,
4222		.flags = CLK_SET_RATE_PARENT,
4223	},
4224};
4225
4226static struct clk_regmap sm1_nna_axi_clk = {
4227	.data = &(struct clk_regmap_gate_data){
4228		.offset = HHI_NNA_CLK_CNTL,
4229		.bit_idx = 8,
4230	},
4231	.hw.init = &(struct clk_init_data){
4232		.name = "nna_axi_clk",
4233		.ops = &clk_regmap_gate_ops,
4234		.parent_hws = (const struct clk_hw *[]) {
4235			&sm1_nna_axi_clk_div.hw
4236		},
4237		.num_parents = 1,
4238		.flags = CLK_SET_RATE_PARENT,
4239	},
4240};
4241
4242static struct clk_regmap sm1_nna_core_clk_sel = {
4243	.data = &(struct clk_regmap_mux_data){
4244		.offset = HHI_NNA_CLK_CNTL,
4245		.mask = 7,
4246		.shift = 25,
4247	},
4248	.hw.init = &(struct clk_init_data){
4249		.name = "nna_core_clk_sel",
4250		.ops = &clk_regmap_mux_ops,
4251		.parent_data = nna_clk_parent_data,
4252		.num_parents = ARRAY_SIZE(nna_clk_parent_data),
4253	},
4254};
4255
4256static struct clk_regmap sm1_nna_core_clk_div = {
4257	.data = &(struct clk_regmap_div_data){
4258		.offset = HHI_NNA_CLK_CNTL,
4259		.shift = 16,
4260		.width = 7,
4261	},
4262	.hw.init = &(struct clk_init_data){
4263		.name = "nna_core_clk_div",
4264		.ops = &clk_regmap_divider_ops,
4265		.parent_hws = (const struct clk_hw *[]) {
4266			&sm1_nna_core_clk_sel.hw
4267		},
4268		.num_parents = 1,
4269		.flags = CLK_SET_RATE_PARENT,
4270	},
4271};
4272
4273static struct clk_regmap sm1_nna_core_clk = {
4274	.data = &(struct clk_regmap_gate_data){
4275		.offset = HHI_NNA_CLK_CNTL,
4276		.bit_idx = 24,
4277	},
4278	.hw.init = &(struct clk_init_data){
4279		.name = "nna_core_clk",
4280		.ops = &clk_regmap_gate_ops,
4281		.parent_hws = (const struct clk_hw *[]) {
4282			&sm1_nna_core_clk_div.hw
4283		},
4284		.num_parents = 1,
4285		.flags = CLK_SET_RATE_PARENT,
4286	},
4287};
4288
4289#define MESON_GATE(_name, _reg, _bit) \
4290	MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
4291
4292#define MESON_GATE_RO(_name, _reg, _bit) \
4293	MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
4294
4295/* Everything Else (EE) domain gates */
4296static MESON_GATE(g12a_ddr,			HHI_GCLK_MPEG0,	0);
4297static MESON_GATE(g12a_dos,			HHI_GCLK_MPEG0,	1);
4298static MESON_GATE(g12a_audio_locker,		HHI_GCLK_MPEG0,	2);
4299static MESON_GATE(g12a_mipi_dsi_host,		HHI_GCLK_MPEG0,	3);
4300static MESON_GATE(g12a_eth_phy,			HHI_GCLK_MPEG0,	4);
4301static MESON_GATE(g12a_isa,			HHI_GCLK_MPEG0,	5);
4302static MESON_GATE(g12a_pl301,			HHI_GCLK_MPEG0,	6);
4303static MESON_GATE(g12a_periphs,			HHI_GCLK_MPEG0,	7);
4304static MESON_GATE(g12a_spicc_0,			HHI_GCLK_MPEG0,	8);
4305static MESON_GATE(g12a_i2c,			HHI_GCLK_MPEG0,	9);
4306static MESON_GATE(g12a_sana,			HHI_GCLK_MPEG0,	10);
4307static MESON_GATE(g12a_sd,			HHI_GCLK_MPEG0,	11);
4308static MESON_GATE(g12a_rng0,			HHI_GCLK_MPEG0,	12);
4309static MESON_GATE(g12a_uart0,			HHI_GCLK_MPEG0,	13);
4310static MESON_GATE(g12a_spicc_1,			HHI_GCLK_MPEG0,	14);
4311static MESON_GATE(g12a_hiu_reg,			HHI_GCLK_MPEG0,	19);
4312static MESON_GATE(g12a_mipi_dsi_phy,		HHI_GCLK_MPEG0,	20);
4313static MESON_GATE(g12a_assist_misc,		HHI_GCLK_MPEG0,	23);
4314static MESON_GATE(g12a_emmc_a,			HHI_GCLK_MPEG0,	4);
4315static MESON_GATE(g12a_emmc_b,			HHI_GCLK_MPEG0,	25);
4316static MESON_GATE(g12a_emmc_c,			HHI_GCLK_MPEG0,	26);
4317static MESON_GATE(g12a_audio_codec,		HHI_GCLK_MPEG0,	28);
4318
4319static MESON_GATE(g12a_audio,			HHI_GCLK_MPEG1,	0);
4320static MESON_GATE(g12a_eth_core,		HHI_GCLK_MPEG1,	3);
4321static MESON_GATE(g12a_demux,			HHI_GCLK_MPEG1,	4);
4322static MESON_GATE(g12a_audio_ififo,		HHI_GCLK_MPEG1,	11);
4323static MESON_GATE(g12a_adc,			HHI_GCLK_MPEG1,	13);
4324static MESON_GATE(g12a_uart1,			HHI_GCLK_MPEG1,	16);
4325static MESON_GATE(g12a_g2d,			HHI_GCLK_MPEG1,	20);
4326static MESON_GATE(g12a_reset,			HHI_GCLK_MPEG1,	23);
4327static MESON_GATE(g12a_pcie_comb,		HHI_GCLK_MPEG1,	24);
4328static MESON_GATE(g12a_parser,			HHI_GCLK_MPEG1,	25);
4329static MESON_GATE(g12a_usb_general,		HHI_GCLK_MPEG1,	26);
4330static MESON_GATE(g12a_pcie_phy,		HHI_GCLK_MPEG1,	27);
4331static MESON_GATE(g12a_ahb_arb0,		HHI_GCLK_MPEG1,	29);
4332
4333static MESON_GATE(g12a_ahb_data_bus,		HHI_GCLK_MPEG2,	1);
4334static MESON_GATE(g12a_ahb_ctrl_bus,		HHI_GCLK_MPEG2,	2);
4335static MESON_GATE(g12a_htx_hdcp22,		HHI_GCLK_MPEG2,	3);
4336static MESON_GATE(g12a_htx_pclk,		HHI_GCLK_MPEG2,	4);
4337static MESON_GATE(g12a_bt656,			HHI_GCLK_MPEG2,	6);
4338static MESON_GATE(g12a_usb1_to_ddr,		HHI_GCLK_MPEG2,	8);
4339static MESON_GATE(g12b_mipi_isp_gate,		HHI_GCLK_MPEG2,	17);
4340static MESON_GATE(g12a_mmc_pclk,		HHI_GCLK_MPEG2,	11);
4341static MESON_GATE(g12a_uart2,			HHI_GCLK_MPEG2,	15);
4342static MESON_GATE(g12a_vpu_intr,		HHI_GCLK_MPEG2,	25);
4343static MESON_GATE(g12b_csi_phy1,		HHI_GCLK_MPEG2,	28);
4344static MESON_GATE(g12b_csi_phy0,		HHI_GCLK_MPEG2,	29);
4345static MESON_GATE(g12a_gic,			HHI_GCLK_MPEG2,	30);
4346
4347static MESON_GATE(g12a_vclk2_venci0,		HHI_GCLK_OTHER,	1);
4348static MESON_GATE(g12a_vclk2_venci1,		HHI_GCLK_OTHER,	2);
4349static MESON_GATE(g12a_vclk2_vencp0,		HHI_GCLK_OTHER,	3);
4350static MESON_GATE(g12a_vclk2_vencp1,		HHI_GCLK_OTHER,	4);
4351static MESON_GATE(g12a_vclk2_venct0,		HHI_GCLK_OTHER,	5);
4352static MESON_GATE(g12a_vclk2_venct1,		HHI_GCLK_OTHER,	6);
4353static MESON_GATE(g12a_vclk2_other,		HHI_GCLK_OTHER,	7);
4354static MESON_GATE(g12a_vclk2_enci,		HHI_GCLK_OTHER,	8);
4355static MESON_GATE(g12a_vclk2_encp,		HHI_GCLK_OTHER,	9);
4356static MESON_GATE(g12a_dac_clk,			HHI_GCLK_OTHER,	10);
4357static MESON_GATE(g12a_aoclk_gate,		HHI_GCLK_OTHER,	14);
4358static MESON_GATE(g12a_iec958_gate,		HHI_GCLK_OTHER,	16);
4359static MESON_GATE(g12a_enc480p,			HHI_GCLK_OTHER,	20);
4360static MESON_GATE(g12a_rng1,			HHI_GCLK_OTHER,	21);
4361static MESON_GATE(g12a_vclk2_enct,		HHI_GCLK_OTHER,	22);
4362static MESON_GATE(g12a_vclk2_encl,		HHI_GCLK_OTHER,	23);
4363static MESON_GATE(g12a_vclk2_venclmmc,		HHI_GCLK_OTHER,	24);
4364static MESON_GATE(g12a_vclk2_vencl,		HHI_GCLK_OTHER,	25);
4365static MESON_GATE(g12a_vclk2_other1,		HHI_GCLK_OTHER,	26);
4366
4367static MESON_GATE_RO(g12a_dma,			HHI_GCLK_OTHER2, 0);
4368static MESON_GATE_RO(g12a_efuse,		HHI_GCLK_OTHER2, 1);
4369static MESON_GATE_RO(g12a_rom_boot,		HHI_GCLK_OTHER2, 2);
4370static MESON_GATE_RO(g12a_reset_sec,		HHI_GCLK_OTHER2, 3);
4371static MESON_GATE_RO(g12a_sec_ahb_apb3,		HHI_GCLK_OTHER2, 4);
4372
4373/* Array of all clocks provided by this provider */
4374static struct clk_hw *g12a_hw_clks[] = {
4375	[CLKID_SYS_PLL]			= &g12a_sys_pll.hw,
4376	[CLKID_FIXED_PLL]		= &g12a_fixed_pll.hw,
4377	[CLKID_FCLK_DIV2]		= &g12a_fclk_div2.hw,
4378	[CLKID_FCLK_DIV3]		= &g12a_fclk_div3.hw,
4379	[CLKID_FCLK_DIV4]		= &g12a_fclk_div4.hw,
4380	[CLKID_FCLK_DIV5]		= &g12a_fclk_div5.hw,
4381	[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
4382	[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
4383	[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
4384	[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
4385	[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
4386	[CLKID_CLK81]			= &g12a_clk81.hw,
4387	[CLKID_MPLL0]			= &g12a_mpll0.hw,
4388	[CLKID_MPLL1]			= &g12a_mpll1.hw,
4389	[CLKID_MPLL2]			= &g12a_mpll2.hw,
4390	[CLKID_MPLL3]			= &g12a_mpll3.hw,
4391	[CLKID_DDR]			= &g12a_ddr.hw,
4392	[CLKID_DOS]			= &g12a_dos.hw,
4393	[CLKID_AUDIO_LOCKER]		= &g12a_audio_locker.hw,
4394	[CLKID_MIPI_DSI_HOST]		= &g12a_mipi_dsi_host.hw,
4395	[CLKID_ETH_PHY]			= &g12a_eth_phy.hw,
4396	[CLKID_ISA]			= &g12a_isa.hw,
4397	[CLKID_PL301]			= &g12a_pl301.hw,
4398	[CLKID_PERIPHS]			= &g12a_periphs.hw,
4399	[CLKID_SPICC0]			= &g12a_spicc_0.hw,
4400	[CLKID_I2C]			= &g12a_i2c.hw,
4401	[CLKID_SANA]			= &g12a_sana.hw,
4402	[CLKID_SD]			= &g12a_sd.hw,
4403	[CLKID_RNG0]			= &g12a_rng0.hw,
4404	[CLKID_UART0]			= &g12a_uart0.hw,
4405	[CLKID_SPICC1]			= &g12a_spicc_1.hw,
4406	[CLKID_HIU_IFACE]		= &g12a_hiu_reg.hw,
4407	[CLKID_MIPI_DSI_PHY]		= &g12a_mipi_dsi_phy.hw,
4408	[CLKID_ASSIST_MISC]		= &g12a_assist_misc.hw,
4409	[CLKID_SD_EMMC_A]		= &g12a_emmc_a.hw,
4410	[CLKID_SD_EMMC_B]		= &g12a_emmc_b.hw,
4411	[CLKID_SD_EMMC_C]		= &g12a_emmc_c.hw,
4412	[CLKID_AUDIO_CODEC]		= &g12a_audio_codec.hw,
4413	[CLKID_AUDIO]			= &g12a_audio.hw,
4414	[CLKID_ETH]			= &g12a_eth_core.hw,
4415	[CLKID_DEMUX]			= &g12a_demux.hw,
4416	[CLKID_AUDIO_IFIFO]		= &g12a_audio_ififo.hw,
4417	[CLKID_ADC]			= &g12a_adc.hw,
4418	[CLKID_UART1]			= &g12a_uart1.hw,
4419	[CLKID_G2D]			= &g12a_g2d.hw,
4420	[CLKID_RESET]			= &g12a_reset.hw,
4421	[CLKID_PCIE_COMB]		= &g12a_pcie_comb.hw,
4422	[CLKID_PARSER]			= &g12a_parser.hw,
4423	[CLKID_USB]			= &g12a_usb_general.hw,
4424	[CLKID_PCIE_PHY]		= &g12a_pcie_phy.hw,
4425	[CLKID_AHB_ARB0]		= &g12a_ahb_arb0.hw,
4426	[CLKID_AHB_DATA_BUS]		= &g12a_ahb_data_bus.hw,
4427	[CLKID_AHB_CTRL_BUS]		= &g12a_ahb_ctrl_bus.hw,
4428	[CLKID_HTX_HDCP22]		= &g12a_htx_hdcp22.hw,
4429	[CLKID_HTX_PCLK]		= &g12a_htx_pclk.hw,
4430	[CLKID_BT656]			= &g12a_bt656.hw,
4431	[CLKID_USB1_DDR_BRIDGE]		= &g12a_usb1_to_ddr.hw,
4432	[CLKID_MMC_PCLK]		= &g12a_mmc_pclk.hw,
4433	[CLKID_UART2]			= &g12a_uart2.hw,
4434	[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
4435	[CLKID_GIC]			= &g12a_gic.hw,
4436	[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
4437	[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
4438	[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
4439	[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
4440	[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
4441	[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
4442	[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
4443	[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
4444	[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
4445	[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
4446	[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
4447	[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
4448	[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
4449	[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
4450	[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
4451	[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
4452	[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
4453	[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
4454	[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
4455	[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
4456	[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
4457	[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
4458	[CLKID_VCLK2_VENCP0]		= &g12a_vclk2_vencp0.hw,
4459	[CLKID_VCLK2_VENCP1]		= &g12a_vclk2_vencp1.hw,
4460	[CLKID_VCLK2_VENCT0]		= &g12a_vclk2_venct0.hw,
4461	[CLKID_VCLK2_VENCT1]		= &g12a_vclk2_venct1.hw,
4462	[CLKID_VCLK2_OTHER]		= &g12a_vclk2_other.hw,
4463	[CLKID_VCLK2_ENCI]		= &g12a_vclk2_enci.hw,
4464	[CLKID_VCLK2_ENCP]		= &g12a_vclk2_encp.hw,
4465	[CLKID_DAC_CLK]			= &g12a_dac_clk.hw,
4466	[CLKID_AOCLK]			= &g12a_aoclk_gate.hw,
4467	[CLKID_IEC958]			= &g12a_iec958_gate.hw,
4468	[CLKID_ENC480P]			= &g12a_enc480p.hw,
4469	[CLKID_RNG1]			= &g12a_rng1.hw,
4470	[CLKID_VCLK2_ENCT]		= &g12a_vclk2_enct.hw,
4471	[CLKID_VCLK2_ENCL]		= &g12a_vclk2_encl.hw,
4472	[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
4473	[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
4474	[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
4475	[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
4476	[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
4477	[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
4478	[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
4479	[CLKID_DMA]			= &g12a_dma.hw,
4480	[CLKID_EFUSE]			= &g12a_efuse.hw,
4481	[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
4482	[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
4483	[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
4484	[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
4485	[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
4486	[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
4487	[CLKID_VPU_0]			= &g12a_vpu_0.hw,
4488	[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
4489	[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
4490	[CLKID_VPU_1]			= &g12a_vpu_1.hw,
4491	[CLKID_VPU]			= &g12a_vpu.hw,
4492	[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
4493	[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
4494	[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
4495	[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
4496	[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
4497	[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
4498	[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
4499	[CLKID_VAPB]			= &g12a_vapb.hw,
4500	[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
4501	[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
4502	[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
4503	[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
4504	[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
4505	[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
4506	[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
4507	[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
4508	[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
4509	[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
4510	[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
4511	[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
4512	[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
4513	[CLKID_VCLK]			= &g12a_vclk.hw,
4514	[CLKID_VCLK2]			= &g12a_vclk2.hw,
4515	[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
4516	[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
4517	[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
4518	[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
4519	[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
4520	[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
4521	[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
4522	[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
4523	[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
4524	[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
4525	[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
4526	[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
4527	[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
4528	[CLKID_VCLK_DIV12]		= &g12a_vclk_div12.hw,
4529	[CLKID_VCLK2_DIV2]		= &g12a_vclk2_div2.hw,
4530	[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
4531	[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
4532	[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
4533	[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
4534	[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
4535	[CLKID_CTS_ENCL_SEL]		= &g12a_cts_encl_sel.hw,
4536	[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
4537	[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
4538	[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
4539	[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
4540	[CLKID_CTS_ENCL]		= &g12a_cts_encl.hw,
4541	[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
4542	[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
4543	[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
4544	[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
4545	[CLKID_HDMI]			= &g12a_hdmi.hw,
4546	[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
4547	[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
4548	[CLKID_MALI_0]			= &g12a_mali_0.hw,
4549	[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
4550	[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
4551	[CLKID_MALI_1]			= &g12a_mali_1.hw,
4552	[CLKID_MALI]			= &g12a_mali.hw,
4553	[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
4554	[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
4555	[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
4556	[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
4557	[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
4558	[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
4559	[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
4560	[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
4561	[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
4562	[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
4563	[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
4564	[CLKID_CPU_CLK]			= &g12a_cpu_clk.hw,
4565	[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
4566	[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
4567	[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
4568	[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
4569	[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
4570	[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
4571	[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
4572	[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
4573	[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
4574	[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
4575	[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
4576	[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
4577	[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
4578	[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
4579	[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
4580	[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
4581	[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
4582	[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
4583	[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
4584	[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
4585	[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
4586	[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
4587	[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
4588	[CLKID_TS_DIV]			= &g12a_ts_div.hw,
4589	[CLKID_TS]			= &g12a_ts.hw,
4590	[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
4591	[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
4592	[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
4593	[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
4594	[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
4595	[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
4596	[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
4597	[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
4598	[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
4599};
4600
4601static struct clk_hw *g12b_hw_clks[] = {
4602	[CLKID_SYS_PLL]			= &g12a_sys_pll.hw,
4603	[CLKID_FIXED_PLL]		= &g12a_fixed_pll.hw,
4604	[CLKID_FCLK_DIV2]		= &g12a_fclk_div2.hw,
4605	[CLKID_FCLK_DIV3]		= &g12a_fclk_div3.hw,
4606	[CLKID_FCLK_DIV4]		= &g12a_fclk_div4.hw,
4607	[CLKID_FCLK_DIV5]		= &g12a_fclk_div5.hw,
4608	[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
4609	[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
4610	[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
4611	[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
4612	[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
4613	[CLKID_CLK81]			= &g12a_clk81.hw,
4614	[CLKID_MPLL0]			= &g12a_mpll0.hw,
4615	[CLKID_MPLL1]			= &g12a_mpll1.hw,
4616	[CLKID_MPLL2]			= &g12a_mpll2.hw,
4617	[CLKID_MPLL3]			= &g12a_mpll3.hw,
4618	[CLKID_DDR]			= &g12a_ddr.hw,
4619	[CLKID_DOS]			= &g12a_dos.hw,
4620	[CLKID_AUDIO_LOCKER]		= &g12a_audio_locker.hw,
4621	[CLKID_MIPI_DSI_HOST]		= &g12a_mipi_dsi_host.hw,
4622	[CLKID_ETH_PHY]			= &g12a_eth_phy.hw,
4623	[CLKID_ISA]			= &g12a_isa.hw,
4624	[CLKID_PL301]			= &g12a_pl301.hw,
4625	[CLKID_PERIPHS]			= &g12a_periphs.hw,
4626	[CLKID_SPICC0]			= &g12a_spicc_0.hw,
4627	[CLKID_I2C]			= &g12a_i2c.hw,
4628	[CLKID_SANA]			= &g12a_sana.hw,
4629	[CLKID_SD]			= &g12a_sd.hw,
4630	[CLKID_RNG0]			= &g12a_rng0.hw,
4631	[CLKID_UART0]			= &g12a_uart0.hw,
4632	[CLKID_SPICC1]			= &g12a_spicc_1.hw,
4633	[CLKID_HIU_IFACE]		= &g12a_hiu_reg.hw,
4634	[CLKID_MIPI_DSI_PHY]		= &g12a_mipi_dsi_phy.hw,
4635	[CLKID_ASSIST_MISC]		= &g12a_assist_misc.hw,
4636	[CLKID_SD_EMMC_A]		= &g12a_emmc_a.hw,
4637	[CLKID_SD_EMMC_B]		= &g12a_emmc_b.hw,
4638	[CLKID_SD_EMMC_C]		= &g12a_emmc_c.hw,
4639	[CLKID_AUDIO_CODEC]		= &g12a_audio_codec.hw,
4640	[CLKID_AUDIO]			= &g12a_audio.hw,
4641	[CLKID_ETH]			= &g12a_eth_core.hw,
4642	[CLKID_DEMUX]			= &g12a_demux.hw,
4643	[CLKID_AUDIO_IFIFO]		= &g12a_audio_ififo.hw,
4644	[CLKID_ADC]			= &g12a_adc.hw,
4645	[CLKID_UART1]			= &g12a_uart1.hw,
4646	[CLKID_G2D]			= &g12a_g2d.hw,
4647	[CLKID_RESET]			= &g12a_reset.hw,
4648	[CLKID_PCIE_COMB]		= &g12a_pcie_comb.hw,
4649	[CLKID_PARSER]			= &g12a_parser.hw,
4650	[CLKID_USB]			= &g12a_usb_general.hw,
4651	[CLKID_PCIE_PHY]		= &g12a_pcie_phy.hw,
4652	[CLKID_AHB_ARB0]		= &g12a_ahb_arb0.hw,
4653	[CLKID_AHB_DATA_BUS]		= &g12a_ahb_data_bus.hw,
4654	[CLKID_AHB_CTRL_BUS]		= &g12a_ahb_ctrl_bus.hw,
4655	[CLKID_HTX_HDCP22]		= &g12a_htx_hdcp22.hw,
4656	[CLKID_HTX_PCLK]		= &g12a_htx_pclk.hw,
4657	[CLKID_BT656]			= &g12a_bt656.hw,
4658	[CLKID_USB1_DDR_BRIDGE]		= &g12a_usb1_to_ddr.hw,
4659	[CLKID_MMC_PCLK]		= &g12a_mmc_pclk.hw,
4660	[CLKID_UART2]			= &g12a_uart2.hw,
4661	[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
4662	[CLKID_GIC]			= &g12a_gic.hw,
4663	[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
4664	[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
4665	[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
4666	[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
4667	[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
4668	[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
4669	[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
4670	[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
4671	[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
4672	[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
4673	[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
4674	[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
4675	[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
4676	[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
4677	[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
4678	[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
4679	[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
4680	[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
4681	[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
4682	[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
4683	[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
4684	[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
4685	[CLKID_VCLK2_VENCP0]		= &g12a_vclk2_vencp0.hw,
4686	[CLKID_VCLK2_VENCP1]		= &g12a_vclk2_vencp1.hw,
4687	[CLKID_VCLK2_VENCT0]		= &g12a_vclk2_venct0.hw,
4688	[CLKID_VCLK2_VENCT1]		= &g12a_vclk2_venct1.hw,
4689	[CLKID_VCLK2_OTHER]		= &g12a_vclk2_other.hw,
4690	[CLKID_VCLK2_ENCI]		= &g12a_vclk2_enci.hw,
4691	[CLKID_VCLK2_ENCP]		= &g12a_vclk2_encp.hw,
4692	[CLKID_DAC_CLK]			= &g12a_dac_clk.hw,
4693	[CLKID_AOCLK]			= &g12a_aoclk_gate.hw,
4694	[CLKID_IEC958]			= &g12a_iec958_gate.hw,
4695	[CLKID_ENC480P]			= &g12a_enc480p.hw,
4696	[CLKID_RNG1]			= &g12a_rng1.hw,
4697	[CLKID_VCLK2_ENCT]		= &g12a_vclk2_enct.hw,
4698	[CLKID_VCLK2_ENCL]		= &g12a_vclk2_encl.hw,
4699	[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
4700	[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
4701	[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
4702	[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
4703	[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
4704	[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
4705	[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
4706	[CLKID_DMA]			= &g12a_dma.hw,
4707	[CLKID_EFUSE]			= &g12a_efuse.hw,
4708	[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
4709	[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
4710	[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
4711	[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
4712	[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
4713	[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
4714	[CLKID_VPU_0]			= &g12a_vpu_0.hw,
4715	[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
4716	[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
4717	[CLKID_VPU_1]			= &g12a_vpu_1.hw,
4718	[CLKID_VPU]			= &g12a_vpu.hw,
4719	[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
4720	[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
4721	[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
4722	[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
4723	[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
4724	[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
4725	[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
4726	[CLKID_VAPB]			= &g12a_vapb.hw,
4727	[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
4728	[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
4729	[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
4730	[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
4731	[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
4732	[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
4733	[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
4734	[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
4735	[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
4736	[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
4737	[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
4738	[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
4739	[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
4740	[CLKID_VCLK]			= &g12a_vclk.hw,
4741	[CLKID_VCLK2]			= &g12a_vclk2.hw,
4742	[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
4743	[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
4744	[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
4745	[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
4746	[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
4747	[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
4748	[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
4749	[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
4750	[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
4751	[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
4752	[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
4753	[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
4754	[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
4755	[CLKID_VCLK_DIV12]		= &g12a_vclk_div12.hw,
4756	[CLKID_VCLK2_DIV2]		= &g12a_vclk2_div2.hw,
4757	[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
4758	[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
4759	[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
4760	[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
4761	[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
4762	[CLKID_CTS_ENCL_SEL]		= &g12a_cts_encl_sel.hw,
4763	[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
4764	[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
4765	[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
4766	[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
4767	[CLKID_CTS_ENCL]		= &g12a_cts_encl.hw,
4768	[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
4769	[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
4770	[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
4771	[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
4772	[CLKID_HDMI]			= &g12a_hdmi.hw,
4773	[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
4774	[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
4775	[CLKID_MALI_0]			= &g12a_mali_0.hw,
4776	[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
4777	[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
4778	[CLKID_MALI_1]			= &g12a_mali_1.hw,
4779	[CLKID_MALI]			= &g12a_mali.hw,
4780	[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
4781	[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
4782	[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
4783	[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
4784	[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
4785	[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
4786	[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
4787	[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
4788	[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
4789	[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
4790	[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
4791	[CLKID_CPU_CLK]			= &g12b_cpu_clk.hw,
4792	[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
4793	[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
4794	[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
4795	[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
4796	[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
4797	[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
4798	[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
4799	[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
4800	[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
4801	[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
4802	[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
4803	[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
4804	[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
4805	[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
4806	[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
4807	[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
4808	[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
4809	[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
4810	[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
4811	[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
4812	[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
4813	[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
4814	[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
4815	[CLKID_TS_DIV]			= &g12a_ts_div.hw,
4816	[CLKID_TS]			= &g12a_ts.hw,
4817	[CLKID_SYS1_PLL_DCO]		= &g12b_sys1_pll_dco.hw,
4818	[CLKID_SYS1_PLL]		= &g12b_sys1_pll.hw,
4819	[CLKID_SYS1_PLL_DIV16_EN]	= &g12b_sys1_pll_div16_en.hw,
4820	[CLKID_SYS1_PLL_DIV16]		= &g12b_sys1_pll_div16.hw,
4821	[CLKID_CPUB_CLK_DYN0_SEL]	= &g12b_cpub_clk_premux0.hw,
4822	[CLKID_CPUB_CLK_DYN0_DIV]	= &g12b_cpub_clk_mux0_div.hw,
4823	[CLKID_CPUB_CLK_DYN0]		= &g12b_cpub_clk_postmux0.hw,
4824	[CLKID_CPUB_CLK_DYN1_SEL]	= &g12b_cpub_clk_premux1.hw,
4825	[CLKID_CPUB_CLK_DYN1_DIV]	= &g12b_cpub_clk_mux1_div.hw,
4826	[CLKID_CPUB_CLK_DYN1]		= &g12b_cpub_clk_postmux1.hw,
4827	[CLKID_CPUB_CLK_DYN]		= &g12b_cpub_clk_dyn.hw,
4828	[CLKID_CPUB_CLK]		= &g12b_cpub_clk.hw,
4829	[CLKID_CPUB_CLK_DIV16_EN]	= &g12b_cpub_clk_div16_en.hw,
4830	[CLKID_CPUB_CLK_DIV16]		= &g12b_cpub_clk_div16.hw,
4831	[CLKID_CPUB_CLK_DIV2]		= &g12b_cpub_clk_div2.hw,
4832	[CLKID_CPUB_CLK_DIV3]		= &g12b_cpub_clk_div3.hw,
4833	[CLKID_CPUB_CLK_DIV4]		= &g12b_cpub_clk_div4.hw,
4834	[CLKID_CPUB_CLK_DIV5]		= &g12b_cpub_clk_div5.hw,
4835	[CLKID_CPUB_CLK_DIV6]		= &g12b_cpub_clk_div6.hw,
4836	[CLKID_CPUB_CLK_DIV7]		= &g12b_cpub_clk_div7.hw,
4837	[CLKID_CPUB_CLK_DIV8]		= &g12b_cpub_clk_div8.hw,
4838	[CLKID_CPUB_CLK_APB_SEL]	= &g12b_cpub_clk_apb_sel.hw,
4839	[CLKID_CPUB_CLK_APB]		= &g12b_cpub_clk_apb.hw,
4840	[CLKID_CPUB_CLK_ATB_SEL]	= &g12b_cpub_clk_atb_sel.hw,
4841	[CLKID_CPUB_CLK_ATB]		= &g12b_cpub_clk_atb.hw,
4842	[CLKID_CPUB_CLK_AXI_SEL]	= &g12b_cpub_clk_axi_sel.hw,
4843	[CLKID_CPUB_CLK_AXI]		= &g12b_cpub_clk_axi.hw,
4844	[CLKID_CPUB_CLK_TRACE_SEL]	= &g12b_cpub_clk_trace_sel.hw,
4845	[CLKID_CPUB_CLK_TRACE]		= &g12b_cpub_clk_trace.hw,
4846	[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
4847	[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
4848	[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
4849	[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
4850	[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
4851	[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
4852	[CLKID_NNA_AXI_CLK_SEL]		= &sm1_nna_axi_clk_sel.hw,
4853	[CLKID_NNA_AXI_CLK_DIV]		= &sm1_nna_axi_clk_div.hw,
4854	[CLKID_NNA_AXI_CLK]		= &sm1_nna_axi_clk.hw,
4855	[CLKID_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
4856	[CLKID_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
4857	[CLKID_NNA_CORE_CLK]		= &sm1_nna_core_clk.hw,
4858	[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
4859	[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
4860	[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
4861	[CLKID_MIPI_ISP_SEL]		= &g12b_mipi_isp_sel.hw,
4862	[CLKID_MIPI_ISP_DIV]		= &g12b_mipi_isp_div.hw,
4863	[CLKID_MIPI_ISP]		= &g12b_mipi_isp.hw,
4864	[CLKID_MIPI_ISP_GATE]		= &g12b_mipi_isp_gate.hw,
4865	[CLKID_MIPI_ISP_CSI_PHY0]	= &g12b_csi_phy0.hw,
4866	[CLKID_MIPI_ISP_CSI_PHY1]	= &g12b_csi_phy1.hw,
4867};
4868
4869static struct clk_hw *sm1_hw_clks[] = {
4870	[CLKID_SYS_PLL]			= &g12a_sys_pll.hw,
4871	[CLKID_FIXED_PLL]		= &g12a_fixed_pll.hw,
4872	[CLKID_FCLK_DIV2]		= &g12a_fclk_div2.hw,
4873	[CLKID_FCLK_DIV3]		= &g12a_fclk_div3.hw,
4874	[CLKID_FCLK_DIV4]		= &g12a_fclk_div4.hw,
4875	[CLKID_FCLK_DIV5]		= &g12a_fclk_div5.hw,
4876	[CLKID_FCLK_DIV7]		= &g12a_fclk_div7.hw,
4877	[CLKID_FCLK_DIV2P5]		= &g12a_fclk_div2p5.hw,
4878	[CLKID_GP0_PLL]			= &g12a_gp0_pll.hw,
4879	[CLKID_MPEG_SEL]		= &g12a_mpeg_clk_sel.hw,
4880	[CLKID_MPEG_DIV]		= &g12a_mpeg_clk_div.hw,
4881	[CLKID_CLK81]			= &g12a_clk81.hw,
4882	[CLKID_MPLL0]			= &g12a_mpll0.hw,
4883	[CLKID_MPLL1]			= &g12a_mpll1.hw,
4884	[CLKID_MPLL2]			= &g12a_mpll2.hw,
4885	[CLKID_MPLL3]			= &g12a_mpll3.hw,
4886	[CLKID_DDR]			= &g12a_ddr.hw,
4887	[CLKID_DOS]			= &g12a_dos.hw,
4888	[CLKID_AUDIO_LOCKER]		= &g12a_audio_locker.hw,
4889	[CLKID_MIPI_DSI_HOST]		= &g12a_mipi_dsi_host.hw,
4890	[CLKID_ETH_PHY]			= &g12a_eth_phy.hw,
4891	[CLKID_ISA]			= &g12a_isa.hw,
4892	[CLKID_PL301]			= &g12a_pl301.hw,
4893	[CLKID_PERIPHS]			= &g12a_periphs.hw,
4894	[CLKID_SPICC0]			= &g12a_spicc_0.hw,
4895	[CLKID_I2C]			= &g12a_i2c.hw,
4896	[CLKID_SANA]			= &g12a_sana.hw,
4897	[CLKID_SD]			= &g12a_sd.hw,
4898	[CLKID_RNG0]			= &g12a_rng0.hw,
4899	[CLKID_UART0]			= &g12a_uart0.hw,
4900	[CLKID_SPICC1]			= &g12a_spicc_1.hw,
4901	[CLKID_HIU_IFACE]		= &g12a_hiu_reg.hw,
4902	[CLKID_MIPI_DSI_PHY]		= &g12a_mipi_dsi_phy.hw,
4903	[CLKID_ASSIST_MISC]		= &g12a_assist_misc.hw,
4904	[CLKID_SD_EMMC_A]		= &g12a_emmc_a.hw,
4905	[CLKID_SD_EMMC_B]		= &g12a_emmc_b.hw,
4906	[CLKID_SD_EMMC_C]		= &g12a_emmc_c.hw,
4907	[CLKID_AUDIO_CODEC]		= &g12a_audio_codec.hw,
4908	[CLKID_AUDIO]			= &g12a_audio.hw,
4909	[CLKID_ETH]			= &g12a_eth_core.hw,
4910	[CLKID_DEMUX]			= &g12a_demux.hw,
4911	[CLKID_AUDIO_IFIFO]		= &g12a_audio_ififo.hw,
4912	[CLKID_ADC]			= &g12a_adc.hw,
4913	[CLKID_UART1]			= &g12a_uart1.hw,
4914	[CLKID_G2D]			= &g12a_g2d.hw,
4915	[CLKID_RESET]			= &g12a_reset.hw,
4916	[CLKID_PCIE_COMB]		= &g12a_pcie_comb.hw,
4917	[CLKID_PARSER]			= &g12a_parser.hw,
4918	[CLKID_USB]			= &g12a_usb_general.hw,
4919	[CLKID_PCIE_PHY]		= &g12a_pcie_phy.hw,
4920	[CLKID_AHB_ARB0]		= &g12a_ahb_arb0.hw,
4921	[CLKID_AHB_DATA_BUS]		= &g12a_ahb_data_bus.hw,
4922	[CLKID_AHB_CTRL_BUS]		= &g12a_ahb_ctrl_bus.hw,
4923	[CLKID_HTX_HDCP22]		= &g12a_htx_hdcp22.hw,
4924	[CLKID_HTX_PCLK]		= &g12a_htx_pclk.hw,
4925	[CLKID_BT656]			= &g12a_bt656.hw,
4926	[CLKID_USB1_DDR_BRIDGE]		= &g12a_usb1_to_ddr.hw,
4927	[CLKID_MMC_PCLK]		= &g12a_mmc_pclk.hw,
4928	[CLKID_UART2]			= &g12a_uart2.hw,
4929	[CLKID_VPU_INTR]		= &g12a_vpu_intr.hw,
4930	[CLKID_GIC]			= &g12a_gic.hw,
4931	[CLKID_SD_EMMC_A_CLK0_SEL]	= &g12a_sd_emmc_a_clk0_sel.hw,
4932	[CLKID_SD_EMMC_A_CLK0_DIV]	= &g12a_sd_emmc_a_clk0_div.hw,
4933	[CLKID_SD_EMMC_A_CLK0]		= &g12a_sd_emmc_a_clk0.hw,
4934	[CLKID_SD_EMMC_B_CLK0_SEL]	= &g12a_sd_emmc_b_clk0_sel.hw,
4935	[CLKID_SD_EMMC_B_CLK0_DIV]	= &g12a_sd_emmc_b_clk0_div.hw,
4936	[CLKID_SD_EMMC_B_CLK0]		= &g12a_sd_emmc_b_clk0.hw,
4937	[CLKID_SD_EMMC_C_CLK0_SEL]	= &g12a_sd_emmc_c_clk0_sel.hw,
4938	[CLKID_SD_EMMC_C_CLK0_DIV]	= &g12a_sd_emmc_c_clk0_div.hw,
4939	[CLKID_SD_EMMC_C_CLK0]		= &g12a_sd_emmc_c_clk0.hw,
4940	[CLKID_MPLL0_DIV]		= &g12a_mpll0_div.hw,
4941	[CLKID_MPLL1_DIV]		= &g12a_mpll1_div.hw,
4942	[CLKID_MPLL2_DIV]		= &g12a_mpll2_div.hw,
4943	[CLKID_MPLL3_DIV]		= &g12a_mpll3_div.hw,
4944	[CLKID_FCLK_DIV2_DIV]		= &g12a_fclk_div2_div.hw,
4945	[CLKID_FCLK_DIV3_DIV]		= &g12a_fclk_div3_div.hw,
4946	[CLKID_FCLK_DIV4_DIV]		= &g12a_fclk_div4_div.hw,
4947	[CLKID_FCLK_DIV5_DIV]		= &g12a_fclk_div5_div.hw,
4948	[CLKID_FCLK_DIV7_DIV]		= &g12a_fclk_div7_div.hw,
4949	[CLKID_FCLK_DIV2P5_DIV]		= &g12a_fclk_div2p5_div.hw,
4950	[CLKID_HIFI_PLL]		= &g12a_hifi_pll.hw,
4951	[CLKID_VCLK2_VENCI0]		= &g12a_vclk2_venci0.hw,
4952	[CLKID_VCLK2_VENCI1]		= &g12a_vclk2_venci1.hw,
4953	[CLKID_VCLK2_VENCP0]		= &g12a_vclk2_vencp0.hw,
4954	[CLKID_VCLK2_VENCP1]		= &g12a_vclk2_vencp1.hw,
4955	[CLKID_VCLK2_VENCT0]		= &g12a_vclk2_venct0.hw,
4956	[CLKID_VCLK2_VENCT1]		= &g12a_vclk2_venct1.hw,
4957	[CLKID_VCLK2_OTHER]		= &g12a_vclk2_other.hw,
4958	[CLKID_VCLK2_ENCI]		= &g12a_vclk2_enci.hw,
4959	[CLKID_VCLK2_ENCP]		= &g12a_vclk2_encp.hw,
4960	[CLKID_DAC_CLK]			= &g12a_dac_clk.hw,
4961	[CLKID_AOCLK]			= &g12a_aoclk_gate.hw,
4962	[CLKID_IEC958]			= &g12a_iec958_gate.hw,
4963	[CLKID_ENC480P]			= &g12a_enc480p.hw,
4964	[CLKID_RNG1]			= &g12a_rng1.hw,
4965	[CLKID_VCLK2_ENCT]		= &g12a_vclk2_enct.hw,
4966	[CLKID_VCLK2_ENCL]		= &g12a_vclk2_encl.hw,
4967	[CLKID_VCLK2_VENCLMMC]		= &g12a_vclk2_venclmmc.hw,
4968	[CLKID_VCLK2_VENCL]		= &g12a_vclk2_vencl.hw,
4969	[CLKID_VCLK2_OTHER1]		= &g12a_vclk2_other1.hw,
4970	[CLKID_FIXED_PLL_DCO]		= &g12a_fixed_pll_dco.hw,
4971	[CLKID_SYS_PLL_DCO]		= &g12a_sys_pll_dco.hw,
4972	[CLKID_GP0_PLL_DCO]		= &g12a_gp0_pll_dco.hw,
4973	[CLKID_HIFI_PLL_DCO]		= &g12a_hifi_pll_dco.hw,
4974	[CLKID_DMA]			= &g12a_dma.hw,
4975	[CLKID_EFUSE]			= &g12a_efuse.hw,
4976	[CLKID_ROM_BOOT]		= &g12a_rom_boot.hw,
4977	[CLKID_RESET_SEC]		= &g12a_reset_sec.hw,
4978	[CLKID_SEC_AHB_APB3]		= &g12a_sec_ahb_apb3.hw,
4979	[CLKID_MPLL_PREDIV]		= &g12a_mpll_prediv.hw,
4980	[CLKID_VPU_0_SEL]		= &g12a_vpu_0_sel.hw,
4981	[CLKID_VPU_0_DIV]		= &g12a_vpu_0_div.hw,
4982	[CLKID_VPU_0]			= &g12a_vpu_0.hw,
4983	[CLKID_VPU_1_SEL]		= &g12a_vpu_1_sel.hw,
4984	[CLKID_VPU_1_DIV]		= &g12a_vpu_1_div.hw,
4985	[CLKID_VPU_1]			= &g12a_vpu_1.hw,
4986	[CLKID_VPU]			= &g12a_vpu.hw,
4987	[CLKID_VAPB_0_SEL]		= &g12a_vapb_0_sel.hw,
4988	[CLKID_VAPB_0_DIV]		= &g12a_vapb_0_div.hw,
4989	[CLKID_VAPB_0]			= &g12a_vapb_0.hw,
4990	[CLKID_VAPB_1_SEL]		= &g12a_vapb_1_sel.hw,
4991	[CLKID_VAPB_1_DIV]		= &g12a_vapb_1_div.hw,
4992	[CLKID_VAPB_1]			= &g12a_vapb_1.hw,
4993	[CLKID_VAPB_SEL]		= &g12a_vapb_sel.hw,
4994	[CLKID_VAPB]			= &g12a_vapb.hw,
4995	[CLKID_HDMI_PLL_DCO]		= &g12a_hdmi_pll_dco.hw,
4996	[CLKID_HDMI_PLL_OD]		= &g12a_hdmi_pll_od.hw,
4997	[CLKID_HDMI_PLL_OD2]		= &g12a_hdmi_pll_od2.hw,
4998	[CLKID_HDMI_PLL]		= &g12a_hdmi_pll.hw,
4999	[CLKID_VID_PLL]			= &g12a_vid_pll_div.hw,
5000	[CLKID_VID_PLL_SEL]		= &g12a_vid_pll_sel.hw,
5001	[CLKID_VID_PLL_DIV]		= &g12a_vid_pll.hw,
5002	[CLKID_VCLK_SEL]		= &g12a_vclk_sel.hw,
5003	[CLKID_VCLK2_SEL]		= &g12a_vclk2_sel.hw,
5004	[CLKID_VCLK_INPUT]		= &g12a_vclk_input.hw,
5005	[CLKID_VCLK2_INPUT]		= &g12a_vclk2_input.hw,
5006	[CLKID_VCLK_DIV]		= &g12a_vclk_div.hw,
5007	[CLKID_VCLK2_DIV]		= &g12a_vclk2_div.hw,
5008	[CLKID_VCLK]			= &g12a_vclk.hw,
5009	[CLKID_VCLK2]			= &g12a_vclk2.hw,
5010	[CLKID_VCLK_DIV1]		= &g12a_vclk_div1.hw,
5011	[CLKID_VCLK_DIV2_EN]		= &g12a_vclk_div2_en.hw,
5012	[CLKID_VCLK_DIV4_EN]		= &g12a_vclk_div4_en.hw,
5013	[CLKID_VCLK_DIV6_EN]		= &g12a_vclk_div6_en.hw,
5014	[CLKID_VCLK_DIV12_EN]		= &g12a_vclk_div12_en.hw,
5015	[CLKID_VCLK2_DIV1]		= &g12a_vclk2_div1.hw,
5016	[CLKID_VCLK2_DIV2_EN]		= &g12a_vclk2_div2_en.hw,
5017	[CLKID_VCLK2_DIV4_EN]		= &g12a_vclk2_div4_en.hw,
5018	[CLKID_VCLK2_DIV6_EN]		= &g12a_vclk2_div6_en.hw,
5019	[CLKID_VCLK2_DIV12_EN]		= &g12a_vclk2_div12_en.hw,
5020	[CLKID_VCLK_DIV2]		= &g12a_vclk_div2.hw,
5021	[CLKID_VCLK_DIV4]		= &g12a_vclk_div4.hw,
5022	[CLKID_VCLK_DIV6]		= &g12a_vclk_div6.hw,
5023	[CLKID_VCLK_DIV12]		= &g12a_vclk_div12.hw,
5024	[CLKID_VCLK2_DIV2]		= &g12a_vclk2_div2.hw,
5025	[CLKID_VCLK2_DIV4]		= &g12a_vclk2_div4.hw,
5026	[CLKID_VCLK2_DIV6]		= &g12a_vclk2_div6.hw,
5027	[CLKID_VCLK2_DIV12]		= &g12a_vclk2_div12.hw,
5028	[CLKID_CTS_ENCI_SEL]		= &g12a_cts_enci_sel.hw,
5029	[CLKID_CTS_ENCP_SEL]		= &g12a_cts_encp_sel.hw,
5030	[CLKID_CTS_ENCL_SEL]		= &g12a_cts_encl_sel.hw,
5031	[CLKID_CTS_VDAC_SEL]		= &g12a_cts_vdac_sel.hw,
5032	[CLKID_HDMI_TX_SEL]		= &g12a_hdmi_tx_sel.hw,
5033	[CLKID_CTS_ENCI]		= &g12a_cts_enci.hw,
5034	[CLKID_CTS_ENCP]		= &g12a_cts_encp.hw,
5035	[CLKID_CTS_ENCL]		= &g12a_cts_encl.hw,
5036	[CLKID_CTS_VDAC]		= &g12a_cts_vdac.hw,
5037	[CLKID_HDMI_TX]			= &g12a_hdmi_tx.hw,
5038	[CLKID_HDMI_SEL]		= &g12a_hdmi_sel.hw,
5039	[CLKID_HDMI_DIV]		= &g12a_hdmi_div.hw,
5040	[CLKID_HDMI]			= &g12a_hdmi.hw,
5041	[CLKID_MALI_0_SEL]		= &g12a_mali_0_sel.hw,
5042	[CLKID_MALI_0_DIV]		= &g12a_mali_0_div.hw,
5043	[CLKID_MALI_0]			= &g12a_mali_0.hw,
5044	[CLKID_MALI_1_SEL]		= &g12a_mali_1_sel.hw,
5045	[CLKID_MALI_1_DIV]		= &g12a_mali_1_div.hw,
5046	[CLKID_MALI_1]			= &g12a_mali_1.hw,
5047	[CLKID_MALI]			= &g12a_mali.hw,
5048	[CLKID_MPLL_50M_DIV]		= &g12a_mpll_50m_div.hw,
5049	[CLKID_MPLL_50M]		= &g12a_mpll_50m.hw,
5050	[CLKID_SYS_PLL_DIV16_EN]	= &g12a_sys_pll_div16_en.hw,
5051	[CLKID_SYS_PLL_DIV16]		= &g12a_sys_pll_div16.hw,
5052	[CLKID_CPU_CLK_DYN0_SEL]	= &g12a_cpu_clk_premux0.hw,
5053	[CLKID_CPU_CLK_DYN0_DIV]	= &g12a_cpu_clk_mux0_div.hw,
5054	[CLKID_CPU_CLK_DYN0]		= &g12a_cpu_clk_postmux0.hw,
5055	[CLKID_CPU_CLK_DYN1_SEL]	= &g12a_cpu_clk_premux1.hw,
5056	[CLKID_CPU_CLK_DYN1_DIV]	= &g12a_cpu_clk_mux1_div.hw,
5057	[CLKID_CPU_CLK_DYN1]		= &g12a_cpu_clk_postmux1.hw,
5058	[CLKID_CPU_CLK_DYN]		= &g12a_cpu_clk_dyn.hw,
5059	[CLKID_CPU_CLK]			= &g12a_cpu_clk.hw,
5060	[CLKID_CPU_CLK_DIV16_EN]	= &g12a_cpu_clk_div16_en.hw,
5061	[CLKID_CPU_CLK_DIV16]		= &g12a_cpu_clk_div16.hw,
5062	[CLKID_CPU_CLK_APB_DIV]		= &g12a_cpu_clk_apb_div.hw,
5063	[CLKID_CPU_CLK_APB]		= &g12a_cpu_clk_apb.hw,
5064	[CLKID_CPU_CLK_ATB_DIV]		= &g12a_cpu_clk_atb_div.hw,
5065	[CLKID_CPU_CLK_ATB]		= &g12a_cpu_clk_atb.hw,
5066	[CLKID_CPU_CLK_AXI_DIV]		= &g12a_cpu_clk_axi_div.hw,
5067	[CLKID_CPU_CLK_AXI]		= &g12a_cpu_clk_axi.hw,
5068	[CLKID_CPU_CLK_TRACE_DIV]	= &g12a_cpu_clk_trace_div.hw,
5069	[CLKID_CPU_CLK_TRACE]		= &g12a_cpu_clk_trace.hw,
5070	[CLKID_PCIE_PLL_DCO]		= &g12a_pcie_pll_dco.hw,
5071	[CLKID_PCIE_PLL_DCO_DIV2]	= &g12a_pcie_pll_dco_div2.hw,
5072	[CLKID_PCIE_PLL_OD]		= &g12a_pcie_pll_od.hw,
5073	[CLKID_PCIE_PLL]		= &g12a_pcie_pll.hw,
5074	[CLKID_VDEC_1_SEL]		= &g12a_vdec_1_sel.hw,
5075	[CLKID_VDEC_1_DIV]		= &g12a_vdec_1_div.hw,
5076	[CLKID_VDEC_1]			= &g12a_vdec_1.hw,
5077	[CLKID_VDEC_HEVC_SEL]		= &g12a_vdec_hevc_sel.hw,
5078	[CLKID_VDEC_HEVC_DIV]		= &g12a_vdec_hevc_div.hw,
5079	[CLKID_VDEC_HEVC]		= &g12a_vdec_hevc.hw,
5080	[CLKID_VDEC_HEVCF_SEL]		= &g12a_vdec_hevcf_sel.hw,
5081	[CLKID_VDEC_HEVCF_DIV]		= &g12a_vdec_hevcf_div.hw,
5082	[CLKID_VDEC_HEVCF]		= &g12a_vdec_hevcf.hw,
5083	[CLKID_TS_DIV]			= &g12a_ts_div.hw,
5084	[CLKID_TS]			= &g12a_ts.hw,
5085	[CLKID_GP1_PLL_DCO]		= &sm1_gp1_pll_dco.hw,
5086	[CLKID_GP1_PLL]			= &sm1_gp1_pll.hw,
5087	[CLKID_DSU_CLK_DYN0_SEL]	= &sm1_dsu_clk_premux0.hw,
5088	[CLKID_DSU_CLK_DYN0_DIV]	= &sm1_dsu_clk_premux1.hw,
5089	[CLKID_DSU_CLK_DYN0]		= &sm1_dsu_clk_mux0_div.hw,
5090	[CLKID_DSU_CLK_DYN1_SEL]	= &sm1_dsu_clk_postmux0.hw,
5091	[CLKID_DSU_CLK_DYN1_DIV]	= &sm1_dsu_clk_mux1_div.hw,
5092	[CLKID_DSU_CLK_DYN1]		= &sm1_dsu_clk_postmux1.hw,
5093	[CLKID_DSU_CLK_DYN]		= &sm1_dsu_clk_dyn.hw,
5094	[CLKID_DSU_CLK_FINAL]		= &sm1_dsu_final_clk.hw,
5095	[CLKID_DSU_CLK]			= &sm1_dsu_clk.hw,
5096	[CLKID_CPU1_CLK]		= &sm1_cpu1_clk.hw,
5097	[CLKID_CPU2_CLK]		= &sm1_cpu2_clk.hw,
5098	[CLKID_CPU3_CLK]		= &sm1_cpu3_clk.hw,
5099	[CLKID_SPICC0_SCLK_SEL]		= &g12a_spicc0_sclk_sel.hw,
5100	[CLKID_SPICC0_SCLK_DIV]		= &g12a_spicc0_sclk_div.hw,
5101	[CLKID_SPICC0_SCLK]		= &g12a_spicc0_sclk.hw,
5102	[CLKID_SPICC1_SCLK_SEL]		= &g12a_spicc1_sclk_sel.hw,
5103	[CLKID_SPICC1_SCLK_DIV]		= &g12a_spicc1_sclk_div.hw,
5104	[CLKID_SPICC1_SCLK]		= &g12a_spicc1_sclk.hw,
5105	[CLKID_NNA_AXI_CLK_SEL]		= &sm1_nna_axi_clk_sel.hw,
5106	[CLKID_NNA_AXI_CLK_DIV]		= &sm1_nna_axi_clk_div.hw,
5107	[CLKID_NNA_AXI_CLK]		= &sm1_nna_axi_clk.hw,
5108	[CLKID_NNA_CORE_CLK_SEL]	= &sm1_nna_core_clk_sel.hw,
5109	[CLKID_NNA_CORE_CLK_DIV]	= &sm1_nna_core_clk_div.hw,
5110	[CLKID_NNA_CORE_CLK]		= &sm1_nna_core_clk.hw,
5111	[CLKID_MIPI_DSI_PXCLK_SEL]	= &g12a_mipi_dsi_pxclk_sel.hw,
5112	[CLKID_MIPI_DSI_PXCLK_DIV]	= &g12a_mipi_dsi_pxclk_div.hw,
5113	[CLKID_MIPI_DSI_PXCLK]		= &g12a_mipi_dsi_pxclk.hw,
5114};
5115
5116/* Convenience table to populate regmap in .probe */
5117static struct clk_regmap *const g12a_clk_regmaps[] = {
5118	&g12a_clk81,
5119	&g12a_dos,
5120	&g12a_ddr,
5121	&g12a_audio_locker,
5122	&g12a_mipi_dsi_host,
5123	&g12a_eth_phy,
5124	&g12a_isa,
5125	&g12a_pl301,
5126	&g12a_periphs,
5127	&g12a_spicc_0,
5128	&g12a_i2c,
5129	&g12a_sana,
5130	&g12a_sd,
5131	&g12a_rng0,
5132	&g12a_uart0,
5133	&g12a_spicc_1,
5134	&g12a_hiu_reg,
5135	&g12a_mipi_dsi_phy,
5136	&g12a_assist_misc,
5137	&g12a_emmc_a,
5138	&g12a_emmc_b,
5139	&g12a_emmc_c,
5140	&g12a_audio_codec,
5141	&g12a_audio,
5142	&g12a_eth_core,
5143	&g12a_demux,
5144	&g12a_audio_ififo,
5145	&g12a_adc,
5146	&g12a_uart1,
5147	&g12a_g2d,
5148	&g12a_reset,
5149	&g12a_pcie_comb,
5150	&g12a_parser,
5151	&g12a_usb_general,
5152	&g12a_pcie_phy,
5153	&g12a_ahb_arb0,
5154	&g12a_ahb_data_bus,
5155	&g12a_ahb_ctrl_bus,
5156	&g12a_htx_hdcp22,
5157	&g12a_htx_pclk,
5158	&g12a_bt656,
5159	&g12a_usb1_to_ddr,
5160	&g12a_mmc_pclk,
5161	&g12a_uart2,
5162	&g12a_vpu_intr,
5163	&g12a_gic,
5164	&g12a_sd_emmc_a_clk0,
5165	&g12a_sd_emmc_b_clk0,
5166	&g12a_sd_emmc_c_clk0,
5167	&g12a_mpeg_clk_div,
5168	&g12a_sd_emmc_a_clk0_div,
5169	&g12a_sd_emmc_b_clk0_div,
5170	&g12a_sd_emmc_c_clk0_div,
5171	&g12a_mpeg_clk_sel,
5172	&g12a_sd_emmc_a_clk0_sel,
5173	&g12a_sd_emmc_b_clk0_sel,
5174	&g12a_sd_emmc_c_clk0_sel,
5175	&g12a_mpll0,
5176	&g12a_mpll1,
5177	&g12a_mpll2,
5178	&g12a_mpll3,
5179	&g12a_mpll0_div,
5180	&g12a_mpll1_div,
5181	&g12a_mpll2_div,
5182	&g12a_mpll3_div,
5183	&g12a_fixed_pll,
5184	&g12a_sys_pll,
5185	&g12a_gp0_pll,
5186	&g12a_hifi_pll,
5187	&g12a_vclk2_venci0,
5188	&g12a_vclk2_venci1,
5189	&g12a_vclk2_vencp0,
5190	&g12a_vclk2_vencp1,
5191	&g12a_vclk2_venct0,
5192	&g12a_vclk2_venct1,
5193	&g12a_vclk2_other,
5194	&g12a_vclk2_enci,
5195	&g12a_vclk2_encp,
5196	&g12a_dac_clk,
5197	&g12a_aoclk_gate,
5198	&g12a_iec958_gate,
5199	&g12a_enc480p,
5200	&g12a_rng1,
5201	&g12a_vclk2_enct,
5202	&g12a_vclk2_encl,
5203	&g12a_vclk2_venclmmc,
5204	&g12a_vclk2_vencl,
5205	&g12a_vclk2_other1,
5206	&g12a_fixed_pll_dco,
5207	&g12a_sys_pll_dco,
5208	&g12a_gp0_pll_dco,
5209	&g12a_hifi_pll_dco,
5210	&g12a_fclk_div2,
5211	&g12a_fclk_div3,
5212	&g12a_fclk_div4,
5213	&g12a_fclk_div5,
5214	&g12a_fclk_div7,
5215	&g12a_fclk_div2p5,
5216	&g12a_dma,
5217	&g12a_efuse,
5218	&g12a_rom_boot,
5219	&g12a_reset_sec,
5220	&g12a_sec_ahb_apb3,
5221	&g12a_vpu_0_sel,
5222	&g12a_vpu_0_div,
5223	&g12a_vpu_0,
5224	&g12a_vpu_1_sel,
5225	&g12a_vpu_1_div,
5226	&g12a_vpu_1,
5227	&g12a_vpu,
5228	&g12a_vapb_0_sel,
5229	&g12a_vapb_0_div,
5230	&g12a_vapb_0,
5231	&g12a_vapb_1_sel,
5232	&g12a_vapb_1_div,
5233	&g12a_vapb_1,
5234	&g12a_vapb_sel,
5235	&g12a_vapb,
5236	&g12a_hdmi_pll_dco,
5237	&g12a_hdmi_pll_od,
5238	&g12a_hdmi_pll_od2,
5239	&g12a_hdmi_pll,
5240	&g12a_vid_pll_div,
5241	&g12a_vid_pll_sel,
5242	&g12a_vid_pll,
5243	&g12a_vclk_sel,
5244	&g12a_vclk2_sel,
5245	&g12a_vclk_input,
5246	&g12a_vclk2_input,
5247	&g12a_vclk_div,
5248	&g12a_vclk2_div,
5249	&g12a_vclk,
5250	&g12a_vclk2,
5251	&g12a_vclk_div1,
5252	&g12a_vclk_div2_en,
5253	&g12a_vclk_div4_en,
5254	&g12a_vclk_div6_en,
5255	&g12a_vclk_div12_en,
5256	&g12a_vclk2_div1,
5257	&g12a_vclk2_div2_en,
5258	&g12a_vclk2_div4_en,
5259	&g12a_vclk2_div6_en,
5260	&g12a_vclk2_div12_en,
5261	&g12a_cts_enci_sel,
5262	&g12a_cts_encp_sel,
5263	&g12a_cts_encl_sel,
5264	&g12a_cts_vdac_sel,
5265	&g12a_hdmi_tx_sel,
5266	&g12a_cts_enci,
5267	&g12a_cts_encp,
5268	&g12a_cts_encl,
5269	&g12a_cts_vdac,
5270	&g12a_hdmi_tx,
5271	&g12a_hdmi_sel,
5272	&g12a_hdmi_div,
5273	&g12a_hdmi,
5274	&g12a_mali_0_sel,
5275	&g12a_mali_0_div,
5276	&g12a_mali_0,
5277	&g12a_mali_1_sel,
5278	&g12a_mali_1_div,
5279	&g12a_mali_1,
5280	&g12a_mali,
5281	&g12a_mpll_50m,
5282	&g12a_sys_pll_div16_en,
5283	&g12a_cpu_clk_premux0,
5284	&g12a_cpu_clk_mux0_div,
5285	&g12a_cpu_clk_postmux0,
5286	&g12a_cpu_clk_premux1,
5287	&g12a_cpu_clk_mux1_div,
5288	&g12a_cpu_clk_postmux1,
5289	&g12a_cpu_clk_dyn,
5290	&g12a_cpu_clk,
5291	&g12a_cpu_clk_div16_en,
5292	&g12a_cpu_clk_apb_div,
5293	&g12a_cpu_clk_apb,
5294	&g12a_cpu_clk_atb_div,
5295	&g12a_cpu_clk_atb,
5296	&g12a_cpu_clk_axi_div,
5297	&g12a_cpu_clk_axi,
5298	&g12a_cpu_clk_trace_div,
5299	&g12a_cpu_clk_trace,
5300	&g12a_pcie_pll_od,
5301	&g12a_pcie_pll_dco,
5302	&g12a_vdec_1_sel,
5303	&g12a_vdec_1_div,
5304	&g12a_vdec_1,
5305	&g12a_vdec_hevc_sel,
5306	&g12a_vdec_hevc_div,
5307	&g12a_vdec_hevc,
5308	&g12a_vdec_hevcf_sel,
5309	&g12a_vdec_hevcf_div,
5310	&g12a_vdec_hevcf,
5311	&g12a_ts_div,
5312	&g12a_ts,
5313	&g12b_cpu_clk,
5314	&g12b_sys1_pll_dco,
5315	&g12b_sys1_pll,
5316	&g12b_sys1_pll_div16_en,
5317	&g12b_cpub_clk_premux0,
5318	&g12b_cpub_clk_mux0_div,
5319	&g12b_cpub_clk_postmux0,
5320	&g12b_cpub_clk_premux1,
5321	&g12b_cpub_clk_mux1_div,
5322	&g12b_cpub_clk_postmux1,
5323	&g12b_cpub_clk_dyn,
5324	&g12b_cpub_clk,
5325	&g12b_cpub_clk_div16_en,
5326	&g12b_cpub_clk_apb_sel,
5327	&g12b_cpub_clk_apb,
5328	&g12b_cpub_clk_atb_sel,
5329	&g12b_cpub_clk_atb,
5330	&g12b_cpub_clk_axi_sel,
5331	&g12b_cpub_clk_axi,
5332	&g12b_cpub_clk_trace_sel,
5333	&g12b_cpub_clk_trace,
5334	&sm1_gp1_pll_dco,
5335	&sm1_gp1_pll,
5336	&sm1_dsu_clk_premux0,
5337	&sm1_dsu_clk_premux1,
5338	&sm1_dsu_clk_mux0_div,
5339	&sm1_dsu_clk_postmux0,
5340	&sm1_dsu_clk_mux1_div,
5341	&sm1_dsu_clk_postmux1,
5342	&sm1_dsu_clk_dyn,
5343	&sm1_dsu_final_clk,
5344	&sm1_dsu_clk,
5345	&sm1_cpu1_clk,
5346	&sm1_cpu2_clk,
5347	&sm1_cpu3_clk,
5348	&g12a_spicc0_sclk_sel,
5349	&g12a_spicc0_sclk_div,
5350	&g12a_spicc0_sclk,
5351	&g12a_spicc1_sclk_sel,
5352	&g12a_spicc1_sclk_div,
5353	&g12a_spicc1_sclk,
5354	&sm1_nna_axi_clk_sel,
5355	&sm1_nna_axi_clk_div,
5356	&sm1_nna_axi_clk,
5357	&sm1_nna_core_clk_sel,
5358	&sm1_nna_core_clk_div,
5359	&sm1_nna_core_clk,
5360	&g12a_mipi_dsi_pxclk_sel,
5361	&g12a_mipi_dsi_pxclk_div,
5362	&g12a_mipi_dsi_pxclk,
5363	&g12b_mipi_isp_sel,
5364	&g12b_mipi_isp_div,
5365	&g12b_mipi_isp,
5366	&g12b_mipi_isp_gate,
5367	&g12b_csi_phy1,
5368	&g12b_csi_phy0,
5369};
5370
5371static const struct reg_sequence g12a_init_regs[] = {
5372	{ .reg = HHI_MPLL_CNTL0,	.def = 0x00000543 },
5373};
5374
5375#define DVFS_CON_ID "dvfs"
5376
5377static int meson_g12a_dvfs_setup_common(struct device *dev,
5378					struct clk_hw **hws)
5379{
5380	struct clk *notifier_clk;
5381	struct clk_hw *xtal;
5382	int ret;
5383
5384	xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
5385
5386	/* Setup clock notifier for cpu_clk_postmux0 */
5387	g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
5388	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_postmux0.hw,
5389					   DVFS_CON_ID);
5390	ret = devm_clk_notifier_register(dev, notifier_clk,
5391					 &g12a_cpu_clk_postmux0_nb_data.nb);
5392	if (ret) {
5393		dev_err(dev, "failed to register the cpu_clk_postmux0 notifier\n");
5394		return ret;
5395	}
5396
5397	/* Setup clock notifier for cpu_clk_dyn mux */
5398	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk_dyn.hw,
5399					   DVFS_CON_ID);
5400	ret = devm_clk_notifier_register(dev, notifier_clk,
5401					 &g12a_cpu_clk_mux_nb);
5402	if (ret) {
5403		dev_err(dev, "failed to register the cpu_clk_dyn notifier\n");
5404		return ret;
5405	}
5406
5407	return 0;
5408}
5409
5410static int meson_g12b_dvfs_setup(struct platform_device *pdev)
5411{
5412	struct clk_hw **hws = g12b_hw_clks;
5413	struct device *dev = &pdev->dev;
5414	struct clk *notifier_clk;
5415	struct clk_hw *xtal;
5416	int ret;
5417
5418	ret = meson_g12a_dvfs_setup_common(dev, hws);
5419	if (ret)
5420		return ret;
5421
5422	xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
5423
5424	/* Setup clock notifier for cpu_clk mux */
5425	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpu_clk.hw,
5426					   DVFS_CON_ID);
5427	ret = devm_clk_notifier_register(dev, notifier_clk,
5428					 &g12a_cpu_clk_mux_nb);
5429	if (ret) {
5430		dev_err(dev, "failed to register the cpu_clk notifier\n");
5431		return ret;
5432	}
5433
5434	/* Setup clock notifier for sys1_pll */
5435	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_sys1_pll.hw,
5436					   DVFS_CON_ID);
5437	ret = devm_clk_notifier_register(dev, notifier_clk,
5438					 &g12b_cpu_clk_sys1_pll_nb_data.nb);
5439	if (ret) {
5440		dev_err(dev, "failed to register the sys1_pll notifier\n");
5441		return ret;
5442	}
5443
5444	/* Add notifiers for the second CPU cluster */
5445
5446	/* Setup clock notifier for cpub_clk_postmux0 */
5447	g12b_cpub_clk_postmux0_nb_data.xtal = xtal;
5448	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_postmux0.hw,
5449					   DVFS_CON_ID);
5450	ret = devm_clk_notifier_register(dev, notifier_clk,
5451					 &g12b_cpub_clk_postmux0_nb_data.nb);
5452	if (ret) {
5453		dev_err(dev, "failed to register the cpub_clk_postmux0 notifier\n");
5454		return ret;
5455	}
5456
5457	/* Setup clock notifier for cpub_clk_dyn mux */
5458	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk_dyn.hw, "dvfs");
5459	ret = devm_clk_notifier_register(dev, notifier_clk,
5460					 &g12a_cpu_clk_mux_nb);
5461	if (ret) {
5462		dev_err(dev, "failed to register the cpub_clk_dyn notifier\n");
5463		return ret;
5464	}
5465
5466	/* Setup clock notifier for cpub_clk mux */
5467	notifier_clk = devm_clk_hw_get_clk(dev, &g12b_cpub_clk.hw, DVFS_CON_ID);
5468	ret = devm_clk_notifier_register(dev, notifier_clk,
5469					 &g12a_cpu_clk_mux_nb);
5470	if (ret) {
5471		dev_err(dev, "failed to register the cpub_clk notifier\n");
5472		return ret;
5473	}
5474
5475	/* Setup clock notifier for sys_pll */
5476	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);
5477	ret = devm_clk_notifier_register(dev, notifier_clk,
5478					 &g12b_cpub_clk_sys_pll_nb_data.nb);
5479	if (ret) {
5480		dev_err(dev, "failed to register the sys_pll notifier\n");
5481		return ret;
5482	}
5483
5484	return 0;
5485}
5486
5487static int meson_g12a_dvfs_setup(struct platform_device *pdev)
5488{
5489	struct clk_hw **hws = g12a_hw_clks;
5490	struct device *dev = &pdev->dev;
5491	struct clk *notifier_clk;
5492	int ret;
5493
5494	ret = meson_g12a_dvfs_setup_common(dev, hws);
5495	if (ret)
5496		return ret;
5497
5498	/* Setup clock notifier for cpu_clk mux */
5499	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_cpu_clk.hw, DVFS_CON_ID);
5500	ret = devm_clk_notifier_register(dev, notifier_clk,
5501				    &g12a_cpu_clk_mux_nb);
5502	if (ret) {
5503		dev_err(dev, "failed to register the cpu_clk notifier\n");
5504		return ret;
5505	}
5506
5507	/* Setup clock notifier for sys_pll */
5508	notifier_clk = devm_clk_hw_get_clk(dev, &g12a_sys_pll.hw, DVFS_CON_ID);
5509	ret = devm_clk_notifier_register(dev, notifier_clk,
5510					 &g12a_sys_pll_nb_data.nb);
5511	if (ret) {
5512		dev_err(dev, "failed to register the sys_pll notifier\n");
5513		return ret;
5514	}
5515
5516	return 0;
5517}
5518
5519struct meson_g12a_data {
5520	const struct meson_eeclkc_data eeclkc_data;
5521	int (*dvfs_setup)(struct platform_device *pdev);
5522};
5523
5524static int meson_g12a_probe(struct platform_device *pdev)
5525{
5526	const struct meson_eeclkc_data *eeclkc_data;
5527	const struct meson_g12a_data *g12a_data;
5528	int ret;
5529
5530	eeclkc_data = of_device_get_match_data(&pdev->dev);
5531	if (!eeclkc_data)
5532		return -EINVAL;
5533
5534	ret = meson_eeclkc_probe(pdev);
5535	if (ret)
5536		return ret;
5537
5538	g12a_data = container_of(eeclkc_data, struct meson_g12a_data,
5539				 eeclkc_data);
5540
5541	if (g12a_data->dvfs_setup)
5542		return g12a_data->dvfs_setup(pdev);
5543
5544	return 0;
5545}
5546
5547static const struct meson_g12a_data g12a_clkc_data = {
5548	.eeclkc_data = {
5549		.regmap_clks = g12a_clk_regmaps,
5550		.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5551		.hw_clks = {
5552			.hws = g12a_hw_clks,
5553			.num = ARRAY_SIZE(g12a_hw_clks),
5554		},
5555		.init_regs = g12a_init_regs,
5556		.init_count = ARRAY_SIZE(g12a_init_regs),
5557	},
5558	.dvfs_setup = meson_g12a_dvfs_setup,
5559};
5560
5561static const struct meson_g12a_data g12b_clkc_data = {
5562	.eeclkc_data = {
5563		.regmap_clks = g12a_clk_regmaps,
5564		.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5565		.hw_clks = {
5566			.hws = g12b_hw_clks,
5567			.num = ARRAY_SIZE(g12b_hw_clks),
5568		},
5569	},
5570	.dvfs_setup = meson_g12b_dvfs_setup,
5571};
5572
5573static const struct meson_g12a_data sm1_clkc_data = {
5574	.eeclkc_data = {
5575		.regmap_clks = g12a_clk_regmaps,
5576		.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5577		.hw_clks = {
5578			.hws = sm1_hw_clks,
5579			.num = ARRAY_SIZE(sm1_hw_clks),
5580		},
5581	},
5582	.dvfs_setup = meson_g12a_dvfs_setup,
5583};
5584
5585static const struct of_device_id clkc_match_table[] = {
5586	{
5587		.compatible = "amlogic,g12a-clkc",
5588		.data = &g12a_clkc_data.eeclkc_data
5589	},
5590	{
5591		.compatible = "amlogic,g12b-clkc",
5592		.data = &g12b_clkc_data.eeclkc_data
5593	},
5594	{
5595		.compatible = "amlogic,sm1-clkc",
5596		.data = &sm1_clkc_data.eeclkc_data
5597	},
5598	{}
5599};
5600MODULE_DEVICE_TABLE(of, clkc_match_table);
5601
5602static struct platform_driver g12a_driver = {
5603	.probe		= meson_g12a_probe,
5604	.driver		= {
5605		.name	= "g12a-clkc",
5606		.of_match_table = clkc_match_table,
5607	},
5608};
5609module_platform_driver(g12a_driver);
5610
5611MODULE_DESCRIPTION("Amlogic G12/SM1 Main Clock Controller driver");
5612MODULE_LICENSE("GPL");
5613MODULE_IMPORT_NS("CLK_MESON");