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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Amlogic C3 Peripherals Clock Controller Driver
4 *
5 * Copyright (c) 2023 Amlogic, inc.
6 * Author: Chuan Liu <chuan.liu@amlogic.com>
7 */
8
9#include <linux/clk-provider.h>
10#include <linux/platform_device.h>
11#include "clk-regmap.h"
12#include "clk-dualdiv.h"
13#include "meson-clkc-utils.h"
14#include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
15
16#define RTC_BY_OSCIN_CTRL0 0x8
17#define RTC_BY_OSCIN_CTRL1 0xc
18#define RTC_CTRL 0x10
19#define SYS_CLK_EN0_REG0 0x44
20#define SYS_CLK_EN0_REG1 0x48
21#define SYS_CLK_EN0_REG2 0x4c
22#define CLK12_24_CTRL 0xa8
23#define AXI_CLK_EN0 0xac
24#define VDIN_MEAS_CLK_CTRL 0xf8
25#define VAPB_CLK_CTRL 0xfc
26#define MIPIDSI_PHY_CLK_CTRL 0x104
27#define GE2D_CLK_CTRL 0x10c
28#define ISP0_CLK_CTRL 0x110
29#define DEWARPA_CLK_CTRL 0x114
30#define VOUTENC_CLK_CTRL 0x118
31#define VDEC_CLK_CTRL 0x140
32#define VDEC3_CLK_CTRL 0x148
33#define TS_CLK_CTRL 0x158
34#define ETH_CLK_CTRL 0x164
35#define NAND_CLK_CTRL 0x168
36#define SD_EMMC_CLK_CTRL 0x16c
37#define SPICC_CLK_CTRL 0x174
38#define GEN_CLK_CTRL 0x178
39#define SAR_CLK_CTRL0 0x17c
40#define PWM_CLK_AB_CTRL 0x180
41#define PWM_CLK_CD_CTRL 0x184
42#define PWM_CLK_EF_CTRL 0x188
43#define PWM_CLK_GH_CTRL 0x18c
44#define PWM_CLK_IJ_CTRL 0x190
45#define PWM_CLK_KL_CTRL 0x194
46#define PWM_CLK_MN_CTRL 0x198
47#define VC9000E_CLK_CTRL 0x19c
48#define SPIFC_CLK_CTRL 0x1a0
49#define NNA_CLK_CTRL 0x220
50
51static struct clk_regmap rtc_xtal_clkin = {
52 .data = &(struct clk_regmap_gate_data) {
53 .offset = RTC_BY_OSCIN_CTRL0,
54 .bit_idx = 31,
55 },
56 .hw.init = &(struct clk_init_data) {
57 .name = "rtc_xtal_clkin",
58 .ops = &clk_regmap_gate_ops,
59 .parent_data = &(const struct clk_parent_data) {
60 .fw_name = "oscin",
61 },
62 .num_parents = 1,
63 },
64};
65
66static const struct meson_clk_dualdiv_param rtc_32k_div_table[] = {
67 { 733, 732, 8, 11, 1 },
68 { /* sentinel */ }
69};
70
71static struct clk_regmap rtc_32k_div = {
72 .data = &(struct meson_clk_dualdiv_data) {
73 .n1 = {
74 .reg_off = RTC_BY_OSCIN_CTRL0,
75 .shift = 0,
76 .width = 12,
77 },
78 .n2 = {
79 .reg_off = RTC_BY_OSCIN_CTRL0,
80 .shift = 12,
81 .width = 12,
82 },
83 .m1 = {
84 .reg_off = RTC_BY_OSCIN_CTRL1,
85 .shift = 0,
86 .width = 12,
87 },
88 .m2 = {
89 .reg_off = RTC_BY_OSCIN_CTRL1,
90 .shift = 12,
91 .width = 12,
92 },
93 .dual = {
94 .reg_off = RTC_BY_OSCIN_CTRL0,
95 .shift = 28,
96 .width = 1,
97 },
98 .table = rtc_32k_div_table,
99 },
100 .hw.init = &(struct clk_init_data) {
101 .name = "rtc_32k_div",
102 .ops = &meson_clk_dualdiv_ops,
103 .parent_hws = (const struct clk_hw *[]) {
104 &rtc_xtal_clkin.hw
105 },
106 .num_parents = 1,
107 },
108};
109
110static const struct clk_parent_data rtc_32k_mux_parent_data[] = {
111 { .hw = &rtc_32k_div.hw },
112 { .hw = &rtc_xtal_clkin.hw }
113};
114
115static struct clk_regmap rtc_32k_mux = {
116 .data = &(struct clk_regmap_mux_data) {
117 .offset = RTC_BY_OSCIN_CTRL1,
118 .mask = 0x1,
119 .shift = 24,
120 },
121 .hw.init = &(struct clk_init_data) {
122 .name = "rtc_32k_mux",
123 .ops = &clk_regmap_mux_ops,
124 .parent_data = rtc_32k_mux_parent_data,
125 .num_parents = ARRAY_SIZE(rtc_32k_mux_parent_data),
126 .flags = CLK_SET_RATE_PARENT,
127 },
128};
129
130static struct clk_regmap rtc_32k = {
131 .data = &(struct clk_regmap_gate_data) {
132 .offset = RTC_BY_OSCIN_CTRL0,
133 .bit_idx = 30,
134 },
135 .hw.init = &(struct clk_init_data) {
136 .name = "rtc_32k",
137 .ops = &clk_regmap_gate_ops,
138 .parent_hws = (const struct clk_hw *[]) {
139 &rtc_32k_mux.hw
140 },
141 .num_parents = 1,
142 .flags = CLK_SET_RATE_PARENT,
143 },
144};
145
146static const struct clk_parent_data rtc_clk_mux_parent_data[] = {
147 { .fw_name = "oscin" },
148 { .hw = &rtc_32k.hw },
149 { .fw_name = "pad_osc" }
150};
151
152static struct clk_regmap rtc_clk = {
153 .data = &(struct clk_regmap_mux_data) {
154 .offset = RTC_CTRL,
155 .mask = 0x3,
156 .shift = 0,
157 },
158 .hw.init = &(struct clk_init_data) {
159 .name = "rtc_clk",
160 .ops = &clk_regmap_mux_ops,
161 .parent_data = rtc_clk_mux_parent_data,
162 .num_parents = ARRAY_SIZE(rtc_clk_mux_parent_data),
163 .flags = CLK_SET_RATE_PARENT,
164 },
165};
166
167#define C3_CLK_GATE(_name, _reg, _bit, _fw_name, _ops, _flags) \
168struct clk_regmap _name = { \
169 .data = &(struct clk_regmap_gate_data){ \
170 .offset = (_reg), \
171 .bit_idx = (_bit), \
172 }, \
173 .hw.init = &(struct clk_init_data) { \
174 .name = #_name, \
175 .ops = _ops, \
176 .parent_data = &(const struct clk_parent_data) { \
177 .fw_name = #_fw_name, \
178 }, \
179 .num_parents = 1, \
180 .flags = (_flags), \
181 }, \
182}
183
184#define C3_SYS_GATE(_name, _reg, _bit, _flags) \
185 C3_CLK_GATE(_name, _reg, _bit, sysclk, \
186 &clk_regmap_gate_ops, _flags)
187
188#define C3_SYS_GATE_RO(_name, _reg, _bit) \
189 C3_CLK_GATE(_name, _reg, _bit, sysclk, \
190 &clk_regmap_gate_ro_ops, 0)
191
192static C3_SYS_GATE(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0);
193static C3_SYS_GATE(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0);
194static C3_SYS_GATE(sys_pad_ctrl, SYS_CLK_EN0_REG0, 4, 0);
195static C3_SYS_GATE(sys_ctrl, SYS_CLK_EN0_REG0, 5, 0);
196static C3_SYS_GATE(sys_ts_pll, SYS_CLK_EN0_REG0, 6, 0);
197
198/*
199 * NOTE: sys_dev_arb provides the clock to the ETH and SPICC arbiters that
200 * access the AXI bus.
201 */
202static C3_SYS_GATE(sys_dev_arb, SYS_CLK_EN0_REG0, 7, 0);
203
204/*
205 * FIXME: sys_mmc_pclk provides the clock for the DDR PHY, DDR will only be
206 * initialized in bl2, and this clock should not be touched in linux.
207 */
208static C3_SYS_GATE_RO(sys_mmc_pclk, SYS_CLK_EN0_REG0, 8);
209
210/*
211 * NOTE: sys_cpu_ctrl provides the clock for CPU controller. After clock is
212 * disabled, cpu_clk and other key CPU-related configurations cannot take effect.
213 */
214static C3_SYS_GATE(sys_cpu_ctrl, SYS_CLK_EN0_REG0, 11, CLK_IS_CRITICAL);
215static C3_SYS_GATE(sys_jtag_ctrl, SYS_CLK_EN0_REG0, 12, 0);
216static C3_SYS_GATE(sys_ir_ctrl, SYS_CLK_EN0_REG0, 13, 0);
217
218/*
219 * NOTE: sys_irq_ctrl provides the clock for IRQ controller. The IRQ controller
220 * collects and distributes the interrupt signal to the GIC, PWR_CTRL, and
221 * AOCPU. If the clock is disabled, interrupt-related functions will occurs an
222 * exception.
223 */
224static C3_SYS_GATE(sys_irq_ctrl, SYS_CLK_EN0_REG0, 14, CLK_IS_CRITICAL);
225static C3_SYS_GATE(sys_msr_clk, SYS_CLK_EN0_REG0, 15, 0);
226static C3_SYS_GATE(sys_rom, SYS_CLK_EN0_REG0, 16, 0);
227static C3_SYS_GATE(sys_uart_f, SYS_CLK_EN0_REG0, 17, 0);
228static C3_SYS_GATE(sys_cpu_apb, SYS_CLK_EN0_REG0, 18, 0);
229static C3_SYS_GATE(sys_rsa, SYS_CLK_EN0_REG0, 19, 0);
230static C3_SYS_GATE(sys_sar_adc, SYS_CLK_EN0_REG0, 20, 0);
231static C3_SYS_GATE(sys_startup, SYS_CLK_EN0_REG0, 21, 0);
232static C3_SYS_GATE(sys_secure, SYS_CLK_EN0_REG0, 22, 0);
233static C3_SYS_GATE(sys_spifc, SYS_CLK_EN0_REG0, 23, 0);
234static C3_SYS_GATE(sys_nna, SYS_CLK_EN0_REG0, 25, 0);
235static C3_SYS_GATE(sys_eth_mac, SYS_CLK_EN0_REG0, 26, 0);
236
237/*
238 * FIXME: sys_gic provides the clock for GIC(Generic Interrupt Controller).
239 * After clock is disabled, The GIC cannot work properly. At present, the driver
240 * used by our GIC is the public driver in kernel, and there is no management
241 * clock in the driver.
242 */
243static C3_SYS_GATE(sys_gic, SYS_CLK_EN0_REG0, 27, CLK_IS_CRITICAL);
244static C3_SYS_GATE(sys_rama, SYS_CLK_EN0_REG0, 28, 0);
245
246/*
247 * NOTE: sys_big_nic provides the clock to the control bus of the NIC(Network
248 * Interface Controller) between multiple devices(CPU, DDR, RAM, ROM, GIC,
249 * SPIFC, CAPU, JTAG, EMMC, SDIO, sec_top, USB, Audio, ETH, SPICC) in the
250 * system. After clock is disabled, The NIC cannot work.
251 */
252static C3_SYS_GATE(sys_big_nic, SYS_CLK_EN0_REG0, 29, CLK_IS_CRITICAL);
253static C3_SYS_GATE(sys_ramb, SYS_CLK_EN0_REG0, 30, 0);
254static C3_SYS_GATE(sys_audio_pclk, SYS_CLK_EN0_REG0, 31, 0);
255static C3_SYS_GATE(sys_pwm_kl, SYS_CLK_EN0_REG1, 0, 0);
256static C3_SYS_GATE(sys_pwm_ij, SYS_CLK_EN0_REG1, 1, 0);
257static C3_SYS_GATE(sys_usb, SYS_CLK_EN0_REG1, 2, 0);
258static C3_SYS_GATE(sys_sd_emmc_a, SYS_CLK_EN0_REG1, 3, 0);
259static C3_SYS_GATE(sys_sd_emmc_c, SYS_CLK_EN0_REG1, 4, 0);
260static C3_SYS_GATE(sys_pwm_ab, SYS_CLK_EN0_REG1, 5, 0);
261static C3_SYS_GATE(sys_pwm_cd, SYS_CLK_EN0_REG1, 6, 0);
262static C3_SYS_GATE(sys_pwm_ef, SYS_CLK_EN0_REG1, 7, 0);
263static C3_SYS_GATE(sys_pwm_gh, SYS_CLK_EN0_REG1, 8, 0);
264static C3_SYS_GATE(sys_spicc_1, SYS_CLK_EN0_REG1, 9, 0);
265static C3_SYS_GATE(sys_spicc_0, SYS_CLK_EN0_REG1, 10, 0);
266static C3_SYS_GATE(sys_uart_a, SYS_CLK_EN0_REG1, 11, 0);
267static C3_SYS_GATE(sys_uart_b, SYS_CLK_EN0_REG1, 12, 0);
268static C3_SYS_GATE(sys_uart_c, SYS_CLK_EN0_REG1, 13, 0);
269static C3_SYS_GATE(sys_uart_d, SYS_CLK_EN0_REG1, 14, 0);
270static C3_SYS_GATE(sys_uart_e, SYS_CLK_EN0_REG1, 15, 0);
271static C3_SYS_GATE(sys_i2c_m_a, SYS_CLK_EN0_REG1, 16, 0);
272static C3_SYS_GATE(sys_i2c_m_b, SYS_CLK_EN0_REG1, 17, 0);
273static C3_SYS_GATE(sys_i2c_m_c, SYS_CLK_EN0_REG1, 18, 0);
274static C3_SYS_GATE(sys_i2c_m_d, SYS_CLK_EN0_REG1, 19, 0);
275static C3_SYS_GATE(sys_i2c_s_a, SYS_CLK_EN0_REG1, 20, 0);
276static C3_SYS_GATE(sys_rtc, SYS_CLK_EN0_REG1, 21, 0);
277static C3_SYS_GATE(sys_ge2d, SYS_CLK_EN0_REG1, 22, 0);
278static C3_SYS_GATE(sys_isp, SYS_CLK_EN0_REG1, 23, 0);
279static C3_SYS_GATE(sys_gpv_isp_nic, SYS_CLK_EN0_REG1, 24, 0);
280static C3_SYS_GATE(sys_gpv_cve_nic, SYS_CLK_EN0_REG1, 25, 0);
281static C3_SYS_GATE(sys_mipi_dsi_host, SYS_CLK_EN0_REG1, 26, 0);
282static C3_SYS_GATE(sys_mipi_dsi_phy, SYS_CLK_EN0_REG1, 27, 0);
283static C3_SYS_GATE(sys_eth_phy, SYS_CLK_EN0_REG1, 28, 0);
284static C3_SYS_GATE(sys_acodec, SYS_CLK_EN0_REG1, 29, 0);
285static C3_SYS_GATE(sys_dwap, SYS_CLK_EN0_REG1, 30, 0);
286static C3_SYS_GATE(sys_dos, SYS_CLK_EN0_REG1, 31, 0);
287static C3_SYS_GATE(sys_cve, SYS_CLK_EN0_REG2, 0, 0);
288static C3_SYS_GATE(sys_vout, SYS_CLK_EN0_REG2, 1, 0);
289static C3_SYS_GATE(sys_vc9000e, SYS_CLK_EN0_REG2, 2, 0);
290static C3_SYS_GATE(sys_pwm_mn, SYS_CLK_EN0_REG2, 3, 0);
291static C3_SYS_GATE(sys_sd_emmc_b, SYS_CLK_EN0_REG2, 4, 0);
292
293#define C3_AXI_GATE(_name, _reg, _bit, _flags) \
294 C3_CLK_GATE(_name, _reg, _bit, axiclk, \
295 &clk_regmap_gate_ops, _flags)
296
297/*
298 * NOTE: axi_sys_nic provides the clock to the AXI bus of the system NIC. After
299 * clock is disabled, The NIC cannot work.
300 */
301static C3_AXI_GATE(axi_sys_nic, AXI_CLK_EN0, 2, CLK_IS_CRITICAL);
302static C3_AXI_GATE(axi_isp_nic, AXI_CLK_EN0, 3, 0);
303static C3_AXI_GATE(axi_cve_nic, AXI_CLK_EN0, 4, 0);
304static C3_AXI_GATE(axi_ramb, AXI_CLK_EN0, 5, 0);
305static C3_AXI_GATE(axi_rama, AXI_CLK_EN0, 6, 0);
306
307/*
308 * NOTE: axi_cpu_dmc provides the clock to the AXI bus where the CPU accesses
309 * the DDR. After clock is disabled, The CPU will not have access to the DDR.
310 */
311static C3_AXI_GATE(axi_cpu_dmc, AXI_CLK_EN0, 7, CLK_IS_CRITICAL);
312static C3_AXI_GATE(axi_nic, AXI_CLK_EN0, 8, 0);
313static C3_AXI_GATE(axi_dma, AXI_CLK_EN0, 9, 0);
314
315/*
316 * NOTE: axi_mux_nic provides the clock to the NIC's AXI bus for NN(Neural
317 * Network) and other devices(CPU, EMMC, SDIO, sec_top, USB, Audio, ETH, SPICC)
318 * to access RAM space.
319 */
320static C3_AXI_GATE(axi_mux_nic, AXI_CLK_EN0, 10, 0);
321static C3_AXI_GATE(axi_cve, AXI_CLK_EN0, 12, 0);
322
323/*
324 * NOTE: axi_dev1_dmc provides the clock for the peripherals(EMMC, SDIO,
325 * sec_top, USB, Audio, ETH, SPICC) to access the AXI bus of the DDR.
326 */
327static C3_AXI_GATE(axi_dev1_dmc, AXI_CLK_EN0, 13, 0);
328static C3_AXI_GATE(axi_dev0_dmc, AXI_CLK_EN0, 14, 0);
329static C3_AXI_GATE(axi_dsp_dmc, AXI_CLK_EN0, 15, 0);
330
331/*
332 * clk_12_24m model
333 *
334 * |------| |-----| clk_12m_24m |-----|
335 * xtal---->| gate |---->| div |------------>| pad |
336 * |------| |-----| |-----|
337 */
338static struct clk_regmap clk_12_24m_in = {
339 .data = &(struct clk_regmap_gate_data) {
340 .offset = CLK12_24_CTRL,
341 .bit_idx = 11,
342 },
343 .hw.init = &(struct clk_init_data) {
344 .name = "clk_12_24m_in",
345 .ops = &clk_regmap_gate_ops,
346 .parent_data = &(const struct clk_parent_data) {
347 .fw_name = "xtal_24m",
348 },
349 .num_parents = 1,
350 },
351};
352
353static struct clk_regmap clk_12_24m = {
354 .data = &(struct clk_regmap_div_data) {
355 .offset = CLK12_24_CTRL,
356 .shift = 10,
357 .width = 1,
358 },
359 .hw.init = &(struct clk_init_data) {
360 .name = "clk_12_24m",
361 .ops = &clk_regmap_divider_ops,
362 .parent_hws = (const struct clk_hw *[]) {
363 &clk_12_24m_in.hw
364 },
365 .num_parents = 1,
366 },
367};
368
369/* Fix me: set value 0 will div by 2 like value 1 */
370static struct clk_regmap fclk_25m_div = {
371 .data = &(struct clk_regmap_div_data) {
372 .offset = CLK12_24_CTRL,
373 .shift = 0,
374 .width = 8,
375 },
376 .hw.init = &(struct clk_init_data) {
377 .name = "fclk_25m_div",
378 .ops = &clk_regmap_divider_ops,
379 .parent_data = &(const struct clk_parent_data) {
380 .fw_name = "fix",
381 },
382 .num_parents = 1,
383 },
384};
385
386static struct clk_regmap fclk_25m = {
387 .data = &(struct clk_regmap_gate_data) {
388 .offset = CLK12_24_CTRL,
389 .bit_idx = 12,
390 },
391 .hw.init = &(struct clk_init_data) {
392 .name = "fclk_25m",
393 .ops = &clk_regmap_gate_ops,
394 .parent_hws = (const struct clk_hw *[]) {
395 &fclk_25m_div.hw
396 },
397 .num_parents = 1,
398 .flags = CLK_SET_RATE_PARENT,
399 },
400};
401
402/*
403 * Channel 3(ddr_dpll_pt_clk) is manged by the DDR module; channel 12(cts_msr_clk)
404 * is manged by clock measures module. Their hardware are out of clock tree.
405 * Channel 4 8 9 10 11 13 14 15 16 18 are not connected.
406 */
407static u32 gen_parent_table[] = { 0, 1, 2, 5, 6, 7, 17, 19, 20, 21, 22, 23, 24};
408
409static const struct clk_parent_data gen_parent_data[] = {
410 { .fw_name = "oscin" },
411 { .hw = &rtc_clk.hw },
412 { .fw_name = "sysplldiv16" },
413 { .fw_name = "gp0" },
414 { .fw_name = "gp1" },
415 { .fw_name = "hifi" },
416 { .fw_name = "cpudiv16" },
417 { .fw_name = "fdiv2" },
418 { .fw_name = "fdiv2p5" },
419 { .fw_name = "fdiv3" },
420 { .fw_name = "fdiv4" },
421 { .fw_name = "fdiv5" },
422 { .fw_name = "fdiv7" }
423};
424
425static struct clk_regmap gen_sel = {
426 .data = &(struct clk_regmap_mux_data) {
427 .offset = GEN_CLK_CTRL,
428 .mask = 0x1f,
429 .shift = 12,
430 .table = gen_parent_table,
431 },
432 .hw.init = &(struct clk_init_data) {
433 .name = "gen_sel",
434 .ops = &clk_regmap_mux_ops,
435 .parent_data = gen_parent_data,
436 .num_parents = ARRAY_SIZE(gen_parent_data),
437 },
438};
439
440static struct clk_regmap gen_div = {
441 .data = &(struct clk_regmap_div_data) {
442 .offset = GEN_CLK_CTRL,
443 .shift = 0,
444 .width = 11,
445 },
446 .hw.init = &(struct clk_init_data) {
447 .name = "gen_div",
448 .ops = &clk_regmap_divider_ops,
449 .parent_hws = (const struct clk_hw *[]) {
450 &gen_sel.hw
451 },
452 .num_parents = 1,
453 .flags = CLK_SET_RATE_PARENT,
454 },
455};
456
457static struct clk_regmap gen = {
458 .data = &(struct clk_regmap_gate_data) {
459 .offset = GEN_CLK_CTRL,
460 .bit_idx = 11,
461 },
462 .hw.init = &(struct clk_init_data) {
463 .name = "gen",
464 .ops = &clk_regmap_gate_ops,
465 .parent_hws = (const struct clk_hw *[]) {
466 &gen_div.hw
467 },
468 .num_parents = 1,
469 .flags = CLK_SET_RATE_PARENT,
470 },
471};
472
473static const struct clk_parent_data saradc_parent_data[] = {
474 { .fw_name = "oscin" },
475 { .fw_name = "sysclk" }
476};
477
478static struct clk_regmap saradc_sel = {
479 .data = &(struct clk_regmap_mux_data) {
480 .offset = SAR_CLK_CTRL0,
481 .mask = 0x1,
482 .shift = 9,
483 },
484 .hw.init = &(struct clk_init_data) {
485 .name = "saradc_sel",
486 .ops = &clk_regmap_mux_ops,
487 .parent_data = saradc_parent_data,
488 .num_parents = ARRAY_SIZE(saradc_parent_data),
489 },
490};
491
492static struct clk_regmap saradc_div = {
493 .data = &(struct clk_regmap_div_data) {
494 .offset = SAR_CLK_CTRL0,
495 .shift = 0,
496 .width = 8,
497 },
498 .hw.init = &(struct clk_init_data) {
499 .name = "saradc_div",
500 .ops = &clk_regmap_divider_ops,
501 .parent_hws = (const struct clk_hw *[]) {
502 &saradc_sel.hw
503 },
504 .num_parents = 1,
505 .flags = CLK_SET_RATE_PARENT,
506 },
507};
508
509static struct clk_regmap saradc = {
510 .data = &(struct clk_regmap_gate_data) {
511 .offset = SAR_CLK_CTRL0,
512 .bit_idx = 8,
513 },
514 .hw.init = &(struct clk_init_data) {
515 .name = "saradc",
516 .ops = &clk_regmap_gate_ops,
517 .parent_hws = (const struct clk_hw *[]) {
518 &saradc_div.hw
519 },
520 .num_parents = 1,
521 .flags = CLK_SET_RATE_PARENT,
522 },
523};
524
525static const struct clk_parent_data pwm_parent_data[] = {
526 { .fw_name = "oscin" },
527 { .fw_name = "gp1" },
528 { .fw_name = "fdiv4" },
529 { .fw_name = "fdiv3" }
530};
531
532#define AML_PWM_CLK_MUX(_name, _reg, _shift) { \
533 .data = &(struct clk_regmap_mux_data) { \
534 .offset = _reg, \
535 .mask = 0x3, \
536 .shift = _shift, \
537 }, \
538 .hw.init = &(struct clk_init_data) { \
539 .name = #_name "_sel", \
540 .ops = &clk_regmap_mux_ops, \
541 .parent_data = pwm_parent_data, \
542 .num_parents = ARRAY_SIZE(pwm_parent_data), \
543 }, \
544}
545
546#define AML_PWM_CLK_DIV(_name, _reg, _shift) { \
547 .data = &(struct clk_regmap_div_data) { \
548 .offset = _reg, \
549 .shift = _shift, \
550 .width = 8, \
551 }, \
552 .hw.init = &(struct clk_init_data) { \
553 .name = #_name "_div", \
554 .ops = &clk_regmap_divider_ops, \
555 .parent_names = (const char *[]) { #_name "_sel" },\
556 .num_parents = 1, \
557 .flags = CLK_SET_RATE_PARENT, \
558 }, \
559}
560
561#define AML_PWM_CLK_GATE(_name, _reg, _bit) { \
562 .data = &(struct clk_regmap_gate_data) { \
563 .offset = _reg, \
564 .bit_idx = _bit, \
565 }, \
566 .hw.init = &(struct clk_init_data) { \
567 .name = #_name, \
568 .ops = &clk_regmap_gate_ops, \
569 .parent_names = (const char *[]) { #_name "_div" },\
570 .num_parents = 1, \
571 .flags = CLK_SET_RATE_PARENT, \
572 }, \
573}
574
575static struct clk_regmap pwm_a_sel =
576 AML_PWM_CLK_MUX(pwm_a, PWM_CLK_AB_CTRL, 9);
577static struct clk_regmap pwm_a_div =
578 AML_PWM_CLK_DIV(pwm_a, PWM_CLK_AB_CTRL, 0);
579static struct clk_regmap pwm_a =
580 AML_PWM_CLK_GATE(pwm_a, PWM_CLK_AB_CTRL, 8);
581
582static struct clk_regmap pwm_b_sel =
583 AML_PWM_CLK_MUX(pwm_b, PWM_CLK_AB_CTRL, 25);
584static struct clk_regmap pwm_b_div =
585 AML_PWM_CLK_DIV(pwm_b, PWM_CLK_AB_CTRL, 16);
586static struct clk_regmap pwm_b =
587 AML_PWM_CLK_GATE(pwm_b, PWM_CLK_AB_CTRL, 24);
588
589static struct clk_regmap pwm_c_sel =
590 AML_PWM_CLK_MUX(pwm_c, PWM_CLK_CD_CTRL, 9);
591static struct clk_regmap pwm_c_div =
592 AML_PWM_CLK_DIV(pwm_c, PWM_CLK_CD_CTRL, 0);
593static struct clk_regmap pwm_c =
594 AML_PWM_CLK_GATE(pwm_c, PWM_CLK_CD_CTRL, 8);
595
596static struct clk_regmap pwm_d_sel =
597 AML_PWM_CLK_MUX(pwm_d, PWM_CLK_CD_CTRL, 25);
598static struct clk_regmap pwm_d_div =
599 AML_PWM_CLK_DIV(pwm_d, PWM_CLK_CD_CTRL, 16);
600static struct clk_regmap pwm_d =
601 AML_PWM_CLK_GATE(pwm_d, PWM_CLK_CD_CTRL, 24);
602
603static struct clk_regmap pwm_e_sel =
604 AML_PWM_CLK_MUX(pwm_e, PWM_CLK_EF_CTRL, 9);
605static struct clk_regmap pwm_e_div =
606 AML_PWM_CLK_DIV(pwm_e, PWM_CLK_EF_CTRL, 0);
607static struct clk_regmap pwm_e =
608 AML_PWM_CLK_GATE(pwm_e, PWM_CLK_EF_CTRL, 8);
609
610static struct clk_regmap pwm_f_sel =
611 AML_PWM_CLK_MUX(pwm_f, PWM_CLK_EF_CTRL, 25);
612static struct clk_regmap pwm_f_div =
613 AML_PWM_CLK_DIV(pwm_f, PWM_CLK_EF_CTRL, 16);
614static struct clk_regmap pwm_f =
615 AML_PWM_CLK_GATE(pwm_f, PWM_CLK_EF_CTRL, 24);
616
617static struct clk_regmap pwm_g_sel =
618 AML_PWM_CLK_MUX(pwm_g, PWM_CLK_GH_CTRL, 9);
619static struct clk_regmap pwm_g_div =
620 AML_PWM_CLK_DIV(pwm_g, PWM_CLK_GH_CTRL, 0);
621static struct clk_regmap pwm_g =
622 AML_PWM_CLK_GATE(pwm_g, PWM_CLK_GH_CTRL, 8);
623
624static struct clk_regmap pwm_h_sel =
625 AML_PWM_CLK_MUX(pwm_h, PWM_CLK_GH_CTRL, 25);
626static struct clk_regmap pwm_h_div =
627 AML_PWM_CLK_DIV(pwm_h, PWM_CLK_GH_CTRL, 16);
628static struct clk_regmap pwm_h =
629 AML_PWM_CLK_GATE(pwm_h, PWM_CLK_GH_CTRL, 24);
630
631static struct clk_regmap pwm_i_sel =
632 AML_PWM_CLK_MUX(pwm_i, PWM_CLK_IJ_CTRL, 9);
633static struct clk_regmap pwm_i_div =
634 AML_PWM_CLK_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0);
635static struct clk_regmap pwm_i =
636 AML_PWM_CLK_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8);
637
638static struct clk_regmap pwm_j_sel =
639 AML_PWM_CLK_MUX(pwm_j, PWM_CLK_IJ_CTRL, 25);
640static struct clk_regmap pwm_j_div =
641 AML_PWM_CLK_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16);
642static struct clk_regmap pwm_j =
643 AML_PWM_CLK_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24);
644
645static struct clk_regmap pwm_k_sel =
646 AML_PWM_CLK_MUX(pwm_k, PWM_CLK_KL_CTRL, 9);
647static struct clk_regmap pwm_k_div =
648 AML_PWM_CLK_DIV(pwm_k, PWM_CLK_KL_CTRL, 0);
649static struct clk_regmap pwm_k =
650 AML_PWM_CLK_GATE(pwm_k, PWM_CLK_KL_CTRL, 8);
651
652static struct clk_regmap pwm_l_sel =
653 AML_PWM_CLK_MUX(pwm_l, PWM_CLK_KL_CTRL, 25);
654static struct clk_regmap pwm_l_div =
655 AML_PWM_CLK_DIV(pwm_l, PWM_CLK_KL_CTRL, 16);
656static struct clk_regmap pwm_l =
657 AML_PWM_CLK_GATE(pwm_l, PWM_CLK_KL_CTRL, 24);
658
659static struct clk_regmap pwm_m_sel =
660 AML_PWM_CLK_MUX(pwm_m, PWM_CLK_MN_CTRL, 9);
661static struct clk_regmap pwm_m_div =
662 AML_PWM_CLK_DIV(pwm_m, PWM_CLK_MN_CTRL, 0);
663static struct clk_regmap pwm_m =
664 AML_PWM_CLK_GATE(pwm_m, PWM_CLK_MN_CTRL, 8);
665
666static struct clk_regmap pwm_n_sel =
667 AML_PWM_CLK_MUX(pwm_n, PWM_CLK_MN_CTRL, 25);
668static struct clk_regmap pwm_n_div =
669 AML_PWM_CLK_DIV(pwm_n, PWM_CLK_MN_CTRL, 16);
670static struct clk_regmap pwm_n =
671 AML_PWM_CLK_GATE(pwm_n, PWM_CLK_MN_CTRL, 24);
672
673static const struct clk_parent_data spicc_parent_data[] = {
674 { .fw_name = "oscin" },
675 { .fw_name = "sysclk" },
676 { .fw_name = "fdiv4" },
677 { .fw_name = "fdiv3" },
678 { .fw_name = "fdiv2" },
679 { .fw_name = "fdiv5" },
680 { .fw_name = "fdiv7" },
681 { .fw_name = "gp1" }
682};
683
684static struct clk_regmap spicc_a_sel = {
685 .data = &(struct clk_regmap_mux_data) {
686 .offset = SPICC_CLK_CTRL,
687 .mask = 0x7,
688 .shift = 7,
689 },
690 .hw.init = &(struct clk_init_data) {
691 .name = "spicc_a_sel",
692 .ops = &clk_regmap_mux_ops,
693 .parent_data = spicc_parent_data,
694 .num_parents = ARRAY_SIZE(spicc_parent_data),
695 },
696};
697
698static struct clk_regmap spicc_a_div = {
699 .data = &(struct clk_regmap_div_data) {
700 .offset = SPICC_CLK_CTRL,
701 .shift = 0,
702 .width = 6,
703 },
704 .hw.init = &(struct clk_init_data) {
705 .name = "spicc_a_div",
706 .ops = &clk_regmap_divider_ops,
707 .parent_hws = (const struct clk_hw *[]) {
708 &spicc_a_sel.hw
709 },
710 .num_parents = 1,
711 .flags = CLK_SET_RATE_PARENT,
712 },
713};
714
715static struct clk_regmap spicc_a = {
716 .data = &(struct clk_regmap_gate_data) {
717 .offset = SPICC_CLK_CTRL,
718 .bit_idx = 6,
719 },
720 .hw.init = &(struct clk_init_data) {
721 .name = "spicc_a",
722 .ops = &clk_regmap_gate_ops,
723 .parent_hws = (const struct clk_hw *[]) {
724 &spicc_a_div.hw
725 },
726 .num_parents = 1,
727 .flags = CLK_SET_RATE_PARENT,
728 },
729};
730
731static struct clk_regmap spicc_b_sel = {
732 .data = &(struct clk_regmap_mux_data) {
733 .offset = SPICC_CLK_CTRL,
734 .mask = 0x7,
735 .shift = 23,
736 },
737 .hw.init = &(struct clk_init_data) {
738 .name = "spicc_b_sel",
739 .ops = &clk_regmap_mux_ops,
740 .parent_data = spicc_parent_data,
741 .num_parents = ARRAY_SIZE(spicc_parent_data),
742 },
743};
744
745static struct clk_regmap spicc_b_div = {
746 .data = &(struct clk_regmap_div_data) {
747 .offset = SPICC_CLK_CTRL,
748 .shift = 16,
749 .width = 6,
750 },
751 .hw.init = &(struct clk_init_data) {
752 .name = "spicc_b_div",
753 .ops = &clk_regmap_divider_ops,
754 .parent_hws = (const struct clk_hw *[]) {
755 &spicc_b_sel.hw
756 },
757 .num_parents = 1,
758 .flags = CLK_SET_RATE_PARENT,
759 },
760};
761
762static struct clk_regmap spicc_b = {
763 .data = &(struct clk_regmap_gate_data) {
764 .offset = SPICC_CLK_CTRL,
765 .bit_idx = 22,
766 },
767 .hw.init = &(struct clk_init_data) {
768 .name = "spicc_b",
769 .ops = &clk_regmap_gate_ops,
770 .parent_hws = (const struct clk_hw *[]) {
771 &spicc_b_div.hw
772 },
773 .num_parents = 1,
774 .flags = CLK_SET_RATE_PARENT,
775 },
776};
777
778static const struct clk_parent_data spifc_parent_data[] = {
779 { .fw_name = "gp0" },
780 { .fw_name = "fdiv2" },
781 { .fw_name = "fdiv3" },
782 { .fw_name = "fdiv2p5" },
783 { .fw_name = "hifi" },
784 { .fw_name = "fdiv4" },
785 { .fw_name = "fdiv5" },
786 { .fw_name = "fdiv7" }
787};
788
789static struct clk_regmap spifc_sel = {
790 .data = &(struct clk_regmap_mux_data) {
791 .offset = SPIFC_CLK_CTRL,
792 .mask = 0x7,
793 .shift = 9,
794 },
795 .hw.init = &(struct clk_init_data) {
796 .name = "spifc_sel",
797 .ops = &clk_regmap_mux_ops,
798 .parent_data = spifc_parent_data,
799 .num_parents = ARRAY_SIZE(spifc_parent_data),
800 },
801};
802
803static struct clk_regmap spifc_div = {
804 .data = &(struct clk_regmap_div_data) {
805 .offset = SPIFC_CLK_CTRL,
806 .shift = 0,
807 .width = 7,
808 },
809 .hw.init = &(struct clk_init_data) {
810 .name = "spifc_div",
811 .ops = &clk_regmap_divider_ops,
812 .parent_hws = (const struct clk_hw *[]) {
813 &spifc_sel.hw
814 },
815 .num_parents = 1,
816 .flags = CLK_SET_RATE_PARENT,
817 },
818};
819
820static struct clk_regmap spifc = {
821 .data = &(struct clk_regmap_gate_data) {
822 .offset = SPIFC_CLK_CTRL,
823 .bit_idx = 8,
824 },
825 .hw.init = &(struct clk_init_data) {
826 .name = "spifc",
827 .ops = &clk_regmap_gate_ops,
828 .parent_hws = (const struct clk_hw *[]) {
829 &spifc_div.hw
830 },
831 .num_parents = 1,
832 .flags = CLK_SET_RATE_PARENT,
833 },
834};
835
836static const struct clk_parent_data emmc_parent_data[] = {
837 { .fw_name = "oscin" },
838 { .fw_name = "fdiv2" },
839 { .fw_name = "fdiv3" },
840 { .fw_name = "hifi" },
841 { .fw_name = "fdiv2p5" },
842 { .fw_name = "fdiv4" },
843 { .fw_name = "gp1" },
844 { .fw_name = "gp0" }
845};
846
847static struct clk_regmap sd_emmc_a_sel = {
848 .data = &(struct clk_regmap_mux_data) {
849 .offset = SD_EMMC_CLK_CTRL,
850 .mask = 0x7,
851 .shift = 9,
852 },
853 .hw.init = &(struct clk_init_data) {
854 .name = "sd_emmc_a_sel",
855 .ops = &clk_regmap_mux_ops,
856 .parent_data = emmc_parent_data,
857 .num_parents = ARRAY_SIZE(emmc_parent_data),
858 },
859};
860
861static struct clk_regmap sd_emmc_a_div = {
862 .data = &(struct clk_regmap_div_data) {
863 .offset = SD_EMMC_CLK_CTRL,
864 .shift = 0,
865 .width = 7,
866 },
867 .hw.init = &(struct clk_init_data) {
868 .name = "sd_emmc_a_div",
869 .ops = &clk_regmap_divider_ops,
870 .parent_hws = (const struct clk_hw *[]) {
871 &sd_emmc_a_sel.hw
872 },
873 .num_parents = 1,
874 .flags = CLK_SET_RATE_PARENT,
875 },
876};
877
878static struct clk_regmap sd_emmc_a = {
879 .data = &(struct clk_regmap_gate_data) {
880 .offset = SD_EMMC_CLK_CTRL,
881 .bit_idx = 7,
882 },
883 .hw.init = &(struct clk_init_data) {
884 .name = "sd_emmc_a",
885 .ops = &clk_regmap_gate_ops,
886 .parent_hws = (const struct clk_hw *[]) {
887 &sd_emmc_a_div.hw
888 },
889 .num_parents = 1,
890 .flags = CLK_SET_RATE_PARENT,
891 },
892};
893
894static struct clk_regmap sd_emmc_b_sel = {
895 .data = &(struct clk_regmap_mux_data) {
896 .offset = SD_EMMC_CLK_CTRL,
897 .mask = 0x7,
898 .shift = 25,
899 },
900 .hw.init = &(struct clk_init_data) {
901 .name = "sd_emmc_b_sel",
902 .ops = &clk_regmap_mux_ops,
903 .parent_data = emmc_parent_data,
904 .num_parents = ARRAY_SIZE(emmc_parent_data),
905 },
906};
907
908static struct clk_regmap sd_emmc_b_div = {
909 .data = &(struct clk_regmap_div_data) {
910 .offset = SD_EMMC_CLK_CTRL,
911 .shift = 16,
912 .width = 7,
913 },
914 .hw.init = &(struct clk_init_data) {
915 .name = "sd_emmc_b_div",
916 .ops = &clk_regmap_divider_ops,
917 .parent_hws = (const struct clk_hw *[]) {
918 &sd_emmc_b_sel.hw
919 },
920 .num_parents = 1,
921 .flags = CLK_SET_RATE_PARENT,
922 },
923};
924
925static struct clk_regmap sd_emmc_b = {
926 .data = &(struct clk_regmap_gate_data) {
927 .offset = SD_EMMC_CLK_CTRL,
928 .bit_idx = 23,
929 },
930 .hw.init = &(struct clk_init_data) {
931 .name = "sd_emmc_b",
932 .ops = &clk_regmap_gate_ops,
933 .parent_hws = (const struct clk_hw *[]) {
934 &sd_emmc_b_div.hw
935 },
936 .num_parents = 1,
937 .flags = CLK_SET_RATE_PARENT,
938 },
939};
940
941static struct clk_regmap sd_emmc_c_sel = {
942 .data = &(struct clk_regmap_mux_data) {
943 .offset = NAND_CLK_CTRL,
944 .mask = 0x7,
945 .shift = 9,
946 },
947 .hw.init = &(struct clk_init_data) {
948 .name = "sd_emmc_c_sel",
949 .ops = &clk_regmap_mux_ops,
950 .parent_data = emmc_parent_data,
951 .num_parents = ARRAY_SIZE(emmc_parent_data),
952 },
953};
954
955static struct clk_regmap sd_emmc_c_div = {
956 .data = &(struct clk_regmap_div_data) {
957 .offset = NAND_CLK_CTRL,
958 .shift = 0,
959 .width = 7,
960 },
961 .hw.init = &(struct clk_init_data) {
962 .name = "sd_emmc_c_div",
963 .ops = &clk_regmap_divider_ops,
964 .parent_hws = (const struct clk_hw *[]) {
965 &sd_emmc_c_sel.hw
966 },
967 .num_parents = 1,
968 .flags = CLK_SET_RATE_PARENT,
969 },
970};
971
972static struct clk_regmap sd_emmc_c = {
973 .data = &(struct clk_regmap_gate_data) {
974 .offset = NAND_CLK_CTRL,
975 .bit_idx = 7,
976 },
977 .hw.init = &(struct clk_init_data) {
978 .name = "sd_emmc_c",
979 .ops = &clk_regmap_gate_ops,
980 .parent_hws = (const struct clk_hw *[]) {
981 &sd_emmc_c_div.hw
982 },
983 .num_parents = 1,
984 .flags = CLK_SET_RATE_PARENT,
985 },
986};
987
988static struct clk_regmap ts_div = {
989 .data = &(struct clk_regmap_div_data) {
990 .offset = TS_CLK_CTRL,
991 .shift = 0,
992 .width = 8,
993 },
994 .hw.init = &(struct clk_init_data) {
995 .name = "ts_div",
996 .ops = &clk_regmap_divider_ops,
997 .parent_data = &(const struct clk_parent_data) {
998 .fw_name = "oscin",
999 },
1000 .num_parents = 1,
1001 },
1002};
1003
1004static struct clk_regmap ts = {
1005 .data = &(struct clk_regmap_gate_data) {
1006 .offset = TS_CLK_CTRL,
1007 .bit_idx = 8,
1008 },
1009 .hw.init = &(struct clk_init_data) {
1010 .name = "ts",
1011 .ops = &clk_regmap_gate_ops,
1012 .parent_hws = (const struct clk_hw *[]) {
1013 &ts_div.hw
1014 },
1015 .num_parents = 1,
1016 .flags = CLK_SET_RATE_PARENT,
1017 },
1018};
1019
1020static const struct clk_parent_data eth_parent = {
1021 .fw_name = "fdiv2",
1022};
1023
1024static struct clk_fixed_factor eth_125m_div = {
1025 .mult = 1,
1026 .div = 8,
1027 .hw.init = &(struct clk_init_data) {
1028 .name = "eth_125m_div",
1029 .ops = &clk_fixed_factor_ops,
1030 .parent_data = ð_parent,
1031 .num_parents = 1,
1032 },
1033};
1034
1035static struct clk_regmap eth_125m = {
1036 .data = &(struct clk_regmap_gate_data) {
1037 .offset = ETH_CLK_CTRL,
1038 .bit_idx = 7,
1039 },
1040 .hw.init = &(struct clk_init_data) {
1041 .name = "eth_125m",
1042 .ops = &clk_regmap_gate_ops,
1043 .parent_hws = (const struct clk_hw *[]) {
1044 ð_125m_div.hw
1045 },
1046 .num_parents = 1,
1047 .flags = CLK_SET_RATE_PARENT,
1048 },
1049};
1050
1051static struct clk_regmap eth_rmii_div = {
1052 .data = &(struct clk_regmap_div_data) {
1053 .offset = ETH_CLK_CTRL,
1054 .shift = 0,
1055 .width = 7,
1056 },
1057 .hw.init = &(struct clk_init_data) {
1058 .name = "eth_rmii_div",
1059 .ops = &clk_regmap_divider_ops,
1060 .parent_data = ð_parent,
1061 .num_parents = 1,
1062 },
1063};
1064
1065static struct clk_regmap eth_rmii = {
1066 .data = &(struct clk_regmap_gate_data) {
1067 .offset = ETH_CLK_CTRL,
1068 .bit_idx = 8,
1069 },
1070 .hw.init = &(struct clk_init_data) {
1071 .name = "eth_rmii",
1072 .ops = &clk_regmap_gate_ops,
1073 .parent_hws = (const struct clk_hw *[]) {
1074 ð_rmii_div.hw
1075 },
1076 .num_parents = 1,
1077 .flags = CLK_SET_RATE_PARENT,
1078 },
1079};
1080
1081static const struct clk_parent_data mipi_dsi_meas_parent_data[] = {
1082 { .fw_name = "oscin" },
1083 { .fw_name = "fdiv4" },
1084 { .fw_name = "fdiv3" },
1085 { .fw_name = "fdiv5" },
1086 { .fw_name = "gp1" },
1087 { .fw_name = "gp0" },
1088 { .fw_name = "fdiv2" },
1089 { .fw_name = "fdiv7" }
1090};
1091
1092static struct clk_regmap mipi_dsi_meas_sel = {
1093 .data = &(struct clk_regmap_mux_data) {
1094 .offset = VDIN_MEAS_CLK_CTRL,
1095 .mask = 0x7,
1096 .shift = 21,
1097 },
1098 .hw.init = &(struct clk_init_data) {
1099 .name = "mipi_dsi_meas_sel",
1100 .ops = &clk_regmap_mux_ops,
1101 .parent_data = mipi_dsi_meas_parent_data,
1102 .num_parents = ARRAY_SIZE(mipi_dsi_meas_parent_data),
1103 },
1104};
1105
1106static struct clk_regmap mipi_dsi_meas_div = {
1107 .data = &(struct clk_regmap_div_data) {
1108 .offset = VDIN_MEAS_CLK_CTRL,
1109 .shift = 12,
1110 .width = 7,
1111 },
1112 .hw.init = &(struct clk_init_data) {
1113 .name = "mipi_dsi_meas_div",
1114 .ops = &clk_regmap_divider_ops,
1115 .parent_hws = (const struct clk_hw *[]) {
1116 &mipi_dsi_meas_sel.hw
1117 },
1118 .num_parents = 1,
1119 .flags = CLK_SET_RATE_PARENT,
1120 },
1121};
1122
1123static struct clk_regmap mipi_dsi_meas = {
1124 .data = &(struct clk_regmap_gate_data) {
1125 .offset = VDIN_MEAS_CLK_CTRL,
1126 .bit_idx = 20,
1127 },
1128 .hw.init = &(struct clk_init_data) {
1129 .name = "mipi_dsi_meas",
1130 .ops = &clk_regmap_gate_ops,
1131 .parent_hws = (const struct clk_hw *[]) {
1132 &mipi_dsi_meas_div.hw
1133 },
1134 .num_parents = 1,
1135 .flags = CLK_SET_RATE_PARENT,
1136 },
1137};
1138
1139static const struct clk_parent_data dsi_phy_parent_data[] = {
1140 { .fw_name = "gp1" },
1141 { .fw_name = "gp0" },
1142 { .fw_name = "hifi" },
1143 { .fw_name = "fdiv3" },
1144 { .fw_name = "fdiv2" },
1145 { .fw_name = "fdiv2p5" },
1146 { .fw_name = "fdiv4" },
1147 { .fw_name = "fdiv7" }
1148};
1149
1150static struct clk_regmap dsi_phy_sel = {
1151 .data = &(struct clk_regmap_mux_data) {
1152 .offset = MIPIDSI_PHY_CLK_CTRL,
1153 .mask = 0x7,
1154 .shift = 12,
1155 },
1156 .hw.init = &(struct clk_init_data) {
1157 .name = "dsi_phy_sel",
1158 .ops = &clk_regmap_mux_ops,
1159 .parent_data = dsi_phy_parent_data,
1160 .num_parents = ARRAY_SIZE(dsi_phy_parent_data),
1161 },
1162};
1163
1164static struct clk_regmap dsi_phy_div = {
1165 .data = &(struct clk_regmap_div_data) {
1166 .offset = MIPIDSI_PHY_CLK_CTRL,
1167 .shift = 0,
1168 .width = 7,
1169 },
1170 .hw.init = &(struct clk_init_data) {
1171 .name = "dsi_phy_div",
1172 .ops = &clk_regmap_divider_ops,
1173 .parent_hws = (const struct clk_hw *[]) {
1174 &dsi_phy_sel.hw
1175 },
1176 .num_parents = 1,
1177 .flags = CLK_SET_RATE_PARENT,
1178 },
1179};
1180
1181static struct clk_regmap dsi_phy = {
1182 .data = &(struct clk_regmap_gate_data) {
1183 .offset = MIPIDSI_PHY_CLK_CTRL,
1184 .bit_idx = 8,
1185 },
1186 .hw.init = &(struct clk_init_data) {
1187 .name = "dsi_phy",
1188 .ops = &clk_regmap_gate_ops,
1189 .parent_hws = (const struct clk_hw *[]) {
1190 &dsi_phy_div.hw
1191 },
1192 .num_parents = 1,
1193 .flags = CLK_SET_RATE_PARENT,
1194 },
1195};
1196
1197static const struct clk_parent_data vout_mclk_parent_data[] = {
1198 { .fw_name = "fdiv2p5" },
1199 { .fw_name = "fdiv3" },
1200 { .fw_name = "fdiv4" },
1201 { .fw_name = "fdiv5" },
1202 { .fw_name = "gp0" },
1203 { .fw_name = "hifi" },
1204 { .fw_name = "gp1" },
1205 { .fw_name = "fdiv7" }
1206};
1207
1208static struct clk_regmap vout_mclk_sel = {
1209 .data = &(struct clk_regmap_mux_data) {
1210 .offset = VOUTENC_CLK_CTRL,
1211 .mask = 0x7,
1212 .shift = 9,
1213 },
1214 .hw.init = &(struct clk_init_data) {
1215 .name = "vout_mclk_sel",
1216 .ops = &clk_regmap_mux_ops,
1217 .parent_data = vout_mclk_parent_data,
1218 .num_parents = ARRAY_SIZE(vout_mclk_parent_data),
1219 },
1220};
1221
1222static struct clk_regmap vout_mclk_div = {
1223 .data = &(struct clk_regmap_div_data) {
1224 .offset = VOUTENC_CLK_CTRL,
1225 .shift = 0,
1226 .width = 7,
1227 },
1228 .hw.init = &(struct clk_init_data) {
1229 .name = "vout_mclk_div",
1230 .ops = &clk_regmap_divider_ops,
1231 .parent_hws = (const struct clk_hw *[]) {
1232 &vout_mclk_sel.hw
1233 },
1234 .num_parents = 1,
1235 .flags = CLK_SET_RATE_PARENT,
1236 },
1237};
1238
1239static struct clk_regmap vout_mclk = {
1240 .data = &(struct clk_regmap_gate_data) {
1241 .offset = VOUTENC_CLK_CTRL,
1242 .bit_idx = 8,
1243 },
1244 .hw.init = &(struct clk_init_data) {
1245 .name = "vout_mclk",
1246 .ops = &clk_regmap_gate_ops,
1247 .parent_hws = (const struct clk_hw *[]) {
1248 &vout_mclk_div.hw
1249 },
1250 .num_parents = 1,
1251 .flags = CLK_SET_RATE_PARENT,
1252 },
1253};
1254
1255static const struct clk_parent_data vout_enc_parent_data[] = {
1256 { .fw_name = "gp1" },
1257 { .fw_name = "fdiv3" },
1258 { .fw_name = "fdiv4" },
1259 { .fw_name = "fdiv5" },
1260 { .fw_name = "gp0" },
1261 { .fw_name = "hifi" },
1262 { .fw_name = "fdiv2p5" },
1263 { .fw_name = "fdiv7" }
1264};
1265
1266static struct clk_regmap vout_enc_sel = {
1267 .data = &(struct clk_regmap_mux_data) {
1268 .offset = VOUTENC_CLK_CTRL,
1269 .mask = 0x7,
1270 .shift = 25,
1271 },
1272 .hw.init = &(struct clk_init_data) {
1273 .name = "vout_enc_sel",
1274 .ops = &clk_regmap_mux_ops,
1275 .parent_data = vout_enc_parent_data,
1276 .num_parents = ARRAY_SIZE(vout_enc_parent_data),
1277 },
1278};
1279
1280static struct clk_regmap vout_enc_div = {
1281 .data = &(struct clk_regmap_div_data) {
1282 .offset = VOUTENC_CLK_CTRL,
1283 .shift = 16,
1284 .width = 7,
1285 },
1286 .hw.init = &(struct clk_init_data) {
1287 .name = "vout_enc_div",
1288 .ops = &clk_regmap_divider_ops,
1289 .parent_hws = (const struct clk_hw *[]) {
1290 &vout_enc_sel.hw
1291 },
1292 .num_parents = 1,
1293 .flags = CLK_SET_RATE_PARENT,
1294 },
1295};
1296
1297static struct clk_regmap vout_enc = {
1298 .data = &(struct clk_regmap_gate_data) {
1299 .offset = VOUTENC_CLK_CTRL,
1300 .bit_idx = 24,
1301 },
1302 .hw.init = &(struct clk_init_data) {
1303 .name = "vout_enc",
1304 .ops = &clk_regmap_gate_ops,
1305 .parent_hws = (const struct clk_hw *[]) {
1306 &vout_enc_div.hw
1307 },
1308 .num_parents = 1,
1309 .flags = CLK_SET_RATE_PARENT,
1310 },
1311};
1312
1313static const struct clk_parent_data hcodec_pre_parent_data[] = {
1314 { .fw_name = "fdiv2p5" },
1315 { .fw_name = "fdiv3" },
1316 { .fw_name = "fdiv4" },
1317 { .fw_name = "fdiv5" },
1318 { .fw_name = "fdiv7" },
1319 { .fw_name = "hifi" },
1320 { .fw_name = "gp0" },
1321 { .fw_name = "oscin" }
1322};
1323
1324static struct clk_regmap hcodec_0_sel = {
1325 .data = &(struct clk_regmap_mux_data) {
1326 .offset = VDEC_CLK_CTRL,
1327 .mask = 0x7,
1328 .shift = 9,
1329 },
1330 .hw.init = &(struct clk_init_data) {
1331 .name = "hcodec_0_sel",
1332 .ops = &clk_regmap_mux_ops,
1333 .parent_data = hcodec_pre_parent_data,
1334 .num_parents = ARRAY_SIZE(hcodec_pre_parent_data),
1335 },
1336};
1337
1338static struct clk_regmap hcodec_0_div = {
1339 .data = &(struct clk_regmap_div_data) {
1340 .offset = VDEC_CLK_CTRL,
1341 .shift = 0,
1342 .width = 7,
1343 },
1344 .hw.init = &(struct clk_init_data) {
1345 .name = "hcodec_0_div",
1346 .ops = &clk_regmap_divider_ops,
1347 .parent_hws = (const struct clk_hw *[]) {
1348 &hcodec_0_sel.hw
1349 },
1350 .num_parents = 1,
1351 .flags = CLK_SET_RATE_PARENT,
1352 },
1353};
1354
1355static struct clk_regmap hcodec_0 = {
1356 .data = &(struct clk_regmap_gate_data) {
1357 .offset = VDEC_CLK_CTRL,
1358 .bit_idx = 8,
1359 },
1360 .hw.init = &(struct clk_init_data) {
1361 .name = "hcodec_0",
1362 .ops = &clk_regmap_gate_ops,
1363 .parent_hws = (const struct clk_hw *[]) {
1364 &hcodec_0_div.hw
1365 },
1366 .num_parents = 1,
1367 .flags = CLK_SET_RATE_PARENT,
1368 },
1369};
1370
1371static struct clk_regmap hcodec_1_sel = {
1372 .data = &(struct clk_regmap_mux_data) {
1373 .offset = VDEC3_CLK_CTRL,
1374 .mask = 0x7,
1375 .shift = 9,
1376 },
1377 .hw.init = &(struct clk_init_data) {
1378 .name = "hcodec_1_sel",
1379 .ops = &clk_regmap_mux_ops,
1380 .parent_data = hcodec_pre_parent_data,
1381 .num_parents = ARRAY_SIZE(hcodec_pre_parent_data),
1382 },
1383};
1384
1385static struct clk_regmap hcodec_1_div = {
1386 .data = &(struct clk_regmap_div_data) {
1387 .offset = VDEC3_CLK_CTRL,
1388 .shift = 0,
1389 .width = 7,
1390 },
1391 .hw.init = &(struct clk_init_data) {
1392 .name = "hcodec_1_div",
1393 .ops = &clk_regmap_divider_ops,
1394 .parent_hws = (const struct clk_hw *[]) {
1395 &hcodec_1_sel.hw
1396 },
1397 .num_parents = 1,
1398 .flags = CLK_SET_RATE_PARENT,
1399 },
1400};
1401
1402static struct clk_regmap hcodec_1 = {
1403 .data = &(struct clk_regmap_gate_data) {
1404 .offset = VDEC3_CLK_CTRL,
1405 .bit_idx = 8,
1406 },
1407 .hw.init = &(struct clk_init_data) {
1408 .name = "hcodec_1",
1409 .ops = &clk_regmap_gate_ops,
1410 .parent_hws = (const struct clk_hw *[]) {
1411 &hcodec_1_div.hw
1412 },
1413 .num_parents = 1,
1414 .flags = CLK_SET_RATE_PARENT,
1415 },
1416};
1417
1418static const struct clk_parent_data hcodec_parent_data[] = {
1419 { .hw = &hcodec_0.hw },
1420 { .hw = &hcodec_1.hw }
1421};
1422
1423static struct clk_regmap hcodec = {
1424 .data = &(struct clk_regmap_mux_data) {
1425 .offset = VDEC3_CLK_CTRL,
1426 .mask = 0x1,
1427 .shift = 15,
1428 },
1429 .hw.init = &(struct clk_init_data) {
1430 .name = "hcodec",
1431 .ops = &clk_regmap_mux_ops,
1432 .parent_data = hcodec_parent_data,
1433 .num_parents = ARRAY_SIZE(hcodec_parent_data),
1434 .flags = CLK_SET_RATE_PARENT,
1435 },
1436};
1437
1438static const struct clk_parent_data vc9000e_parent_data[] = {
1439 { .fw_name = "oscin" },
1440 { .fw_name = "fdiv4" },
1441 { .fw_name = "fdiv3" },
1442 { .fw_name = "fdiv5" },
1443 { .fw_name = "fdiv7" },
1444 { .fw_name = "fdiv2p5" },
1445 { .fw_name = "hifi" },
1446 { .fw_name = "gp0" }
1447};
1448
1449static struct clk_regmap vc9000e_aclk_sel = {
1450 .data = &(struct clk_regmap_mux_data) {
1451 .offset = VC9000E_CLK_CTRL,
1452 .mask = 0x7,
1453 .shift = 9,
1454 },
1455 .hw.init = &(struct clk_init_data) {
1456 .name = "vc9000e_aclk_sel",
1457 .ops = &clk_regmap_mux_ops,
1458 .parent_data = vc9000e_parent_data,
1459 .num_parents = ARRAY_SIZE(vc9000e_parent_data),
1460 },
1461};
1462
1463static struct clk_regmap vc9000e_aclk_div = {
1464 .data = &(struct clk_regmap_div_data) {
1465 .offset = VC9000E_CLK_CTRL,
1466 .shift = 0,
1467 .width = 7,
1468 },
1469 .hw.init = &(struct clk_init_data) {
1470 .name = "vc9000e_aclk_div",
1471 .ops = &clk_regmap_divider_ops,
1472 .parent_hws = (const struct clk_hw *[]) {
1473 &vc9000e_aclk_sel.hw
1474 },
1475 .num_parents = 1,
1476 .flags = CLK_SET_RATE_PARENT,
1477 },
1478};
1479
1480static struct clk_regmap vc9000e_aclk = {
1481 .data = &(struct clk_regmap_gate_data) {
1482 .offset = VC9000E_CLK_CTRL,
1483 .bit_idx = 8,
1484 },
1485 .hw.init = &(struct clk_init_data) {
1486 .name = "vc9000e_aclk",
1487 .ops = &clk_regmap_gate_ops,
1488 .parent_hws = (const struct clk_hw *[]) {
1489 &vc9000e_aclk_div.hw
1490 },
1491 .num_parents = 1,
1492 .flags = CLK_SET_RATE_PARENT,
1493 },
1494};
1495
1496static struct clk_regmap vc9000e_core_sel = {
1497 .data = &(struct clk_regmap_mux_data) {
1498 .offset = VC9000E_CLK_CTRL,
1499 .mask = 0x7,
1500 .shift = 25,
1501 },
1502 .hw.init = &(struct clk_init_data) {
1503 .name = "vc9000e_core_sel",
1504 .ops = &clk_regmap_mux_ops,
1505 .parent_data = vc9000e_parent_data,
1506 .num_parents = ARRAY_SIZE(vc9000e_parent_data),
1507 },
1508};
1509
1510static struct clk_regmap vc9000e_core_div = {
1511 .data = &(struct clk_regmap_div_data) {
1512 .offset = VC9000E_CLK_CTRL,
1513 .shift = 16,
1514 .width = 7,
1515 },
1516 .hw.init = &(struct clk_init_data) {
1517 .name = "vc9000e_core_div",
1518 .ops = &clk_regmap_divider_ops,
1519 .parent_hws = (const struct clk_hw *[]) {
1520 &vc9000e_core_sel.hw
1521 },
1522 .num_parents = 1,
1523 .flags = CLK_SET_RATE_PARENT,
1524 },
1525};
1526
1527static struct clk_regmap vc9000e_core = {
1528 .data = &(struct clk_regmap_gate_data) {
1529 .offset = VC9000E_CLK_CTRL,
1530 .bit_idx = 24,
1531 },
1532 .hw.init = &(struct clk_init_data) {
1533 .name = "vc9000e_core",
1534 .ops = &clk_regmap_gate_ops,
1535 .parent_hws = (const struct clk_hw *[]) {
1536 &vc9000e_core_div.hw
1537 },
1538 .num_parents = 1,
1539 .flags = CLK_SET_RATE_PARENT,
1540 },
1541};
1542
1543static const struct clk_parent_data csi_phy_parent_data[] = {
1544 { .fw_name = "fdiv2p5" },
1545 { .fw_name = "fdiv3" },
1546 { .fw_name = "fdiv4" },
1547 { .fw_name = "fdiv5" },
1548 { .fw_name = "gp0" },
1549 { .fw_name = "hifi" },
1550 { .fw_name = "gp1" },
1551 { .fw_name = "oscin" }
1552};
1553
1554static struct clk_regmap csi_phy0_sel = {
1555 .data = &(struct clk_regmap_mux_data) {
1556 .offset = ISP0_CLK_CTRL,
1557 .mask = 0x7,
1558 .shift = 25,
1559 },
1560 .hw.init = &(struct clk_init_data) {
1561 .name = "csi_phy0_sel",
1562 .ops = &clk_regmap_mux_ops,
1563 .parent_data = csi_phy_parent_data,
1564 .num_parents = ARRAY_SIZE(csi_phy_parent_data),
1565 },
1566};
1567
1568static struct clk_regmap csi_phy0_div = {
1569 .data = &(struct clk_regmap_div_data) {
1570 .offset = ISP0_CLK_CTRL,
1571 .shift = 16,
1572 .width = 7,
1573 },
1574 .hw.init = &(struct clk_init_data) {
1575 .name = "csi_phy0_div",
1576 .ops = &clk_regmap_divider_ops,
1577 .parent_hws = (const struct clk_hw *[]) {
1578 &csi_phy0_sel.hw
1579 },
1580 .num_parents = 1,
1581 .flags = CLK_SET_RATE_PARENT,
1582 },
1583};
1584
1585static struct clk_regmap csi_phy0 = {
1586 .data = &(struct clk_regmap_gate_data) {
1587 .offset = ISP0_CLK_CTRL,
1588 .bit_idx = 24,
1589 },
1590 .hw.init = &(struct clk_init_data) {
1591 .name = "csi_phy0",
1592 .ops = &clk_regmap_gate_ops,
1593 .parent_hws = (const struct clk_hw *[]) {
1594 &csi_phy0_div.hw
1595 },
1596 .num_parents = 1,
1597 .flags = CLK_SET_RATE_PARENT,
1598 },
1599};
1600
1601static const struct clk_parent_data dewarpa_parent_data[] = {
1602 { .fw_name = "fdiv2p5" },
1603 { .fw_name = "fdiv3" },
1604 { .fw_name = "fdiv4" },
1605 { .fw_name = "fdiv5" },
1606 { .fw_name = "gp0" },
1607 { .fw_name = "hifi" },
1608 { .fw_name = "gp1" },
1609 { .fw_name = "fdiv7" }
1610};
1611
1612static struct clk_regmap dewarpa_sel = {
1613 .data = &(struct clk_regmap_mux_data) {
1614 .offset = DEWARPA_CLK_CTRL,
1615 .mask = 0x7,
1616 .shift = 9,
1617 },
1618 .hw.init = &(struct clk_init_data) {
1619 .name = "dewarpa_sel",
1620 .ops = &clk_regmap_mux_ops,
1621 .parent_data = dewarpa_parent_data,
1622 .num_parents = ARRAY_SIZE(dewarpa_parent_data),
1623 },
1624};
1625
1626static struct clk_regmap dewarpa_div = {
1627 .data = &(struct clk_regmap_div_data) {
1628 .offset = DEWARPA_CLK_CTRL,
1629 .shift = 0,
1630 .width = 7,
1631 },
1632 .hw.init = &(struct clk_init_data) {
1633 .name = "dewarpa_div",
1634 .ops = &clk_regmap_divider_ops,
1635 .parent_hws = (const struct clk_hw *[]) {
1636 &dewarpa_sel.hw
1637 },
1638 .num_parents = 1,
1639 .flags = CLK_SET_RATE_PARENT,
1640 },
1641};
1642
1643static struct clk_regmap dewarpa = {
1644 .data = &(struct clk_regmap_gate_data) {
1645 .offset = DEWARPA_CLK_CTRL,
1646 .bit_idx = 8,
1647 },
1648 .hw.init = &(struct clk_init_data) {
1649 .name = "dewarpa",
1650 .ops = &clk_regmap_gate_ops,
1651 .parent_hws = (const struct clk_hw *[]) {
1652 &dewarpa_div.hw
1653 },
1654 .num_parents = 1,
1655 .flags = CLK_SET_RATE_PARENT,
1656 },
1657};
1658
1659static const struct clk_parent_data isp_parent_data[] = {
1660 { .fw_name = "fdiv2p5" },
1661 { .fw_name = "fdiv3" },
1662 { .fw_name = "fdiv4" },
1663 { .fw_name = "fdiv5" },
1664 { .fw_name = "gp0" },
1665 { .fw_name = "hifi" },
1666 { .fw_name = "gp1" },
1667 { .fw_name = "oscin" }
1668};
1669
1670static struct clk_regmap isp0_sel = {
1671 .data = &(struct clk_regmap_mux_data) {
1672 .offset = ISP0_CLK_CTRL,
1673 .mask = 0x7,
1674 .shift = 9,
1675 },
1676 .hw.init = &(struct clk_init_data) {
1677 .name = "isp0_sel",
1678 .ops = &clk_regmap_mux_ops,
1679 .parent_data = isp_parent_data,
1680 .num_parents = ARRAY_SIZE(isp_parent_data),
1681 },
1682};
1683
1684static struct clk_regmap isp0_div = {
1685 .data = &(struct clk_regmap_div_data) {
1686 .offset = ISP0_CLK_CTRL,
1687 .shift = 0,
1688 .width = 7,
1689 },
1690 .hw.init = &(struct clk_init_data) {
1691 .name = "isp0_div",
1692 .ops = &clk_regmap_divider_ops,
1693 .parent_hws = (const struct clk_hw *[]) {
1694 &isp0_sel.hw
1695 },
1696 .num_parents = 1,
1697 .flags = CLK_SET_RATE_PARENT,
1698 },
1699};
1700
1701static struct clk_regmap isp0 = {
1702 .data = &(struct clk_regmap_gate_data) {
1703 .offset = ISP0_CLK_CTRL,
1704 .bit_idx = 8,
1705 },
1706 .hw.init = &(struct clk_init_data) {
1707 .name = "isp0",
1708 .ops = &clk_regmap_gate_ops,
1709 .parent_hws = (const struct clk_hw *[]) {
1710 &isp0_div.hw
1711 },
1712 .num_parents = 1,
1713 .flags = CLK_SET_RATE_PARENT,
1714 },
1715};
1716
1717static const struct clk_parent_data nna_core_parent_data[] = {
1718 { .fw_name = "oscin" },
1719 { .fw_name = "fdiv2p5" },
1720 { .fw_name = "fdiv4" },
1721 { .fw_name = "fdiv3" },
1722 { .fw_name = "fdiv5" },
1723 { .fw_name = "fdiv2" },
1724 { .fw_name = "gp1" },
1725 { .fw_name = "hifi" }
1726};
1727
1728static struct clk_regmap nna_core_sel = {
1729 .data = &(struct clk_regmap_mux_data) {
1730 .offset = NNA_CLK_CTRL,
1731 .mask = 0x7,
1732 .shift = 9,
1733 },
1734 .hw.init = &(struct clk_init_data) {
1735 .name = "nna_core_sel",
1736 .ops = &clk_regmap_mux_ops,
1737 .parent_data = nna_core_parent_data,
1738 .num_parents = ARRAY_SIZE(nna_core_parent_data),
1739 },
1740};
1741
1742static struct clk_regmap nna_core_div = {
1743 .data = &(struct clk_regmap_div_data) {
1744 .offset = NNA_CLK_CTRL,
1745 .shift = 0,
1746 .width = 7,
1747 },
1748 .hw.init = &(struct clk_init_data) {
1749 .name = "nna_core_div",
1750 .ops = &clk_regmap_divider_ops,
1751 .parent_hws = (const struct clk_hw *[]) {
1752 &nna_core_sel.hw
1753 },
1754 .num_parents = 1,
1755 .flags = CLK_SET_RATE_PARENT,
1756 },
1757};
1758
1759static struct clk_regmap nna_core = {
1760 .data = &(struct clk_regmap_gate_data) {
1761 .offset = NNA_CLK_CTRL,
1762 .bit_idx = 8,
1763 },
1764 .hw.init = &(struct clk_init_data) {
1765 .name = "nna_core",
1766 .ops = &clk_regmap_gate_ops,
1767 .parent_hws = (const struct clk_hw *[]) {
1768 &nna_core_div.hw
1769 },
1770 .num_parents = 1,
1771 .flags = CLK_SET_RATE_PARENT,
1772 },
1773};
1774
1775static const struct clk_parent_data ge2d_parent_data[] = {
1776 { .fw_name = "oscin" },
1777 { .fw_name = "fdiv2p5" },
1778 { .fw_name = "fdiv3" },
1779 { .fw_name = "fdiv4" },
1780 { .fw_name = "hifi" },
1781 { .fw_name = "fdiv5" },
1782 { .fw_name = "gp0" },
1783 { .hw = &rtc_clk.hw }
1784};
1785
1786static struct clk_regmap ge2d_sel = {
1787 .data = &(struct clk_regmap_mux_data) {
1788 .offset = GE2D_CLK_CTRL,
1789 .mask = 0x7,
1790 .shift = 9,
1791 },
1792 .hw.init = &(struct clk_init_data) {
1793 .name = "ge2d_sel",
1794 .ops = &clk_regmap_mux_ops,
1795 .parent_data = ge2d_parent_data,
1796 .num_parents = ARRAY_SIZE(ge2d_parent_data),
1797 },
1798};
1799
1800static struct clk_regmap ge2d_div = {
1801 .data = &(struct clk_regmap_div_data) {
1802 .offset = GE2D_CLK_CTRL,
1803 .shift = 0,
1804 .width = 7,
1805 },
1806 .hw.init = &(struct clk_init_data) {
1807 .name = "ge2d_div",
1808 .ops = &clk_regmap_divider_ops,
1809 .parent_hws = (const struct clk_hw *[]) {
1810 &ge2d_sel.hw
1811 },
1812 .num_parents = 1,
1813 .flags = CLK_SET_RATE_PARENT,
1814 },
1815};
1816
1817static struct clk_regmap ge2d = {
1818 .data = &(struct clk_regmap_gate_data) {
1819 .offset = GE2D_CLK_CTRL,
1820 .bit_idx = 8,
1821 },
1822 .hw.init = &(struct clk_init_data) {
1823 .name = "ge2d",
1824 .ops = &clk_regmap_gate_ops,
1825 .parent_hws = (const struct clk_hw *[]) {
1826 &ge2d_div.hw
1827 },
1828 .num_parents = 1,
1829 .flags = CLK_SET_RATE_PARENT,
1830 },
1831};
1832
1833static const struct clk_parent_data vapb_parent_data[] = {
1834 { .fw_name = "fdiv2p5" },
1835 { .fw_name = "fdiv3" },
1836 { .fw_name = "fdiv4" },
1837 { .fw_name = "fdiv5" },
1838 { .fw_name = "gp0" },
1839 { .fw_name = "hifi" },
1840 { .fw_name = "gp1" },
1841 { .fw_name = "oscin" },
1842};
1843
1844static struct clk_regmap vapb_sel = {
1845 .data = &(struct clk_regmap_mux_data) {
1846 .offset = VAPB_CLK_CTRL,
1847 .mask = 0x7,
1848 .shift = 9,
1849 },
1850 .hw.init = &(struct clk_init_data) {
1851 .name = "vapb_sel",
1852 .ops = &clk_regmap_mux_ops,
1853 .parent_data = vapb_parent_data,
1854 .num_parents = ARRAY_SIZE(vapb_parent_data),
1855 },
1856};
1857
1858static struct clk_regmap vapb_div = {
1859 .data = &(struct clk_regmap_div_data) {
1860 .offset = VAPB_CLK_CTRL,
1861 .shift = 0,
1862 .width = 7,
1863 },
1864 .hw.init = &(struct clk_init_data) {
1865 .name = "vapb_div",
1866 .ops = &clk_regmap_divider_ops,
1867 .parent_hws = (const struct clk_hw *[]) {
1868 &vapb_sel.hw
1869 },
1870 .num_parents = 1,
1871 .flags = CLK_SET_RATE_PARENT,
1872 },
1873};
1874
1875static struct clk_regmap vapb = {
1876 .data = &(struct clk_regmap_gate_data) {
1877 .offset = VAPB_CLK_CTRL,
1878 .bit_idx = 8,
1879 },
1880 .hw.init = &(struct clk_init_data) {
1881 .name = "vapb",
1882 .ops = &clk_regmap_gate_ops,
1883 .parent_hws = (const struct clk_hw *[]) {
1884 &vapb_div.hw
1885 },
1886 .num_parents = 1,
1887 .flags = CLK_SET_RATE_PARENT,
1888 },
1889};
1890
1891static struct clk_hw *c3_periphs_hw_clks[] = {
1892 [CLKID_RTC_XTAL_CLKIN] = &rtc_xtal_clkin.hw,
1893 [CLKID_RTC_32K_DIV] = &rtc_32k_div.hw,
1894 [CLKID_RTC_32K_MUX] = &rtc_32k_mux.hw,
1895 [CLKID_RTC_32K] = &rtc_32k.hw,
1896 [CLKID_RTC_CLK] = &rtc_clk.hw,
1897 [CLKID_SYS_RESET_CTRL] = &sys_reset_ctrl.hw,
1898 [CLKID_SYS_PWR_CTRL] = &sys_pwr_ctrl.hw,
1899 [CLKID_SYS_PAD_CTRL] = &sys_pad_ctrl.hw,
1900 [CLKID_SYS_CTRL] = &sys_ctrl.hw,
1901 [CLKID_SYS_TS_PLL] = &sys_ts_pll.hw,
1902 [CLKID_SYS_DEV_ARB] = &sys_dev_arb.hw,
1903 [CLKID_SYS_MMC_PCLK] = &sys_mmc_pclk.hw,
1904 [CLKID_SYS_CPU_CTRL] = &sys_cpu_ctrl.hw,
1905 [CLKID_SYS_JTAG_CTRL] = &sys_jtag_ctrl.hw,
1906 [CLKID_SYS_IR_CTRL] = &sys_ir_ctrl.hw,
1907 [CLKID_SYS_IRQ_CTRL] = &sys_irq_ctrl.hw,
1908 [CLKID_SYS_MSR_CLK] = &sys_msr_clk.hw,
1909 [CLKID_SYS_ROM] = &sys_rom.hw,
1910 [CLKID_SYS_UART_F] = &sys_uart_f.hw,
1911 [CLKID_SYS_CPU_ARB] = &sys_cpu_apb.hw,
1912 [CLKID_SYS_RSA] = &sys_rsa.hw,
1913 [CLKID_SYS_SAR_ADC] = &sys_sar_adc.hw,
1914 [CLKID_SYS_STARTUP] = &sys_startup.hw,
1915 [CLKID_SYS_SECURE] = &sys_secure.hw,
1916 [CLKID_SYS_SPIFC] = &sys_spifc.hw,
1917 [CLKID_SYS_NNA] = &sys_nna.hw,
1918 [CLKID_SYS_ETH_MAC] = &sys_eth_mac.hw,
1919 [CLKID_SYS_GIC] = &sys_gic.hw,
1920 [CLKID_SYS_RAMA] = &sys_rama.hw,
1921 [CLKID_SYS_BIG_NIC] = &sys_big_nic.hw,
1922 [CLKID_SYS_RAMB] = &sys_ramb.hw,
1923 [CLKID_SYS_AUDIO_PCLK] = &sys_audio_pclk.hw,
1924 [CLKID_SYS_PWM_KL] = &sys_pwm_kl.hw,
1925 [CLKID_SYS_PWM_IJ] = &sys_pwm_ij.hw,
1926 [CLKID_SYS_USB] = &sys_usb.hw,
1927 [CLKID_SYS_SD_EMMC_A] = &sys_sd_emmc_a.hw,
1928 [CLKID_SYS_SD_EMMC_C] = &sys_sd_emmc_c.hw,
1929 [CLKID_SYS_PWM_AB] = &sys_pwm_ab.hw,
1930 [CLKID_SYS_PWM_CD] = &sys_pwm_cd.hw,
1931 [CLKID_SYS_PWM_EF] = &sys_pwm_ef.hw,
1932 [CLKID_SYS_PWM_GH] = &sys_pwm_gh.hw,
1933 [CLKID_SYS_SPICC_1] = &sys_spicc_1.hw,
1934 [CLKID_SYS_SPICC_0] = &sys_spicc_0.hw,
1935 [CLKID_SYS_UART_A] = &sys_uart_a.hw,
1936 [CLKID_SYS_UART_B] = &sys_uart_b.hw,
1937 [CLKID_SYS_UART_C] = &sys_uart_c.hw,
1938 [CLKID_SYS_UART_D] = &sys_uart_d.hw,
1939 [CLKID_SYS_UART_E] = &sys_uart_e.hw,
1940 [CLKID_SYS_I2C_M_A] = &sys_i2c_m_a.hw,
1941 [CLKID_SYS_I2C_M_B] = &sys_i2c_m_b.hw,
1942 [CLKID_SYS_I2C_M_C] = &sys_i2c_m_c.hw,
1943 [CLKID_SYS_I2C_M_D] = &sys_i2c_m_d.hw,
1944 [CLKID_SYS_I2S_S_A] = &sys_i2c_s_a.hw,
1945 [CLKID_SYS_RTC] = &sys_rtc.hw,
1946 [CLKID_SYS_GE2D] = &sys_ge2d.hw,
1947 [CLKID_SYS_ISP] = &sys_isp.hw,
1948 [CLKID_SYS_GPV_ISP_NIC] = &sys_gpv_isp_nic.hw,
1949 [CLKID_SYS_GPV_CVE_NIC] = &sys_gpv_cve_nic.hw,
1950 [CLKID_SYS_MIPI_DSI_HOST] = &sys_mipi_dsi_host.hw,
1951 [CLKID_SYS_MIPI_DSI_PHY] = &sys_mipi_dsi_phy.hw,
1952 [CLKID_SYS_ETH_PHY] = &sys_eth_phy.hw,
1953 [CLKID_SYS_ACODEC] = &sys_acodec.hw,
1954 [CLKID_SYS_DWAP] = &sys_dwap.hw,
1955 [CLKID_SYS_DOS] = &sys_dos.hw,
1956 [CLKID_SYS_CVE] = &sys_cve.hw,
1957 [CLKID_SYS_VOUT] = &sys_vout.hw,
1958 [CLKID_SYS_VC9000E] = &sys_vc9000e.hw,
1959 [CLKID_SYS_PWM_MN] = &sys_pwm_mn.hw,
1960 [CLKID_SYS_SD_EMMC_B] = &sys_sd_emmc_b.hw,
1961 [CLKID_AXI_SYS_NIC] = &axi_sys_nic.hw,
1962 [CLKID_AXI_ISP_NIC] = &axi_isp_nic.hw,
1963 [CLKID_AXI_CVE_NIC] = &axi_cve_nic.hw,
1964 [CLKID_AXI_RAMB] = &axi_ramb.hw,
1965 [CLKID_AXI_RAMA] = &axi_rama.hw,
1966 [CLKID_AXI_CPU_DMC] = &axi_cpu_dmc.hw,
1967 [CLKID_AXI_NIC] = &axi_nic.hw,
1968 [CLKID_AXI_DMA] = &axi_dma.hw,
1969 [CLKID_AXI_MUX_NIC] = &axi_mux_nic.hw,
1970 [CLKID_AXI_CVE] = &axi_cve.hw,
1971 [CLKID_AXI_DEV1_DMC] = &axi_dev1_dmc.hw,
1972 [CLKID_AXI_DEV0_DMC] = &axi_dev0_dmc.hw,
1973 [CLKID_AXI_DSP_DMC] = &axi_dsp_dmc.hw,
1974 [CLKID_12_24M_IN] = &clk_12_24m_in.hw,
1975 [CLKID_12M_24M] = &clk_12_24m.hw,
1976 [CLKID_FCLK_25M_DIV] = &fclk_25m_div.hw,
1977 [CLKID_FCLK_25M] = &fclk_25m.hw,
1978 [CLKID_GEN_SEL] = &gen_sel.hw,
1979 [CLKID_GEN_DIV] = &gen_div.hw,
1980 [CLKID_GEN] = &gen.hw,
1981 [CLKID_SARADC_SEL] = &saradc_sel.hw,
1982 [CLKID_SARADC_DIV] = &saradc_div.hw,
1983 [CLKID_SARADC] = &saradc.hw,
1984 [CLKID_PWM_A_SEL] = &pwm_a_sel.hw,
1985 [CLKID_PWM_A_DIV] = &pwm_a_div.hw,
1986 [CLKID_PWM_A] = &pwm_a.hw,
1987 [CLKID_PWM_B_SEL] = &pwm_b_sel.hw,
1988 [CLKID_PWM_B_DIV] = &pwm_b_div.hw,
1989 [CLKID_PWM_B] = &pwm_b.hw,
1990 [CLKID_PWM_C_SEL] = &pwm_c_sel.hw,
1991 [CLKID_PWM_C_DIV] = &pwm_c_div.hw,
1992 [CLKID_PWM_C] = &pwm_c.hw,
1993 [CLKID_PWM_D_SEL] = &pwm_d_sel.hw,
1994 [CLKID_PWM_D_DIV] = &pwm_d_div.hw,
1995 [CLKID_PWM_D] = &pwm_d.hw,
1996 [CLKID_PWM_E_SEL] = &pwm_e_sel.hw,
1997 [CLKID_PWM_E_DIV] = &pwm_e_div.hw,
1998 [CLKID_PWM_E] = &pwm_e.hw,
1999 [CLKID_PWM_F_SEL] = &pwm_f_sel.hw,
2000 [CLKID_PWM_F_DIV] = &pwm_f_div.hw,
2001 [CLKID_PWM_F] = &pwm_f.hw,
2002 [CLKID_PWM_G_SEL] = &pwm_g_sel.hw,
2003 [CLKID_PWM_G_DIV] = &pwm_g_div.hw,
2004 [CLKID_PWM_G] = &pwm_g.hw,
2005 [CLKID_PWM_H_SEL] = &pwm_h_sel.hw,
2006 [CLKID_PWM_H_DIV] = &pwm_h_div.hw,
2007 [CLKID_PWM_H] = &pwm_h.hw,
2008 [CLKID_PWM_I_SEL] = &pwm_i_sel.hw,
2009 [CLKID_PWM_I_DIV] = &pwm_i_div.hw,
2010 [CLKID_PWM_I] = &pwm_i.hw,
2011 [CLKID_PWM_J_SEL] = &pwm_j_sel.hw,
2012 [CLKID_PWM_J_DIV] = &pwm_j_div.hw,
2013 [CLKID_PWM_J] = &pwm_j.hw,
2014 [CLKID_PWM_K_SEL] = &pwm_k_sel.hw,
2015 [CLKID_PWM_K_DIV] = &pwm_k_div.hw,
2016 [CLKID_PWM_K] = &pwm_k.hw,
2017 [CLKID_PWM_L_SEL] = &pwm_l_sel.hw,
2018 [CLKID_PWM_L_DIV] = &pwm_l_div.hw,
2019 [CLKID_PWM_L] = &pwm_l.hw,
2020 [CLKID_PWM_M_SEL] = &pwm_m_sel.hw,
2021 [CLKID_PWM_M_DIV] = &pwm_m_div.hw,
2022 [CLKID_PWM_M] = &pwm_m.hw,
2023 [CLKID_PWM_N_SEL] = &pwm_n_sel.hw,
2024 [CLKID_PWM_N_DIV] = &pwm_n_div.hw,
2025 [CLKID_PWM_N] = &pwm_n.hw,
2026 [CLKID_SPICC_A_SEL] = &spicc_a_sel.hw,
2027 [CLKID_SPICC_A_DIV] = &spicc_a_div.hw,
2028 [CLKID_SPICC_A] = &spicc_a.hw,
2029 [CLKID_SPICC_B_SEL] = &spicc_b_sel.hw,
2030 [CLKID_SPICC_B_DIV] = &spicc_b_div.hw,
2031 [CLKID_SPICC_B] = &spicc_b.hw,
2032 [CLKID_SPIFC_SEL] = &spifc_sel.hw,
2033 [CLKID_SPIFC_DIV] = &spifc_div.hw,
2034 [CLKID_SPIFC] = &spifc.hw,
2035 [CLKID_SD_EMMC_A_SEL] = &sd_emmc_a_sel.hw,
2036 [CLKID_SD_EMMC_A_DIV] = &sd_emmc_a_div.hw,
2037 [CLKID_SD_EMMC_A] = &sd_emmc_a.hw,
2038 [CLKID_SD_EMMC_B_SEL] = &sd_emmc_b_sel.hw,
2039 [CLKID_SD_EMMC_B_DIV] = &sd_emmc_b_div.hw,
2040 [CLKID_SD_EMMC_B] = &sd_emmc_b.hw,
2041 [CLKID_SD_EMMC_C_SEL] = &sd_emmc_c_sel.hw,
2042 [CLKID_SD_EMMC_C_DIV] = &sd_emmc_c_div.hw,
2043 [CLKID_SD_EMMC_C] = &sd_emmc_c.hw,
2044 [CLKID_TS_DIV] = &ts_div.hw,
2045 [CLKID_TS] = &ts.hw,
2046 [CLKID_ETH_125M_DIV] = ð_125m_div.hw,
2047 [CLKID_ETH_125M] = ð_125m.hw,
2048 [CLKID_ETH_RMII_DIV] = ð_rmii_div.hw,
2049 [CLKID_ETH_RMII] = ð_rmii.hw,
2050 [CLKID_MIPI_DSI_MEAS_SEL] = &mipi_dsi_meas_sel.hw,
2051 [CLKID_MIPI_DSI_MEAS_DIV] = &mipi_dsi_meas_div.hw,
2052 [CLKID_MIPI_DSI_MEAS] = &mipi_dsi_meas.hw,
2053 [CLKID_DSI_PHY_SEL] = &dsi_phy_sel.hw,
2054 [CLKID_DSI_PHY_DIV] = &dsi_phy_div.hw,
2055 [CLKID_DSI_PHY] = &dsi_phy.hw,
2056 [CLKID_VOUT_MCLK_SEL] = &vout_mclk_sel.hw,
2057 [CLKID_VOUT_MCLK_DIV] = &vout_mclk_div.hw,
2058 [CLKID_VOUT_MCLK] = &vout_mclk.hw,
2059 [CLKID_VOUT_ENC_SEL] = &vout_enc_sel.hw,
2060 [CLKID_VOUT_ENC_DIV] = &vout_enc_div.hw,
2061 [CLKID_VOUT_ENC] = &vout_enc.hw,
2062 [CLKID_HCODEC_0_SEL] = &hcodec_0_sel.hw,
2063 [CLKID_HCODEC_0_DIV] = &hcodec_0_div.hw,
2064 [CLKID_HCODEC_0] = &hcodec_0.hw,
2065 [CLKID_HCODEC_1_SEL] = &hcodec_1_sel.hw,
2066 [CLKID_HCODEC_1_DIV] = &hcodec_1_div.hw,
2067 [CLKID_HCODEC_1] = &hcodec_1.hw,
2068 [CLKID_HCODEC] = &hcodec.hw,
2069 [CLKID_VC9000E_ACLK_SEL] = &vc9000e_aclk_sel.hw,
2070 [CLKID_VC9000E_ACLK_DIV] = &vc9000e_aclk_div.hw,
2071 [CLKID_VC9000E_ACLK] = &vc9000e_aclk.hw,
2072 [CLKID_VC9000E_CORE_SEL] = &vc9000e_core_sel.hw,
2073 [CLKID_VC9000E_CORE_DIV] = &vc9000e_core_div.hw,
2074 [CLKID_VC9000E_CORE] = &vc9000e_core.hw,
2075 [CLKID_CSI_PHY0_SEL] = &csi_phy0_sel.hw,
2076 [CLKID_CSI_PHY0_DIV] = &csi_phy0_div.hw,
2077 [CLKID_CSI_PHY0] = &csi_phy0.hw,
2078 [CLKID_DEWARPA_SEL] = &dewarpa_sel.hw,
2079 [CLKID_DEWARPA_DIV] = &dewarpa_div.hw,
2080 [CLKID_DEWARPA] = &dewarpa.hw,
2081 [CLKID_ISP0_SEL] = &isp0_sel.hw,
2082 [CLKID_ISP0_DIV] = &isp0_div.hw,
2083 [CLKID_ISP0] = &isp0.hw,
2084 [CLKID_NNA_CORE_SEL] = &nna_core_sel.hw,
2085 [CLKID_NNA_CORE_DIV] = &nna_core_div.hw,
2086 [CLKID_NNA_CORE] = &nna_core.hw,
2087 [CLKID_GE2D_SEL] = &ge2d_sel.hw,
2088 [CLKID_GE2D_DIV] = &ge2d_div.hw,
2089 [CLKID_GE2D] = &ge2d.hw,
2090 [CLKID_VAPB_SEL] = &vapb_sel.hw,
2091 [CLKID_VAPB_DIV] = &vapb_div.hw,
2092 [CLKID_VAPB] = &vapb.hw,
2093};
2094
2095/* Convenience table to populate regmap in .probe */
2096static struct clk_regmap *const c3_periphs_clk_regmaps[] = {
2097 &rtc_xtal_clkin,
2098 &rtc_32k_div,
2099 &rtc_32k_mux,
2100 &rtc_32k,
2101 &rtc_clk,
2102 &sys_reset_ctrl,
2103 &sys_pwr_ctrl,
2104 &sys_pad_ctrl,
2105 &sys_ctrl,
2106 &sys_ts_pll,
2107 &sys_dev_arb,
2108 &sys_mmc_pclk,
2109 &sys_cpu_ctrl,
2110 &sys_jtag_ctrl,
2111 &sys_ir_ctrl,
2112 &sys_irq_ctrl,
2113 &sys_msr_clk,
2114 &sys_rom,
2115 &sys_uart_f,
2116 &sys_cpu_apb,
2117 &sys_rsa,
2118 &sys_sar_adc,
2119 &sys_startup,
2120 &sys_secure,
2121 &sys_spifc,
2122 &sys_nna,
2123 &sys_eth_mac,
2124 &sys_gic,
2125 &sys_rama,
2126 &sys_big_nic,
2127 &sys_ramb,
2128 &sys_audio_pclk,
2129 &sys_pwm_kl,
2130 &sys_pwm_ij,
2131 &sys_usb,
2132 &sys_sd_emmc_a,
2133 &sys_sd_emmc_c,
2134 &sys_pwm_ab,
2135 &sys_pwm_cd,
2136 &sys_pwm_ef,
2137 &sys_pwm_gh,
2138 &sys_spicc_1,
2139 &sys_spicc_0,
2140 &sys_uart_a,
2141 &sys_uart_b,
2142 &sys_uart_c,
2143 &sys_uart_d,
2144 &sys_uart_e,
2145 &sys_i2c_m_a,
2146 &sys_i2c_m_b,
2147 &sys_i2c_m_c,
2148 &sys_i2c_m_d,
2149 &sys_i2c_s_a,
2150 &sys_rtc,
2151 &sys_ge2d,
2152 &sys_isp,
2153 &sys_gpv_isp_nic,
2154 &sys_gpv_cve_nic,
2155 &sys_mipi_dsi_host,
2156 &sys_mipi_dsi_phy,
2157 &sys_eth_phy,
2158 &sys_acodec,
2159 &sys_dwap,
2160 &sys_dos,
2161 &sys_cve,
2162 &sys_vout,
2163 &sys_vc9000e,
2164 &sys_pwm_mn,
2165 &sys_sd_emmc_b,
2166 &axi_sys_nic,
2167 &axi_isp_nic,
2168 &axi_cve_nic,
2169 &axi_ramb,
2170 &axi_rama,
2171 &axi_cpu_dmc,
2172 &axi_nic,
2173 &axi_dma,
2174 &axi_mux_nic,
2175 &axi_cve,
2176 &axi_dev1_dmc,
2177 &axi_dev0_dmc,
2178 &axi_dsp_dmc,
2179 &clk_12_24m_in,
2180 &clk_12_24m,
2181 &fclk_25m_div,
2182 &fclk_25m,
2183 &gen_sel,
2184 &gen_div,
2185 &gen,
2186 &saradc_sel,
2187 &saradc_div,
2188 &saradc,
2189 &pwm_a_sel,
2190 &pwm_a_div,
2191 &pwm_a,
2192 &pwm_b_sel,
2193 &pwm_b_div,
2194 &pwm_b,
2195 &pwm_c_sel,
2196 &pwm_c_div,
2197 &pwm_c,
2198 &pwm_d_sel,
2199 &pwm_d_div,
2200 &pwm_d,
2201 &pwm_e_sel,
2202 &pwm_e_div,
2203 &pwm_e,
2204 &pwm_f_sel,
2205 &pwm_f_div,
2206 &pwm_f,
2207 &pwm_g_sel,
2208 &pwm_g_div,
2209 &pwm_g,
2210 &pwm_h_sel,
2211 &pwm_h_div,
2212 &pwm_h,
2213 &pwm_i_sel,
2214 &pwm_i_div,
2215 &pwm_i,
2216 &pwm_j_sel,
2217 &pwm_j_div,
2218 &pwm_j,
2219 &pwm_k_sel,
2220 &pwm_k_div,
2221 &pwm_k,
2222 &pwm_l_sel,
2223 &pwm_l_div,
2224 &pwm_l,
2225 &pwm_m_sel,
2226 &pwm_m_div,
2227 &pwm_m,
2228 &pwm_n_sel,
2229 &pwm_n_div,
2230 &pwm_n,
2231 &spicc_a_sel,
2232 &spicc_a_div,
2233 &spicc_a,
2234 &spicc_b_sel,
2235 &spicc_b_div,
2236 &spicc_b,
2237 &spifc_sel,
2238 &spifc_div,
2239 &spifc,
2240 &sd_emmc_a_sel,
2241 &sd_emmc_a_div,
2242 &sd_emmc_a,
2243 &sd_emmc_b_sel,
2244 &sd_emmc_b_div,
2245 &sd_emmc_b,
2246 &sd_emmc_c_sel,
2247 &sd_emmc_c_div,
2248 &sd_emmc_c,
2249 &ts_div,
2250 &ts,
2251 ð_125m,
2252 ð_rmii_div,
2253 ð_rmii,
2254 &mipi_dsi_meas_sel,
2255 &mipi_dsi_meas_div,
2256 &mipi_dsi_meas,
2257 &dsi_phy_sel,
2258 &dsi_phy_div,
2259 &dsi_phy,
2260 &vout_mclk_sel,
2261 &vout_mclk_div,
2262 &vout_mclk,
2263 &vout_enc_sel,
2264 &vout_enc_div,
2265 &vout_enc,
2266 &hcodec_0_sel,
2267 &hcodec_0_div,
2268 &hcodec_0,
2269 &hcodec_1_sel,
2270 &hcodec_1_div,
2271 &hcodec_1,
2272 &hcodec,
2273 &vc9000e_aclk_sel,
2274 &vc9000e_aclk_div,
2275 &vc9000e_aclk,
2276 &vc9000e_core_sel,
2277 &vc9000e_core_div,
2278 &vc9000e_core,
2279 &csi_phy0_sel,
2280 &csi_phy0_div,
2281 &csi_phy0,
2282 &dewarpa_sel,
2283 &dewarpa_div,
2284 &dewarpa,
2285 &isp0_sel,
2286 &isp0_div,
2287 &isp0,
2288 &nna_core_sel,
2289 &nna_core_div,
2290 &nna_core,
2291 &ge2d_sel,
2292 &ge2d_div,
2293 &ge2d,
2294 &vapb_sel,
2295 &vapb_div,
2296 &vapb,
2297};
2298
2299static const struct regmap_config clkc_regmap_config = {
2300 .reg_bits = 32,
2301 .val_bits = 32,
2302 .reg_stride = 4,
2303 .max_register = NNA_CLK_CTRL,
2304};
2305
2306static struct meson_clk_hw_data c3_periphs_clks = {
2307 .hws = c3_periphs_hw_clks,
2308 .num = ARRAY_SIZE(c3_periphs_hw_clks),
2309};
2310
2311static int c3_peripherals_probe(struct platform_device *pdev)
2312{
2313 struct device *dev = &pdev->dev;
2314 struct regmap *regmap;
2315 void __iomem *base;
2316 int clkid, ret, i;
2317
2318 base = devm_platform_ioremap_resource(pdev, 0);
2319 if (IS_ERR(base))
2320 return PTR_ERR(base);
2321
2322 regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
2323 if (IS_ERR(regmap))
2324 return PTR_ERR(regmap);
2325
2326 /* Populate regmap for the regmap backed clocks */
2327 for (i = 0; i < ARRAY_SIZE(c3_periphs_clk_regmaps); i++)
2328 c3_periphs_clk_regmaps[i]->map = regmap;
2329
2330 for (clkid = 0; clkid < c3_periphs_clks.num; clkid++) {
2331 /* array might be sparse */
2332 if (!c3_periphs_clks.hws[clkid])
2333 continue;
2334
2335 ret = devm_clk_hw_register(dev, c3_periphs_clks.hws[clkid]);
2336 if (ret) {
2337 dev_err(dev, "Clock registration failed\n");
2338 return ret;
2339 }
2340 }
2341
2342 return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get,
2343 &c3_periphs_clks);
2344}
2345
2346static const struct of_device_id c3_peripherals_clkc_match_table[] = {
2347 {
2348 .compatible = "amlogic,c3-peripherals-clkc",
2349 },
2350 { /* sentinel */ }
2351};
2352
2353MODULE_DEVICE_TABLE(of, c3_peripherals_clkc_match_table);
2354
2355static struct platform_driver c3_peripherals_driver = {
2356 .probe = c3_peripherals_probe,
2357 .driver = {
2358 .name = "c3-peripherals-clkc",
2359 .of_match_table = c3_peripherals_clkc_match_table,
2360 },
2361};
2362module_platform_driver(c3_peripherals_driver);
2363
2364MODULE_DESCRIPTION("Amlogic C3 Peripherals Clock Controller driver");
2365MODULE_AUTHOR("Chuan Liu <chuan.liu@amlogic.com>");
2366MODULE_LICENSE("GPL");
2367MODULE_IMPORT_NS("CLK_MESON");