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1/*
2 * head.S: The initial boot code for the Sparc port of Linux.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995,1999 Pete Zaitcev (zaitcev@yahoo.com)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 * Copyright (C) 1997 Michael A. Griffith (grif@acm.org)
9 *
10 * CompactPCI platform by Eric Brower, 1999.
11 */
12
13#include <linux/version.h>
14#include <linux/init.h>
15
16#include <asm/head.h>
17#include <asm/asi.h>
18#include <asm/contregs.h>
19#include <asm/ptrace.h>
20#include <asm/psr.h>
21#include <asm/page.h>
22#include <asm/kdebug.h>
23#include <asm/winmacro.h>
24#include <asm/thread_info.h> /* TI_UWINMASK */
25#include <asm/errno.h>
26#include <asm/pgtsrmmu.h> /* SRMMU_PGDIR_SHIFT */
27
28 .data
29/* The following are used with the prom_vector node-ops to figure out
30 * the cpu-type
31 */
32 .align 4
33 .globl cputypval
34cputypval:
35 .asciz "sun4m"
36 .ascii " "
37
38/* Tested on SS-5, SS-10 */
39 .align 4
40cputypvar:
41 .asciz "compatible"
42
43 .align 4
44
45notsup:
46 .asciz "Sparc-Linux sun4/sun4c or MMU-less not supported\n\n"
47 .align 4
48
49sun4e_notsup:
50 .asciz "Sparc-Linux sun4e support does not exist\n\n"
51 .align 4
52
53/* The trap-table - located in the __HEAD section */
54#include "ttable_32.S"
55
56 .align PAGE_SIZE
57
58/* This was the only reasonable way I could think of to properly align
59 * these page-table data structures.
60 */
61 .globl empty_zero_page
62empty_zero_page: .skip PAGE_SIZE
63
64 .global root_flags
65 .global ram_flags
66 .global root_dev
67 .global sparc_ramdisk_image
68 .global sparc_ramdisk_size
69
70/* This stuff has to be in sync with SILO and other potential boot loaders
71 * Fields should be kept upward compatible and whenever any change is made,
72 * HdrS version should be incremented.
73 */
74 .ascii "HdrS"
75 .word LINUX_VERSION_CODE
76 .half 0x0203 /* HdrS version */
77root_flags:
78 .half 1
79root_dev:
80 .half 0
81ram_flags:
82 .half 0
83sparc_ramdisk_image:
84 .word 0
85sparc_ramdisk_size:
86 .word 0
87 .word reboot_command
88 .word 0, 0, 0
89 .word _end
90
91/* Cool, here we go. Pick up the romvec pointer in %o0 and stash it in
92 * %g7 and at prom_vector_p. And also quickly check whether we are on
93 * a v0, v2, or v3 prom.
94 */
95gokernel:
96 /* Ok, it's nice to know, as early as possible, if we
97 * are already mapped where we expect to be in virtual
98 * memory. The Solaris /boot elf format bootloader
99 * will peek into our elf header and load us where
100 * we want to be, otherwise we have to re-map.
101 *
102 * Some boot loaders don't place the jmp'rs address
103 * in %o7, so we do a pc-relative call to a local
104 * label, then see what %o7 has.
105 */
106
107 mov %o7, %g4 ! Save %o7
108
109 /* Jump to it, and pray... */
110current_pc:
111 call 1f
112 nop
113
1141:
115 mov %o7, %g3
116
117 tst %o0
118 be no_sun4u_here
119 mov %g4, %o7 /* Previous %o7. */
120
121 mov %o0, %l0 ! stash away romvec
122 mov %o0, %g7 ! put it here too
123 mov %o1, %l1 ! stash away debug_vec too
124
125 /* Ok, let's check out our run time program counter. */
126 set current_pc, %g5
127 cmp %g3, %g5
128 be already_mapped
129 nop
130
131 /* %l6 will hold the offset we have to subtract
132 * from absolute symbols in order to access areas
133 * in our own image. If already mapped this is
134 * just plain zero, else it is KERNBASE.
135 */
136 set KERNBASE, %l6
137 b copy_prom_lvl14
138 nop
139
140already_mapped:
141 mov 0, %l6
142
143 /* Copy over the Prom's level 14 clock handler. */
144copy_prom_lvl14:
145#if 1
146 /* DJHR
147 * preserve our linked/calculated instructions
148 */
149 set lvl14_save, %g1
150 set t_irq14, %g3
151 sub %g1, %l6, %g1 ! translate to physical
152 sub %g3, %l6, %g3 ! translate to physical
153 ldd [%g3], %g4
154 std %g4, [%g1]
155 ldd [%g3+8], %g4
156 std %g4, [%g1+8]
157#endif
158 rd %tbr, %g1
159 andn %g1, 0xfff, %g1 ! proms trap table base
160 or %g0, (0x1e<<4), %g2 ! offset to lvl14 intr
161 or %g1, %g2, %g2
162 set t_irq14, %g3
163 sub %g3, %l6, %g3
164 ldd [%g2], %g4
165 std %g4, [%g3]
166 ldd [%g2 + 0x8], %g4
167 std %g4, [%g3 + 0x8] ! Copy proms handler
168
169/* DON'T TOUCH %l0 thru %l5 in these remapping routines,
170 * we need their values afterwards!
171 */
172
173 /* Now check whether we are already mapped, if we
174 * are we can skip all this garbage coming up.
175 */
176copy_prom_done:
177 cmp %l6, 0
178 be go_to_highmem ! this will be a nop then
179 nop
180
181 /* Validate that we are in fact running on an
182 * SRMMU based cpu.
183 */
184 set 0x4000, %g6
185 cmp %g7, %g6
186 bne not_a_sun4
187 nop
188
189halt_notsup:
190 ld [%g7 + 0x68], %o1
191 set notsup, %o0
192 sub %o0, %l6, %o0
193 call %o1
194 nop
195 ba halt_me
196 nop
197
198not_a_sun4:
199 /* It looks like this is a machine we support.
200 * Now find out what MMU we are dealing with
201 * LEON - identified by the psr.impl field
202 * Viking - identified by the psr.impl field
203 * In all other cases a sun4m srmmu.
204 * We check that the MMU is enabled in all cases.
205 */
206
207 /* Check if this is a LEON CPU */
208 rd %psr, %g3
209 srl %g3, PSR_IMPL_SHIFT, %g3
210 and %g3, PSR_IMPL_SHIFTED_MASK, %g3
211 cmp %g3, PSR_IMPL_LEON
212 be leon_remap /* It is a LEON - jump */
213 nop
214
215 /* Sanity-check, is MMU enabled */
216 lda [%g0] ASI_M_MMUREGS, %g1
217 andcc %g1, 1, %g0
218 be halt_notsup
219 nop
220
221 /* Check for a viking (TI) module. */
222 cmp %g3, PSR_IMPL_TI
223 bne srmmu_not_viking
224 nop
225
226 /* Figure out what kind of viking we are on.
227 * We need to know if we have to play with the
228 * AC bit and disable traps or not.
229 */
230
231 /* I've only seen MicroSparc's on SparcClassics with this
232 * bit set.
233 */
234 set 0x800, %g2
235 lda [%g0] ASI_M_MMUREGS, %g3 ! peek in the control reg
236 and %g2, %g3, %g3
237 subcc %g3, 0x0, %g0
238 bnz srmmu_not_viking ! is in mbus mode
239 nop
240
241 rd %psr, %g3 ! DO NOT TOUCH %g3
242 andn %g3, PSR_ET, %g2
243 wr %g2, 0x0, %psr
244 WRITE_PAUSE
245
246 /* Get context table pointer, then convert to
247 * a physical address, which is 36 bits.
248 */
249 set AC_M_CTPR, %g4
250 lda [%g4] ASI_M_MMUREGS, %g4
251 sll %g4, 0x4, %g4 ! We use this below
252 ! DO NOT TOUCH %g4
253
254 /* Set the AC bit in the Viking's MMU control reg. */
255 lda [%g0] ASI_M_MMUREGS, %g5 ! DO NOT TOUCH %g5
256 set 0x8000, %g6 ! AC bit mask
257 or %g5, %g6, %g6 ! Or it in...
258 sta %g6, [%g0] ASI_M_MMUREGS ! Close your eyes...
259
260 /* Grrr, why does it seem like every other load/store
261 * on the sun4m is in some ASI space...
262 * Fine with me, let's get the pointer to the level 1
263 * page table directory and fetch its entry.
264 */
265 lda [%g4] ASI_M_BYPASS, %o1 ! This is a level 1 ptr
266 srl %o1, 0x4, %o1 ! Clear low 4 bits
267 sll %o1, 0x8, %o1 ! Make physical
268
269 /* Ok, pull in the PTD. */
270 lda [%o1] ASI_M_BYPASS, %o2 ! This is the 0x0 16MB pgd
271
272 /* Calculate to KERNBASE entry. */
273 add %o1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %o3
274
275 /* Poke the entry into the calculated address. */
276 sta %o2, [%o3] ASI_M_BYPASS
277
278 /* I don't get it Sun, if you engineered all these
279 * boot loaders and the PROM (thank you for the debugging
280 * features btw) why did you not have them load kernel
281 * images up in high address space, since this is necessary
282 * for ABI compliance anyways? Does this low-mapping provide
283 * enhanced interoperability?
284 *
285 * "The PROM is the computer."
286 */
287
288 /* Ok, restore the MMU control register we saved in %g5 */
289 sta %g5, [%g0] ASI_M_MMUREGS ! POW... ouch
290
291 /* Turn traps back on. We saved it in %g3 earlier. */
292 wr %g3, 0x0, %psr ! tick tock, tick tock
293
294 /* Now we burn precious CPU cycles due to bad engineering. */
295 WRITE_PAUSE
296
297 /* Wow, all that just to move a 32-bit value from one
298 * place to another... Jump to high memory.
299 */
300 b go_to_highmem
301 nop
302
303srmmu_not_viking:
304 /* This works on viking's in Mbus mode and all
305 * other MBUS modules. It is virtually the same as
306 * the above madness sans turning traps off and flipping
307 * the AC bit.
308 */
309 set AC_M_CTPR, %g1
310 lda [%g1] ASI_M_MMUREGS, %g1 ! get ctx table ptr
311 sll %g1, 0x4, %g1 ! make physical addr
312 lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table
313 srl %g1, 0x4, %g1
314 sll %g1, 0x8, %g1 ! make phys addr for l1 tbl
315
316 lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0
317 add %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3
318 sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry
319 b go_to_highmem
320 nop ! wheee....
321
322
323leon_remap:
324 /* Sanity-check, is MMU enabled */
325 lda [%g0] ASI_LEON_MMUREGS, %g1
326 andcc %g1, 1, %g0
327 be halt_notsup
328 nop
329
330 /* Same code as in the srmmu_not_viking case,
331 * with the LEON ASI for mmuregs
332 */
333 set AC_M_CTPR, %g1
334 lda [%g1] ASI_LEON_MMUREGS, %g1 ! get ctx table ptr
335 sll %g1, 0x4, %g1 ! make physical addr
336 lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table
337 srl %g1, 0x4, %g1
338 sll %g1, 0x8, %g1 ! make phys addr for l1 tbl
339
340 lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0
341 add %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3
342 sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry
343 b go_to_highmem
344 nop ! wheee....
345
346/* Now do a non-relative jump so that PC is in high-memory */
347go_to_highmem:
348 set execute_in_high_mem, %g1
349 jmpl %g1, %g0
350 nop
351
352/* The code above should be at beginning and we have to take care about
353 * short jumps, as branching to .init.text section from .text is usually
354 * impossible */
355 __INIT
356/* Acquire boot time privileged register values, this will help debugging.
357 * I figure out and store nwindows and nwindowsm1 later on.
358 */
359execute_in_high_mem:
360 mov %l0, %o0 ! put back romvec
361 mov %l1, %o1 ! and debug_vec
362
363 sethi %hi(prom_vector_p), %g1
364 st %o0, [%g1 + %lo(prom_vector_p)]
365
366 sethi %hi(linux_dbvec), %g1
367 st %o1, [%g1 + %lo(linux_dbvec)]
368
369 /* Get the machine type via the romvec
370 * getprops node operation
371 */
372 add %g7, 0x1c, %l1
373 ld [%l1], %l0
374 ld [%l0], %l0
375 call %l0
376 or %g0, %g0, %o0 ! next_node(0) = first_node
377 or %o0, %g0, %g6
378
379 sethi %hi(cputypvar), %o1 ! First node has cpu-arch
380 or %o1, %lo(cputypvar), %o1
381 sethi %hi(cputypval), %o2 ! information, the string
382 or %o2, %lo(cputypval), %o2
383 ld [%l1], %l0 ! 'compatible' tells
384 ld [%l0 + 0xc], %l0 ! that we want 'sun4x' where
385 call %l0 ! x is one of 'm', 'd' or 'e'.
386 nop ! %o2 holds pointer
387 ! to a buf where above string
388 ! will get stored by the prom.
389
390
391 /* Check value of "compatible" property.
392 * "value" => "model"
393 * leon => sparc_leon
394 * sun4m => sun4m
395 * sun4s => sun4m
396 * sun4d => sun4d
397 * sun4e => "no_sun4e_here"
398 * '*' => "no_sun4u_here"
399 * Check single letters only
400 */
401
402 set cputypval, %o2
403 /* If cputypval[0] == 'l' (lower case letter L) this is leon */
404 ldub [%o2], %l1
405 cmp %l1, 'l'
406 be leon_init
407 nop
408
409 /* Check cputypval[4] to find the sun model */
410 ldub [%o2 + 0x4], %l1
411
412 cmp %l1, 'm'
413 be sun4m_init
414 cmp %l1, 's'
415 be sun4m_init
416 cmp %l1, 'd'
417 be sun4d_init
418 cmp %l1, 'e'
419 be no_sun4e_here ! Could be a sun4e.
420 nop
421 b no_sun4u_here ! AIEEE, a V9 sun4u... Get our BIG BROTHER kernel :))
422 nop
423
424leon_init:
425 /* LEON CPU - set boot_cpu_id */
426 sethi %hi(boot_cpu_id), %g2 ! boot-cpu index
427
428#ifdef CONFIG_SMP
429 ldub [%g2 + %lo(boot_cpu_id)], %g1
430 cmp %g1, 0xff ! unset means first CPU
431 bne leon_smp_cpu_startup ! continue only with master
432 nop
433#endif
434 /* Get CPU-ID from most significant 4-bit of ASR17 */
435 rd %asr17, %g1
436 srl %g1, 28, %g1
437
438 /* Update boot_cpu_id only on boot cpu */
439 stub %g1, [%g2 + %lo(boot_cpu_id)]
440
441 ba continue_boot
442 nop
443
444/* CPUID in bootbus can be found at PA 0xff0140000 */
445#define SUN4D_BOOTBUS_CPUID 0xf0140000
446
447sun4d_init:
448 /* Need to patch call to handler_irq */
449 set patch_handler_irq, %g4
450 set sun4d_handler_irq, %g5
451 sethi %hi(0x40000000), %g3 ! call
452 sub %g5, %g4, %g5
453 srl %g5, 2, %g5
454 or %g5, %g3, %g5
455 st %g5, [%g4]
456
457#ifdef CONFIG_SMP
458 /* Get our CPU id out of bootbus */
459 set SUN4D_BOOTBUS_CPUID, %g3
460 lduba [%g3] ASI_M_CTL, %g3
461 and %g3, 0xf8, %g3
462 srl %g3, 3, %g4
463 sta %g4, [%g0] ASI_M_VIKING_TMP1
464 sethi %hi(boot_cpu_id), %g5
465 stb %g4, [%g5 + %lo(boot_cpu_id)]
466#endif
467
468 /* Fall through to sun4m_init */
469
470sun4m_init:
471/* Ok, the PROM could have done funny things and apple cider could still
472 * be sitting in the fault status/address registers. Read them all to
473 * clear them so we don't get magic faults later on.
474 */
475/* This sucks, apparently this makes Vikings call prom panic, will fix later */
4762:
477 rd %psr, %o1
478 srl %o1, PSR_IMPL_SHIFT, %o1 ! Get a type of the CPU
479
480 subcc %o1, PSR_IMPL_TI, %g0 ! TI: Viking or MicroSPARC
481 be continue_boot
482 nop
483
484 set AC_M_SFSR, %o0
485 lda [%o0] ASI_M_MMUREGS, %g0
486 set AC_M_SFAR, %o0
487 lda [%o0] ASI_M_MMUREGS, %g0
488
489 /* Fujitsu MicroSPARC-II has no asynchronous flavors of FARs */
490 subcc %o1, 0, %g0
491 be continue_boot
492 nop
493
494 set AC_M_AFSR, %o0
495 lda [%o0] ASI_M_MMUREGS, %g0
496 set AC_M_AFAR, %o0
497 lda [%o0] ASI_M_MMUREGS, %g0
498 nop
499
500
501continue_boot:
502
503/* Aieee, now set PC and nPC, enable traps, give ourselves a stack and it's
504 * show-time!
505 */
506 /* Turn on Supervisor, EnableFloating, and all the PIL bits.
507 * Also puts us in register window zero with traps off.
508 */
509 set (PSR_PS | PSR_S | PSR_PIL | PSR_EF), %g2
510 wr %g2, 0x0, %psr
511 WRITE_PAUSE
512
513 /* I want a kernel stack NOW! */
514 set init_thread_union, %g1
515 set (THREAD_SIZE - STACKFRAME_SZ), %g2
516 add %g1, %g2, %sp
517 mov 0, %fp /* And for good luck */
518
519 /* Zero out our BSS section. */
520 set __bss_start , %o0 ! First address of BSS
521 set _end , %o1 ! Last address of BSS
522 add %o0, 0x1, %o0
5231:
524 stb %g0, [%o0]
525 subcc %o0, %o1, %g0
526 bl 1b
527 add %o0, 0x1, %o0
528
529 /* If boot_cpu_id has not been setup by machine specific
530 * init-code above we default it to zero.
531 */
532 sethi %hi(boot_cpu_id), %g2
533 ldub [%g2 + %lo(boot_cpu_id)], %g3
534 cmp %g3, 0xff
535 bne 1f
536 nop
537 mov %g0, %g3
538 stub %g3, [%g2 + %lo(boot_cpu_id)]
539
5401: sll %g3, 2, %g3
541
542 /* Initialize the uwinmask value for init task just in case.
543 * But first make current_set[boot_cpu_id] point to something useful.
544 */
545 set init_thread_union, %g6
546 set current_set, %g2
547#ifdef CONFIG_SMP
548 st %g6, [%g2]
549 add %g2, %g3, %g2
550#endif
551 st %g6, [%g2]
552
553 st %g0, [%g6 + TI_UWINMASK]
554
555/* Compute NWINDOWS and stash it away. Now uses %wim trick explained
556 * in the V8 manual. Ok, this method seems to work, Sparc is cool...
557 * No, it doesn't work, have to play the save/readCWP/restore trick.
558 */
559
560 wr %g0, 0x0, %wim ! so we do not get a trap
561 WRITE_PAUSE
562
563 save
564
565 rd %psr, %g3
566
567 restore
568
569 and %g3, 0x1f, %g3
570 add %g3, 0x1, %g3
571
572 mov 2, %g1
573 wr %g1, 0x0, %wim ! make window 1 invalid
574 WRITE_PAUSE
575
576 cmp %g3, 0x7
577 bne 2f
578 nop
579
580 /* Adjust our window handling routines to
581 * do things correctly on 7 window Sparcs.
582 */
583
584#define PATCH_INSN(src, dest) \
585 set src, %g5; \
586 set dest, %g2; \
587 ld [%g5], %g4; \
588 st %g4, [%g2];
589
590 /* Patch for window spills... */
591 PATCH_INSN(spnwin_patch1_7win, spnwin_patch1)
592 PATCH_INSN(spnwin_patch2_7win, spnwin_patch2)
593 PATCH_INSN(spnwin_patch3_7win, spnwin_patch3)
594
595 /* Patch for window fills... */
596 PATCH_INSN(fnwin_patch1_7win, fnwin_patch1)
597 PATCH_INSN(fnwin_patch2_7win, fnwin_patch2)
598
599 /* Patch for trap entry setup... */
600 PATCH_INSN(tsetup_7win_patch1, tsetup_patch1)
601 PATCH_INSN(tsetup_7win_patch2, tsetup_patch2)
602 PATCH_INSN(tsetup_7win_patch3, tsetup_patch3)
603 PATCH_INSN(tsetup_7win_patch4, tsetup_patch4)
604 PATCH_INSN(tsetup_7win_patch5, tsetup_patch5)
605 PATCH_INSN(tsetup_7win_patch6, tsetup_patch6)
606
607 /* Patch for returning from traps... */
608 PATCH_INSN(rtrap_7win_patch1, rtrap_patch1)
609 PATCH_INSN(rtrap_7win_patch2, rtrap_patch2)
610 PATCH_INSN(rtrap_7win_patch3, rtrap_patch3)
611 PATCH_INSN(rtrap_7win_patch4, rtrap_patch4)
612 PATCH_INSN(rtrap_7win_patch5, rtrap_patch5)
613
614 /* Patch for killing user windows from the register file. */
615 PATCH_INSN(kuw_patch1_7win, kuw_patch1)
616
617 /* Now patch the kernel window flush sequences.
618 * This saves 2 traps on every switch and fork.
619 */
620 set 0x01000000, %g4
621 set flush_patch_one, %g5
622 st %g4, [%g5 + 0x18]
623 st %g4, [%g5 + 0x1c]
624 set flush_patch_two, %g5
625 st %g4, [%g5 + 0x18]
626 st %g4, [%g5 + 0x1c]
627 set flush_patch_three, %g5
628 st %g4, [%g5 + 0x18]
629 st %g4, [%g5 + 0x1c]
630 set flush_patch_four, %g5
631 st %g4, [%g5 + 0x18]
632 st %g4, [%g5 + 0x1c]
633 set flush_patch_exception, %g5
634 st %g4, [%g5 + 0x18]
635 st %g4, [%g5 + 0x1c]
636 set flush_patch_switch, %g5
637 st %g4, [%g5 + 0x18]
638 st %g4, [%g5 + 0x1c]
639
6402:
641 sethi %hi(nwindows), %g4
642 st %g3, [%g4 + %lo(nwindows)] ! store final value
643 sub %g3, 0x1, %g3
644 sethi %hi(nwindowsm1), %g4
645 st %g3, [%g4 + %lo(nwindowsm1)]
646
647 /* Here we go, start using Linux's trap table... */
648 set trapbase, %g3
649 wr %g3, 0x0, %tbr
650 WRITE_PAUSE
651
652 /* Finally, turn on traps so that we can call c-code. */
653 rd %psr, %g3
654 wr %g3, 0x0, %psr
655 WRITE_PAUSE
656
657 wr %g3, PSR_ET, %psr
658 WRITE_PAUSE
659
660 /* Call sparc32_start_kernel(struct linux_romvec *rp) */
661 sethi %hi(prom_vector_p), %g5
662 ld [%g5 + %lo(prom_vector_p)], %o0
663 call sparc32_start_kernel
664 nop
665
666 /* We should not get here. */
667 call halt_me
668 nop
669
670no_sun4e_here:
671 ld [%g7 + 0x68], %o1
672 set sun4e_notsup, %o0
673 call %o1
674 nop
675 b halt_me
676 nop
677
678 __INITDATA
679
680sun4u_1:
681 .asciz "finddevice"
682 .align 4
683sun4u_2:
684 .asciz "/chosen"
685 .align 4
686sun4u_3:
687 .asciz "getprop"
688 .align 4
689sun4u_4:
690 .asciz "stdout"
691 .align 4
692sun4u_5:
693 .asciz "write"
694 .align 4
695sun4u_6:
696 .asciz "\n\rOn sun4u you have to use sparc64 kernel\n\rand not a sparc32 version\n\r\n\r"
697sun4u_6e:
698 .align 4
699sun4u_7:
700 .asciz "exit"
701 .align 8
702sun4u_a1:
703 .word 0, sun4u_1, 0, 1, 0, 1, 0, sun4u_2, 0
704sun4u_r1:
705 .word 0
706sun4u_a2:
707 .word 0, sun4u_3, 0, 4, 0, 1, 0
708sun4u_i2:
709 .word 0, 0, sun4u_4, 0, sun4u_1, 0, 8, 0
710sun4u_r2:
711 .word 0
712sun4u_a3:
713 .word 0, sun4u_5, 0, 3, 0, 1, 0
714sun4u_i3:
715 .word 0, 0, sun4u_6, 0, sun4u_6e - sun4u_6 - 1, 0
716sun4u_r3:
717 .word 0
718sun4u_a4:
719 .word 0, sun4u_7, 0, 0, 0, 0
720sun4u_r4:
721
722 __INIT
723no_sun4u_here:
724 set sun4u_a1, %o0
725 set current_pc, %l2
726 cmp %l2, %g3
727 be 1f
728 mov %o4, %l0
729 sub %g3, %l2, %l6
730 add %o0, %l6, %o0
731 mov %o0, %l4
732 mov sun4u_r4 - sun4u_a1, %l3
733 ld [%l4], %l5
7342:
735 add %l4, 4, %l4
736 cmp %l5, %l2
737 add %l5, %l6, %l5
738 bgeu,a 3f
739 st %l5, [%l4 - 4]
7403:
741 subcc %l3, 4, %l3
742 bne 2b
743 ld [%l4], %l5
7441:
745 call %l0
746 mov %o0, %l1
747
748 ld [%l1 + (sun4u_r1 - sun4u_a1)], %o1
749 add %l1, (sun4u_a2 - sun4u_a1), %o0
750 call %l0
751 st %o1, [%o0 + (sun4u_i2 - sun4u_a2)]
752
753 ld [%l1 + (sun4u_1 - sun4u_a1)], %o1
754 add %l1, (sun4u_a3 - sun4u_a1), %o0
755 call %l0
756 st %o1, [%o0 + (sun4u_i3 - sun4u_a3)]
757
758 call %l0
759 add %l1, (sun4u_a4 - sun4u_a1), %o0
760
761 /* Not reached */
762halt_me:
763 ld [%g7 + 0x74], %o0
764 call %o0 ! Get us out of here...
765 nop ! Apparently Solaris is better.
766
767/* Ok, now we continue in the .data/.text sections */
768
769 .data
770 .align 4
771
772/*
773 * Fill up the prom vector, note in particular the kind first element,
774 * no joke. I don't need all of them in here as the entire prom vector
775 * gets initialized in c-code so all routines can use it.
776 */
777
778prom_vector_p:
779 .word 0
780
781/* We calculate the following at boot time, window fills/spills and trap entry
782 * code uses these to keep track of the register windows.
783 */
784
785 .align 4
786 .globl nwindows
787 .globl nwindowsm1
788nwindows:
789 .word 8
790nwindowsm1:
791 .word 7
792
793/* Boot time debugger vector value. We need this later on. */
794
795 .align 4
796 .globl linux_dbvec
797linux_dbvec:
798 .word 0
799 .word 0
800
801 .align 8
802
803 .globl lvl14_save
804lvl14_save:
805 .word 0
806 .word 0
807 .word 0
808 .word 0
809 .word t_irq14
810
811 .section ".fixup",#alloc,#execinstr
812 .globl __ret_efault
813__ret_efault:
814 ret
815 restore %g0, -EFAULT, %o0
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * head.S: The initial boot code for the Sparc port of Linux.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1995,1999 Pete Zaitcev (zaitcev@yahoo.com)
7 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 * Copyright (C) 1997 Michael A. Griffith (grif@acm.org)
10 *
11 * CompactPCI platform by Eric Brower, 1999.
12 */
13
14#include <linux/export.h>
15#include <linux/version.h>
16#include <linux/init.h>
17
18#include <asm/head.h>
19#include <asm/asi.h>
20#include <asm/contregs.h>
21#include <asm/ptrace.h>
22#include <asm/psr.h>
23#include <asm/page.h>
24#include <asm/kdebug.h>
25#include <asm/winmacro.h>
26#include <asm/thread_info.h> /* TI_UWINMASK */
27#include <asm/errno.h>
28#include <asm/pgtable.h> /* PGDIR_SHIFT */
29
30 .data
31/* The following are used with the prom_vector node-ops to figure out
32 * the cpu-type
33 */
34 .align 4
35 .globl cputypval
36cputypval:
37 .asciz "sun4m"
38 .ascii " "
39
40/* Tested on SS-5, SS-10 */
41 .align 4
42cputypvar:
43 .asciz "compatible"
44
45 .align 4
46
47notsup:
48 .asciz "Sparc-Linux sun4/sun4c or MMU-less not supported\n\n"
49 .align 4
50
51sun4e_notsup:
52 .asciz "Sparc-Linux sun4e support does not exist\n\n"
53 .align 4
54
55/* The trap-table - located in the __HEAD section */
56#include "ttable_32.S"
57
58 .align PAGE_SIZE
59
60/* This was the only reasonable way I could think of to properly align
61 * these page-table data structures.
62 */
63 .globl empty_zero_page
64empty_zero_page: .skip PAGE_SIZE
65EXPORT_SYMBOL(empty_zero_page)
66
67 .global root_flags
68 .global ram_flags
69 .global root_dev
70 .global sparc_ramdisk_image
71 .global sparc_ramdisk_size
72
73/* This stuff has to be in sync with SILO and other potential boot loaders
74 * Fields should be kept upward compatible and whenever any change is made,
75 * HdrS version should be incremented.
76 */
77 .ascii "HdrS"
78 .word LINUX_VERSION_CODE
79 .half 0x0203 /* HdrS version */
80root_flags:
81 .half 1
82root_dev:
83 .half 0
84ram_flags:
85 .half 0
86sparc_ramdisk_image:
87 .word 0
88sparc_ramdisk_size:
89 .word 0
90 .word reboot_command
91 .word 0, 0, 0
92 .word _end
93
94/* Cool, here we go. Pick up the romvec pointer in %o0 and stash it in
95 * %g7 and at prom_vector_p. And also quickly check whether we are on
96 * a v0, v2, or v3 prom.
97 */
98gokernel:
99 /* Ok, it's nice to know, as early as possible, if we
100 * are already mapped where we expect to be in virtual
101 * memory. The Solaris /boot elf format bootloader
102 * will peek into our elf header and load us where
103 * we want to be, otherwise we have to re-map.
104 *
105 * Some boot loaders don't place the jmp'rs address
106 * in %o7, so we do a pc-relative call to a local
107 * label, then see what %o7 has.
108 */
109
110 mov %o7, %g4 ! Save %o7
111
112 /* Jump to it, and pray... */
113current_pc:
114 call 1f
115 nop
116
1171:
118 mov %o7, %g3
119
120 tst %o0
121 bne 2f
122 mov %g4, %o7 /* Previous %o7. */
123 sethi %hi(no_sun4u_here), %l1
124 jmpl %l1 + %lo(no_sun4u_here), %g0
125 nop
1262:
127 mov %o0, %l0 ! stash away romvec
128 mov %o0, %g7 ! put it here too
129 mov %o1, %l1 ! stash away debug_vec too
130
131 /* Ok, let's check out our run time program counter. */
132 set current_pc, %g5
133 cmp %g3, %g5
134 be already_mapped
135 nop
136
137 /* %l6 will hold the offset we have to subtract
138 * from absolute symbols in order to access areas
139 * in our own image. If already mapped this is
140 * just plain zero, else it is KERNBASE.
141 */
142 set KERNBASE, %l6
143 b copy_prom_lvl14
144 nop
145
146already_mapped:
147 mov 0, %l6
148
149 /* Copy over the Prom's level 14 clock handler. */
150copy_prom_lvl14:
151#if 1
152 /* DJHR
153 * preserve our linked/calculated instructions
154 */
155 set lvl14_save, %g1
156 set t_irq14, %g3
157 sub %g1, %l6, %g1 ! translate to physical
158 sub %g3, %l6, %g3 ! translate to physical
159 ldd [%g3], %g4
160 std %g4, [%g1]
161 ldd [%g3+8], %g4
162 std %g4, [%g1+8]
163#endif
164 rd %tbr, %g1
165 andn %g1, 0xfff, %g1 ! proms trap table base
166 or %g0, (0x1e<<4), %g2 ! offset to lvl14 intr
167 or %g1, %g2, %g2
168 set t_irq14, %g3
169 sub %g3, %l6, %g3
170 ldd [%g2], %g4
171 std %g4, [%g3]
172 ldd [%g2 + 0x8], %g4
173 std %g4, [%g3 + 0x8] ! Copy proms handler
174
175/* DON'T TOUCH %l0 thru %l5 in these remapping routines,
176 * we need their values afterwards!
177 */
178
179 /* Now check whether we are already mapped, if we
180 * are we can skip all this garbage coming up.
181 */
182copy_prom_done:
183 cmp %l6, 0
184 be go_to_highmem ! this will be a nop then
185 nop
186
187 /* Validate that we are in fact running on an
188 * SRMMU based cpu.
189 */
190 set 0x4000, %g6
191 cmp %g7, %g6
192 bne not_a_sun4
193 nop
194
195halt_notsup:
196 ld [%g7 + 0x68], %o1
197 set notsup, %o0
198 sub %o0, %l6, %o0
199 call %o1
200 nop
201 sethi %hi(halt_me), %o0
202 jmpl %o0 + %lo(halt_me), %g0
203 nop
204
205not_a_sun4:
206 /* It looks like this is a machine we support.
207 * Now find out what MMU we are dealing with
208 * LEON - identified by the psr.impl field
209 * Viking - identified by the psr.impl field
210 * In all other cases a sun4m srmmu.
211 * We check that the MMU is enabled in all cases.
212 */
213
214 /* Check if this is a LEON CPU */
215 rd %psr, %g3
216 srl %g3, PSR_IMPL_SHIFT, %g3
217 and %g3, PSR_IMPL_SHIFTED_MASK, %g3
218 cmp %g3, PSR_IMPL_LEON
219 be leon_remap /* It is a LEON - jump */
220 nop
221
222 /* Sanity-check, is MMU enabled */
223 lda [%g0] ASI_M_MMUREGS, %g1
224 andcc %g1, 1, %g0
225 be halt_notsup
226 nop
227
228 /* Check for a viking (TI) module. */
229 cmp %g3, PSR_IMPL_TI
230 bne srmmu_not_viking
231 nop
232
233 /* Figure out what kind of viking we are on.
234 * We need to know if we have to play with the
235 * AC bit and disable traps or not.
236 */
237
238 /* I've only seen MicroSparc's on SparcClassics with this
239 * bit set.
240 */
241 set 0x800, %g2
242 lda [%g0] ASI_M_MMUREGS, %g3 ! peek in the control reg
243 and %g2, %g3, %g3
244 subcc %g3, 0x0, %g0
245 bnz srmmu_not_viking ! is in mbus mode
246 nop
247
248 rd %psr, %g3 ! DO NOT TOUCH %g3
249 andn %g3, PSR_ET, %g2
250 wr %g2, 0x0, %psr
251 WRITE_PAUSE
252
253 /* Get context table pointer, then convert to
254 * a physical address, which is 36 bits.
255 */
256 set AC_M_CTPR, %g4
257 lda [%g4] ASI_M_MMUREGS, %g4
258 sll %g4, 0x4, %g4 ! We use this below
259 ! DO NOT TOUCH %g4
260
261 /* Set the AC bit in the Viking's MMU control reg. */
262 lda [%g0] ASI_M_MMUREGS, %g5 ! DO NOT TOUCH %g5
263 set 0x8000, %g6 ! AC bit mask
264 or %g5, %g6, %g6 ! Or it in...
265 sta %g6, [%g0] ASI_M_MMUREGS ! Close your eyes...
266
267 /* Grrr, why does it seem like every other load/store
268 * on the sun4m is in some ASI space...
269 * Fine with me, let's get the pointer to the level 1
270 * page table directory and fetch its entry.
271 */
272 lda [%g4] ASI_M_BYPASS, %o1 ! This is a level 1 ptr
273 srl %o1, 0x4, %o1 ! Clear low 4 bits
274 sll %o1, 0x8, %o1 ! Make physical
275
276 /* Ok, pull in the PTD. */
277 lda [%o1] ASI_M_BYPASS, %o2 ! This is the 0x0 16MB pgd
278
279 /* Calculate to KERNBASE entry. */
280 add %o1, KERNBASE >> (PGDIR_SHIFT - 2), %o3
281
282 /* Poke the entry into the calculated address. */
283 sta %o2, [%o3] ASI_M_BYPASS
284
285 /* I don't get it Sun, if you engineered all these
286 * boot loaders and the PROM (thank you for the debugging
287 * features btw) why did you not have them load kernel
288 * images up in high address space, since this is necessary
289 * for ABI compliance anyways? Does this low-mapping provide
290 * enhanced interoperability?
291 *
292 * "The PROM is the computer."
293 */
294
295 /* Ok, restore the MMU control register we saved in %g5 */
296 sta %g5, [%g0] ASI_M_MMUREGS ! POW... ouch
297
298 /* Turn traps back on. We saved it in %g3 earlier. */
299 wr %g3, 0x0, %psr ! tick tock, tick tock
300
301 /* Now we burn precious CPU cycles due to bad engineering. */
302 WRITE_PAUSE
303
304 /* Wow, all that just to move a 32-bit value from one
305 * place to another... Jump to high memory.
306 */
307 b go_to_highmem
308 nop
309
310srmmu_not_viking:
311 /* This works on viking's in Mbus mode and all
312 * other MBUS modules. It is virtually the same as
313 * the above madness sans turning traps off and flipping
314 * the AC bit.
315 */
316 set AC_M_CTPR, %g1
317 lda [%g1] ASI_M_MMUREGS, %g1 ! get ctx table ptr
318 sll %g1, 0x4, %g1 ! make physical addr
319 lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table
320 srl %g1, 0x4, %g1
321 sll %g1, 0x8, %g1 ! make phys addr for l1 tbl
322
323 lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0
324 add %g1, KERNBASE >> (PGDIR_SHIFT - 2), %g3
325 sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry
326 b go_to_highmem
327 nop ! wheee....
328
329
330leon_remap:
331 /* Sanity-check, is MMU enabled */
332 lda [%g0] ASI_LEON_MMUREGS, %g1
333 andcc %g1, 1, %g0
334 be halt_notsup
335 nop
336
337 /* Same code as in the srmmu_not_viking case,
338 * with the LEON ASI for mmuregs
339 */
340 set AC_M_CTPR, %g1
341 lda [%g1] ASI_LEON_MMUREGS, %g1 ! get ctx table ptr
342 sll %g1, 0x4, %g1 ! make physical addr
343 lda [%g1] ASI_M_BYPASS, %g1 ! ptr to level 1 pg_table
344 srl %g1, 0x4, %g1
345 sll %g1, 0x8, %g1 ! make phys addr for l1 tbl
346
347 lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0
348 add %g1, KERNBASE >> (PGDIR_SHIFT - 2), %g3
349 sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry
350 b go_to_highmem
351 nop ! wheee....
352
353/* Now do a non-relative jump so that PC is in high-memory */
354go_to_highmem:
355 set execute_in_high_mem, %g1
356 jmpl %g1, %g0
357 nop
358
359/* The code above should be at beginning and we have to take care about
360 * short jumps, as branching to .init.text section from .text is usually
361 * impossible */
362 __INIT
363/* Acquire boot time privileged register values, this will help debugging.
364 * I figure out and store nwindows and nwindowsm1 later on.
365 */
366execute_in_high_mem:
367 mov %l0, %o0 ! put back romvec
368 mov %l1, %o1 ! and debug_vec
369
370 sethi %hi(prom_vector_p), %g1
371 st %o0, [%g1 + %lo(prom_vector_p)]
372
373 sethi %hi(linux_dbvec), %g1
374 st %o1, [%g1 + %lo(linux_dbvec)]
375
376 /* Get the machine type via the romvec
377 * getprops node operation
378 */
379 add %g7, 0x1c, %l1
380 ld [%l1], %l0
381 ld [%l0], %l0
382 call %l0
383 or %g0, %g0, %o0 ! next_node(0) = first_node
384 or %o0, %g0, %g6
385
386 sethi %hi(cputypvar), %o1 ! First node has cpu-arch
387 or %o1, %lo(cputypvar), %o1
388 sethi %hi(cputypval), %o2 ! information, the string
389 or %o2, %lo(cputypval), %o2
390 ld [%l1], %l0 ! 'compatible' tells
391 ld [%l0 + 0xc], %l0 ! that we want 'sun4x' where
392 call %l0 ! x is one of 'm', 'd' or 'e'.
393 nop ! %o2 holds pointer
394 ! to a buf where above string
395 ! will get stored by the prom.
396
397
398 /* Check value of "compatible" property.
399 * "value" => "model"
400 * leon => sparc_leon
401 * sun4m => sun4m
402 * sun4s => sun4m
403 * sun4d => sun4d
404 * sun4e => "no_sun4e_here"
405 * '*' => "no_sun4u_here"
406 * Check single letters only
407 */
408
409 set cputypval, %o2
410 /* If cputypval[0] == 'l' (lower case letter L) this is leon */
411 ldub [%o2], %l1
412 cmp %l1, 'l'
413 be leon_init
414 nop
415
416 /* Check cputypval[4] to find the sun model */
417 ldub [%o2 + 0x4], %l1
418
419 cmp %l1, 'm'
420 be sun4m_init
421 cmp %l1, 's'
422 be sun4m_init
423 cmp %l1, 'd'
424 be sun4d_init
425 cmp %l1, 'e'
426 be no_sun4e_here ! Could be a sun4e.
427 nop
428 b no_sun4u_here ! AIEEE, a V9 sun4u... Get our BIG BROTHER kernel :))
429 nop
430
431leon_init:
432 /* LEON CPU - set boot_cpu_id */
433 sethi %hi(boot_cpu_id), %g2 ! boot-cpu index
434
435#ifdef CONFIG_SMP
436 ldub [%g2 + %lo(boot_cpu_id)], %g1
437 cmp %g1, 0xff ! unset means first CPU
438 be 1f
439 sethi %hi(leon_smp_cpu_startup), %g1
440 jmpl %g1 + %lo(leon_smp_cpu_startup), %g0
441 nop
4421:
443#endif
444 /* Get CPU-ID from most significant 4-bit of ASR17 */
445 rd %asr17, %g1
446 srl %g1, 28, %g1
447
448 /* Update boot_cpu_id only on boot cpu */
449 stub %g1, [%g2 + %lo(boot_cpu_id)]
450
451 ba continue_boot
452 nop
453
454/* CPUID in bootbus can be found at PA 0xff0140000 */
455#define SUN4D_BOOTBUS_CPUID 0xf0140000
456
457sun4d_init:
458 /* Need to patch call to handler_irq */
459 set patch_handler_irq, %g4
460 set sun4d_handler_irq, %g5
461 sethi %hi(0x40000000), %g3 ! call
462 sub %g5, %g4, %g5
463 srl %g5, 2, %g5
464 or %g5, %g3, %g5
465 st %g5, [%g4]
466
467#ifdef CONFIG_SMP
468 /* Get our CPU id out of bootbus */
469 set SUN4D_BOOTBUS_CPUID, %g3
470 lduba [%g3] ASI_M_CTL, %g3
471 and %g3, 0xf8, %g3
472 srl %g3, 3, %g4
473 sta %g4, [%g0] ASI_M_VIKING_TMP1
474 sethi %hi(boot_cpu_id), %g5
475 stb %g4, [%g5 + %lo(boot_cpu_id)]
476#endif
477
478 /* Fall through to sun4m_init */
479
480sun4m_init:
481/* Ok, the PROM could have done funny things and apple cider could still
482 * be sitting in the fault status/address registers. Read them all to
483 * clear them so we don't get magic faults later on.
484 */
485/* This sucks, apparently this makes Vikings call prom panic, will fix later */
4862:
487 rd %psr, %o1
488 srl %o1, PSR_IMPL_SHIFT, %o1 ! Get a type of the CPU
489
490 subcc %o1, PSR_IMPL_TI, %g0 ! TI: Viking or MicroSPARC
491 be continue_boot
492 nop
493
494 set AC_M_SFSR, %o0
495 lda [%o0] ASI_M_MMUREGS, %g0
496 set AC_M_SFAR, %o0
497 lda [%o0] ASI_M_MMUREGS, %g0
498
499 /* Fujitsu MicroSPARC-II has no asynchronous flavors of FARs */
500 subcc %o1, 0, %g0
501 be continue_boot
502 nop
503
504 set AC_M_AFSR, %o0
505 lda [%o0] ASI_M_MMUREGS, %g0
506 set AC_M_AFAR, %o0
507 lda [%o0] ASI_M_MMUREGS, %g0
508 nop
509
510
511continue_boot:
512
513/* Aieee, now set PC and nPC, enable traps, give ourselves a stack and it's
514 * show-time!
515 */
516 /* Turn on Supervisor, EnableFloating, and all the PIL bits.
517 * Also puts us in register window zero with traps off.
518 */
519 set (PSR_PS | PSR_S | PSR_PIL | PSR_EF), %g2
520 wr %g2, 0x0, %psr
521 WRITE_PAUSE
522
523 /* I want a kernel stack NOW! */
524 set init_thread_union, %g1
525 set (THREAD_SIZE - STACKFRAME_SZ - TRACEREG_SZ), %g2
526 add %g1, %g2, %sp
527 mov 0, %fp /* And for good luck */
528
529 /* Zero out our BSS section. */
530 set __bss_start , %o0 ! First address of BSS
531 set _end , %o1 ! Last address of BSS
532 add %o0, 0x1, %o0
5331:
534 stb %g0, [%o0]
535 subcc %o0, %o1, %g0
536 bl 1b
537 add %o0, 0x1, %o0
538
539 /* If boot_cpu_id has not been setup by machine specific
540 * init-code above we default it to zero.
541 */
542 sethi %hi(boot_cpu_id), %g2
543 ldub [%g2 + %lo(boot_cpu_id)], %g3
544 cmp %g3, 0xff
545 bne 1f
546 nop
547 mov %g0, %g3
548 stub %g3, [%g2 + %lo(boot_cpu_id)]
549
5501: sll %g3, 2, %g3
551
552 /* Initialize the uwinmask value for init task just in case.
553 * But first make current_set[boot_cpu_id] point to something useful.
554 */
555 set init_thread_union, %g6
556 set current_set, %g2
557#ifdef CONFIG_SMP
558 st %g6, [%g2]
559 add %g2, %g3, %g2
560#endif
561 st %g6, [%g2]
562
563 st %g0, [%g6 + TI_UWINMASK]
564
565/* Compute NWINDOWS and stash it away. Now uses %wim trick explained
566 * in the V8 manual. Ok, this method seems to work, Sparc is cool...
567 * No, it doesn't work, have to play the save/readCWP/restore trick.
568 */
569
570 wr %g0, 0x0, %wim ! so we do not get a trap
571 WRITE_PAUSE
572
573 save
574
575 rd %psr, %g3
576
577 restore
578
579 and %g3, 0x1f, %g3
580 add %g3, 0x1, %g3
581
582 mov 2, %g1
583 wr %g1, 0x0, %wim ! make window 1 invalid
584 WRITE_PAUSE
585
586 cmp %g3, 0x7
587 bne 2f
588 nop
589
590 /* Adjust our window handling routines to
591 * do things correctly on 7 window Sparcs.
592 */
593
594#define PATCH_INSN(src, dest) \
595 set src, %g5; \
596 set dest, %g2; \
597 ld [%g5], %g4; \
598 st %g4, [%g2];
599
600 /* Patch for window spills... */
601 PATCH_INSN(spnwin_patch1_7win, spnwin_patch1)
602 PATCH_INSN(spnwin_patch2_7win, spnwin_patch2)
603 PATCH_INSN(spnwin_patch3_7win, spnwin_patch3)
604
605 /* Patch for window fills... */
606 PATCH_INSN(fnwin_patch1_7win, fnwin_patch1)
607 PATCH_INSN(fnwin_patch2_7win, fnwin_patch2)
608
609 /* Patch for trap entry setup... */
610 PATCH_INSN(tsetup_7win_patch1, tsetup_patch1)
611 PATCH_INSN(tsetup_7win_patch2, tsetup_patch2)
612 PATCH_INSN(tsetup_7win_patch3, tsetup_patch3)
613 PATCH_INSN(tsetup_7win_patch4, tsetup_patch4)
614 PATCH_INSN(tsetup_7win_patch5, tsetup_patch5)
615 PATCH_INSN(tsetup_7win_patch6, tsetup_patch6)
616
617 /* Patch for returning from traps... */
618 PATCH_INSN(rtrap_7win_patch1, rtrap_patch1)
619 PATCH_INSN(rtrap_7win_patch2, rtrap_patch2)
620 PATCH_INSN(rtrap_7win_patch3, rtrap_patch3)
621 PATCH_INSN(rtrap_7win_patch4, rtrap_patch4)
622 PATCH_INSN(rtrap_7win_patch5, rtrap_patch5)
623
624 /* Patch for killing user windows from the register file. */
625 PATCH_INSN(kuw_patch1_7win, kuw_patch1)
626
627 /* Now patch the kernel window flush sequences.
628 * This saves 2 traps on every switch and fork.
629 */
630 set 0x01000000, %g4
631 set flush_patch_one, %g5
632 st %g4, [%g5 + 0x18]
633 st %g4, [%g5 + 0x1c]
634 set flush_patch_two, %g5
635 st %g4, [%g5 + 0x18]
636 st %g4, [%g5 + 0x1c]
637 set flush_patch_three, %g5
638 st %g4, [%g5 + 0x18]
639 st %g4, [%g5 + 0x1c]
640 set flush_patch_four, %g5
641 st %g4, [%g5 + 0x18]
642 st %g4, [%g5 + 0x1c]
643 set flush_patch_exception, %g5
644 st %g4, [%g5 + 0x18]
645 st %g4, [%g5 + 0x1c]
646 set flush_patch_switch, %g5
647 st %g4, [%g5 + 0x18]
648 st %g4, [%g5 + 0x1c]
649
6502:
651 sethi %hi(nwindows), %g4
652 st %g3, [%g4 + %lo(nwindows)] ! store final value
653 sub %g3, 0x1, %g3
654 sethi %hi(nwindowsm1), %g4
655 st %g3, [%g4 + %lo(nwindowsm1)]
656
657 /* Here we go, start using Linux's trap table... */
658 set trapbase, %g3
659 wr %g3, 0x0, %tbr
660 WRITE_PAUSE
661
662 /* Finally, turn on traps so that we can call c-code. */
663 rd %psr, %g3
664 wr %g3, 0x0, %psr
665 WRITE_PAUSE
666
667 wr %g3, PSR_ET, %psr
668 WRITE_PAUSE
669
670 /* Call sparc32_start_kernel(struct linux_romvec *rp) */
671 sethi %hi(prom_vector_p), %g5
672 ld [%g5 + %lo(prom_vector_p)], %o0
673 call sparc32_start_kernel
674 nop
675
676 /* We should not get here. */
677 call halt_me
678 nop
679
680no_sun4e_here:
681 ld [%g7 + 0x68], %o1
682 set sun4e_notsup, %o0
683 call %o1
684 nop
685 b halt_me
686 nop
687
688 __INITDATA
689
690sun4u_1:
691 .asciz "finddevice"
692 .align 4
693sun4u_2:
694 .asciz "/chosen"
695 .align 4
696sun4u_3:
697 .asciz "getprop"
698 .align 4
699sun4u_4:
700 .asciz "stdout"
701 .align 4
702sun4u_5:
703 .asciz "write"
704 .align 4
705sun4u_6:
706 .asciz "\n\rOn sun4u you have to use sparc64 kernel\n\rand not a sparc32 version\n\r\n\r"
707sun4u_6e:
708 .align 4
709sun4u_7:
710 .asciz "exit"
711 .align 8
712sun4u_a1:
713 .word 0, sun4u_1, 0, 1, 0, 1, 0, sun4u_2, 0
714sun4u_r1:
715 .word 0
716sun4u_a2:
717 .word 0, sun4u_3, 0, 4, 0, 1, 0
718sun4u_i2:
719 .word 0, 0, sun4u_4, 0, sun4u_1, 0, 8, 0
720sun4u_r2:
721 .word 0
722sun4u_a3:
723 .word 0, sun4u_5, 0, 3, 0, 1, 0
724sun4u_i3:
725 .word 0, 0, sun4u_6, 0, sun4u_6e - sun4u_6 - 1, 0
726sun4u_r3:
727 .word 0
728sun4u_a4:
729 .word 0, sun4u_7, 0, 0, 0, 0
730sun4u_r4:
731
732 __INIT
733no_sun4u_here:
734 set sun4u_a1, %o0
735 set current_pc, %l2
736 cmp %l2, %g3
737 be 1f
738 mov %o4, %l0
739 sub %g3, %l2, %l6
740 add %o0, %l6, %o0
741 mov %o0, %l4
742 mov sun4u_r4 - sun4u_a1, %l3
743 ld [%l4], %l5
7442:
745 add %l4, 4, %l4
746 cmp %l5, %l2
747 add %l5, %l6, %l5
748 bgeu,a 3f
749 st %l5, [%l4 - 4]
7503:
751 subcc %l3, 4, %l3
752 bne 2b
753 ld [%l4], %l5
7541:
755 call %l0
756 mov %o0, %l1
757
758 ld [%l1 + (sun4u_r1 - sun4u_a1)], %o1
759 add %l1, (sun4u_a2 - sun4u_a1), %o0
760 call %l0
761 st %o1, [%o0 + (sun4u_i2 - sun4u_a2)]
762
763 ld [%l1 + (sun4u_1 - sun4u_a1)], %o1
764 add %l1, (sun4u_a3 - sun4u_a1), %o0
765 call %l0
766 st %o1, [%o0 + (sun4u_i3 - sun4u_a3)]
767
768 call %l0
769 add %l1, (sun4u_a4 - sun4u_a1), %o0
770
771 /* Not reached */
772halt_me:
773 ld [%g7 + 0x74], %o0
774 call %o0 ! Get us out of here...
775 nop ! Apparently Solaris is better.
776
777/* Ok, now we continue in the .data/.text sections */
778
779 .data
780 .align 4
781
782/*
783 * Fill up the prom vector, note in particular the kind first element,
784 * no joke. I don't need all of them in here as the entire prom vector
785 * gets initialized in c-code so all routines can use it.
786 */
787
788prom_vector_p:
789 .word 0
790
791/* We calculate the following at boot time, window fills/spills and trap entry
792 * code uses these to keep track of the register windows.
793 */
794
795 .align 4
796 .globl nwindows
797 .globl nwindowsm1
798nwindows:
799 .word 8
800nwindowsm1:
801 .word 7
802
803/* Boot time debugger vector value. We need this later on. */
804
805 .align 4
806 .globl linux_dbvec
807linux_dbvec:
808 .word 0
809 .word 0
810
811 .align 8
812
813 .globl lvl14_save
814lvl14_save:
815 .word 0
816 .word 0
817 .word 0
818 .word 0
819 .word t_irq14