1/*
   2 *   ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
   3 *
   4 *      Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
   5 *                              Pilo Chambert <pilo.c@wanadoo.fr>
   6 *
   7 *      Thanks to :        Anders Torger <torger@ludd.luth.se>,
   8 *                         Henk Hesselink <henk@anda.nl>
   9 *                         for writing the digi96-driver 
  10 *                         and RME for all informations.
  11 *
  12 *   This program is free software; you can redistribute it and/or modify
  13 *   it under the terms of the GNU General Public License as published by
  14 *   the Free Software Foundation; either version 2 of the License, or
  15 *   (at your option) any later version.
  16 *
  17 *   This program is distributed in the hope that it will be useful,
  18 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 *   GNU General Public License for more details.
  21 *
  22 *   You should have received a copy of the GNU General Public License
  23 *   along with this program; if not, write to the Free Software
  24 *   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25 * 
  26 * 
  27 * ****************************************************************************
  28 * 
  29 * Note #1 "Sek'd models" ................................... martin 2002-12-07
  30 * 
  31 * Identical soundcards by Sek'd were labeled:
  32 * RME Digi 32     = Sek'd Prodif 32
  33 * RME Digi 32 Pro = Sek'd Prodif 96
  34 * RME Digi 32/8   = Sek'd Prodif Gold
  35 * 
  36 * ****************************************************************************
  37 * 
  38 * Note #2 "full duplex mode" ............................... martin 2002-12-07
  39 * 
  40 * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
  41 * in this mode. Rec data and play data are using the same buffer therefore. At
  42 * first you have got the playing bits in the buffer and then (after playing
  43 * them) they were overwitten by the captured sound of the CS8412/14. Both 
  44 * modes (play/record) are running harmonically hand in hand in the same buffer
  45 * and you have only one start bit plus one interrupt bit to control this 
  46 * paired action.
  47 * This is opposite to the latter rme96 where playing and capturing is totally
  48 * separated and so their full duplex mode is supported by alsa (using two 
  49 * start bits and two interrupts for two different buffers). 
  50 * But due to the wrong sequence of playing and capturing ALSA shows no solved
  51 * full duplex support for the rme32 at the moment. That's bad, but I'm not
  52 * able to solve it. Are you motivated enough to solve this problem now? Your
  53 * patch would be welcome!
  54 * 
  55 * ****************************************************************************
  56 *
  57 * "The story after the long seeking" -- tiwai
  58 *
  59 * Ok, the situation regarding the full duplex is now improved a bit.
  60 * In the fullduplex mode (given by the module parameter), the hardware buffer
  61 * is split to halves for read and write directions at the DMA pointer.
  62 * That is, the half above the current DMA pointer is used for write, and
  63 * the half below is used for read.  To mangle this strange behavior, an
  64 * software intermediate buffer is introduced.  This is, of course, not good
  65 * from the viewpoint of the data transfer efficiency.  However, this allows
  66 * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
  67 *
  68 * ****************************************************************************
  69 */
  70
  71
  72#include <linux/delay.h>
  73#include <linux/gfp.h>
  74#include <linux/init.h>
  75#include <linux/interrupt.h>
  76#include <linux/pci.h>
  77#include <linux/module.h>
 
  78
  79#include <sound/core.h>
  80#include <sound/info.h>
  81#include <sound/control.h>
  82#include <sound/pcm.h>
  83#include <sound/pcm_params.h>
  84#include <sound/pcm-indirect.h>
  85#include <sound/asoundef.h>
  86#include <sound/initval.h>
  87
  88#include <asm/io.h>
  89
  90static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	/* Index 0-MAX */
  91static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	/* ID for this card */
  92static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;	/* Enable this card */
  93static bool fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
  94
  95module_param_array(index, int, NULL, 0444);
  96MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
  97module_param_array(id, charp, NULL, 0444);
  98MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
  99module_param_array(enable, bool, NULL, 0444);
 100MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
 101module_param_array(fullduplex, bool, NULL, 0444);
 102MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
 103MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
 104MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
 105MODULE_LICENSE("GPL");
 106MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
 107
 108/* Defines for RME Digi32 series */
 109#define RME32_SPDIF_NCHANNELS 2
 110
 111/* Playback and capture buffer size */
 112#define RME32_BUFFER_SIZE 0x20000
 113
 114/* IO area size */
 115#define RME32_IO_SIZE 0x30000
 116
 117/* IO area offsets */
 118#define RME32_IO_DATA_BUFFER        0x0
 119#define RME32_IO_CONTROL_REGISTER   0x20000
 120#define RME32_IO_GET_POS            0x20000
 121#define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
 122#define RME32_IO_RESET_POS          0x20100
 123
 124/* Write control register bits */
 125#define RME32_WCR_START     (1 << 0)    /* startbit */
 126#define RME32_WCR_MONO      (1 << 1)    /* 0=stereo, 1=mono
 127                                           Setting the whole card to mono
 128                                           doesn't seem to be very useful.
 129                                           A software-solution can handle 
 130                                           full-duplex with one direction in
 131                                           stereo and the other way in mono. 
 132                                           So, the hardware should work all 
 133                                           the time in stereo! */
 134#define RME32_WCR_MODE24    (1 << 2)    /* 0=16bit, 1=32bit */
 135#define RME32_WCR_SEL       (1 << 3)    /* 0=input on output, 1=normal playback/capture */
 136#define RME32_WCR_FREQ_0    (1 << 4)    /* frequency (play) */
 137#define RME32_WCR_FREQ_1    (1 << 5)
 138#define RME32_WCR_INP_0     (1 << 6)    /* input switch */
 139#define RME32_WCR_INP_1     (1 << 7)
 140#define RME32_WCR_RESET     (1 << 8)    /* Reset address */
 141#define RME32_WCR_MUTE      (1 << 9)    /* digital mute for output */
 142#define RME32_WCR_PRO       (1 << 10)   /* 1=professional, 0=consumer */
 143#define RME32_WCR_DS_BM     (1 << 11)	/* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
 144#define RME32_WCR_ADAT      (1 << 12)	/* Adat Mode (only Adat-Version) */
 145#define RME32_WCR_AUTOSYNC  (1 << 13)   /* AutoSync */
 146#define RME32_WCR_PD        (1 << 14)	/* DAC Reset (only PRO-Version) */
 147#define RME32_WCR_EMP       (1 << 15)	/* 1=Emphasis on (only PRO-Version) */
 148
 149#define RME32_WCR_BITPOS_FREQ_0 4
 150#define RME32_WCR_BITPOS_FREQ_1 5
 151#define RME32_WCR_BITPOS_INP_0 6
 152#define RME32_WCR_BITPOS_INP_1 7
 153
 154/* Read control register bits */
 155#define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
 156#define RME32_RCR_LOCK      (1 << 23)   /* 1=locked, 0=not locked */
 157#define RME32_RCR_ERF       (1 << 26)   /* 1=Error, 0=no Error */
 158#define RME32_RCR_FREQ_0    (1 << 27)   /* CS841x frequency (record) */
 159#define RME32_RCR_FREQ_1    (1 << 28)
 160#define RME32_RCR_FREQ_2    (1 << 29)
 161#define RME32_RCR_KMODE     (1 << 30)   /* card mode: 1=PLL, 0=quartz */
 162#define RME32_RCR_IRQ       (1 << 31)   /* interrupt */
 163
 164#define RME32_RCR_BITPOS_F0 27
 165#define RME32_RCR_BITPOS_F1 28
 166#define RME32_RCR_BITPOS_F2 29
 167
 168/* Input types */
 169#define RME32_INPUT_OPTICAL 0
 170#define RME32_INPUT_COAXIAL 1
 171#define RME32_INPUT_INTERNAL 2
 172#define RME32_INPUT_XLR 3
 173
 174/* Clock modes */
 175#define RME32_CLOCKMODE_SLAVE 0
 176#define RME32_CLOCKMODE_MASTER_32 1
 177#define RME32_CLOCKMODE_MASTER_44 2
 178#define RME32_CLOCKMODE_MASTER_48 3
 179
 180/* Block sizes in bytes */
 181#define RME32_BLOCK_SIZE 8192
 182
 183/* Software intermediate buffer (max) size */
 184#define RME32_MID_BUFFER_SIZE (1024*1024)
 185
 186/* Hardware revisions */
 187#define RME32_32_REVISION 192
 188#define RME32_328_REVISION_OLD 100
 189#define RME32_328_REVISION_NEW 101
 190#define RME32_PRO_REVISION_WITH_8412 192
 191#define RME32_PRO_REVISION_WITH_8414 150
 192
 193
 194struct rme32 {
 195	spinlock_t lock;
 196	int irq;
 197	unsigned long port;
 198	void __iomem *iobase;
 199
 200	u32 wcreg;		/* cached write control register value */
 201	u32 wcreg_spdif;	/* S/PDIF setup */
 202	u32 wcreg_spdif_stream;	/* S/PDIF setup (temporary) */
 203	u32 rcreg;		/* cached read control register value */
 204
 205	u8 rev;			/* card revision number */
 206
 207	struct snd_pcm_substream *playback_substream;
 208	struct snd_pcm_substream *capture_substream;
 209
 210	int playback_frlog;	/* log2 of framesize */
 211	int capture_frlog;
 212
 213	size_t playback_periodsize;	/* in bytes, zero if not used */
 214	size_t capture_periodsize;	/* in bytes, zero if not used */
 215
 216	unsigned int fullduplex_mode;
 217	int running;
 218
 219	struct snd_pcm_indirect playback_pcm;
 220	struct snd_pcm_indirect capture_pcm;
 221
 222	struct snd_card *card;
 223	struct snd_pcm *spdif_pcm;
 224	struct snd_pcm *adat_pcm;
 225	struct pci_dev *pci;
 226	struct snd_kcontrol *spdif_ctl;
 227};
 228
 229static DEFINE_PCI_DEVICE_TABLE(snd_rme32_ids) = {
 230	{PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,},
 231	{PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,},
 232	{PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,},
 233	{0,}
 234};
 235
 236MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
 237
 238#define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
 239#define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
 240
 241static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream);
 242
 243static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream);
 244
 245static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
 246
 247static void snd_rme32_proc_init(struct rme32 * rme32);
 248
 249static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32);
 250
 251static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32)
 252{
 253	return (readl(rme32->iobase + RME32_IO_GET_POS)
 254		& RME32_RCR_AUDIO_ADDR_MASK);
 255}
 256
 257/* silence callback for halfduplex mode */
 258static int snd_rme32_playback_silence(struct snd_pcm_substream *substream, int channel,	/* not used (interleaved data) */
 259				      snd_pcm_uframes_t pos,
 260				      snd_pcm_uframes_t count)
 261{
 262	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 263	count <<= rme32->playback_frlog;
 264	pos <<= rme32->playback_frlog;
 265	memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
 266	return 0;
 267}
 268
 269/* copy callback for halfduplex mode */
 270static int snd_rme32_playback_copy(struct snd_pcm_substream *substream, int channel,	/* not used (interleaved data) */
 271				   snd_pcm_uframes_t pos,
 272				   void __user *src, snd_pcm_uframes_t count)
 273{
 274	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 275	count <<= rme32->playback_frlog;
 276	pos <<= rme32->playback_frlog;
 277	if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
 278			    src, count))
 279		return -EFAULT;
 280	return 0;
 281}
 282
 283/* copy callback for halfduplex mode */
 284static int snd_rme32_capture_copy(struct snd_pcm_substream *substream, int channel,	/* not used (interleaved data) */
 285				  snd_pcm_uframes_t pos,
 286				  void __user *dst, snd_pcm_uframes_t count)
 287{
 288	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 289	count <<= rme32->capture_frlog;
 290	pos <<= rme32->capture_frlog;
 291	if (copy_to_user_fromio(dst,
 292			    rme32->iobase + RME32_IO_DATA_BUFFER + pos,
 293			    count))
 294		return -EFAULT;
 295	return 0;
 296}
 297
 298/*
 299 * SPDIF I/O capabilities (half-duplex mode)
 300 */
 301static struct snd_pcm_hardware snd_rme32_spdif_info = {
 302	.info =		(SNDRV_PCM_INFO_MMAP_IOMEM |
 303			 SNDRV_PCM_INFO_MMAP_VALID |
 304			 SNDRV_PCM_INFO_INTERLEAVED | 
 305			 SNDRV_PCM_INFO_PAUSE |
 306			 SNDRV_PCM_INFO_SYNC_START),
 
 307	.formats =	(SNDRV_PCM_FMTBIT_S16_LE | 
 308			 SNDRV_PCM_FMTBIT_S32_LE),
 309	.rates =	(SNDRV_PCM_RATE_32000 |
 310			 SNDRV_PCM_RATE_44100 | 
 311			 SNDRV_PCM_RATE_48000),
 312	.rate_min =	32000,
 313	.rate_max =	48000,
 314	.channels_min =	2,
 315	.channels_max =	2,
 316	.buffer_bytes_max = RME32_BUFFER_SIZE,
 317	.period_bytes_min = RME32_BLOCK_SIZE,
 318	.period_bytes_max = RME32_BLOCK_SIZE,
 319	.periods_min =	RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
 320	.periods_max =	RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
 321	.fifo_size =	0,
 322};
 323
 324/*
 325 * ADAT I/O capabilities (half-duplex mode)
 326 */
 327static struct snd_pcm_hardware snd_rme32_adat_info =
 328{
 329	.info =		     (SNDRV_PCM_INFO_MMAP_IOMEM |
 330			      SNDRV_PCM_INFO_MMAP_VALID |
 331			      SNDRV_PCM_INFO_INTERLEAVED |
 332			      SNDRV_PCM_INFO_PAUSE |
 333			      SNDRV_PCM_INFO_SYNC_START),
 
 334	.formats=            SNDRV_PCM_FMTBIT_S16_LE,
 335	.rates =             (SNDRV_PCM_RATE_44100 | 
 336			      SNDRV_PCM_RATE_48000),
 337	.rate_min =          44100,
 338	.rate_max =          48000,
 339	.channels_min =      8,
 340	.channels_max =	     8,
 341	.buffer_bytes_max =  RME32_BUFFER_SIZE,
 342	.period_bytes_min =  RME32_BLOCK_SIZE,
 343	.period_bytes_max =  RME32_BLOCK_SIZE,
 344	.periods_min =	    RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
 345	.periods_max =	    RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
 346	.fifo_size =	    0,
 347};
 348
 349/*
 350 * SPDIF I/O capabilities (full-duplex mode)
 351 */
 352static struct snd_pcm_hardware snd_rme32_spdif_fd_info = {
 353	.info =		(SNDRV_PCM_INFO_MMAP |
 354			 SNDRV_PCM_INFO_MMAP_VALID |
 355			 SNDRV_PCM_INFO_INTERLEAVED | 
 356			 SNDRV_PCM_INFO_PAUSE |
 357			 SNDRV_PCM_INFO_SYNC_START),
 
 358	.formats =	(SNDRV_PCM_FMTBIT_S16_LE | 
 359			 SNDRV_PCM_FMTBIT_S32_LE),
 360	.rates =	(SNDRV_PCM_RATE_32000 |
 361			 SNDRV_PCM_RATE_44100 | 
 362			 SNDRV_PCM_RATE_48000),
 363	.rate_min =	32000,
 364	.rate_max =	48000,
 365	.channels_min =	2,
 366	.channels_max =	2,
 367	.buffer_bytes_max = RME32_MID_BUFFER_SIZE,
 368	.period_bytes_min = RME32_BLOCK_SIZE,
 369	.period_bytes_max = RME32_BLOCK_SIZE,
 370	.periods_min =	2,
 371	.periods_max =	RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
 372	.fifo_size =	0,
 373};
 374
 375/*
 376 * ADAT I/O capabilities (full-duplex mode)
 377 */
 378static struct snd_pcm_hardware snd_rme32_adat_fd_info =
 379{
 380	.info =		     (SNDRV_PCM_INFO_MMAP |
 381			      SNDRV_PCM_INFO_MMAP_VALID |
 382			      SNDRV_PCM_INFO_INTERLEAVED |
 383			      SNDRV_PCM_INFO_PAUSE |
 384			      SNDRV_PCM_INFO_SYNC_START),
 
 385	.formats=            SNDRV_PCM_FMTBIT_S16_LE,
 386	.rates =             (SNDRV_PCM_RATE_44100 | 
 387			      SNDRV_PCM_RATE_48000),
 388	.rate_min =          44100,
 389	.rate_max =          48000,
 390	.channels_min =      8,
 391	.channels_max =	     8,
 392	.buffer_bytes_max =  RME32_MID_BUFFER_SIZE,
 393	.period_bytes_min =  RME32_BLOCK_SIZE,
 394	.period_bytes_max =  RME32_BLOCK_SIZE,
 395	.periods_min =	    2,
 396	.periods_max =	    RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
 397	.fifo_size =	    0,
 398};
 399
 400static void snd_rme32_reset_dac(struct rme32 *rme32)
 401{
 402        writel(rme32->wcreg | RME32_WCR_PD,
 403               rme32->iobase + RME32_IO_CONTROL_REGISTER);
 404        writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 405}
 406
 407static int snd_rme32_playback_getrate(struct rme32 * rme32)
 408{
 409	int rate;
 410
 411	rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
 412	       (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
 413	switch (rate) {
 414	case 1:
 415		rate = 32000;
 416		break;
 417	case 2:
 418		rate = 44100;
 419		break;
 420	case 3:
 421		rate = 48000;
 422		break;
 423	default:
 424		return -1;
 425	}
 426	return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
 427}
 428
 429static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat)
 430{
 431	int n;
 432
 433	*is_adat = 0;
 434	if (rme32->rcreg & RME32_RCR_LOCK) { 
 435                /* ADAT rate */
 436                *is_adat = 1;
 437	}
 438	if (rme32->rcreg & RME32_RCR_ERF) {
 439		return -1;
 440	}
 441
 442        /* S/PDIF rate */
 443	n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
 444		(((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
 445		(((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
 446
 447	if (RME32_PRO_WITH_8414(rme32))
 448		switch (n) {	/* supporting the CS8414 */
 449		case 0:
 450		case 1:
 451		case 2:
 452			return -1;
 453		case 3:
 454			return 96000;
 455		case 4:
 456			return 88200;
 457		case 5:
 458			return 48000;
 459		case 6:
 460			return 44100;
 461		case 7:
 462			return 32000;
 463		default:
 464			return -1;
 465			break;
 466		} 
 467	else
 468		switch (n) {	/* supporting the CS8412 */
 469		case 0:
 470			return -1;
 471		case 1:
 472			return 48000;
 473		case 2:
 474			return 44100;
 475		case 3:
 476			return 32000;
 477		case 4:
 478			return 48000;
 479		case 5:
 480			return 44100;
 481		case 6:
 482			return 44056;
 483		case 7:
 484			return 32000;
 485		default:
 486			break;
 487		}
 488	return -1;
 489}
 490
 491static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate)
 492{
 493        int ds;
 494
 495        ds = rme32->wcreg & RME32_WCR_DS_BM;
 496	switch (rate) {
 497	case 32000:
 498		rme32->wcreg &= ~RME32_WCR_DS_BM;
 499		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 
 500			~RME32_WCR_FREQ_1;
 501		break;
 502	case 44100:
 503		rme32->wcreg &= ~RME32_WCR_DS_BM;
 504		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & 
 505			~RME32_WCR_FREQ_0;
 506		break;
 507	case 48000:
 508		rme32->wcreg &= ~RME32_WCR_DS_BM;
 509		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 
 510			RME32_WCR_FREQ_1;
 511		break;
 512	case 64000:
 513		if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
 514			return -EINVAL;
 515		rme32->wcreg |= RME32_WCR_DS_BM;
 516		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 
 517			~RME32_WCR_FREQ_1;
 518		break;
 519	case 88200:
 520		if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
 521			return -EINVAL;
 522		rme32->wcreg |= RME32_WCR_DS_BM;
 523		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & 
 524			~RME32_WCR_FREQ_0;
 525		break;
 526	case 96000:
 527		if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
 528			return -EINVAL;
 529		rme32->wcreg |= RME32_WCR_DS_BM;
 530		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 
 531			RME32_WCR_FREQ_1;
 532		break;
 533	default:
 534		return -EINVAL;
 535	}
 536        if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
 537            (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
 538        {
 539                /* change to/from double-speed: reset the DAC (if available) */
 540                snd_rme32_reset_dac(rme32);
 541        } else {
 542                writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 543	}
 544	return 0;
 545}
 546
 547static int snd_rme32_setclockmode(struct rme32 * rme32, int mode)
 548{
 549	switch (mode) {
 550	case RME32_CLOCKMODE_SLAVE:
 551		/* AutoSync */
 552		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) & 
 553			~RME32_WCR_FREQ_1;
 554		break;
 555	case RME32_CLOCKMODE_MASTER_32:
 556		/* Internal 32.0kHz */
 557		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 
 558			~RME32_WCR_FREQ_1;
 559		break;
 560	case RME32_CLOCKMODE_MASTER_44:
 561		/* Internal 44.1kHz */
 562		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) | 
 563			RME32_WCR_FREQ_1;
 564		break;
 565	case RME32_CLOCKMODE_MASTER_48:
 566		/* Internal 48.0kHz */
 567		rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 
 568			RME32_WCR_FREQ_1;
 569		break;
 570	default:
 571		return -EINVAL;
 572	}
 573	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 574	return 0;
 575}
 576
 577static int snd_rme32_getclockmode(struct rme32 * rme32)
 578{
 579	return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
 580	    (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
 581}
 582
 583static int snd_rme32_setinputtype(struct rme32 * rme32, int type)
 584{
 585	switch (type) {
 586	case RME32_INPUT_OPTICAL:
 587		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) & 
 588			~RME32_WCR_INP_1;
 589		break;
 590	case RME32_INPUT_COAXIAL:
 591		rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) & 
 592			~RME32_WCR_INP_1;
 593		break;
 594	case RME32_INPUT_INTERNAL:
 595		rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) | 
 596			RME32_WCR_INP_1;
 597		break;
 598	case RME32_INPUT_XLR:
 599		rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) | 
 600			RME32_WCR_INP_1;
 601		break;
 602	default:
 603		return -EINVAL;
 604	}
 605	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 606	return 0;
 607}
 608
 609static int snd_rme32_getinputtype(struct rme32 * rme32)
 610{
 611	return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
 612	    (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
 613}
 614
 615static void
 616snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback)
 617{
 618	int frlog;
 619
 620	if (n_channels == 2) {
 621		frlog = 1;
 622	} else {
 623		/* assume 8 channels */
 624		frlog = 3;
 625	}
 626	if (is_playback) {
 627		frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
 628		rme32->playback_frlog = frlog;
 629	} else {
 630		frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
 631		rme32->capture_frlog = frlog;
 632	}
 633}
 634
 635static int snd_rme32_setformat(struct rme32 * rme32, int format)
 636{
 637	switch (format) {
 638	case SNDRV_PCM_FORMAT_S16_LE:
 639		rme32->wcreg &= ~RME32_WCR_MODE24;
 640		break;
 641	case SNDRV_PCM_FORMAT_S32_LE:
 642		rme32->wcreg |= RME32_WCR_MODE24;
 643		break;
 644	default:
 645		return -EINVAL;
 646	}
 647	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 648	return 0;
 649}
 650
 651static int
 652snd_rme32_playback_hw_params(struct snd_pcm_substream *substream,
 653			     struct snd_pcm_hw_params *params)
 654{
 655	int err, rate, dummy;
 656	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 657	struct snd_pcm_runtime *runtime = substream->runtime;
 658
 659	if (rme32->fullduplex_mode) {
 660		err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
 661		if (err < 0)
 662			return err;
 663	} else {
 664		runtime->dma_area = (void __force *)(rme32->iobase +
 665						     RME32_IO_DATA_BUFFER);
 666		runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
 667		runtime->dma_bytes = RME32_BUFFER_SIZE;
 668	}
 669
 670	spin_lock_irq(&rme32->lock);
 671	if ((rme32->rcreg & RME32_RCR_KMODE) &&
 672	    (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
 
 
 673		/* AutoSync */
 674		if ((int)params_rate(params) != rate) {
 675			spin_unlock_irq(&rme32->lock);
 676			return -EIO;
 677		}
 678	} else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
 679		spin_unlock_irq(&rme32->lock);
 680		return err;
 
 
 
 681	}
 682	if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
 
 683		spin_unlock_irq(&rme32->lock);
 684		return err;
 685	}
 686
 687	snd_rme32_setframelog(rme32, params_channels(params), 1);
 688	if (rme32->capture_periodsize != 0) {
 689		if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
 690			spin_unlock_irq(&rme32->lock);
 691			return -EBUSY;
 692		}
 693	}
 694	rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
 695	/* S/PDIF setup */
 696	if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
 697		rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
 698		rme32->wcreg |= rme32->wcreg_spdif_stream;
 699		writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 700	}
 701	spin_unlock_irq(&rme32->lock);
 702
 703	return 0;
 704}
 705
 706static int
 707snd_rme32_capture_hw_params(struct snd_pcm_substream *substream,
 708			    struct snd_pcm_hw_params *params)
 709{
 710	int err, isadat, rate;
 711	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 712	struct snd_pcm_runtime *runtime = substream->runtime;
 713
 714	if (rme32->fullduplex_mode) {
 715		err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
 716		if (err < 0)
 717			return err;
 718	} else {
 719		runtime->dma_area = (void __force *)rme32->iobase +
 720					RME32_IO_DATA_BUFFER;
 721		runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
 722		runtime->dma_bytes = RME32_BUFFER_SIZE;
 723	}
 724
 725	spin_lock_irq(&rme32->lock);
 726	/* enable AutoSync for record-preparing */
 727	rme32->wcreg |= RME32_WCR_AUTOSYNC;
 728	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 729
 730	if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
 
 731		spin_unlock_irq(&rme32->lock);
 732		return err;
 733	}
 734	if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
 
 735		spin_unlock_irq(&rme32->lock);
 736		return err;
 737	}
 738	if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
 
 739                if ((int)params_rate(params) != rate) {
 740			spin_unlock_irq(&rme32->lock);
 741                        return -EIO;                    
 742                }
 743                if ((isadat && runtime->hw.channels_min == 2) ||
 744                    (!isadat && runtime->hw.channels_min == 8)) {
 745			spin_unlock_irq(&rme32->lock);
 746                        return -EIO;
 747                }
 748	}
 749	/* AutoSync off for recording */
 750	rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
 751	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 752
 753	snd_rme32_setframelog(rme32, params_channels(params), 0);
 754	if (rme32->playback_periodsize != 0) {
 755		if (params_period_size(params) << rme32->capture_frlog !=
 756		    rme32->playback_periodsize) {
 757			spin_unlock_irq(&rme32->lock);
 758			return -EBUSY;
 759		}
 760	}
 761	rme32->capture_periodsize =
 762	    params_period_size(params) << rme32->capture_frlog;
 763	spin_unlock_irq(&rme32->lock);
 764
 765	return 0;
 766}
 767
 768static int snd_rme32_pcm_hw_free(struct snd_pcm_substream *substream)
 769{
 770	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 771	if (! rme32->fullduplex_mode)
 772		return 0;
 773	return snd_pcm_lib_free_pages(substream);
 774}
 775
 776static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause)
 777{
 778	if (!from_pause) {
 779		writel(0, rme32->iobase + RME32_IO_RESET_POS);
 780	}
 781
 782	rme32->wcreg |= RME32_WCR_START;
 783	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 784}
 785
 786static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause)
 787{
 788	/*
 789	 * Check if there is an unconfirmed IRQ, if so confirm it, or else
 790	 * the hardware will not stop generating interrupts
 791	 */
 792	rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
 793	if (rme32->rcreg & RME32_RCR_IRQ) {
 794		writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
 795	}
 796	rme32->wcreg &= ~RME32_WCR_START;
 797	if (rme32->wcreg & RME32_WCR_SEL)
 798		rme32->wcreg |= RME32_WCR_MUTE;
 799	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 800	if (! to_pause)
 801		writel(0, rme32->iobase + RME32_IO_RESET_POS);
 802}
 803
 804static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id)
 805{
 806	struct rme32 *rme32 = (struct rme32 *) dev_id;
 807
 808	rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
 809	if (!(rme32->rcreg & RME32_RCR_IRQ)) {
 810		return IRQ_NONE;
 811	} else {
 812		if (rme32->capture_substream) {
 813			snd_pcm_period_elapsed(rme32->capture_substream);
 814		}
 815		if (rme32->playback_substream) {
 816			snd_pcm_period_elapsed(rme32->playback_substream);
 817		}
 818		writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
 819	}
 820	return IRQ_HANDLED;
 821}
 822
 823static unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
 824
 825
 826static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
 827	.count = ARRAY_SIZE(period_bytes),
 828	.list = period_bytes,
 829	.mask = 0
 830};
 831
 832static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime)
 833{
 834	if (! rme32->fullduplex_mode) {
 835		snd_pcm_hw_constraint_minmax(runtime,
 836					     SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
 837					     RME32_BUFFER_SIZE, RME32_BUFFER_SIZE);
 838		snd_pcm_hw_constraint_list(runtime, 0,
 839					   SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 840					   &hw_constraints_period_bytes);
 841	}
 842}
 843
 844static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream)
 845{
 846	int rate, dummy;
 847	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 848	struct snd_pcm_runtime *runtime = substream->runtime;
 849
 850	snd_pcm_set_sync(substream);
 851
 852	spin_lock_irq(&rme32->lock);
 853	if (rme32->playback_substream != NULL) {
 854		spin_unlock_irq(&rme32->lock);
 855		return -EBUSY;
 856	}
 857	rme32->wcreg &= ~RME32_WCR_ADAT;
 858	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 859	rme32->playback_substream = substream;
 860	spin_unlock_irq(&rme32->lock);
 861
 862	if (rme32->fullduplex_mode)
 863		runtime->hw = snd_rme32_spdif_fd_info;
 864	else
 865		runtime->hw = snd_rme32_spdif_info;
 866	if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) {
 867		runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
 868		runtime->hw.rate_max = 96000;
 869	}
 870	if ((rme32->rcreg & RME32_RCR_KMODE) &&
 871	    (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
 
 
 872		/* AutoSync */
 873		runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
 874		runtime->hw.rate_min = rate;
 875		runtime->hw.rate_max = rate;
 876	}       
 877
 878	snd_rme32_set_buffer_constraint(rme32, runtime);
 879
 880	rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
 881	rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
 882	snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
 883		       SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
 884	return 0;
 885}
 886
 887static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream)
 888{
 889	int isadat, rate;
 890	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 891	struct snd_pcm_runtime *runtime = substream->runtime;
 892
 893	snd_pcm_set_sync(substream);
 894
 895	spin_lock_irq(&rme32->lock);
 896        if (rme32->capture_substream != NULL) {
 897		spin_unlock_irq(&rme32->lock);
 898                return -EBUSY;
 899        }
 900	rme32->capture_substream = substream;
 901	spin_unlock_irq(&rme32->lock);
 902
 903	if (rme32->fullduplex_mode)
 904		runtime->hw = snd_rme32_spdif_fd_info;
 905	else
 906		runtime->hw = snd_rme32_spdif_info;
 907	if (RME32_PRO_WITH_8414(rme32)) {
 908		runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
 909		runtime->hw.rate_max = 96000;
 910	}
 911	if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
 
 912		if (isadat) {
 913			return -EIO;
 914		}
 915		runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
 916		runtime->hw.rate_min = rate;
 917		runtime->hw.rate_max = rate;
 918	}
 919
 920	snd_rme32_set_buffer_constraint(rme32, runtime);
 921
 922	return 0;
 923}
 924
 925static int
 926snd_rme32_playback_adat_open(struct snd_pcm_substream *substream)
 927{
 928	int rate, dummy;
 929	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 930	struct snd_pcm_runtime *runtime = substream->runtime;
 931	
 932	snd_pcm_set_sync(substream);
 933
 934	spin_lock_irq(&rme32->lock);	
 935        if (rme32->playback_substream != NULL) {
 936		spin_unlock_irq(&rme32->lock);
 937                return -EBUSY;
 938        }
 939	rme32->wcreg |= RME32_WCR_ADAT;
 940	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
 941	rme32->playback_substream = substream;
 942	spin_unlock_irq(&rme32->lock);
 943	
 944	if (rme32->fullduplex_mode)
 945		runtime->hw = snd_rme32_adat_fd_info;
 946	else
 947		runtime->hw = snd_rme32_adat_info;
 948	if ((rme32->rcreg & RME32_RCR_KMODE) &&
 949	    (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
 
 
 950                /* AutoSync */
 951                runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
 952                runtime->hw.rate_min = rate;
 953                runtime->hw.rate_max = rate;
 954	}        
 955
 956	snd_rme32_set_buffer_constraint(rme32, runtime);
 957	return 0;
 958}
 959
 960static int
 961snd_rme32_capture_adat_open(struct snd_pcm_substream *substream)
 962{
 963	int isadat, rate;
 964	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 965	struct snd_pcm_runtime *runtime = substream->runtime;
 966
 967	if (rme32->fullduplex_mode)
 968		runtime->hw = snd_rme32_adat_fd_info;
 969	else
 970		runtime->hw = snd_rme32_adat_info;
 971	if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
 
 972		if (!isadat) {
 973			return -EIO;
 974		}
 975                runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
 976                runtime->hw.rate_min = rate;
 977                runtime->hw.rate_max = rate;
 978        }
 979
 980	snd_pcm_set_sync(substream);
 981        
 982	spin_lock_irq(&rme32->lock);	
 983	if (rme32->capture_substream != NULL) {
 984		spin_unlock_irq(&rme32->lock);
 985		return -EBUSY;
 986        }
 987	rme32->capture_substream = substream;
 988	spin_unlock_irq(&rme32->lock);
 989
 990	snd_rme32_set_buffer_constraint(rme32, runtime);
 991	return 0;
 992}
 993
 994static int snd_rme32_playback_close(struct snd_pcm_substream *substream)
 995{
 996	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
 997	int spdif = 0;
 998
 999	spin_lock_irq(&rme32->lock);
1000	rme32->playback_substream = NULL;
1001	rme32->playback_periodsize = 0;
1002	spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
1003	spin_unlock_irq(&rme32->lock);
1004	if (spdif) {
1005		rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1006		snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
1007			       SNDRV_CTL_EVENT_MASK_INFO,
1008			       &rme32->spdif_ctl->id);
1009	}
1010	return 0;
1011}
1012
1013static int snd_rme32_capture_close(struct snd_pcm_substream *substream)
1014{
1015	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1016
1017	spin_lock_irq(&rme32->lock);
1018	rme32->capture_substream = NULL;
1019	rme32->capture_periodsize = 0;
1020	spin_unlock_irq(&rme32->lock);
1021	return 0;
1022}
1023
1024static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream)
1025{
1026	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1027
1028	spin_lock_irq(&rme32->lock);
1029	if (rme32->fullduplex_mode) {
1030		memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
1031		rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1032		rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1033	} else {
1034		writel(0, rme32->iobase + RME32_IO_RESET_POS);
1035	}
1036	if (rme32->wcreg & RME32_WCR_SEL)
1037		rme32->wcreg &= ~RME32_WCR_MUTE;
1038	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1039	spin_unlock_irq(&rme32->lock);
1040	return 0;
1041}
1042
1043static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream)
1044{
1045	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1046
1047	spin_lock_irq(&rme32->lock);
1048	if (rme32->fullduplex_mode) {
1049		memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
1050		rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
1051		rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
1052		rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1053	} else {
1054		writel(0, rme32->iobase + RME32_IO_RESET_POS);
1055	}
1056	spin_unlock_irq(&rme32->lock);
1057	return 0;
1058}
1059
1060static int
1061snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1062{
1063	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1064	struct snd_pcm_substream *s;
1065
1066	spin_lock(&rme32->lock);
1067	snd_pcm_group_for_each_entry(s, substream) {
1068		if (s != rme32->playback_substream &&
1069		    s != rme32->capture_substream)
1070			continue;
1071		switch (cmd) {
1072		case SNDRV_PCM_TRIGGER_START:
1073			rme32->running |= (1 << s->stream);
1074			if (rme32->fullduplex_mode) {
1075				/* remember the current DMA position */
1076				if (s == rme32->playback_substream) {
1077					rme32->playback_pcm.hw_io =
1078					rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1079				} else {
1080					rme32->capture_pcm.hw_io =
1081					rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
1082				}
1083			}
1084			break;
1085		case SNDRV_PCM_TRIGGER_STOP:
1086			rme32->running &= ~(1 << s->stream);
1087			break;
1088		}
1089		snd_pcm_trigger_done(s, substream);
1090	}
1091	
1092	/* prefill playback buffer */
1093	if (cmd == SNDRV_PCM_TRIGGER_START && rme32->fullduplex_mode) {
1094		snd_pcm_group_for_each_entry(s, substream) {
1095			if (s == rme32->playback_substream) {
1096				s->ops->ack(s);
1097				break;
1098			}
1099		}
1100	}
1101
1102	switch (cmd) {
1103	case SNDRV_PCM_TRIGGER_START:
1104		if (rme32->running && ! RME32_ISWORKING(rme32))
1105			snd_rme32_pcm_start(rme32, 0);
1106		break;
1107	case SNDRV_PCM_TRIGGER_STOP:
1108		if (! rme32->running && RME32_ISWORKING(rme32))
1109			snd_rme32_pcm_stop(rme32, 0);
1110		break;
1111	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1112		if (rme32->running && RME32_ISWORKING(rme32))
1113			snd_rme32_pcm_stop(rme32, 1);
1114		break;
1115	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1116		if (rme32->running && ! RME32_ISWORKING(rme32))
1117			snd_rme32_pcm_start(rme32, 1);
1118		break;
1119	}
1120	spin_unlock(&rme32->lock);
1121	return 0;
1122}
1123
1124/* pointer callback for halfduplex mode */
1125static snd_pcm_uframes_t
1126snd_rme32_playback_pointer(struct snd_pcm_substream *substream)
1127{
1128	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1129	return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
1130}
1131
1132static snd_pcm_uframes_t
1133snd_rme32_capture_pointer(struct snd_pcm_substream *substream)
1134{
1135	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1136	return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
1137}
1138
1139
1140/* ack and pointer callbacks for fullduplex mode */
1141static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream,
1142				    struct snd_pcm_indirect *rec, size_t bytes)
1143{
1144	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1145	memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1146		    substream->runtime->dma_area + rec->sw_data, bytes);
1147}
1148
1149static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream)
1150{
1151	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1152	struct snd_pcm_indirect *rec, *cprec;
1153
1154	rec = &rme32->playback_pcm;
1155	cprec = &rme32->capture_pcm;
1156	spin_lock(&rme32->lock);
1157	rec->hw_queue_size = RME32_BUFFER_SIZE;
1158	if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
1159		rec->hw_queue_size -= cprec->hw_ready;
1160	spin_unlock(&rme32->lock);
1161	snd_pcm_indirect_playback_transfer(substream, rec,
1162					   snd_rme32_pb_trans_copy);
1163	return 0;
1164}
1165
1166static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream,
1167				    struct snd_pcm_indirect *rec, size_t bytes)
1168{
1169	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1170	memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
1171		      rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
1172		      bytes);
1173}
1174
1175static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream)
1176{
1177	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1178	snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
1179					  snd_rme32_cp_trans_copy);
1180	return 0;
1181}
1182
1183static snd_pcm_uframes_t
1184snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream)
1185{
1186	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1187	return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
1188						 snd_rme32_pcm_byteptr(rme32));
1189}
1190
1191static snd_pcm_uframes_t
1192snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream)
1193{
1194	struct rme32 *rme32 = snd_pcm_substream_chip(substream);
1195	return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
1196						snd_rme32_pcm_byteptr(rme32));
1197}
1198
1199/* for halfduplex mode */
1200static struct snd_pcm_ops snd_rme32_playback_spdif_ops = {
1201	.open =		snd_rme32_playback_spdif_open,
1202	.close =	snd_rme32_playback_close,
1203	.ioctl =	snd_pcm_lib_ioctl,
1204	.hw_params =	snd_rme32_playback_hw_params,
1205	.hw_free =	snd_rme32_pcm_hw_free,
1206	.prepare =	snd_rme32_playback_prepare,
1207	.trigger =	snd_rme32_pcm_trigger,
1208	.pointer =	snd_rme32_playback_pointer,
1209	.copy =		snd_rme32_playback_copy,
1210	.silence =	snd_rme32_playback_silence,
1211	.mmap =		snd_pcm_lib_mmap_iomem,
1212};
1213
1214static struct snd_pcm_ops snd_rme32_capture_spdif_ops = {
1215	.open =		snd_rme32_capture_spdif_open,
1216	.close =	snd_rme32_capture_close,
1217	.ioctl =	snd_pcm_lib_ioctl,
1218	.hw_params =	snd_rme32_capture_hw_params,
1219	.hw_free =	snd_rme32_pcm_hw_free,
1220	.prepare =	snd_rme32_capture_prepare,
1221	.trigger =	snd_rme32_pcm_trigger,
1222	.pointer =	snd_rme32_capture_pointer,
1223	.copy =		snd_rme32_capture_copy,
1224	.mmap =		snd_pcm_lib_mmap_iomem,
1225};
1226
1227static struct snd_pcm_ops snd_rme32_playback_adat_ops = {
1228	.open =		snd_rme32_playback_adat_open,
1229	.close =	snd_rme32_playback_close,
1230	.ioctl =	snd_pcm_lib_ioctl,
1231	.hw_params =	snd_rme32_playback_hw_params,
1232	.prepare =	snd_rme32_playback_prepare,
1233	.trigger =	snd_rme32_pcm_trigger,
1234	.pointer =	snd_rme32_playback_pointer,
1235	.copy =		snd_rme32_playback_copy,
1236	.silence =	snd_rme32_playback_silence,
1237	.mmap =		snd_pcm_lib_mmap_iomem,
1238};
1239
1240static struct snd_pcm_ops snd_rme32_capture_adat_ops = {
1241	.open =		snd_rme32_capture_adat_open,
1242	.close =	snd_rme32_capture_close,
1243	.ioctl =	snd_pcm_lib_ioctl,
1244	.hw_params =	snd_rme32_capture_hw_params,
1245	.prepare =	snd_rme32_capture_prepare,
1246	.trigger =	snd_rme32_pcm_trigger,
1247	.pointer =	snd_rme32_capture_pointer,
1248	.copy =		snd_rme32_capture_copy,
1249	.mmap =		snd_pcm_lib_mmap_iomem,
1250};
1251
1252/* for fullduplex mode */
1253static struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = {
1254	.open =		snd_rme32_playback_spdif_open,
1255	.close =	snd_rme32_playback_close,
1256	.ioctl =	snd_pcm_lib_ioctl,
1257	.hw_params =	snd_rme32_playback_hw_params,
1258	.hw_free =	snd_rme32_pcm_hw_free,
1259	.prepare =	snd_rme32_playback_prepare,
1260	.trigger =	snd_rme32_pcm_trigger,
1261	.pointer =	snd_rme32_playback_fd_pointer,
1262	.ack =		snd_rme32_playback_fd_ack,
1263};
1264
1265static struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = {
1266	.open =		snd_rme32_capture_spdif_open,
1267	.close =	snd_rme32_capture_close,
1268	.ioctl =	snd_pcm_lib_ioctl,
1269	.hw_params =	snd_rme32_capture_hw_params,
1270	.hw_free =	snd_rme32_pcm_hw_free,
1271	.prepare =	snd_rme32_capture_prepare,
1272	.trigger =	snd_rme32_pcm_trigger,
1273	.pointer =	snd_rme32_capture_fd_pointer,
1274	.ack =		snd_rme32_capture_fd_ack,
1275};
1276
1277static struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = {
1278	.open =		snd_rme32_playback_adat_open,
1279	.close =	snd_rme32_playback_close,
1280	.ioctl =	snd_pcm_lib_ioctl,
1281	.hw_params =	snd_rme32_playback_hw_params,
1282	.prepare =	snd_rme32_playback_prepare,
1283	.trigger =	snd_rme32_pcm_trigger,
1284	.pointer =	snd_rme32_playback_fd_pointer,
1285	.ack =		snd_rme32_playback_fd_ack,
1286};
1287
1288static struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = {
1289	.open =		snd_rme32_capture_adat_open,
1290	.close =	snd_rme32_capture_close,
1291	.ioctl =	snd_pcm_lib_ioctl,
1292	.hw_params =	snd_rme32_capture_hw_params,
1293	.prepare =	snd_rme32_capture_prepare,
1294	.trigger =	snd_rme32_pcm_trigger,
1295	.pointer =	snd_rme32_capture_fd_pointer,
1296	.ack =		snd_rme32_capture_fd_ack,
1297};
1298
1299static void snd_rme32_free(void *private_data)
1300{
1301	struct rme32 *rme32 = (struct rme32 *) private_data;
1302
1303	if (rme32 == NULL) {
1304		return;
1305	}
1306	if (rme32->irq >= 0) {
1307		snd_rme32_pcm_stop(rme32, 0);
1308		free_irq(rme32->irq, (void *) rme32);
1309		rme32->irq = -1;
1310	}
1311	if (rme32->iobase) {
1312		iounmap(rme32->iobase);
1313		rme32->iobase = NULL;
1314	}
1315	if (rme32->port) {
1316		pci_release_regions(rme32->pci);
1317		rme32->port = 0;
1318	}
1319	pci_disable_device(rme32->pci);
1320}
1321
1322static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm)
1323{
1324	struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1325	rme32->spdif_pcm = NULL;
1326}
1327
1328static void
1329snd_rme32_free_adat_pcm(struct snd_pcm *pcm)
1330{
1331	struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
1332	rme32->adat_pcm = NULL;
1333}
1334
1335static int snd_rme32_create(struct rme32 *rme32)
1336{
1337	struct pci_dev *pci = rme32->pci;
1338	int err;
1339
1340	rme32->irq = -1;
1341	spin_lock_init(&rme32->lock);
1342
1343	if ((err = pci_enable_device(pci)) < 0)
 
1344		return err;
1345
1346	if ((err = pci_request_regions(pci, "RME32")) < 0)
 
1347		return err;
1348	rme32->port = pci_resource_start(rme32->pci, 0);
1349
1350	rme32->iobase = ioremap_nocache(rme32->port, RME32_IO_SIZE);
1351	if (!rme32->iobase) {
1352		dev_err(rme32->card->dev,
1353			"unable to remap memory region 0x%lx-0x%lx\n",
1354			   rme32->port, rme32->port + RME32_IO_SIZE - 1);
1355		return -ENOMEM;
1356	}
1357
1358	if (request_irq(pci->irq, snd_rme32_interrupt, IRQF_SHARED,
1359			KBUILD_MODNAME, rme32)) {
1360		dev_err(rme32->card->dev, "unable to grab IRQ %d\n", pci->irq);
1361		return -EBUSY;
1362	}
1363	rme32->irq = pci->irq;
 
1364
1365	/* read the card's revision number */
1366	pci_read_config_byte(pci, 8, &rme32->rev);
1367
1368	/* set up ALSA pcm device for S/PDIF */
1369	if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
 
1370		return err;
1371	}
1372	rme32->spdif_pcm->private_data = rme32;
1373	rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
1374	strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
1375	if (rme32->fullduplex_mode) {
1376		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1377				&snd_rme32_playback_spdif_fd_ops);
1378		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1379				&snd_rme32_capture_spdif_fd_ops);
1380		snd_pcm_lib_preallocate_pages_for_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1381						      snd_dma_continuous_data(GFP_KERNEL),
1382						      0, RME32_MID_BUFFER_SIZE);
1383		rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1384	} else {
1385		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
1386				&snd_rme32_playback_spdif_ops);
1387		snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
1388				&snd_rme32_capture_spdif_ops);
1389		rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1390	}
1391
1392	/* set up ALSA pcm device for ADAT */
1393	if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) ||
1394	    (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) {
1395		/* ADAT is not available on DIGI32 and DIGI32 Pro */
1396		rme32->adat_pcm = NULL;
1397	}
1398	else {
1399		if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
1400				       1, 1, &rme32->adat_pcm)) < 0)
1401		{
1402			return err;
1403		}		
1404		rme32->adat_pcm->private_data = rme32;
1405		rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
1406		strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
1407		if (rme32->fullduplex_mode) {
1408			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, 
1409					&snd_rme32_playback_adat_fd_ops);
1410			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, 
1411					&snd_rme32_capture_adat_fd_ops);
1412			snd_pcm_lib_preallocate_pages_for_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1413							      snd_dma_continuous_data(GFP_KERNEL),
1414							      0, RME32_MID_BUFFER_SIZE);
1415			rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
1416		} else {
1417			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, 
1418					&snd_rme32_playback_adat_ops);
1419			snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, 
1420					&snd_rme32_capture_adat_ops);
1421			rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
1422		}
1423	}
1424
1425
1426	rme32->playback_periodsize = 0;
1427	rme32->capture_periodsize = 0;
1428
1429	/* make sure playback/capture is stopped, if by some reason active */
1430	snd_rme32_pcm_stop(rme32, 0);
1431
1432        /* reset DAC */
1433        snd_rme32_reset_dac(rme32);
1434
1435	/* reset buffer pointer */
1436	writel(0, rme32->iobase + RME32_IO_RESET_POS);
1437
1438	/* set default values in registers */
1439	rme32->wcreg = RME32_WCR_SEL |	 /* normal playback */
1440		RME32_WCR_INP_0 | /* input select */
1441		RME32_WCR_MUTE;	 /* muting on */
1442	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1443
1444
1445	/* init switch interface */
1446	if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
 
1447		return err;
1448	}
1449
1450	/* init proc interface */
1451	snd_rme32_proc_init(rme32);
1452
1453	rme32->capture_substream = NULL;
1454	rme32->playback_substream = NULL;
1455
1456	return 0;
1457}
1458
1459/*
1460 * proc interface
1461 */
1462
1463static void
1464snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
1465{
1466	int n;
1467	struct rme32 *rme32 = (struct rme32 *) entry->private_data;
1468
1469	rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
1470
1471	snd_iprintf(buffer, rme32->card->longname);
1472	snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
1473
1474	snd_iprintf(buffer, "\nGeneral settings\n");
1475	if (rme32->fullduplex_mode)
1476		snd_iprintf(buffer, "  Full-duplex mode\n");
1477	else
1478		snd_iprintf(buffer, "  Half-duplex mode\n");
1479	if (RME32_PRO_WITH_8414(rme32)) {
1480		snd_iprintf(buffer, "  receiver: CS8414\n");
1481	} else {
1482		snd_iprintf(buffer, "  receiver: CS8412\n");
1483	}
1484	if (rme32->wcreg & RME32_WCR_MODE24) {
1485		snd_iprintf(buffer, "  format: 24 bit");
1486	} else {
1487		snd_iprintf(buffer, "  format: 16 bit");
1488	}
1489	if (rme32->wcreg & RME32_WCR_MONO) {
1490		snd_iprintf(buffer, ", Mono\n");
1491	} else {
1492		snd_iprintf(buffer, ", Stereo\n");
1493	}
1494
1495	snd_iprintf(buffer, "\nInput settings\n");
1496	switch (snd_rme32_getinputtype(rme32)) {
1497	case RME32_INPUT_OPTICAL:
1498		snd_iprintf(buffer, "  input: optical");
1499		break;
1500	case RME32_INPUT_COAXIAL:
1501		snd_iprintf(buffer, "  input: coaxial");
1502		break;
1503	case RME32_INPUT_INTERNAL:
1504		snd_iprintf(buffer, "  input: internal");
1505		break;
1506	case RME32_INPUT_XLR:
1507		snd_iprintf(buffer, "  input: XLR");
1508		break;
1509	}
1510	if (snd_rme32_capture_getrate(rme32, &n) < 0) {
1511		snd_iprintf(buffer, "\n  sample rate: no valid signal\n");
1512	} else {
1513		if (n) {
1514			snd_iprintf(buffer, " (8 channels)\n");
1515		} else {
1516			snd_iprintf(buffer, " (2 channels)\n");
1517		}
1518		snd_iprintf(buffer, "  sample rate: %d Hz\n",
1519			    snd_rme32_capture_getrate(rme32, &n));
1520	}
1521
1522	snd_iprintf(buffer, "\nOutput settings\n");
1523	if (rme32->wcreg & RME32_WCR_SEL) {
1524		snd_iprintf(buffer, "  output signal: normal playback");
1525	} else {
1526		snd_iprintf(buffer, "  output signal: same as input");
1527	}
1528	if (rme32->wcreg & RME32_WCR_MUTE) {
1529		snd_iprintf(buffer, " (muted)\n");
1530	} else {
1531		snd_iprintf(buffer, "\n");
1532	}
1533
1534	/* master output frequency */
1535	if (!
1536	    ((!(rme32->wcreg & RME32_WCR_FREQ_0))
1537	     && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
1538		snd_iprintf(buffer, "  sample rate: %d Hz\n",
1539			    snd_rme32_playback_getrate(rme32));
1540	}
1541	if (rme32->rcreg & RME32_RCR_KMODE) {
1542		snd_iprintf(buffer, "  sample clock source: AutoSync\n");
1543	} else {
1544		snd_iprintf(buffer, "  sample clock source: Internal\n");
1545	}
1546	if (rme32->wcreg & RME32_WCR_PRO) {
1547		snd_iprintf(buffer, "  format: AES/EBU (professional)\n");
1548	} else {
1549		snd_iprintf(buffer, "  format: IEC958 (consumer)\n");
1550	}
1551	if (rme32->wcreg & RME32_WCR_EMP) {
1552		snd_iprintf(buffer, "  emphasis: on\n");
1553	} else {
1554		snd_iprintf(buffer, "  emphasis: off\n");
1555	}
1556}
1557
1558static void snd_rme32_proc_init(struct rme32 *rme32)
1559{
1560	struct snd_info_entry *entry;
1561
1562	if (! snd_card_proc_new(rme32->card, "rme32", &entry))
1563		snd_info_set_text_ops(entry, rme32, snd_rme32_proc_read);
1564}
1565
1566/*
1567 * control interface
1568 */
1569
1570#define snd_rme32_info_loopback_control		snd_ctl_boolean_mono_info
1571
1572static int
1573snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol,
1574			       struct snd_ctl_elem_value *ucontrol)
1575{
1576	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1577
1578	spin_lock_irq(&rme32->lock);
1579	ucontrol->value.integer.value[0] =
1580	    rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
1581	spin_unlock_irq(&rme32->lock);
1582	return 0;
1583}
1584static int
1585snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol,
1586			       struct snd_ctl_elem_value *ucontrol)
1587{
1588	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1589	unsigned int val;
1590	int change;
1591
1592	val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
1593	spin_lock_irq(&rme32->lock);
1594	val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
1595	change = val != rme32->wcreg;
1596	if (ucontrol->value.integer.value[0])
1597		val &= ~RME32_WCR_MUTE;
1598	else
1599		val |= RME32_WCR_MUTE;
1600	rme32->wcreg = val;
1601	writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1602	spin_unlock_irq(&rme32->lock);
1603	return change;
1604}
1605
1606static int
1607snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol,
1608				 struct snd_ctl_elem_info *uinfo)
1609{
1610	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1611	static char *texts[4] = { "Optical", "Coaxial", "Internal", "XLR" };
 
 
 
1612
1613	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1614	uinfo->count = 1;
1615	switch (rme32->pci->device) {
1616	case PCI_DEVICE_ID_RME_DIGI32:
1617	case PCI_DEVICE_ID_RME_DIGI32_8:
1618		uinfo->value.enumerated.items = 3;
1619		break;
1620	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1621		uinfo->value.enumerated.items = 4;
1622		break;
1623	default:
1624		snd_BUG();
1625		break;
1626	}
1627	if (uinfo->value.enumerated.item >
1628	    uinfo->value.enumerated.items - 1) {
1629		uinfo->value.enumerated.item =
1630		    uinfo->value.enumerated.items - 1;
1631	}
1632	strcpy(uinfo->value.enumerated.name,
1633	       texts[uinfo->value.enumerated.item]);
1634	return 0;
1635}
1636static int
1637snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol,
1638				struct snd_ctl_elem_value *ucontrol)
1639{
1640	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1641	unsigned int items = 3;
1642
1643	spin_lock_irq(&rme32->lock);
1644	ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
1645
1646	switch (rme32->pci->device) {
1647	case PCI_DEVICE_ID_RME_DIGI32:
1648	case PCI_DEVICE_ID_RME_DIGI32_8:
1649		items = 3;
1650		break;
1651	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1652		items = 4;
1653		break;
1654	default:
1655		snd_BUG();
1656		break;
1657	}
1658	if (ucontrol->value.enumerated.item[0] >= items) {
1659		ucontrol->value.enumerated.item[0] = items - 1;
1660	}
1661
1662	spin_unlock_irq(&rme32->lock);
1663	return 0;
1664}
1665static int
1666snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol,
1667				struct snd_ctl_elem_value *ucontrol)
1668{
1669	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1670	unsigned int val;
1671	int change, items = 3;
1672
1673	switch (rme32->pci->device) {
1674	case PCI_DEVICE_ID_RME_DIGI32:
1675	case PCI_DEVICE_ID_RME_DIGI32_8:
1676		items = 3;
1677		break;
1678	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1679		items = 4;
1680		break;
1681	default:
1682		snd_BUG();
1683		break;
1684	}
1685	val = ucontrol->value.enumerated.item[0] % items;
1686
1687	spin_lock_irq(&rme32->lock);
1688	change = val != (unsigned int)snd_rme32_getinputtype(rme32);
1689	snd_rme32_setinputtype(rme32, val);
1690	spin_unlock_irq(&rme32->lock);
1691	return change;
1692}
1693
1694static int
1695snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol,
1696				 struct snd_ctl_elem_info *uinfo)
1697{
1698	static char *texts[4] = { "AutoSync", 
1699				  "Internal 32.0kHz", 
1700				  "Internal 44.1kHz", 
1701				  "Internal 48.0kHz" };
1702
1703	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1704	uinfo->count = 1;
1705	uinfo->value.enumerated.items = 4;
1706	if (uinfo->value.enumerated.item > 3) {
1707		uinfo->value.enumerated.item = 3;
1708	}
1709	strcpy(uinfo->value.enumerated.name,
1710	       texts[uinfo->value.enumerated.item]);
1711	return 0;
1712}
1713static int
1714snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol,
1715				struct snd_ctl_elem_value *ucontrol)
1716{
1717	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1718
1719	spin_lock_irq(&rme32->lock);
1720	ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
1721	spin_unlock_irq(&rme32->lock);
1722	return 0;
1723}
1724static int
1725snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol,
1726				struct snd_ctl_elem_value *ucontrol)
1727{
1728	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1729	unsigned int val;
1730	int change;
1731
1732	val = ucontrol->value.enumerated.item[0] % 3;
1733	spin_lock_irq(&rme32->lock);
1734	change = val != (unsigned int)snd_rme32_getclockmode(rme32);
1735	snd_rme32_setclockmode(rme32, val);
1736	spin_unlock_irq(&rme32->lock);
1737	return change;
1738}
1739
1740static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)
1741{
1742	u32 val = 0;
1743	val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
1744	if (val & RME32_WCR_PRO)
1745		val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1746	else
1747		val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
1748	return val;
1749}
1750
1751static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val)
1752{
1753	aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
1754	if (val & RME32_WCR_PRO)
1755		aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1756	else
1757		aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1758}
1759
1760static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol,
1761					struct snd_ctl_elem_info *uinfo)
1762{
1763	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1764	uinfo->count = 1;
1765	return 0;
1766}
1767
1768static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol,
1769				       struct snd_ctl_elem_value *ucontrol)
1770{
1771	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1772
1773	snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1774				 rme32->wcreg_spdif);
1775	return 0;
1776}
1777
1778static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol,
1779				       struct snd_ctl_elem_value *ucontrol)
1780{
1781	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1782	int change;
1783	u32 val;
1784
1785	val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1786	spin_lock_irq(&rme32->lock);
1787	change = val != rme32->wcreg_spdif;
1788	rme32->wcreg_spdif = val;
1789	spin_unlock_irq(&rme32->lock);
1790	return change;
1791}
1792
1793static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol,
1794					       struct snd_ctl_elem_info *uinfo)
1795{
1796	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1797	uinfo->count = 1;
1798	return 0;
1799}
1800
1801static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol,
1802					      struct snd_ctl_elem_value *
1803					      ucontrol)
1804{
1805	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1806
1807	snd_rme32_convert_to_aes(&ucontrol->value.iec958,
1808				 rme32->wcreg_spdif_stream);
1809	return 0;
1810}
1811
1812static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol,
1813					      struct snd_ctl_elem_value *
1814					      ucontrol)
1815{
1816	struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
1817	int change;
1818	u32 val;
1819
1820	val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
1821	spin_lock_irq(&rme32->lock);
1822	change = val != rme32->wcreg_spdif_stream;
1823	rme32->wcreg_spdif_stream = val;
1824	rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
1825	rme32->wcreg |= val;
1826	writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
1827	spin_unlock_irq(&rme32->lock);
1828	return change;
1829}
1830
1831static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol,
1832					     struct snd_ctl_elem_info *uinfo)
1833{
1834	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1835	uinfo->count = 1;
1836	return 0;
1837}
1838
1839static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol,
1840					    struct snd_ctl_elem_value *
1841					    ucontrol)
1842{
1843	ucontrol->value.iec958.status[0] = kcontrol->private_value;
1844	return 0;
1845}
1846
1847static struct snd_kcontrol_new snd_rme32_controls[] = {
1848	{
1849		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1850		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1851		.info =	snd_rme32_control_spdif_info,
1852		.get =	snd_rme32_control_spdif_get,
1853		.put =	snd_rme32_control_spdif_put
1854	},
1855	{
1856		.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
1857		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1858		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
1859		.info =	snd_rme32_control_spdif_stream_info,
1860		.get =	snd_rme32_control_spdif_stream_get,
1861		.put =	snd_rme32_control_spdif_stream_put
1862	},
1863	{
1864		.access = SNDRV_CTL_ELEM_ACCESS_READ,
1865		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1866		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
1867		.info =	snd_rme32_control_spdif_mask_info,
1868		.get =	snd_rme32_control_spdif_mask_get,
1869		.private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
1870	},
1871	{
1872		.access = SNDRV_CTL_ELEM_ACCESS_READ,
1873		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
1874		.name =	SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
1875		.info =	snd_rme32_control_spdif_mask_info,
1876		.get =	snd_rme32_control_spdif_mask_get,
1877		.private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
1878	},
1879	{
1880		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1881		.name =	"Input Connector",
1882		.info =	snd_rme32_info_inputtype_control,
1883		.get =	snd_rme32_get_inputtype_control,
1884		.put =	snd_rme32_put_inputtype_control
1885	},
1886	{
1887		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1888		.name =	"Loopback Input",
1889		.info =	snd_rme32_info_loopback_control,
1890		.get =	snd_rme32_get_loopback_control,
1891		.put =	snd_rme32_put_loopback_control
1892	},
1893	{
1894		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
1895		.name =	"Sample Clock Source",
1896		.info =	snd_rme32_info_clockmode_control,
1897		.get =	snd_rme32_get_clockmode_control,
1898		.put =	snd_rme32_put_clockmode_control
1899	}
1900};
1901
1902static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32)
1903{
1904	int idx, err;
1905	struct snd_kcontrol *kctl;
1906
1907	for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
1908		if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
 
 
1909			return err;
1910		if (idx == 1)	/* IEC958 (S/PDIF) Stream */
1911			rme32->spdif_ctl = kctl;
1912	}
1913
1914	return 0;
1915}
1916
1917/*
1918 * Card initialisation
1919 */
1920
1921static void snd_rme32_card_free(struct snd_card *card)
1922{
1923	snd_rme32_free(card->private_data);
1924}
1925
1926static int
1927snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1928{
1929	static int dev;
1930	struct rme32 *rme32;
1931	struct snd_card *card;
1932	int err;
1933
1934	if (dev >= SNDRV_CARDS) {
1935		return -ENODEV;
1936	}
1937	if (!enable[dev]) {
1938		dev++;
1939		return -ENOENT;
1940	}
1941
1942	err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
1943			   sizeof(struct rme32), &card);
1944	if (err < 0)
1945		return err;
1946	card->private_free = snd_rme32_card_free;
1947	rme32 = (struct rme32 *) card->private_data;
1948	rme32->card = card;
1949	rme32->pci = pci;
1950        if (fullduplex[dev])
1951		rme32->fullduplex_mode = 1;
1952	if ((err = snd_rme32_create(rme32)) < 0) {
1953		snd_card_free(card);
1954		return err;
1955	}
1956
1957	strcpy(card->driver, "Digi32");
1958	switch (rme32->pci->device) {
1959	case PCI_DEVICE_ID_RME_DIGI32:
1960		strcpy(card->shortname, "RME Digi32");
1961		break;
1962	case PCI_DEVICE_ID_RME_DIGI32_8:
1963		strcpy(card->shortname, "RME Digi32/8");
1964		break;
1965	case PCI_DEVICE_ID_RME_DIGI32_PRO:
1966		strcpy(card->shortname, "RME Digi32 PRO");
1967		break;
1968	}
1969	sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
1970		card->shortname, rme32->rev, rme32->port, rme32->irq);
1971
1972	if ((err = snd_card_register(card)) < 0) {
1973		snd_card_free(card);
1974		return err;
1975	}
1976	pci_set_drvdata(pci, card);
1977	dev++;
1978	return 0;
1979}
1980
1981static void snd_rme32_remove(struct pci_dev *pci)
 
1982{
1983	snd_card_free(pci_get_drvdata(pci));
1984}
1985
1986static struct pci_driver rme32_driver = {
1987	.name =		KBUILD_MODNAME,
1988	.id_table =	snd_rme32_ids,
1989	.probe =	snd_rme32_probe,
1990	.remove =	snd_rme32_remove,
1991};
1992
1993module_pci_driver(rme32_driver);