Loading...
Note: File does not exist in v3.15.
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright 2017 Microsemi Corporation
3 * Copyright 2018-2019 NXP
4 */
5#include <linux/fsl/enetc_mdio.h>
6#include <soc/mscc/ocelot_qsys.h>
7#include <soc/mscc/ocelot_vcap.h>
8#include <soc/mscc/ocelot_ana.h>
9#include <soc/mscc/ocelot_dev.h>
10#include <soc/mscc/ocelot_ptp.h>
11#include <soc/mscc/ocelot_sys.h>
12#include <net/tc_act/tc_gate.h>
13#include <soc/mscc/ocelot.h>
14#include <linux/dsa/ocelot.h>
15#include <linux/pcs-lynx.h>
16#include <net/pkt_sched.h>
17#include <linux/iopoll.h>
18#include <linux/mdio.h>
19#include <linux/of.h>
20#include <linux/pci.h>
21#include <linux/time.h>
22#include "felix.h"
23
24#define VSC9959_NUM_PORTS 6
25
26#define VSC9959_TAS_GCL_ENTRY_MAX 63
27#define VSC9959_TAS_MIN_GATE_LEN_NS 35
28#define VSC9959_VCAP_POLICER_BASE 63
29#define VSC9959_VCAP_POLICER_MAX 383
30#define VSC9959_SWITCH_PCI_BAR 4
31#define VSC9959_IMDIO_PCI_BAR 0
32
33#define VSC9959_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \
34 OCELOT_PORT_MODE_QSGMII | \
35 OCELOT_PORT_MODE_1000BASEX | \
36 OCELOT_PORT_MODE_2500BASEX | \
37 OCELOT_PORT_MODE_USXGMII)
38
39static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = {
40 VSC9959_PORT_MODE_SERDES,
41 VSC9959_PORT_MODE_SERDES,
42 VSC9959_PORT_MODE_SERDES,
43 VSC9959_PORT_MODE_SERDES,
44 OCELOT_PORT_MODE_INTERNAL,
45 OCELOT_PORT_MODE_INTERNAL,
46};
47
48static const u32 vsc9959_ana_regmap[] = {
49 REG(ANA_ADVLEARN, 0x0089a0),
50 REG(ANA_VLANMASK, 0x0089a4),
51 REG_RESERVED(ANA_PORT_B_DOMAIN),
52 REG(ANA_ANAGEFIL, 0x0089ac),
53 REG(ANA_ANEVENTS, 0x0089b0),
54 REG(ANA_STORMLIMIT_BURST, 0x0089b4),
55 REG(ANA_STORMLIMIT_CFG, 0x0089b8),
56 REG(ANA_ISOLATED_PORTS, 0x0089c8),
57 REG(ANA_COMMUNITY_PORTS, 0x0089cc),
58 REG(ANA_AUTOAGE, 0x0089d0),
59 REG(ANA_MACTOPTIONS, 0x0089d4),
60 REG(ANA_LEARNDISC, 0x0089d8),
61 REG(ANA_AGENCTRL, 0x0089dc),
62 REG(ANA_MIRRORPORTS, 0x0089e0),
63 REG(ANA_EMIRRORPORTS, 0x0089e4),
64 REG(ANA_FLOODING, 0x0089e8),
65 REG(ANA_FLOODING_IPMC, 0x008a08),
66 REG(ANA_SFLOW_CFG, 0x008a0c),
67 REG(ANA_PORT_MODE, 0x008a28),
68 REG(ANA_CUT_THRU_CFG, 0x008a48),
69 REG(ANA_PGID_PGID, 0x008400),
70 REG(ANA_TABLES_ANMOVED, 0x007f1c),
71 REG(ANA_TABLES_MACHDATA, 0x007f20),
72 REG(ANA_TABLES_MACLDATA, 0x007f24),
73 REG(ANA_TABLES_STREAMDATA, 0x007f28),
74 REG(ANA_TABLES_MACACCESS, 0x007f2c),
75 REG(ANA_TABLES_MACTINDX, 0x007f30),
76 REG(ANA_TABLES_VLANACCESS, 0x007f34),
77 REG(ANA_TABLES_VLANTIDX, 0x007f38),
78 REG(ANA_TABLES_ISDXACCESS, 0x007f3c),
79 REG(ANA_TABLES_ISDXTIDX, 0x007f40),
80 REG(ANA_TABLES_ENTRYLIM, 0x007f00),
81 REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44),
82 REG(ANA_TABLES_PTP_ID_LOW, 0x007f48),
83 REG(ANA_TABLES_STREAMACCESS, 0x007f4c),
84 REG(ANA_TABLES_STREAMTIDX, 0x007f50),
85 REG(ANA_TABLES_SEQ_HISTORY, 0x007f54),
86 REG(ANA_TABLES_SEQ_MASK, 0x007f58),
87 REG(ANA_TABLES_SFID_MASK, 0x007f5c),
88 REG(ANA_TABLES_SFIDACCESS, 0x007f60),
89 REG(ANA_TABLES_SFIDTIDX, 0x007f64),
90 REG(ANA_MSTI_STATE, 0x008600),
91 REG(ANA_OAM_UPM_LM_CNT, 0x008000),
92 REG(ANA_SG_ACCESS_CTRL, 0x008a64),
93 REG(ANA_SG_CONFIG_REG_1, 0x007fb0),
94 REG(ANA_SG_CONFIG_REG_2, 0x007fb4),
95 REG(ANA_SG_CONFIG_REG_3, 0x007fb8),
96 REG(ANA_SG_CONFIG_REG_4, 0x007fbc),
97 REG(ANA_SG_CONFIG_REG_5, 0x007fc0),
98 REG(ANA_SG_GCL_GS_CONFIG, 0x007f80),
99 REG(ANA_SG_GCL_TI_CONFIG, 0x007f90),
100 REG(ANA_SG_STATUS_REG_1, 0x008980),
101 REG(ANA_SG_STATUS_REG_2, 0x008984),
102 REG(ANA_SG_STATUS_REG_3, 0x008988),
103 REG(ANA_PORT_VLAN_CFG, 0x007800),
104 REG(ANA_PORT_DROP_CFG, 0x007804),
105 REG(ANA_PORT_QOS_CFG, 0x007808),
106 REG(ANA_PORT_VCAP_CFG, 0x00780c),
107 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810),
108 REG(ANA_PORT_VCAP_S2_CFG, 0x00781c),
109 REG(ANA_PORT_PCP_DEI_MAP, 0x007820),
110 REG(ANA_PORT_CPU_FWD_CFG, 0x007860),
111 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864),
112 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868),
113 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c),
114 REG(ANA_PORT_PORT_CFG, 0x007870),
115 REG(ANA_PORT_POL_CFG, 0x007874),
116 REG(ANA_PORT_PTP_CFG, 0x007878),
117 REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c),
118 REG(ANA_PORT_PTP_DLY2_CFG, 0x007880),
119 REG(ANA_PORT_SFID_CFG, 0x007884),
120 REG(ANA_PFC_PFC_CFG, 0x008800),
121 REG_RESERVED(ANA_PFC_PFC_TIMER),
122 REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
123 REG_RESERVED(ANA_IPT_IPT),
124 REG_RESERVED(ANA_PPT_PPT),
125 REG_RESERVED(ANA_FID_MAP_FID_MAP),
126 REG(ANA_AGGR_CFG, 0x008a68),
127 REG(ANA_CPUQ_CFG, 0x008a6c),
128 REG_RESERVED(ANA_CPUQ_CFG2),
129 REG(ANA_CPUQ_8021_CFG, 0x008a74),
130 REG(ANA_DSCP_CFG, 0x008ab4),
131 REG(ANA_DSCP_REWR_CFG, 0x008bb4),
132 REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4),
133 REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14),
134 REG_RESERVED(ANA_VRAP_CFG),
135 REG_RESERVED(ANA_VRAP_HDR_DATA),
136 REG_RESERVED(ANA_VRAP_HDR_MASK),
137 REG(ANA_DISCARD_CFG, 0x008c40),
138 REG(ANA_FID_CFG, 0x008c44),
139 REG(ANA_POL_PIR_CFG, 0x004000),
140 REG(ANA_POL_CIR_CFG, 0x004004),
141 REG(ANA_POL_MODE_CFG, 0x004008),
142 REG(ANA_POL_PIR_STATE, 0x00400c),
143 REG(ANA_POL_CIR_STATE, 0x004010),
144 REG_RESERVED(ANA_POL_STATE),
145 REG(ANA_POL_FLOWC, 0x008c48),
146 REG(ANA_POL_HYST, 0x008cb4),
147 REG_RESERVED(ANA_POL_MISC_CFG),
148};
149
150static const u32 vsc9959_qs_regmap[] = {
151 REG(QS_XTR_GRP_CFG, 0x000000),
152 REG(QS_XTR_RD, 0x000008),
153 REG(QS_XTR_FRM_PRUNING, 0x000010),
154 REG(QS_XTR_FLUSH, 0x000018),
155 REG(QS_XTR_DATA_PRESENT, 0x00001c),
156 REG(QS_XTR_CFG, 0x000020),
157 REG(QS_INJ_GRP_CFG, 0x000024),
158 REG(QS_INJ_WR, 0x00002c),
159 REG(QS_INJ_CTRL, 0x000034),
160 REG(QS_INJ_STATUS, 0x00003c),
161 REG(QS_INJ_ERR, 0x000040),
162 REG_RESERVED(QS_INH_DBG),
163};
164
165static const u32 vsc9959_vcap_regmap[] = {
166 /* VCAP_CORE_CFG */
167 REG(VCAP_CORE_UPDATE_CTRL, 0x000000),
168 REG(VCAP_CORE_MV_CFG, 0x000004),
169 /* VCAP_CORE_CACHE */
170 REG(VCAP_CACHE_ENTRY_DAT, 0x000008),
171 REG(VCAP_CACHE_MASK_DAT, 0x000108),
172 REG(VCAP_CACHE_ACTION_DAT, 0x000208),
173 REG(VCAP_CACHE_CNT_DAT, 0x000308),
174 REG(VCAP_CACHE_TG_DAT, 0x000388),
175 /* VCAP_CONST */
176 REG(VCAP_CONST_VCAP_VER, 0x000398),
177 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c),
178 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0),
179 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4),
180 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8),
181 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac),
182 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0),
183 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4),
184 REG(VCAP_CONST_CORE_CNT, 0x0003b8),
185 REG(VCAP_CONST_IF_CNT, 0x0003bc),
186};
187
188static const u32 vsc9959_qsys_regmap[] = {
189 REG(QSYS_PORT_MODE, 0x00f460),
190 REG(QSYS_SWITCH_PORT_MODE, 0x00f480),
191 REG(QSYS_STAT_CNT_CFG, 0x00f49c),
192 REG(QSYS_EEE_CFG, 0x00f4a0),
193 REG(QSYS_EEE_THRES, 0x00f4b8),
194 REG(QSYS_IGR_NO_SHARING, 0x00f4bc),
195 REG(QSYS_EGR_NO_SHARING, 0x00f4c0),
196 REG(QSYS_SW_STATUS, 0x00f4c4),
197 REG(QSYS_EXT_CPU_CFG, 0x00f4e0),
198 REG_RESERVED(QSYS_PAD_CFG),
199 REG(QSYS_CPU_GROUP_MAP, 0x00f4e8),
200 REG_RESERVED(QSYS_QMAP),
201 REG_RESERVED(QSYS_ISDX_SGRP),
202 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
203 REG(QSYS_TFRM_MISC, 0x00f50c),
204 REG(QSYS_TFRM_PORT_DLY, 0x00f510),
205 REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514),
206 REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518),
207 REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c),
208 REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520),
209 REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524),
210 REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528),
211 REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c),
212 REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530),
213 REG(QSYS_RED_PROFILE, 0x00f534),
214 REG(QSYS_RES_QOS_MODE, 0x00f574),
215 REG(QSYS_RES_CFG, 0x00c000),
216 REG(QSYS_RES_STAT, 0x00c004),
217 REG(QSYS_EGR_DROP_MODE, 0x00f578),
218 REG(QSYS_EQ_CTRL, 0x00f57c),
219 REG_RESERVED(QSYS_EVENTS_CORE),
220 REG(QSYS_QMAXSDU_CFG_0, 0x00f584),
221 REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0),
222 REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc),
223 REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8),
224 REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4),
225 REG(QSYS_QMAXSDU_CFG_5, 0x00f610),
226 REG(QSYS_QMAXSDU_CFG_6, 0x00f62c),
227 REG(QSYS_QMAXSDU_CFG_7, 0x00f648),
228 REG(QSYS_PREEMPTION_CFG, 0x00f664),
229 REG(QSYS_CIR_CFG, 0x000000),
230 REG(QSYS_EIR_CFG, 0x000004),
231 REG(QSYS_SE_CFG, 0x000008),
232 REG(QSYS_SE_DWRR_CFG, 0x00000c),
233 REG_RESERVED(QSYS_SE_CONNECT),
234 REG(QSYS_SE_DLB_SENSE, 0x000040),
235 REG(QSYS_CIR_STATE, 0x000044),
236 REG(QSYS_EIR_STATE, 0x000048),
237 REG_RESERVED(QSYS_SE_STATE),
238 REG(QSYS_HSCH_MISC_CFG, 0x00f67c),
239 REG(QSYS_TAG_CONFIG, 0x00f680),
240 REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698),
241 REG(QSYS_PORT_MAX_SDU, 0x00f69c),
242 REG(QSYS_PARAM_CFG_REG_1, 0x00f440),
243 REG(QSYS_PARAM_CFG_REG_2, 0x00f444),
244 REG(QSYS_PARAM_CFG_REG_3, 0x00f448),
245 REG(QSYS_PARAM_CFG_REG_4, 0x00f44c),
246 REG(QSYS_PARAM_CFG_REG_5, 0x00f450),
247 REG(QSYS_GCL_CFG_REG_1, 0x00f454),
248 REG(QSYS_GCL_CFG_REG_2, 0x00f458),
249 REG(QSYS_PARAM_STATUS_REG_1, 0x00f400),
250 REG(QSYS_PARAM_STATUS_REG_2, 0x00f404),
251 REG(QSYS_PARAM_STATUS_REG_3, 0x00f408),
252 REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c),
253 REG(QSYS_PARAM_STATUS_REG_5, 0x00f410),
254 REG(QSYS_PARAM_STATUS_REG_6, 0x00f414),
255 REG(QSYS_PARAM_STATUS_REG_7, 0x00f418),
256 REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c),
257 REG(QSYS_PARAM_STATUS_REG_9, 0x00f420),
258 REG(QSYS_GCL_STATUS_REG_1, 0x00f424),
259 REG(QSYS_GCL_STATUS_REG_2, 0x00f428),
260};
261
262static const u32 vsc9959_rew_regmap[] = {
263 REG(REW_PORT_VLAN_CFG, 0x000000),
264 REG(REW_TAG_CFG, 0x000004),
265 REG(REW_PORT_CFG, 0x000008),
266 REG(REW_DSCP_CFG, 0x00000c),
267 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010),
268 REG(REW_PTP_CFG, 0x000050),
269 REG(REW_PTP_DLY1_CFG, 0x000054),
270 REG(REW_RED_TAG_CFG, 0x000058),
271 REG(REW_DSCP_REMAP_DP1_CFG, 0x000410),
272 REG(REW_DSCP_REMAP_CFG, 0x000510),
273 REG_RESERVED(REW_STAT_CFG),
274 REG_RESERVED(REW_REW_STICKY),
275 REG_RESERVED(REW_PPT),
276};
277
278static const u32 vsc9959_sys_regmap[] = {
279 REG(SYS_COUNT_RX_OCTETS, 0x000000),
280 REG(SYS_COUNT_RX_UNICAST, 0x000004),
281 REG(SYS_COUNT_RX_MULTICAST, 0x000008),
282 REG(SYS_COUNT_RX_BROADCAST, 0x00000c),
283 REG(SYS_COUNT_RX_SHORTS, 0x000010),
284 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014),
285 REG(SYS_COUNT_RX_JABBERS, 0x000018),
286 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c),
287 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020),
288 REG(SYS_COUNT_RX_64, 0x000024),
289 REG(SYS_COUNT_RX_65_127, 0x000028),
290 REG(SYS_COUNT_RX_128_255, 0x00002c),
291 REG(SYS_COUNT_RX_256_511, 0x000030),
292 REG(SYS_COUNT_RX_512_1023, 0x000034),
293 REG(SYS_COUNT_RX_1024_1526, 0x000038),
294 REG(SYS_COUNT_RX_1527_MAX, 0x00003c),
295 REG(SYS_COUNT_RX_PAUSE, 0x000040),
296 REG(SYS_COUNT_RX_CONTROL, 0x000044),
297 REG(SYS_COUNT_RX_LONGS, 0x000048),
298 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c),
299 REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050),
300 REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054),
301 REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058),
302 REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c),
303 REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060),
304 REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064),
305 REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068),
306 REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c),
307 REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070),
308 REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074),
309 REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078),
310 REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c),
311 REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080),
312 REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084),
313 REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088),
314 REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c),
315 REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090),
316 REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094),
317 REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098),
318 REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c),
319 REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0),
320 REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4),
321 REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8),
322 REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac),
323 REG(SYS_COUNT_RX_ASSEMBLY_ERRS, 0x0000b0),
324 REG(SYS_COUNT_RX_SMD_ERRS, 0x0000b4),
325 REG(SYS_COUNT_RX_ASSEMBLY_OK, 0x0000b8),
326 REG(SYS_COUNT_RX_MERGE_FRAGMENTS, 0x0000bc),
327 REG(SYS_COUNT_RX_PMAC_OCTETS, 0x0000c0),
328 REG(SYS_COUNT_RX_PMAC_UNICAST, 0x0000c4),
329 REG(SYS_COUNT_RX_PMAC_MULTICAST, 0x0000c8),
330 REG(SYS_COUNT_RX_PMAC_BROADCAST, 0x0000cc),
331 REG(SYS_COUNT_RX_PMAC_SHORTS, 0x0000d0),
332 REG(SYS_COUNT_RX_PMAC_FRAGMENTS, 0x0000d4),
333 REG(SYS_COUNT_RX_PMAC_JABBERS, 0x0000d8),
334 REG(SYS_COUNT_RX_PMAC_CRC_ALIGN_ERRS, 0x0000dc),
335 REG(SYS_COUNT_RX_PMAC_SYM_ERRS, 0x0000e0),
336 REG(SYS_COUNT_RX_PMAC_64, 0x0000e4),
337 REG(SYS_COUNT_RX_PMAC_65_127, 0x0000e8),
338 REG(SYS_COUNT_RX_PMAC_128_255, 0x0000ec),
339 REG(SYS_COUNT_RX_PMAC_256_511, 0x0000f0),
340 REG(SYS_COUNT_RX_PMAC_512_1023, 0x0000f4),
341 REG(SYS_COUNT_RX_PMAC_1024_1526, 0x0000f8),
342 REG(SYS_COUNT_RX_PMAC_1527_MAX, 0x0000fc),
343 REG(SYS_COUNT_RX_PMAC_PAUSE, 0x000100),
344 REG(SYS_COUNT_RX_PMAC_CONTROL, 0x000104),
345 REG(SYS_COUNT_RX_PMAC_LONGS, 0x000108),
346 REG(SYS_COUNT_TX_OCTETS, 0x000200),
347 REG(SYS_COUNT_TX_UNICAST, 0x000204),
348 REG(SYS_COUNT_TX_MULTICAST, 0x000208),
349 REG(SYS_COUNT_TX_BROADCAST, 0x00020c),
350 REG(SYS_COUNT_TX_COLLISION, 0x000210),
351 REG(SYS_COUNT_TX_DROPS, 0x000214),
352 REG(SYS_COUNT_TX_PAUSE, 0x000218),
353 REG(SYS_COUNT_TX_64, 0x00021c),
354 REG(SYS_COUNT_TX_65_127, 0x000220),
355 REG(SYS_COUNT_TX_128_255, 0x000224),
356 REG(SYS_COUNT_TX_256_511, 0x000228),
357 REG(SYS_COUNT_TX_512_1023, 0x00022c),
358 REG(SYS_COUNT_TX_1024_1526, 0x000230),
359 REG(SYS_COUNT_TX_1527_MAX, 0x000234),
360 REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000238),
361 REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00023c),
362 REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000240),
363 REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000244),
364 REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000248),
365 REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00024c),
366 REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000250),
367 REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000254),
368 REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000258),
369 REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00025c),
370 REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000260),
371 REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000264),
372 REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000268),
373 REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00026c),
374 REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000270),
375 REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000274),
376 REG(SYS_COUNT_TX_AGED, 0x000278),
377 REG(SYS_COUNT_TX_MM_HOLD, 0x00027c),
378 REG(SYS_COUNT_TX_MERGE_FRAGMENTS, 0x000280),
379 REG(SYS_COUNT_TX_PMAC_OCTETS, 0x000284),
380 REG(SYS_COUNT_TX_PMAC_UNICAST, 0x000288),
381 REG(SYS_COUNT_TX_PMAC_MULTICAST, 0x00028c),
382 REG(SYS_COUNT_TX_PMAC_BROADCAST, 0x000290),
383 REG(SYS_COUNT_TX_PMAC_PAUSE, 0x000294),
384 REG(SYS_COUNT_TX_PMAC_64, 0x000298),
385 REG(SYS_COUNT_TX_PMAC_65_127, 0x00029c),
386 REG(SYS_COUNT_TX_PMAC_128_255, 0x0002a0),
387 REG(SYS_COUNT_TX_PMAC_256_511, 0x0002a4),
388 REG(SYS_COUNT_TX_PMAC_512_1023, 0x0002a8),
389 REG(SYS_COUNT_TX_PMAC_1024_1526, 0x0002ac),
390 REG(SYS_COUNT_TX_PMAC_1527_MAX, 0x0002b0),
391 REG(SYS_COUNT_DROP_LOCAL, 0x000400),
392 REG(SYS_COUNT_DROP_TAIL, 0x000404),
393 REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000408),
394 REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00040c),
395 REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000410),
396 REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000414),
397 REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000418),
398 REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00041c),
399 REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000420),
400 REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000424),
401 REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000428),
402 REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00042c),
403 REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000430),
404 REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000434),
405 REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000438),
406 REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00043c),
407 REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000440),
408 REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000444),
409 REG(SYS_COUNT_SF_MATCHING_FRAMES, 0x000800),
410 REG(SYS_COUNT_SF_NOT_PASSING_FRAMES, 0x000804),
411 REG(SYS_COUNT_SF_NOT_PASSING_SDU, 0x000808),
412 REG(SYS_COUNT_SF_RED_FRAMES, 0x00080c),
413 REG(SYS_RESET_CFG, 0x000e00),
414 REG(SYS_SR_ETYPE_CFG, 0x000e04),
415 REG(SYS_VLAN_ETYPE_CFG, 0x000e08),
416 REG(SYS_PORT_MODE, 0x000e0c),
417 REG(SYS_FRONT_PORT_MODE, 0x000e2c),
418 REG(SYS_FRM_AGING, 0x000e44),
419 REG(SYS_STAT_CFG, 0x000e48),
420 REG(SYS_SW_STATUS, 0x000e4c),
421 REG_RESERVED(SYS_MISC_CFG),
422 REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c),
423 REG(SYS_REW_MAC_LOW_CFG, 0x000e84),
424 REG(SYS_TIMESTAMP_OFFSET, 0x000e9c),
425 REG(SYS_PAUSE_CFG, 0x000ea0),
426 REG(SYS_PAUSE_TOT_CFG, 0x000ebc),
427 REG(SYS_ATOP, 0x000ec0),
428 REG(SYS_ATOP_TOT_CFG, 0x000edc),
429 REG(SYS_MAC_FC_CFG, 0x000ee0),
430 REG(SYS_MMGT, 0x000ef8),
431 REG_RESERVED(SYS_MMGT_FAST),
432 REG_RESERVED(SYS_EVENTS_DIF),
433 REG_RESERVED(SYS_EVENTS_CORE),
434 REG(SYS_PTP_STATUS, 0x000f14),
435 REG(SYS_PTP_TXSTAMP, 0x000f18),
436 REG(SYS_PTP_NXT, 0x000f1c),
437 REG(SYS_PTP_CFG, 0x000f20),
438 REG(SYS_RAM_INIT, 0x000f24),
439 REG_RESERVED(SYS_CM_ADDR),
440 REG_RESERVED(SYS_CM_DATA_WR),
441 REG_RESERVED(SYS_CM_DATA_RD),
442 REG_RESERVED(SYS_CM_OP),
443 REG_RESERVED(SYS_CM_DATA),
444};
445
446static const u32 vsc9959_ptp_regmap[] = {
447 REG(PTP_PIN_CFG, 0x000000),
448 REG(PTP_PIN_TOD_SEC_MSB, 0x000004),
449 REG(PTP_PIN_TOD_SEC_LSB, 0x000008),
450 REG(PTP_PIN_TOD_NSEC, 0x00000c),
451 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014),
452 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018),
453 REG(PTP_CFG_MISC, 0x0000a0),
454 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4),
455 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8),
456};
457
458static const u32 vsc9959_gcb_regmap[] = {
459 REG(GCB_SOFT_RST, 0x000004),
460};
461
462static const u32 vsc9959_dev_gmii_regmap[] = {
463 REG(DEV_CLOCK_CFG, 0x0),
464 REG(DEV_PORT_MISC, 0x4),
465 REG(DEV_EVENTS, 0x8),
466 REG(DEV_EEE_CFG, 0xc),
467 REG(DEV_RX_PATH_DELAY, 0x10),
468 REG(DEV_TX_PATH_DELAY, 0x14),
469 REG(DEV_PTP_PREDICT_CFG, 0x18),
470 REG(DEV_MAC_ENA_CFG, 0x1c),
471 REG(DEV_MAC_MODE_CFG, 0x20),
472 REG(DEV_MAC_MAXLEN_CFG, 0x24),
473 REG(DEV_MAC_TAGS_CFG, 0x28),
474 REG(DEV_MAC_ADV_CHK_CFG, 0x2c),
475 REG(DEV_MAC_IFG_CFG, 0x30),
476 REG(DEV_MAC_HDX_CFG, 0x34),
477 REG(DEV_MAC_DBG_CFG, 0x38),
478 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c),
479 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40),
480 REG(DEV_MAC_STICKY, 0x44),
481 REG(DEV_MM_ENABLE_CONFIG, 0x48),
482 REG(DEV_MM_VERIF_CONFIG, 0x4C),
483 REG(DEV_MM_STATUS, 0x50),
484 REG_RESERVED(PCS1G_CFG),
485 REG_RESERVED(PCS1G_MODE_CFG),
486 REG_RESERVED(PCS1G_SD_CFG),
487 REG_RESERVED(PCS1G_ANEG_CFG),
488 REG_RESERVED(PCS1G_ANEG_NP_CFG),
489 REG_RESERVED(PCS1G_LB_CFG),
490 REG_RESERVED(PCS1G_DBG_CFG),
491 REG_RESERVED(PCS1G_CDET_CFG),
492 REG_RESERVED(PCS1G_ANEG_STATUS),
493 REG_RESERVED(PCS1G_ANEG_NP_STATUS),
494 REG_RESERVED(PCS1G_LINK_STATUS),
495 REG_RESERVED(PCS1G_LINK_DOWN_CNT),
496 REG_RESERVED(PCS1G_STICKY),
497 REG_RESERVED(PCS1G_DEBUG_STATUS),
498 REG_RESERVED(PCS1G_LPI_CFG),
499 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT),
500 REG_RESERVED(PCS1G_LPI_STATUS),
501 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG),
502 REG_RESERVED(PCS1G_TSTPAT_STATUS),
503 REG_RESERVED(DEV_PCS_FX100_CFG),
504 REG_RESERVED(DEV_PCS_FX100_STATUS),
505};
506
507static const u32 *vsc9959_regmap[TARGET_MAX] = {
508 [ANA] = vsc9959_ana_regmap,
509 [QS] = vsc9959_qs_regmap,
510 [QSYS] = vsc9959_qsys_regmap,
511 [REW] = vsc9959_rew_regmap,
512 [SYS] = vsc9959_sys_regmap,
513 [S0] = vsc9959_vcap_regmap,
514 [S1] = vsc9959_vcap_regmap,
515 [S2] = vsc9959_vcap_regmap,
516 [PTP] = vsc9959_ptp_regmap,
517 [GCB] = vsc9959_gcb_regmap,
518 [DEV_GMII] = vsc9959_dev_gmii_regmap,
519};
520
521/* Addresses are relative to the PCI device's base address */
522static const struct resource vsc9959_resources[] = {
523 DEFINE_RES_MEM_NAMED(0x0010000, 0x0010000, "sys"),
524 DEFINE_RES_MEM_NAMED(0x0030000, 0x0010000, "rew"),
525 DEFINE_RES_MEM_NAMED(0x0040000, 0x0000400, "s0"),
526 DEFINE_RES_MEM_NAMED(0x0050000, 0x0000400, "s1"),
527 DEFINE_RES_MEM_NAMED(0x0060000, 0x0000400, "s2"),
528 DEFINE_RES_MEM_NAMED(0x0070000, 0x0000200, "devcpu_gcb"),
529 DEFINE_RES_MEM_NAMED(0x0080000, 0x0000100, "qs"),
530 DEFINE_RES_MEM_NAMED(0x0090000, 0x00000cc, "ptp"),
531 DEFINE_RES_MEM_NAMED(0x0100000, 0x0010000, "port0"),
532 DEFINE_RES_MEM_NAMED(0x0110000, 0x0010000, "port1"),
533 DEFINE_RES_MEM_NAMED(0x0120000, 0x0010000, "port2"),
534 DEFINE_RES_MEM_NAMED(0x0130000, 0x0010000, "port3"),
535 DEFINE_RES_MEM_NAMED(0x0140000, 0x0010000, "port4"),
536 DEFINE_RES_MEM_NAMED(0x0150000, 0x0010000, "port5"),
537 DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys"),
538 DEFINE_RES_MEM_NAMED(0x0280000, 0x0010000, "ana"),
539};
540
541static const char * const vsc9959_resource_names[TARGET_MAX] = {
542 [SYS] = "sys",
543 [REW] = "rew",
544 [S0] = "s0",
545 [S1] = "s1",
546 [S2] = "s2",
547 [GCB] = "devcpu_gcb",
548 [QS] = "qs",
549 [PTP] = "ptp",
550 [QSYS] = "qsys",
551 [ANA] = "ana",
552};
553
554/* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
555 * SGMII/QSGMII MAC PCS can be found.
556 */
557static const struct resource vsc9959_imdio_res =
558 DEFINE_RES_MEM_NAMED(0x8030, 0x10, "imdio");
559
560static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = {
561 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
562 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
563 [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30),
564 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26),
565 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24),
566 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23),
567 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22),
568 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21),
569 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20),
570 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19),
571 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
572 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17),
573 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15),
574 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14),
575 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13),
576 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12),
577 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
578 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
579 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9),
580 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8),
581 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7),
582 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
583 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
584 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4),
585 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3),
586 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2),
587 [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1),
588 [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0),
589 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
590 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
591 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
592 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),
593 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
594 /* Replicated per number of ports (7), register size 4 per port */
595 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4),
596 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4),
597 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4),
598 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4),
599 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4),
600 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4),
601 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4),
602 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4),
603 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4),
604 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4),
605 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4),
606 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4),
607 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4),
608};
609
610static const struct vcap_field vsc9959_vcap_es0_keys[] = {
611 [VCAP_ES0_EGR_PORT] = { 0, 3},
612 [VCAP_ES0_IGR_PORT] = { 3, 3},
613 [VCAP_ES0_RSV] = { 6, 2},
614 [VCAP_ES0_L2_MC] = { 8, 1},
615 [VCAP_ES0_L2_BC] = { 9, 1},
616 [VCAP_ES0_VID] = { 10, 12},
617 [VCAP_ES0_DP] = { 22, 1},
618 [VCAP_ES0_PCP] = { 23, 3},
619};
620
621static const struct vcap_field vsc9959_vcap_es0_actions[] = {
622 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2},
623 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1},
624 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2},
625 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1},
626 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2},
627 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2},
628 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2},
629 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1},
630 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2},
631 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2},
632 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12},
633 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3},
634 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1},
635 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12},
636 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3},
637 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1},
638 [VCAP_ES0_ACT_RSV] = { 49, 23},
639 [VCAP_ES0_ACT_HIT_STICKY] = { 72, 1},
640};
641
642static const struct vcap_field vsc9959_vcap_is1_keys[] = {
643 [VCAP_IS1_HK_TYPE] = { 0, 1},
644 [VCAP_IS1_HK_LOOKUP] = { 1, 2},
645 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 7},
646 [VCAP_IS1_HK_RSV] = { 10, 9},
647 [VCAP_IS1_HK_OAM_Y1731] = { 19, 1},
648 [VCAP_IS1_HK_L2_MC] = { 20, 1},
649 [VCAP_IS1_HK_L2_BC] = { 21, 1},
650 [VCAP_IS1_HK_IP_MC] = { 22, 1},
651 [VCAP_IS1_HK_VLAN_TAGGED] = { 23, 1},
652 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 24, 1},
653 [VCAP_IS1_HK_TPID] = { 25, 1},
654 [VCAP_IS1_HK_VID] = { 26, 12},
655 [VCAP_IS1_HK_DEI] = { 38, 1},
656 [VCAP_IS1_HK_PCP] = { 39, 3},
657 /* Specific Fields for IS1 Half Key S1_NORMAL */
658 [VCAP_IS1_HK_L2_SMAC] = { 42, 48},
659 [VCAP_IS1_HK_ETYPE_LEN] = { 90, 1},
660 [VCAP_IS1_HK_ETYPE] = { 91, 16},
661 [VCAP_IS1_HK_IP_SNAP] = {107, 1},
662 [VCAP_IS1_HK_IP4] = {108, 1},
663 /* Layer-3 Information */
664 [VCAP_IS1_HK_L3_FRAGMENT] = {109, 1},
665 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {110, 1},
666 [VCAP_IS1_HK_L3_OPTIONS] = {111, 1},
667 [VCAP_IS1_HK_L3_DSCP] = {112, 6},
668 [VCAP_IS1_HK_L3_IP4_SIP] = {118, 32},
669 /* Layer-4 Information */
670 [VCAP_IS1_HK_TCP_UDP] = {150, 1},
671 [VCAP_IS1_HK_TCP] = {151, 1},
672 [VCAP_IS1_HK_L4_SPORT] = {152, 16},
673 [VCAP_IS1_HK_L4_RNG] = {168, 8},
674 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
675 [VCAP_IS1_HK_IP4_INNER_TPID] = { 42, 1},
676 [VCAP_IS1_HK_IP4_INNER_VID] = { 43, 12},
677 [VCAP_IS1_HK_IP4_INNER_DEI] = { 55, 1},
678 [VCAP_IS1_HK_IP4_INNER_PCP] = { 56, 3},
679 [VCAP_IS1_HK_IP4_IP4] = { 59, 1},
680 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 60, 1},
681 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 61, 1},
682 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 62, 1},
683 [VCAP_IS1_HK_IP4_L3_DSCP] = { 63, 6},
684 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 69, 32},
685 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {101, 32},
686 [VCAP_IS1_HK_IP4_L3_PROTO] = {133, 8},
687 [VCAP_IS1_HK_IP4_TCP_UDP] = {141, 1},
688 [VCAP_IS1_HK_IP4_TCP] = {142, 1},
689 [VCAP_IS1_HK_IP4_L4_RNG] = {143, 8},
690 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {151, 32},
691};
692
693static const struct vcap_field vsc9959_vcap_is1_actions[] = {
694 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1},
695 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6},
696 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1},
697 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3},
698 [VCAP_IS1_ACT_DP_ENA] = { 11, 1},
699 [VCAP_IS1_ACT_DP_VAL] = { 12, 1},
700 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8},
701 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8},
702 [VCAP_IS1_ACT_RSV] = { 29, 9},
703 /* The fields below are incorrectly shifted by 2 in the manual */
704 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1},
705 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12},
706 [VCAP_IS1_ACT_FID_SEL] = { 51, 2},
707 [VCAP_IS1_ACT_FID_VAL] = { 53, 13},
708 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1},
709 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3},
710 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1},
711 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1},
712 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2},
713 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4},
714 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1},
715};
716
717static struct vcap_field vsc9959_vcap_is2_keys[] = {
718 /* Common: 41 bits */
719 [VCAP_IS2_TYPE] = { 0, 4},
720 [VCAP_IS2_HK_FIRST] = { 4, 1},
721 [VCAP_IS2_HK_PAG] = { 5, 8},
722 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7},
723 [VCAP_IS2_HK_RSV2] = { 20, 1},
724 [VCAP_IS2_HK_HOST_MATCH] = { 21, 1},
725 [VCAP_IS2_HK_L2_MC] = { 22, 1},
726 [VCAP_IS2_HK_L2_BC] = { 23, 1},
727 [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1},
728 [VCAP_IS2_HK_VID] = { 25, 12},
729 [VCAP_IS2_HK_DEI] = { 37, 1},
730 [VCAP_IS2_HK_PCP] = { 38, 3},
731 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
732 [VCAP_IS2_HK_L2_DMAC] = { 41, 48},
733 [VCAP_IS2_HK_L2_SMAC] = { 89, 48},
734 /* MAC_ETYPE (TYPE=000) */
735 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16},
736 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16},
737 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8},
738 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3},
739 /* MAC_LLC (TYPE=001) */
740 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40},
741 /* MAC_SNAP (TYPE=010) */
742 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40},
743 /* MAC_ARP (TYPE=011) */
744 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48},
745 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1},
746 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1},
747 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1},
748 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1},
749 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1},
750 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1},
751 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2},
752 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32},
753 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32},
754 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1},
755 /* IP4_TCP_UDP / IP4_OTHER common */
756 [VCAP_IS2_HK_IP4] = { 41, 1},
757 [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1},
758 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1},
759 [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1},
760 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1},
761 [VCAP_IS2_HK_L3_TOS] = { 46, 8},
762 [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32},
763 [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32},
764 [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1},
765 /* IP4_TCP_UDP (TYPE=100) */
766 [VCAP_IS2_HK_TCP] = {119, 1},
767 [VCAP_IS2_HK_L4_DPORT] = {120, 16},
768 [VCAP_IS2_HK_L4_SPORT] = {136, 16},
769 [VCAP_IS2_HK_L4_RNG] = {152, 8},
770 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1},
771 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1},
772 [VCAP_IS2_HK_L4_FIN] = {162, 1},
773 [VCAP_IS2_HK_L4_SYN] = {163, 1},
774 [VCAP_IS2_HK_L4_RST] = {164, 1},
775 [VCAP_IS2_HK_L4_PSH] = {165, 1},
776 [VCAP_IS2_HK_L4_ACK] = {166, 1},
777 [VCAP_IS2_HK_L4_URG] = {167, 1},
778 [VCAP_IS2_HK_L4_1588_DOM] = {168, 8},
779 [VCAP_IS2_HK_L4_1588_VER] = {176, 4},
780 /* IP4_OTHER (TYPE=101) */
781 [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8},
782 [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56},
783 /* IP6_STD (TYPE=110) */
784 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1},
785 [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128},
786 [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8},
787 /* OAM (TYPE=111) */
788 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7},
789 [VCAP_IS2_HK_OAM_VER] = {144, 5},
790 [VCAP_IS2_HK_OAM_OPCODE] = {149, 8},
791 [VCAP_IS2_HK_OAM_FLAGS] = {157, 8},
792 [VCAP_IS2_HK_OAM_MEPID] = {165, 16},
793 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1},
794 [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1},
795};
796
797static struct vcap_field vsc9959_vcap_is2_actions[] = {
798 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1},
799 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1},
800 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3},
801 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2},
802 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1},
803 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1},
804 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1},
805 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9},
806 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1},
807 [VCAP_IS2_ACT_PORT_MASK] = { 20, 6},
808 [VCAP_IS2_ACT_REW_OP] = { 26, 9},
809 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 35, 1},
810 [VCAP_IS2_ACT_RSV] = { 36, 2},
811 [VCAP_IS2_ACT_ACL_ID] = { 38, 6},
812 [VCAP_IS2_ACT_HIT_CNT] = { 44, 32},
813};
814
815static struct vcap_props vsc9959_vcap_props[] = {
816 [VCAP_ES0] = {
817 .action_type_width = 0,
818 .action_table = {
819 [ES0_ACTION_TYPE_NORMAL] = {
820 .width = 72, /* HIT_STICKY not included */
821 .count = 1,
822 },
823 },
824 .target = S0,
825 .keys = vsc9959_vcap_es0_keys,
826 .actions = vsc9959_vcap_es0_actions,
827 },
828 [VCAP_IS1] = {
829 .action_type_width = 0,
830 .action_table = {
831 [IS1_ACTION_TYPE_NORMAL] = {
832 .width = 78, /* HIT_STICKY not included */
833 .count = 4,
834 },
835 },
836 .target = S1,
837 .keys = vsc9959_vcap_is1_keys,
838 .actions = vsc9959_vcap_is1_actions,
839 },
840 [VCAP_IS2] = {
841 .action_type_width = 1,
842 .action_table = {
843 [IS2_ACTION_TYPE_NORMAL] = {
844 .width = 44,
845 .count = 2
846 },
847 [IS2_ACTION_TYPE_SMAC_SIP] = {
848 .width = 6,
849 .count = 4
850 },
851 },
852 .target = S2,
853 .keys = vsc9959_vcap_is2_keys,
854 .actions = vsc9959_vcap_is2_actions,
855 },
856};
857
858static const struct ptp_clock_info vsc9959_ptp_caps = {
859 .owner = THIS_MODULE,
860 .name = "felix ptp",
861 .max_adj = 0x7fffffff,
862 .n_alarm = 0,
863 .n_ext_ts = 0,
864 .n_per_out = OCELOT_PTP_PINS_NUM,
865 .n_pins = OCELOT_PTP_PINS_NUM,
866 .pps = 0,
867 .gettime64 = ocelot_ptp_gettime64,
868 .settime64 = ocelot_ptp_settime64,
869 .adjtime = ocelot_ptp_adjtime,
870 .adjfine = ocelot_ptp_adjfine,
871 .verify = ocelot_ptp_verify,
872 .enable = ocelot_ptp_enable,
873};
874
875#define VSC9959_INIT_TIMEOUT 50000
876#define VSC9959_GCB_RST_SLEEP 100
877#define VSC9959_SYS_RAMINIT_SLEEP 80
878
879static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot)
880{
881 int val;
882
883 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val);
884
885 return val;
886}
887
888static int vsc9959_sys_ram_init_status(struct ocelot *ocelot)
889{
890 return ocelot_read(ocelot, SYS_RAM_INIT);
891}
892
893/* CORE_ENA is in SYS:SYSTEM:RESET_CFG
894 * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT
895 */
896static int vsc9959_reset(struct ocelot *ocelot)
897{
898 int val, err;
899
900 /* soft-reset the switch core */
901 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1);
902
903 err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val,
904 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT);
905 if (err) {
906 dev_err(ocelot->dev, "timeout: switch core reset\n");
907 return err;
908 }
909
910 /* initialize switch mem ~40us */
911 ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT);
912 err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val,
913 VSC9959_SYS_RAMINIT_SLEEP,
914 VSC9959_INIT_TIMEOUT);
915 if (err) {
916 dev_err(ocelot->dev, "timeout: switch sram init\n");
917 return err;
918 }
919
920 /* enable switch core */
921 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1);
922
923 return 0;
924}
925
926/* Watermark encode
927 * Bit 8: Unit; 0:1, 1:16
928 * Bit 7-0: Value to be multiplied with unit
929 */
930static u16 vsc9959_wm_enc(u16 value)
931{
932 WARN_ON(value >= 16 * BIT(8));
933
934 if (value >= BIT(8))
935 return BIT(8) | (value / 16);
936
937 return value;
938}
939
940static u16 vsc9959_wm_dec(u16 wm)
941{
942 WARN_ON(wm & ~GENMASK(8, 0));
943
944 if (wm & BIT(8))
945 return (wm & GENMASK(7, 0)) * 16;
946
947 return wm;
948}
949
950static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse)
951{
952 *inuse = (val & GENMASK(23, 12)) >> 12;
953 *maxuse = val & GENMASK(11, 0);
954}
955
956static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)
957{
958 struct pci_dev *pdev = to_pci_dev(ocelot->dev);
959 struct felix *felix = ocelot_to_felix(ocelot);
960 struct enetc_mdio_priv *mdio_priv;
961 struct device *dev = ocelot->dev;
962 resource_size_t imdio_base;
963 void __iomem *imdio_regs;
964 struct resource res;
965 struct enetc_hw *hw;
966 struct mii_bus *bus;
967 int port;
968 int rc;
969
970 felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
971 sizeof(struct phylink_pcs *),
972 GFP_KERNEL);
973 if (!felix->pcs) {
974 dev_err(dev, "failed to allocate array for PCS PHYs\n");
975 return -ENOMEM;
976 }
977
978 imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR);
979
980 memcpy(&res, &vsc9959_imdio_res, sizeof(res));
981 res.start += imdio_base;
982 res.end += imdio_base;
983
984 imdio_regs = devm_ioremap_resource(dev, &res);
985 if (IS_ERR(imdio_regs))
986 return PTR_ERR(imdio_regs);
987
988 hw = enetc_hw_alloc(dev, imdio_regs);
989 if (IS_ERR(hw)) {
990 dev_err(dev, "failed to allocate ENETC HW structure\n");
991 return PTR_ERR(hw);
992 }
993
994 bus = mdiobus_alloc_size(sizeof(*mdio_priv));
995 if (!bus)
996 return -ENOMEM;
997
998 bus->name = "VSC9959 internal MDIO bus";
999 bus->read = enetc_mdio_read_c22;
1000 bus->write = enetc_mdio_write_c22;
1001 bus->read_c45 = enetc_mdio_read_c45;
1002 bus->write_c45 = enetc_mdio_write_c45;
1003 bus->parent = dev;
1004 mdio_priv = bus->priv;
1005 mdio_priv->hw = hw;
1006 /* This gets added to imdio_regs, which already maps addresses
1007 * starting with the proper offset.
1008 */
1009 mdio_priv->mdio_base = 0;
1010 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
1011
1012 /* Needed in order to initialize the bus mutex lock */
1013 rc = mdiobus_register(bus);
1014 if (rc < 0) {
1015 dev_err(dev, "failed to register MDIO bus\n");
1016 mdiobus_free(bus);
1017 return rc;
1018 }
1019
1020 felix->imdio = bus;
1021
1022 for (port = 0; port < felix->info->num_ports; port++) {
1023 struct ocelot_port *ocelot_port = ocelot->ports[port];
1024 struct phylink_pcs *phylink_pcs;
1025
1026 if (dsa_is_unused_port(felix->ds, port))
1027 continue;
1028
1029 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)
1030 continue;
1031
1032 phylink_pcs = lynx_pcs_create_mdiodev(felix->imdio, port);
1033 if (IS_ERR(phylink_pcs))
1034 continue;
1035
1036 felix->pcs[port] = phylink_pcs;
1037
1038 dev_info(dev, "Found PCS at internal MDIO address %d\n", port);
1039 }
1040
1041 return 0;
1042}
1043
1044static void vsc9959_mdio_bus_free(struct ocelot *ocelot)
1045{
1046 struct felix *felix = ocelot_to_felix(ocelot);
1047 int port;
1048
1049 for (port = 0; port < ocelot->num_phys_ports; port++) {
1050 struct phylink_pcs *phylink_pcs = felix->pcs[port];
1051
1052 if (phylink_pcs)
1053 lynx_pcs_destroy(phylink_pcs);
1054 }
1055 mdiobus_unregister(felix->imdio);
1056 mdiobus_free(felix->imdio);
1057}
1058
1059/* The switch considers any frame (regardless of size) as eligible
1060 * for transmission if the traffic class gate is open for at least
1061 * VSC9959_TAS_MIN_GATE_LEN_NS.
1062 *
1063 * Overruns are prevented by cropping an interval at the end of the gate time
1064 * slot for which egress scheduling is blocked, but we need to still keep
1065 * VSC9959_TAS_MIN_GATE_LEN_NS available for one packet to be transmitted,
1066 * otherwise the port tc will hang.
1067 *
1068 * This function returns the size of a gate interval that remains available for
1069 * setting the guard band, after reserving the space for one egress frame.
1070 */
1071static u64 vsc9959_tas_remaining_gate_len_ps(u64 gate_len_ns)
1072{
1073 /* Gate always open */
1074 if (gate_len_ns == U64_MAX)
1075 return U64_MAX;
1076
1077 if (gate_len_ns < VSC9959_TAS_MIN_GATE_LEN_NS)
1078 return 0;
1079
1080 return (gate_len_ns - VSC9959_TAS_MIN_GATE_LEN_NS) * PSEC_PER_NSEC;
1081}
1082
1083/* Extract shortest continuous gate open intervals in ns for each traffic class
1084 * of a cyclic tc-taprio schedule. If a gate is always open, the duration is
1085 * considered U64_MAX. If the gate is always closed, it is considered 0.
1086 */
1087static void vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload *taprio,
1088 u64 min_gate_len[OCELOT_NUM_TC])
1089{
1090 struct tc_taprio_sched_entry *entry;
1091 u64 gate_len[OCELOT_NUM_TC];
1092 u8 gates_ever_opened = 0;
1093 int tc, i, n;
1094
1095 /* Initialize arrays */
1096 for (tc = 0; tc < OCELOT_NUM_TC; tc++) {
1097 min_gate_len[tc] = U64_MAX;
1098 gate_len[tc] = 0;
1099 }
1100
1101 /* If we don't have taprio, consider all gates as permanently open */
1102 if (!taprio)
1103 return;
1104
1105 n = taprio->num_entries;
1106
1107 /* Walk through the gate list twice to determine the length
1108 * of consecutively open gates for a traffic class, including
1109 * open gates that wrap around. We are just interested in the
1110 * minimum window size, and this doesn't change what the
1111 * minimum is (if the gate never closes, min_gate_len will
1112 * remain U64_MAX).
1113 */
1114 for (i = 0; i < 2 * n; i++) {
1115 entry = &taprio->entries[i % n];
1116
1117 for (tc = 0; tc < OCELOT_NUM_TC; tc++) {
1118 if (entry->gate_mask & BIT(tc)) {
1119 gate_len[tc] += entry->interval;
1120 gates_ever_opened |= BIT(tc);
1121 } else {
1122 /* Gate closes now, record a potential new
1123 * minimum and reinitialize length
1124 */
1125 if (min_gate_len[tc] > gate_len[tc] &&
1126 gate_len[tc])
1127 min_gate_len[tc] = gate_len[tc];
1128 gate_len[tc] = 0;
1129 }
1130 }
1131 }
1132
1133 /* min_gate_len[tc] actually tracks minimum *open* gate time, so for
1134 * permanently closed gates, min_gate_len[tc] will still be U64_MAX.
1135 * Therefore they are currently indistinguishable from permanently
1136 * open gates. Overwrite the gate len with 0 when we know they're
1137 * actually permanently closed, i.e. after the loop above.
1138 */
1139 for (tc = 0; tc < OCELOT_NUM_TC; tc++)
1140 if (!(gates_ever_opened & BIT(tc)))
1141 min_gate_len[tc] = 0;
1142}
1143
1144/* ocelot_write_rix is a macro that concatenates QSYS_MAXSDU_CFG_* with _RSZ,
1145 * so we need to spell out the register access to each traffic class in helper
1146 * functions, to simplify callers
1147 */
1148static void vsc9959_port_qmaxsdu_set(struct ocelot *ocelot, int port, int tc,
1149 u32 max_sdu)
1150{
1151 switch (tc) {
1152 case 0:
1153 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_0,
1154 port);
1155 break;
1156 case 1:
1157 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_1,
1158 port);
1159 break;
1160 case 2:
1161 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_2,
1162 port);
1163 break;
1164 case 3:
1165 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_3,
1166 port);
1167 break;
1168 case 4:
1169 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_4,
1170 port);
1171 break;
1172 case 5:
1173 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_5,
1174 port);
1175 break;
1176 case 6:
1177 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_6,
1178 port);
1179 break;
1180 case 7:
1181 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_7,
1182 port);
1183 break;
1184 }
1185}
1186
1187static u32 vsc9959_port_qmaxsdu_get(struct ocelot *ocelot, int port, int tc)
1188{
1189 switch (tc) {
1190 case 0: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_0, port);
1191 case 1: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_1, port);
1192 case 2: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_2, port);
1193 case 3: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_3, port);
1194 case 4: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_4, port);
1195 case 5: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_5, port);
1196 case 6: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_6, port);
1197 case 7: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_7, port);
1198 default:
1199 return 0;
1200 }
1201}
1202
1203static u32 vsc9959_tas_tc_max_sdu(struct tc_taprio_qopt_offload *taprio, int tc)
1204{
1205 if (!taprio || !taprio->max_sdu[tc])
1206 return 0;
1207
1208 return taprio->max_sdu[tc] + ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN;
1209}
1210
1211/* Update QSYS_PORT_MAX_SDU to make sure the static guard bands added by the
1212 * switch (see the ALWAYS_GUARD_BAND_SCH_Q comment) are correct at all MTU
1213 * values (the default value is 1518). Also, for traffic class windows smaller
1214 * than one MTU sized frame, update QSYS_QMAXSDU_CFG to enable oversized frame
1215 * dropping, such that these won't hang the port, as they will never be sent.
1216 */
1217static void vsc9959_tas_guard_bands_update(struct ocelot *ocelot, int port)
1218{
1219 struct ocelot_port *ocelot_port = ocelot->ports[port];
1220 struct ocelot_mm_state *mm = &ocelot->mm[port];
1221 struct tc_taprio_qopt_offload *taprio;
1222 u64 min_gate_len[OCELOT_NUM_TC];
1223 u32 val, maxlen, add_frag_size;
1224 u64 needed_min_frag_time_ps;
1225 int speed, picos_per_byte;
1226 u64 needed_bit_time_ps;
1227 u8 tas_speed;
1228 int tc;
1229
1230 lockdep_assert_held(&ocelot->fwd_domain_lock);
1231
1232 taprio = ocelot_port->taprio;
1233
1234 val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port);
1235 tas_speed = QSYS_TAG_CONFIG_LINK_SPEED_X(val);
1236
1237 switch (tas_speed) {
1238 case OCELOT_SPEED_10:
1239 speed = SPEED_10;
1240 break;
1241 case OCELOT_SPEED_100:
1242 speed = SPEED_100;
1243 break;
1244 case OCELOT_SPEED_1000:
1245 speed = SPEED_1000;
1246 break;
1247 case OCELOT_SPEED_2500:
1248 speed = SPEED_2500;
1249 break;
1250 default:
1251 return;
1252 }
1253
1254 picos_per_byte = (USEC_PER_SEC * 8) / speed;
1255
1256 val = ocelot_port_readl(ocelot_port, DEV_MAC_MAXLEN_CFG);
1257 /* MAXLEN_CFG accounts automatically for VLAN. We need to include it
1258 * manually in the bit time calculation, plus the preamble and SFD.
1259 */
1260 maxlen = val + 2 * VLAN_HLEN;
1261 /* Consider the standard Ethernet overhead of 8 octets preamble+SFD,
1262 * 4 octets FCS, 12 octets IFG.
1263 */
1264 needed_bit_time_ps = (u64)(maxlen + 24) * picos_per_byte;
1265
1266 /* Preemptible TCs don't need to pass a full MTU, the port will
1267 * automatically emit a HOLD request when a preemptible TC gate closes
1268 */
1269 val = ocelot_read_rix(ocelot, QSYS_PREEMPTION_CFG, port);
1270 add_frag_size = QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(val);
1271 needed_min_frag_time_ps = picos_per_byte *
1272 (u64)(24 + 2 * ethtool_mm_frag_size_add_to_min(add_frag_size));
1273
1274 dev_dbg(ocelot->dev,
1275 "port %d: max frame size %d needs %llu ps, %llu ps for mPackets at speed %d\n",
1276 port, maxlen, needed_bit_time_ps, needed_min_frag_time_ps,
1277 speed);
1278
1279 vsc9959_tas_min_gate_lengths(taprio, min_gate_len);
1280
1281 for (tc = 0; tc < OCELOT_NUM_TC; tc++) {
1282 u32 requested_max_sdu = vsc9959_tas_tc_max_sdu(taprio, tc);
1283 u64 remaining_gate_len_ps;
1284 u32 max_sdu;
1285
1286 remaining_gate_len_ps =
1287 vsc9959_tas_remaining_gate_len_ps(min_gate_len[tc]);
1288
1289 if ((mm->active_preemptible_tcs & BIT(tc)) ?
1290 remaining_gate_len_ps > needed_min_frag_time_ps :
1291 remaining_gate_len_ps > needed_bit_time_ps) {
1292 /* Setting QMAXSDU_CFG to 0 disables oversized frame
1293 * dropping.
1294 */
1295 max_sdu = requested_max_sdu;
1296 dev_dbg(ocelot->dev,
1297 "port %d tc %d min gate len %llu"
1298 ", sending all frames\n",
1299 port, tc, min_gate_len[tc]);
1300 } else {
1301 /* If traffic class doesn't support a full MTU sized
1302 * frame, make sure to enable oversize frame dropping
1303 * for frames larger than the smallest that would fit.
1304 *
1305 * However, the exact same register, QSYS_QMAXSDU_CFG_*,
1306 * controls not only oversized frame dropping, but also
1307 * per-tc static guard band lengths, so it reduces the
1308 * useful gate interval length. Therefore, be careful
1309 * to calculate a guard band (and therefore max_sdu)
1310 * that still leaves VSC9959_TAS_MIN_GATE_LEN_NS
1311 * available in the time slot.
1312 */
1313 max_sdu = div_u64(remaining_gate_len_ps, picos_per_byte);
1314 /* A TC gate may be completely closed, which is a
1315 * special case where all packets are oversized.
1316 * Any limit smaller than 64 octets accomplishes this
1317 */
1318 if (!max_sdu)
1319 max_sdu = 1;
1320 /* Take L1 overhead into account, but just don't allow
1321 * max_sdu to go negative or to 0. Here we use 20
1322 * because QSYS_MAXSDU_CFG_* already counts the 4 FCS
1323 * octets as part of packet size.
1324 */
1325 if (max_sdu > 20)
1326 max_sdu -= 20;
1327
1328 if (requested_max_sdu && requested_max_sdu < max_sdu)
1329 max_sdu = requested_max_sdu;
1330
1331 dev_info(ocelot->dev,
1332 "port %d tc %d min gate length %llu"
1333 " ns not enough for max frame size %d at %d"
1334 " Mbps, dropping frames over %d"
1335 " octets including FCS\n",
1336 port, tc, min_gate_len[tc], maxlen, speed,
1337 max_sdu);
1338 }
1339
1340 vsc9959_port_qmaxsdu_set(ocelot, port, tc, max_sdu);
1341 }
1342
1343 ocelot_write_rix(ocelot, maxlen, QSYS_PORT_MAX_SDU, port);
1344
1345 ocelot->ops->cut_through_fwd(ocelot);
1346}
1347
1348static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port,
1349 u32 speed)
1350{
1351 struct ocelot_port *ocelot_port = ocelot->ports[port];
1352 u8 tas_speed;
1353
1354 switch (speed) {
1355 case SPEED_10:
1356 tas_speed = OCELOT_SPEED_10;
1357 break;
1358 case SPEED_100:
1359 tas_speed = OCELOT_SPEED_100;
1360 break;
1361 case SPEED_1000:
1362 tas_speed = OCELOT_SPEED_1000;
1363 break;
1364 case SPEED_2500:
1365 tas_speed = OCELOT_SPEED_2500;
1366 break;
1367 default:
1368 tas_speed = OCELOT_SPEED_1000;
1369 break;
1370 }
1371
1372 mutex_lock(&ocelot->fwd_domain_lock);
1373
1374 ocelot_rmw_rix(ocelot,
1375 QSYS_TAG_CONFIG_LINK_SPEED(tas_speed),
1376 QSYS_TAG_CONFIG_LINK_SPEED_M,
1377 QSYS_TAG_CONFIG, port);
1378
1379 if (ocelot_port->taprio)
1380 vsc9959_tas_guard_bands_update(ocelot, port);
1381
1382 mutex_unlock(&ocelot->fwd_domain_lock);
1383}
1384
1385static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time,
1386 u64 cycle_time,
1387 struct timespec64 *new_base_ts)
1388{
1389 struct timespec64 ts;
1390 ktime_t new_base_time;
1391 ktime_t current_time;
1392
1393 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1394 current_time = timespec64_to_ktime(ts);
1395 new_base_time = base_time;
1396
1397 if (base_time < current_time) {
1398 u64 nr_of_cycles = current_time - base_time;
1399
1400 do_div(nr_of_cycles, cycle_time);
1401 new_base_time += cycle_time * (nr_of_cycles + 1);
1402 }
1403
1404 *new_base_ts = ktime_to_timespec64(new_base_time);
1405}
1406
1407static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot)
1408{
1409 return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL);
1410}
1411
1412static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix,
1413 struct tc_taprio_sched_entry *entry)
1414{
1415 ocelot_write(ocelot,
1416 QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) |
1417 QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask),
1418 QSYS_GCL_CFG_REG_1);
1419 ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2);
1420}
1421
1422static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port,
1423 struct tc_taprio_qopt_offload *taprio)
1424{
1425 struct ocelot_port *ocelot_port = ocelot->ports[port];
1426 struct timespec64 base_ts;
1427 int ret, i;
1428 u32 val;
1429
1430 mutex_lock(&ocelot->fwd_domain_lock);
1431
1432 if (taprio->cmd == TAPRIO_CMD_DESTROY) {
1433 ocelot_port_mqprio(ocelot, port, &taprio->mqprio);
1434 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE,
1435 QSYS_TAG_CONFIG, port);
1436
1437 taprio_offload_free(ocelot_port->taprio);
1438 ocelot_port->taprio = NULL;
1439
1440 vsc9959_tas_guard_bands_update(ocelot, port);
1441
1442 mutex_unlock(&ocelot->fwd_domain_lock);
1443 return 0;
1444 } else if (taprio->cmd != TAPRIO_CMD_REPLACE) {
1445 ret = -EOPNOTSUPP;
1446 goto err_unlock;
1447 }
1448
1449 ret = ocelot_port_mqprio(ocelot, port, &taprio->mqprio);
1450 if (ret)
1451 goto err_unlock;
1452
1453 if (taprio->cycle_time > NSEC_PER_SEC ||
1454 taprio->cycle_time_extension >= NSEC_PER_SEC) {
1455 ret = -EINVAL;
1456 goto err_reset_tc;
1457 }
1458
1459 if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) {
1460 ret = -ERANGE;
1461 goto err_reset_tc;
1462 }
1463
1464 /* Enable guard band. The switch will schedule frames without taking
1465 * their length into account. Thus we'll always need to enable the
1466 * guard band which reserves the time of a maximum sized frame at the
1467 * end of the time window.
1468 *
1469 * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we
1470 * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n
1471 * operate on the port number.
1472 */
1473 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) |
1474 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1475 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M |
1476 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1477 QSYS_TAS_PARAM_CFG_CTRL);
1478
1479 /* Hardware errata - Admin config could not be overwritten if
1480 * config is pending, need reset the TAS module
1481 */
1482 val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port);
1483 if (val & QSYS_TAG_CONFIG_ENABLE) {
1484 val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
1485 if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) {
1486 ret = -EBUSY;
1487 goto err_reset_tc;
1488 }
1489 }
1490
1491 ocelot_rmw_rix(ocelot,
1492 QSYS_TAG_CONFIG_ENABLE |
1493 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) |
1494 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF),
1495 QSYS_TAG_CONFIG_ENABLE |
1496 QSYS_TAG_CONFIG_INIT_GATE_STATE_M |
1497 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M,
1498 QSYS_TAG_CONFIG, port);
1499
1500 vsc9959_new_base_time(ocelot, taprio->base_time,
1501 taprio->cycle_time, &base_ts);
1502 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
1503 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2);
1504 val = upper_32_bits(base_ts.tv_sec);
1505 ocelot_write(ocelot,
1506 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) |
1507 QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries),
1508 QSYS_PARAM_CFG_REG_3);
1509 ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4);
1510 ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5);
1511
1512 for (i = 0; i < taprio->num_entries; i++)
1513 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]);
1514
1515 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1516 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1517 QSYS_TAS_PARAM_CFG_CTRL);
1518
1519 ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val,
1520 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE),
1521 10, 100000);
1522 if (ret)
1523 goto err_reset_tc;
1524
1525 ocelot_port->taprio = taprio_offload_get(taprio);
1526 vsc9959_tas_guard_bands_update(ocelot, port);
1527
1528 mutex_unlock(&ocelot->fwd_domain_lock);
1529
1530 return 0;
1531
1532err_reset_tc:
1533 taprio->mqprio.qopt.num_tc = 0;
1534 ocelot_port_mqprio(ocelot, port, &taprio->mqprio);
1535err_unlock:
1536 mutex_unlock(&ocelot->fwd_domain_lock);
1537
1538 return ret;
1539}
1540
1541static void vsc9959_tas_clock_adjust(struct ocelot *ocelot)
1542{
1543 struct tc_taprio_qopt_offload *taprio;
1544 struct ocelot_port *ocelot_port;
1545 struct timespec64 base_ts;
1546 int port;
1547 u32 val;
1548
1549 mutex_lock(&ocelot->fwd_domain_lock);
1550
1551 for (port = 0; port < ocelot->num_phys_ports; port++) {
1552 ocelot_port = ocelot->ports[port];
1553 taprio = ocelot_port->taprio;
1554 if (!taprio)
1555 continue;
1556
1557 ocelot_rmw(ocelot,
1558 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port),
1559 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M,
1560 QSYS_TAS_PARAM_CFG_CTRL);
1561
1562 /* Disable time-aware shaper */
1563 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE,
1564 QSYS_TAG_CONFIG, port);
1565
1566 vsc9959_new_base_time(ocelot, taprio->base_time,
1567 taprio->cycle_time, &base_ts);
1568
1569 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
1570 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec),
1571 QSYS_PARAM_CFG_REG_2);
1572 val = upper_32_bits(base_ts.tv_sec);
1573 ocelot_rmw(ocelot,
1574 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val),
1575 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M,
1576 QSYS_PARAM_CFG_REG_3);
1577
1578 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1579 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1580 QSYS_TAS_PARAM_CFG_CTRL);
1581
1582 /* Re-enable time-aware shaper */
1583 ocelot_rmw_rix(ocelot, QSYS_TAG_CONFIG_ENABLE,
1584 QSYS_TAG_CONFIG_ENABLE,
1585 QSYS_TAG_CONFIG, port);
1586 }
1587 mutex_unlock(&ocelot->fwd_domain_lock);
1588}
1589
1590static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port,
1591 struct tc_cbs_qopt_offload *cbs_qopt)
1592{
1593 struct ocelot *ocelot = ds->priv;
1594 int port_ix = port * 8 + cbs_qopt->queue;
1595 u32 rate, burst;
1596
1597 if (cbs_qopt->queue >= ds->num_tx_queues)
1598 return -EINVAL;
1599
1600 if (!cbs_qopt->enable) {
1601 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) |
1602 QSYS_CIR_CFG_CIR_BURST(0),
1603 QSYS_CIR_CFG, port_ix);
1604
1605 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA,
1606 QSYS_SE_CFG, port_ix);
1607
1608 return 0;
1609 }
1610
1611 /* Rate unit is 100 kbps */
1612 rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100);
1613 /* Avoid using zero rate */
1614 rate = clamp_t(u32, rate, 1, GENMASK(14, 0));
1615 /* Burst unit is 4kB */
1616 burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096);
1617 /* Avoid using zero burst size */
1618 burst = clamp_t(u32, burst, 1, GENMASK(5, 0));
1619 ocelot_write_gix(ocelot,
1620 QSYS_CIR_CFG_CIR_RATE(rate) |
1621 QSYS_CIR_CFG_CIR_BURST(burst),
1622 QSYS_CIR_CFG,
1623 port_ix);
1624
1625 ocelot_rmw_gix(ocelot,
1626 QSYS_SE_CFG_SE_FRM_MODE(0) |
1627 QSYS_SE_CFG_SE_AVB_ENA,
1628 QSYS_SE_CFG_SE_AVB_ENA |
1629 QSYS_SE_CFG_SE_FRM_MODE_M,
1630 QSYS_SE_CFG,
1631 port_ix);
1632
1633 return 0;
1634}
1635
1636static int vsc9959_qos_query_caps(struct tc_query_caps_base *base)
1637{
1638 switch (base->type) {
1639 case TC_SETUP_QDISC_MQPRIO: {
1640 struct tc_mqprio_caps *caps = base->caps;
1641
1642 caps->validate_queue_counts = true;
1643
1644 return 0;
1645 }
1646 case TC_SETUP_QDISC_TAPRIO: {
1647 struct tc_taprio_caps *caps = base->caps;
1648
1649 caps->supports_queue_max_sdu = true;
1650
1651 return 0;
1652 }
1653 default:
1654 return -EOPNOTSUPP;
1655 }
1656}
1657
1658static int vsc9959_qos_port_mqprio(struct ocelot *ocelot, int port,
1659 struct tc_mqprio_qopt_offload *mqprio)
1660{
1661 int ret;
1662
1663 mutex_lock(&ocelot->fwd_domain_lock);
1664 ret = ocelot_port_mqprio(ocelot, port, mqprio);
1665 mutex_unlock(&ocelot->fwd_domain_lock);
1666
1667 return ret;
1668}
1669
1670static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port,
1671 enum tc_setup_type type,
1672 void *type_data)
1673{
1674 struct ocelot *ocelot = ds->priv;
1675
1676 switch (type) {
1677 case TC_QUERY_CAPS:
1678 return vsc9959_qos_query_caps(type_data);
1679 case TC_SETUP_QDISC_TAPRIO:
1680 return vsc9959_qos_port_tas_set(ocelot, port, type_data);
1681 case TC_SETUP_QDISC_MQPRIO:
1682 return vsc9959_qos_port_mqprio(ocelot, port, type_data);
1683 case TC_SETUP_QDISC_CBS:
1684 return vsc9959_qos_port_cbs_set(ds, port, type_data);
1685 default:
1686 return -EOPNOTSUPP;
1687 }
1688}
1689
1690#define VSC9959_PSFP_SFID_MAX 175
1691#define VSC9959_PSFP_GATE_ID_MAX 183
1692#define VSC9959_PSFP_POLICER_BASE 63
1693#define VSC9959_PSFP_POLICER_MAX 383
1694#define VSC9959_PSFP_GATE_LIST_NUM 4
1695#define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000
1696
1697struct felix_stream {
1698 struct list_head list;
1699 unsigned long id;
1700 bool dummy;
1701 int ports;
1702 int port;
1703 u8 dmac[ETH_ALEN];
1704 u16 vid;
1705 s8 prio;
1706 u8 sfid_valid;
1707 u8 ssid_valid;
1708 u32 sfid;
1709 u32 ssid;
1710};
1711
1712struct felix_stream_filter_counters {
1713 u64 match;
1714 u64 not_pass_gate;
1715 u64 not_pass_sdu;
1716 u64 red;
1717};
1718
1719struct felix_stream_filter {
1720 struct felix_stream_filter_counters stats;
1721 struct list_head list;
1722 refcount_t refcount;
1723 u32 index;
1724 u8 enable;
1725 int portmask;
1726 u8 sg_valid;
1727 u32 sgid;
1728 u8 fm_valid;
1729 u32 fmid;
1730 u8 prio_valid;
1731 u8 prio;
1732 u32 maxsdu;
1733};
1734
1735struct felix_stream_gate {
1736 u32 index;
1737 u8 enable;
1738 u8 ipv_valid;
1739 u8 init_ipv;
1740 u64 basetime;
1741 u64 cycletime;
1742 u64 cycletime_ext;
1743 u32 num_entries;
1744 struct action_gate_entry entries[] __counted_by(num_entries);
1745};
1746
1747struct felix_stream_gate_entry {
1748 struct list_head list;
1749 refcount_t refcount;
1750 u32 index;
1751};
1752
1753static int vsc9959_stream_identify(struct flow_cls_offload *f,
1754 struct felix_stream *stream)
1755{
1756 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1757 struct flow_dissector *dissector = rule->match.dissector;
1758
1759 if (dissector->used_keys &
1760 ~(BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
1761 BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
1762 BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
1763 BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS)))
1764 return -EOPNOTSUPP;
1765
1766 if (flow_rule_match_has_control_flags(rule, f->common.extack))
1767 return -EOPNOTSUPP;
1768
1769 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1770 struct flow_match_eth_addrs match;
1771
1772 flow_rule_match_eth_addrs(rule, &match);
1773 ether_addr_copy(stream->dmac, match.key->dst);
1774 if (!is_zero_ether_addr(match.mask->src))
1775 return -EOPNOTSUPP;
1776 } else {
1777 return -EOPNOTSUPP;
1778 }
1779
1780 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
1781 struct flow_match_vlan match;
1782
1783 flow_rule_match_vlan(rule, &match);
1784 if (match.mask->vlan_priority)
1785 stream->prio = match.key->vlan_priority;
1786 else
1787 stream->prio = -1;
1788
1789 if (!match.mask->vlan_id)
1790 return -EOPNOTSUPP;
1791 stream->vid = match.key->vlan_id;
1792 } else {
1793 return -EOPNOTSUPP;
1794 }
1795
1796 stream->id = f->cookie;
1797
1798 return 0;
1799}
1800
1801static int vsc9959_mact_stream_set(struct ocelot *ocelot,
1802 struct felix_stream *stream,
1803 struct netlink_ext_ack *extack)
1804{
1805 enum macaccess_entry_type type;
1806 int ret, sfid, ssid;
1807 u32 vid, dst_idx;
1808 u8 mac[ETH_ALEN];
1809
1810 ether_addr_copy(mac, stream->dmac);
1811 vid = stream->vid;
1812
1813 /* Stream identification desn't support to add a stream with non
1814 * existent MAC (The MAC entry has not been learned in MAC table).
1815 */
1816 ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type);
1817 if (ret) {
1818 if (extack)
1819 NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table");
1820 return -EOPNOTSUPP;
1821 }
1822
1823 if ((stream->sfid_valid || stream->ssid_valid) &&
1824 type == ENTRYTYPE_NORMAL)
1825 type = ENTRYTYPE_LOCKED;
1826
1827 sfid = stream->sfid_valid ? stream->sfid : -1;
1828 ssid = stream->ssid_valid ? stream->ssid : -1;
1829
1830 ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type,
1831 sfid, ssid);
1832
1833 return ret;
1834}
1835
1836static struct felix_stream *
1837vsc9959_stream_table_lookup(struct list_head *stream_list,
1838 struct felix_stream *stream)
1839{
1840 struct felix_stream *tmp;
1841
1842 list_for_each_entry(tmp, stream_list, list)
1843 if (ether_addr_equal(tmp->dmac, stream->dmac) &&
1844 tmp->vid == stream->vid)
1845 return tmp;
1846
1847 return NULL;
1848}
1849
1850static int vsc9959_stream_table_add(struct ocelot *ocelot,
1851 struct list_head *stream_list,
1852 struct felix_stream *stream,
1853 struct netlink_ext_ack *extack)
1854{
1855 struct felix_stream *stream_entry;
1856 int ret;
1857
1858 stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL);
1859 if (!stream_entry)
1860 return -ENOMEM;
1861
1862 if (!stream->dummy) {
1863 ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack);
1864 if (ret) {
1865 kfree(stream_entry);
1866 return ret;
1867 }
1868 }
1869
1870 list_add_tail(&stream_entry->list, stream_list);
1871
1872 return 0;
1873}
1874
1875static struct felix_stream *
1876vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id)
1877{
1878 struct felix_stream *tmp;
1879
1880 list_for_each_entry(tmp, stream_list, list)
1881 if (tmp->id == id)
1882 return tmp;
1883
1884 return NULL;
1885}
1886
1887static void vsc9959_stream_table_del(struct ocelot *ocelot,
1888 struct felix_stream *stream)
1889{
1890 if (!stream->dummy)
1891 vsc9959_mact_stream_set(ocelot, stream, NULL);
1892
1893 list_del(&stream->list);
1894 kfree(stream);
1895}
1896
1897static u32 vsc9959_sfi_access_status(struct ocelot *ocelot)
1898{
1899 return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS);
1900}
1901
1902static int vsc9959_psfp_sfi_set(struct ocelot *ocelot,
1903 struct felix_stream_filter *sfi)
1904{
1905 u32 val;
1906
1907 if (sfi->index > VSC9959_PSFP_SFID_MAX)
1908 return -EINVAL;
1909
1910 if (!sfi->enable) {
1911 ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index),
1912 ANA_TABLES_SFIDTIDX);
1913
1914 val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE);
1915 ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS);
1916
1917 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1918 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1919 10, 100000);
1920 }
1921
1922 if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX ||
1923 sfi->fmid > VSC9959_PSFP_POLICER_MAX)
1924 return -EINVAL;
1925
1926 ocelot_write(ocelot,
1927 (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) |
1928 ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) |
1929 (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) |
1930 ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) |
1931 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index),
1932 ANA_TABLES_SFIDTIDX);
1933
1934 ocelot_write(ocelot,
1935 (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) |
1936 ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) |
1937 ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) |
1938 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE),
1939 ANA_TABLES_SFIDACCESS);
1940
1941 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1942 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1943 10, 100000);
1944}
1945
1946static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports)
1947{
1948 u32 val;
1949
1950 ocelot_rmw(ocelot,
1951 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid),
1952 ANA_TABLES_SFIDTIDX_SFID_INDEX_M,
1953 ANA_TABLES_SFIDTIDX);
1954
1955 ocelot_write(ocelot,
1956 ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) |
1957 ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA,
1958 ANA_TABLES_SFID_MASK);
1959
1960 ocelot_rmw(ocelot,
1961 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE),
1962 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M,
1963 ANA_TABLES_SFIDACCESS);
1964
1965 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1966 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1967 10, 100000);
1968}
1969
1970static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot,
1971 struct felix_stream_filter *sfi,
1972 struct list_head *pos)
1973{
1974 struct felix_stream_filter *sfi_entry;
1975 int ret;
1976
1977 sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL);
1978 if (!sfi_entry)
1979 return -ENOMEM;
1980
1981 refcount_set(&sfi_entry->refcount, 1);
1982
1983 ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry);
1984 if (ret) {
1985 kfree(sfi_entry);
1986 return ret;
1987 }
1988
1989 vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask);
1990
1991 list_add(&sfi_entry->list, pos);
1992
1993 return 0;
1994}
1995
1996static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot,
1997 struct felix_stream_filter *sfi)
1998{
1999 struct list_head *pos, *q, *last;
2000 struct felix_stream_filter *tmp;
2001 struct ocelot_psfp_list *psfp;
2002 u32 insert = 0;
2003
2004 psfp = &ocelot->psfp;
2005 last = &psfp->sfi_list;
2006
2007 list_for_each_safe(pos, q, &psfp->sfi_list) {
2008 tmp = list_entry(pos, struct felix_stream_filter, list);
2009 if (sfi->sg_valid == tmp->sg_valid &&
2010 sfi->fm_valid == tmp->fm_valid &&
2011 sfi->portmask == tmp->portmask &&
2012 tmp->sgid == sfi->sgid &&
2013 tmp->fmid == sfi->fmid) {
2014 sfi->index = tmp->index;
2015 refcount_inc(&tmp->refcount);
2016 return 0;
2017 }
2018 /* Make sure that the index is increasing in order. */
2019 if (tmp->index == insert) {
2020 last = pos;
2021 insert++;
2022 }
2023 }
2024 sfi->index = insert;
2025
2026 return vsc9959_psfp_sfi_list_add(ocelot, sfi, last);
2027}
2028
2029static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot,
2030 struct felix_stream_filter *sfi,
2031 struct felix_stream_filter *sfi2)
2032{
2033 struct felix_stream_filter *tmp;
2034 struct list_head *pos, *q, *last;
2035 struct ocelot_psfp_list *psfp;
2036 u32 insert = 0;
2037 int ret;
2038
2039 psfp = &ocelot->psfp;
2040 last = &psfp->sfi_list;
2041
2042 list_for_each_safe(pos, q, &psfp->sfi_list) {
2043 tmp = list_entry(pos, struct felix_stream_filter, list);
2044 /* Make sure that the index is increasing in order. */
2045 if (tmp->index >= insert + 2)
2046 break;
2047
2048 insert = tmp->index + 1;
2049 last = pos;
2050 }
2051 sfi->index = insert;
2052
2053 ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last);
2054 if (ret)
2055 return ret;
2056
2057 sfi2->index = insert + 1;
2058
2059 return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next);
2060}
2061
2062static struct felix_stream_filter *
2063vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index)
2064{
2065 struct felix_stream_filter *tmp;
2066
2067 list_for_each_entry(tmp, sfi_list, list)
2068 if (tmp->index == index)
2069 return tmp;
2070
2071 return NULL;
2072}
2073
2074static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index)
2075{
2076 struct felix_stream_filter *tmp, *n;
2077 struct ocelot_psfp_list *psfp;
2078 u8 z;
2079
2080 psfp = &ocelot->psfp;
2081
2082 list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list)
2083 if (tmp->index == index) {
2084 z = refcount_dec_and_test(&tmp->refcount);
2085 if (z) {
2086 tmp->enable = 0;
2087 vsc9959_psfp_sfi_set(ocelot, tmp);
2088 list_del(&tmp->list);
2089 kfree(tmp);
2090 }
2091 break;
2092 }
2093}
2094
2095static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry,
2096 struct felix_stream_gate *sgi)
2097{
2098 sgi->index = entry->hw_index;
2099 sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1;
2100 sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0;
2101 sgi->basetime = entry->gate.basetime;
2102 sgi->cycletime = entry->gate.cycletime;
2103 sgi->num_entries = entry->gate.num_entries;
2104 sgi->enable = 1;
2105
2106 memcpy(sgi->entries, entry->gate.entries,
2107 entry->gate.num_entries * sizeof(struct action_gate_entry));
2108}
2109
2110static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot)
2111{
2112 return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL);
2113}
2114
2115static int vsc9959_psfp_sgi_set(struct ocelot *ocelot,
2116 struct felix_stream_gate *sgi)
2117{
2118 struct action_gate_entry *e;
2119 struct timespec64 base_ts;
2120 u32 interval_sum = 0;
2121 u32 val;
2122 int i;
2123
2124 if (sgi->index > VSC9959_PSFP_GATE_ID_MAX)
2125 return -EINVAL;
2126
2127 ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index),
2128 ANA_SG_ACCESS_CTRL);
2129
2130 if (!sgi->enable) {
2131 ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE,
2132 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE |
2133 ANA_SG_CONFIG_REG_3_GATE_ENABLE,
2134 ANA_SG_CONFIG_REG_3);
2135
2136 return 0;
2137 }
2138
2139 if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN ||
2140 sgi->cycletime > NSEC_PER_SEC)
2141 return -EINVAL;
2142
2143 if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM)
2144 return -EINVAL;
2145
2146 vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts);
2147 ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1);
2148 val = lower_32_bits(base_ts.tv_sec);
2149 ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2);
2150
2151 val = upper_32_bits(base_ts.tv_sec);
2152 ocelot_write(ocelot,
2153 (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) |
2154 ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) |
2155 ANA_SG_CONFIG_REG_3_GATE_ENABLE |
2156 ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) |
2157 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE |
2158 ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val),
2159 ANA_SG_CONFIG_REG_3);
2160
2161 ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4);
2162
2163 e = sgi->entries;
2164 for (i = 0; i < sgi->num_entries; i++) {
2165 u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8);
2166
2167 ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) |
2168 (e[i].gate_state ?
2169 ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0),
2170 ANA_SG_GCL_GS_CONFIG, i);
2171
2172 interval_sum += e[i].interval;
2173 ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i);
2174 }
2175
2176 ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE,
2177 ANA_SG_ACCESS_CTRL_CONFIG_CHANGE,
2178 ANA_SG_ACCESS_CTRL);
2179
2180 return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val,
2181 (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)),
2182 10, 100000);
2183}
2184
2185static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot,
2186 struct felix_stream_gate *sgi)
2187{
2188 struct felix_stream_gate_entry *tmp;
2189 struct ocelot_psfp_list *psfp;
2190 int ret;
2191
2192 psfp = &ocelot->psfp;
2193
2194 list_for_each_entry(tmp, &psfp->sgi_list, list)
2195 if (tmp->index == sgi->index) {
2196 refcount_inc(&tmp->refcount);
2197 return 0;
2198 }
2199
2200 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
2201 if (!tmp)
2202 return -ENOMEM;
2203
2204 ret = vsc9959_psfp_sgi_set(ocelot, sgi);
2205 if (ret) {
2206 kfree(tmp);
2207 return ret;
2208 }
2209
2210 tmp->index = sgi->index;
2211 refcount_set(&tmp->refcount, 1);
2212 list_add_tail(&tmp->list, &psfp->sgi_list);
2213
2214 return 0;
2215}
2216
2217static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot,
2218 u32 index)
2219{
2220 struct felix_stream_gate_entry *tmp, *n;
2221 struct felix_stream_gate sgi = {0};
2222 struct ocelot_psfp_list *psfp;
2223 u8 z;
2224
2225 psfp = &ocelot->psfp;
2226
2227 list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list)
2228 if (tmp->index == index) {
2229 z = refcount_dec_and_test(&tmp->refcount);
2230 if (z) {
2231 sgi.index = index;
2232 sgi.enable = 0;
2233 vsc9959_psfp_sgi_set(ocelot, &sgi);
2234 list_del(&tmp->list);
2235 kfree(tmp);
2236 }
2237 break;
2238 }
2239}
2240
2241static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port,
2242 struct flow_cls_offload *f)
2243{
2244 struct netlink_ext_ack *extack = f->common.extack;
2245 struct felix_stream_filter old_sfi, *sfi_entry;
2246 struct felix_stream_filter sfi = {0};
2247 const struct flow_action_entry *a;
2248 struct felix_stream *stream_entry;
2249 struct felix_stream stream = {0};
2250 struct felix_stream_gate *sgi;
2251 struct ocelot_psfp_list *psfp;
2252 struct ocelot_policer pol;
2253 int ret, i, size;
2254 u64 rate, burst;
2255 u32 index;
2256
2257 psfp = &ocelot->psfp;
2258
2259 ret = vsc9959_stream_identify(f, &stream);
2260 if (ret) {
2261 NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC");
2262 return ret;
2263 }
2264
2265 mutex_lock(&psfp->lock);
2266
2267 flow_action_for_each(i, a, &f->rule->action) {
2268 switch (a->id) {
2269 case FLOW_ACTION_GATE:
2270 size = struct_size(sgi, entries, a->gate.num_entries);
2271 sgi = kzalloc(size, GFP_KERNEL);
2272 if (!sgi) {
2273 ret = -ENOMEM;
2274 goto err;
2275 }
2276 vsc9959_psfp_parse_gate(a, sgi);
2277 ret = vsc9959_psfp_sgi_table_add(ocelot, sgi);
2278 if (ret) {
2279 kfree(sgi);
2280 goto err;
2281 }
2282 sfi.sg_valid = 1;
2283 sfi.sgid = sgi->index;
2284 kfree(sgi);
2285 break;
2286 case FLOW_ACTION_POLICE:
2287 index = a->hw_index + VSC9959_PSFP_POLICER_BASE;
2288 if (index > VSC9959_PSFP_POLICER_MAX) {
2289 ret = -EINVAL;
2290 goto err;
2291 }
2292
2293 rate = a->police.rate_bytes_ps;
2294 burst = rate * PSCHED_NS2TICKS(a->police.burst);
2295 pol = (struct ocelot_policer) {
2296 .burst = div_u64(burst, PSCHED_TICKS_PER_SEC),
2297 .rate = div_u64(rate, 1000) * 8,
2298 };
2299 ret = ocelot_vcap_policer_add(ocelot, index, &pol);
2300 if (ret)
2301 goto err;
2302
2303 sfi.fm_valid = 1;
2304 sfi.fmid = index;
2305 sfi.maxsdu = a->police.mtu;
2306 break;
2307 default:
2308 mutex_unlock(&psfp->lock);
2309 return -EOPNOTSUPP;
2310 }
2311 }
2312
2313 stream.ports = BIT(port);
2314 stream.port = port;
2315
2316 sfi.portmask = stream.ports;
2317 sfi.prio_valid = (stream.prio < 0 ? 0 : 1);
2318 sfi.prio = (sfi.prio_valid ? stream.prio : 0);
2319 sfi.enable = 1;
2320
2321 /* Check if stream is set. */
2322 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream);
2323 if (stream_entry) {
2324 if (stream_entry->ports & BIT(port)) {
2325 NL_SET_ERR_MSG_MOD(extack,
2326 "The stream is added on this port");
2327 ret = -EEXIST;
2328 goto err;
2329 }
2330
2331 if (stream_entry->ports != BIT(stream_entry->port)) {
2332 NL_SET_ERR_MSG_MOD(extack,
2333 "The stream is added on two ports");
2334 ret = -EEXIST;
2335 goto err;
2336 }
2337
2338 stream_entry->ports |= BIT(port);
2339 stream.ports = stream_entry->ports;
2340
2341 sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list,
2342 stream_entry->sfid);
2343 memcpy(&old_sfi, sfi_entry, sizeof(old_sfi));
2344
2345 vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid);
2346
2347 old_sfi.portmask = stream_entry->ports;
2348 sfi.portmask = stream.ports;
2349
2350 if (stream_entry->port > port) {
2351 ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi,
2352 &old_sfi);
2353 stream_entry->dummy = true;
2354 } else {
2355 ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi,
2356 &sfi);
2357 stream.dummy = true;
2358 }
2359 if (ret)
2360 goto err;
2361
2362 stream_entry->sfid = old_sfi.index;
2363 } else {
2364 ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi);
2365 if (ret)
2366 goto err;
2367 }
2368
2369 stream.sfid = sfi.index;
2370 stream.sfid_valid = 1;
2371 ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list,
2372 &stream, extack);
2373 if (ret) {
2374 vsc9959_psfp_sfi_table_del(ocelot, stream.sfid);
2375 goto err;
2376 }
2377
2378 mutex_unlock(&psfp->lock);
2379
2380 return 0;
2381
2382err:
2383 if (sfi.sg_valid)
2384 vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid);
2385
2386 if (sfi.fm_valid)
2387 ocelot_vcap_policer_del(ocelot, sfi.fmid);
2388
2389 mutex_unlock(&psfp->lock);
2390
2391 return ret;
2392}
2393
2394static int vsc9959_psfp_filter_del(struct ocelot *ocelot,
2395 struct flow_cls_offload *f)
2396{
2397 struct felix_stream *stream, tmp, *stream_entry;
2398 struct ocelot_psfp_list *psfp = &ocelot->psfp;
2399 static struct felix_stream_filter *sfi;
2400
2401 mutex_lock(&psfp->lock);
2402
2403 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie);
2404 if (!stream) {
2405 mutex_unlock(&psfp->lock);
2406 return -ENOMEM;
2407 }
2408
2409 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid);
2410 if (!sfi) {
2411 mutex_unlock(&psfp->lock);
2412 return -ENOMEM;
2413 }
2414
2415 if (sfi->sg_valid)
2416 vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid);
2417
2418 if (sfi->fm_valid)
2419 ocelot_vcap_policer_del(ocelot, sfi->fmid);
2420
2421 vsc9959_psfp_sfi_table_del(ocelot, stream->sfid);
2422
2423 memcpy(&tmp, stream, sizeof(tmp));
2424
2425 stream->sfid_valid = 0;
2426 vsc9959_stream_table_del(ocelot, stream);
2427
2428 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp);
2429 if (stream_entry) {
2430 stream_entry->ports = BIT(stream_entry->port);
2431 if (stream_entry->dummy) {
2432 stream_entry->dummy = false;
2433 vsc9959_mact_stream_set(ocelot, stream_entry, NULL);
2434 }
2435 vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid,
2436 stream_entry->ports);
2437 }
2438
2439 mutex_unlock(&psfp->lock);
2440
2441 return 0;
2442}
2443
2444static void vsc9959_update_sfid_stats(struct ocelot *ocelot,
2445 struct felix_stream_filter *sfi)
2446{
2447 struct felix_stream_filter_counters *s = &sfi->stats;
2448 u32 match, not_pass_gate, not_pass_sdu, red;
2449 u32 sfid = sfi->index;
2450
2451 lockdep_assert_held(&ocelot->stat_view_lock);
2452
2453 ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(sfid),
2454 SYS_STAT_CFG_STAT_VIEW_M,
2455 SYS_STAT_CFG);
2456
2457 match = ocelot_read(ocelot, SYS_COUNT_SF_MATCHING_FRAMES);
2458 not_pass_gate = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_FRAMES);
2459 not_pass_sdu = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_SDU);
2460 red = ocelot_read(ocelot, SYS_COUNT_SF_RED_FRAMES);
2461
2462 /* Clear the PSFP counter. */
2463 ocelot_write(ocelot,
2464 SYS_STAT_CFG_STAT_VIEW(sfid) |
2465 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10),
2466 SYS_STAT_CFG);
2467
2468 s->match += match;
2469 s->not_pass_gate += not_pass_gate;
2470 s->not_pass_sdu += not_pass_sdu;
2471 s->red += red;
2472}
2473
2474/* Caller must hold &ocelot->stat_view_lock */
2475static void vsc9959_update_stats(struct ocelot *ocelot)
2476{
2477 struct ocelot_psfp_list *psfp = &ocelot->psfp;
2478 struct felix_stream_filter *sfi;
2479
2480 mutex_lock(&psfp->lock);
2481
2482 list_for_each_entry(sfi, &psfp->sfi_list, list)
2483 vsc9959_update_sfid_stats(ocelot, sfi);
2484
2485 mutex_unlock(&psfp->lock);
2486}
2487
2488static int vsc9959_psfp_stats_get(struct ocelot *ocelot,
2489 struct flow_cls_offload *f,
2490 struct flow_stats *stats)
2491{
2492 struct ocelot_psfp_list *psfp = &ocelot->psfp;
2493 struct felix_stream_filter_counters *s;
2494 static struct felix_stream_filter *sfi;
2495 struct felix_stream *stream;
2496
2497 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie);
2498 if (!stream)
2499 return -ENOMEM;
2500
2501 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid);
2502 if (!sfi)
2503 return -EINVAL;
2504
2505 mutex_lock(&ocelot->stat_view_lock);
2506
2507 vsc9959_update_sfid_stats(ocelot, sfi);
2508
2509 s = &sfi->stats;
2510 stats->pkts = s->match;
2511 stats->drops = s->not_pass_gate + s->not_pass_sdu + s->red;
2512
2513 memset(s, 0, sizeof(*s));
2514
2515 mutex_unlock(&ocelot->stat_view_lock);
2516
2517 return 0;
2518}
2519
2520static void vsc9959_psfp_init(struct ocelot *ocelot)
2521{
2522 struct ocelot_psfp_list *psfp = &ocelot->psfp;
2523
2524 INIT_LIST_HEAD(&psfp->stream_list);
2525 INIT_LIST_HEAD(&psfp->sfi_list);
2526 INIT_LIST_HEAD(&psfp->sgi_list);
2527 mutex_init(&psfp->lock);
2528}
2529
2530/* When using cut-through forwarding and the egress port runs at a higher data
2531 * rate than the ingress port, the packet currently under transmission would
2532 * suffer an underrun since it would be transmitted faster than it is received.
2533 * The Felix switch implementation of cut-through forwarding does not check in
2534 * hardware whether this condition is satisfied or not, so we must restrict the
2535 * list of ports that have cut-through forwarding enabled on egress to only be
2536 * the ports operating at the lowest link speed within their respective
2537 * forwarding domain.
2538 */
2539static void vsc9959_cut_through_fwd(struct ocelot *ocelot)
2540{
2541 struct felix *felix = ocelot_to_felix(ocelot);
2542 struct dsa_switch *ds = felix->ds;
2543 int tc, port, other_port;
2544
2545 lockdep_assert_held(&ocelot->fwd_domain_lock);
2546
2547 for (port = 0; port < ocelot->num_phys_ports; port++) {
2548 struct ocelot_port *ocelot_port = ocelot->ports[port];
2549 struct ocelot_mm_state *mm = &ocelot->mm[port];
2550 int min_speed = ocelot_port->speed;
2551 unsigned long mask = 0;
2552 u32 tmp, val = 0;
2553
2554 /* Disable cut-through on ports that are down */
2555 if (ocelot_port->speed <= 0)
2556 goto set;
2557
2558 if (dsa_is_cpu_port(ds, port)) {
2559 /* Ocelot switches forward from the NPI port towards
2560 * any port, regardless of it being in the NPI port's
2561 * forwarding domain or not.
2562 */
2563 mask = dsa_user_ports(ds);
2564 } else {
2565 mask = ocelot_get_bridge_fwd_mask(ocelot, port);
2566 mask &= ~BIT(port);
2567 if (ocelot->npi >= 0)
2568 mask |= BIT(ocelot->npi);
2569 else
2570 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot,
2571 port);
2572 }
2573
2574 /* Calculate the minimum link speed, among the ports that are
2575 * up, of this source port's forwarding domain.
2576 */
2577 for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) {
2578 struct ocelot_port *other_ocelot_port;
2579
2580 other_ocelot_port = ocelot->ports[other_port];
2581 if (other_ocelot_port->speed <= 0)
2582 continue;
2583
2584 if (min_speed > other_ocelot_port->speed)
2585 min_speed = other_ocelot_port->speed;
2586 }
2587
2588 /* Enable cut-through forwarding for all traffic classes that
2589 * don't have oversized dropping enabled, since this check is
2590 * bypassed in cut-through mode. Also exclude preemptible
2591 * traffic classes, since these would hang the port for some
2592 * reason, if sent as cut-through.
2593 */
2594 if (ocelot_port->speed == min_speed) {
2595 val = GENMASK(7, 0) & ~mm->active_preemptible_tcs;
2596
2597 for (tc = 0; tc < OCELOT_NUM_TC; tc++)
2598 if (vsc9959_port_qmaxsdu_get(ocelot, port, tc))
2599 val &= ~BIT(tc);
2600 }
2601
2602set:
2603 tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port);
2604 if (tmp == val)
2605 continue;
2606
2607 dev_dbg(ocelot->dev,
2608 "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding on TC mask 0x%x\n",
2609 port, mask, ocelot_port->speed, min_speed,
2610 val ? "enabling" : "disabling", val);
2611
2612 ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port);
2613 }
2614}
2615
2616/* The INTB interrupt is shared between for PTP TX timestamp availability
2617 * notification and MAC Merge status change on each port.
2618 */
2619static irqreturn_t vsc9959_irq_handler(int irq, void *data)
2620{
2621 struct ocelot *ocelot = data;
2622
2623 ocelot_get_txtstamp(ocelot);
2624 ocelot_mm_irq(ocelot);
2625
2626 return IRQ_HANDLED;
2627}
2628
2629static int vsc9959_request_irq(struct ocelot *ocelot)
2630{
2631 struct pci_dev *pdev = to_pci_dev(ocelot->dev);
2632
2633 return devm_request_threaded_irq(ocelot->dev, pdev->irq, NULL,
2634 &vsc9959_irq_handler, IRQF_ONESHOT,
2635 "felix-intb", ocelot);
2636}
2637
2638static const struct ocelot_ops vsc9959_ops = {
2639 .reset = vsc9959_reset,
2640 .wm_enc = vsc9959_wm_enc,
2641 .wm_dec = vsc9959_wm_dec,
2642 .wm_stat = vsc9959_wm_stat,
2643 .port_to_netdev = felix_port_to_netdev,
2644 .netdev_to_port = felix_netdev_to_port,
2645 .psfp_init = vsc9959_psfp_init,
2646 .psfp_filter_add = vsc9959_psfp_filter_add,
2647 .psfp_filter_del = vsc9959_psfp_filter_del,
2648 .psfp_stats_get = vsc9959_psfp_stats_get,
2649 .cut_through_fwd = vsc9959_cut_through_fwd,
2650 .tas_clock_adjust = vsc9959_tas_clock_adjust,
2651 .update_stats = vsc9959_update_stats,
2652 .tas_guard_bands_update = vsc9959_tas_guard_bands_update,
2653};
2654
2655static const struct felix_info felix_info_vsc9959 = {
2656 .resources = vsc9959_resources,
2657 .num_resources = ARRAY_SIZE(vsc9959_resources),
2658 .resource_names = vsc9959_resource_names,
2659 .regfields = vsc9959_regfields,
2660 .map = vsc9959_regmap,
2661 .ops = &vsc9959_ops,
2662 .vcap = vsc9959_vcap_props,
2663 .vcap_pol_base = VSC9959_VCAP_POLICER_BASE,
2664 .vcap_pol_max = VSC9959_VCAP_POLICER_MAX,
2665 .vcap_pol_base2 = 0,
2666 .vcap_pol_max2 = 0,
2667 .num_mact_rows = 2048,
2668 .num_ports = VSC9959_NUM_PORTS,
2669 .quirks = FELIX_MAC_QUIRKS,
2670 .quirk_no_xtr_irq = true,
2671 .ptp_caps = &vsc9959_ptp_caps,
2672 .mdio_bus_alloc = vsc9959_mdio_bus_alloc,
2673 .mdio_bus_free = vsc9959_mdio_bus_free,
2674 .port_modes = vsc9959_port_modes,
2675 .port_setup_tc = vsc9959_port_setup_tc,
2676 .port_sched_speed_set = vsc9959_sched_speed_set,
2677 .request_irq = vsc9959_request_irq,
2678};
2679
2680static int felix_pci_probe(struct pci_dev *pdev,
2681 const struct pci_device_id *id)
2682{
2683 struct device *dev = &pdev->dev;
2684 resource_size_t switch_base;
2685 int err;
2686
2687 err = pci_enable_device(pdev);
2688 if (err) {
2689 dev_err(dev, "device enable failed: %pe\n", ERR_PTR(err));
2690 return err;
2691 }
2692
2693 pci_set_master(pdev);
2694
2695 switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR);
2696
2697 err = felix_register_switch(dev, switch_base, OCELOT_NUM_TC,
2698 true, true, DSA_TAG_PROTO_OCELOT,
2699 &felix_info_vsc9959);
2700 if (err)
2701 goto out_disable;
2702
2703 return 0;
2704
2705out_disable:
2706 pci_disable_device(pdev);
2707 return err;
2708}
2709
2710static void felix_pci_remove(struct pci_dev *pdev)
2711{
2712 struct felix *felix = pci_get_drvdata(pdev);
2713
2714 if (!felix)
2715 return;
2716
2717 dsa_unregister_switch(felix->ds);
2718
2719 pci_disable_device(pdev);
2720}
2721
2722static void felix_pci_shutdown(struct pci_dev *pdev)
2723{
2724 struct felix *felix = pci_get_drvdata(pdev);
2725
2726 if (!felix)
2727 return;
2728
2729 dsa_switch_shutdown(felix->ds);
2730
2731 pci_set_drvdata(pdev, NULL);
2732}
2733
2734static struct pci_device_id felix_ids[] = {
2735 {
2736 /* NXP LS1028A */
2737 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0),
2738 },
2739 { 0, }
2740};
2741MODULE_DEVICE_TABLE(pci, felix_ids);
2742
2743static struct pci_driver felix_vsc9959_pci_driver = {
2744 .name = "mscc_felix",
2745 .id_table = felix_ids,
2746 .probe = felix_pci_probe,
2747 .remove = felix_pci_remove,
2748 .shutdown = felix_pci_shutdown,
2749};
2750module_pci_driver(felix_vsc9959_pci_driver);
2751
2752MODULE_DESCRIPTION("Felix Switch driver");
2753MODULE_LICENSE("GPL v2");