Loading...
1/*
2 *
3 * OMAP SRAM detection and management
4 *
5 * Copyright (C) 2005 Nokia Corporation
6 * Written by Tony Lindgren <tony@atomide.com>
7 *
8 * Copyright (C) 2009-2012 Texas Instruments
9 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/io.h>
20
21#include <asm/fncpy.h>
22#include <asm/tlb.h>
23#include <asm/cacheflush.h>
24
25#include <asm/mach/map.h>
26
27#include "soc.h"
28#include "iomap.h"
29#include "prm2xxx_3xxx.h"
30#include "sdrc.h"
31#include "sram.h"
32
33#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
34#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
35#ifdef CONFIG_OMAP4_ERRATA_I688
36#define OMAP4_SRAM_PUB_PA OMAP4_SRAM_PA
37#else
38#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
39#endif
40#define OMAP5_SRAM_PA 0x40300000
41
42#define SRAM_BOOTLOADER_SZ 0x00
43
44#define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
45#define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
46#define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
47
48#define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
49#define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
50#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
51#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
52#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
53
54#define GP_DEVICE 0x300
55
56#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
57
58static unsigned long omap_sram_start;
59static unsigned long omap_sram_skip;
60static unsigned long omap_sram_size;
61
62/*
63 * Depending on the target RAMFS firewall setup, the public usable amount of
64 * SRAM varies. The default accessible size for all device types is 2k. A GP
65 * device allows ARM11 but not other initiators for full size. This
66 * functionality seems ok until some nice security API happens.
67 */
68static int is_sram_locked(void)
69{
70 if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
71 /* RAMFW: R/W access to all initiators for all qualifier sets */
72 if (cpu_is_omap242x()) {
73 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
74 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
75 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
76 }
77 if (cpu_is_omap34xx()) {
78 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
79 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
80 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
81 __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
82 __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
83 }
84 return 0;
85 } else
86 return 1; /* assume locked with no PPA or security driver */
87}
88
89/*
90 * The amount of SRAM depends on the core type.
91 * Note that we cannot try to test for SRAM here because writes
92 * to secure SRAM will hang the system. Also the SRAM is not
93 * yet mapped at this point.
94 */
95static void __init omap_detect_sram(void)
96{
97 omap_sram_skip = SRAM_BOOTLOADER_SZ;
98 if (is_sram_locked()) {
99 if (cpu_is_omap34xx()) {
100 omap_sram_start = OMAP3_SRAM_PUB_PA;
101 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
102 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
103 omap_sram_size = 0x7000; /* 28K */
104 omap_sram_skip += SZ_16K;
105 } else {
106 omap_sram_size = 0x8000; /* 32K */
107 }
108 } else if (cpu_is_omap44xx()) {
109 omap_sram_start = OMAP4_SRAM_PUB_PA;
110 omap_sram_size = 0xa000; /* 40K */
111 } else if (soc_is_omap54xx()) {
112 omap_sram_start = OMAP5_SRAM_PA;
113 omap_sram_size = SZ_128K; /* 128KB */
114 } else {
115 omap_sram_start = OMAP2_SRAM_PUB_PA;
116 omap_sram_size = 0x800; /* 2K */
117 }
118 } else {
119 if (soc_is_am33xx()) {
120 omap_sram_start = AM33XX_SRAM_PA;
121 omap_sram_size = 0x10000; /* 64K */
122 } else if (soc_is_am43xx()) {
123 omap_sram_start = AM33XX_SRAM_PA;
124 omap_sram_size = SZ_256K;
125 } else if (cpu_is_omap34xx()) {
126 omap_sram_start = OMAP3_SRAM_PA;
127 omap_sram_size = 0x10000; /* 64K */
128 } else if (cpu_is_omap44xx()) {
129 omap_sram_start = OMAP4_SRAM_PA;
130 omap_sram_size = 0xe000; /* 56K */
131 } else if (soc_is_omap54xx()) {
132 omap_sram_start = OMAP5_SRAM_PA;
133 omap_sram_size = SZ_128K; /* 128KB */
134 } else {
135 omap_sram_start = OMAP2_SRAM_PA;
136 if (cpu_is_omap242x())
137 omap_sram_size = 0xa0000; /* 640K */
138 else if (cpu_is_omap243x())
139 omap_sram_size = 0x10000; /* 64K */
140 }
141 }
142}
143
144/*
145 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
146 */
147static void __init omap2_map_sram(void)
148{
149 int cached = 1;
150
151#ifdef CONFIG_OMAP4_ERRATA_I688
152 if (cpu_is_omap44xx()) {
153 omap_sram_start += PAGE_SIZE;
154 omap_sram_size -= SZ_16K;
155 }
156#endif
157 if (cpu_is_omap34xx()) {
158 /*
159 * SRAM must be marked as non-cached on OMAP3 since the
160 * CORE DPLL M2 divider change code (in SRAM) runs with the
161 * SDRAM controller disabled, and if it is marked cached,
162 * the ARM may attempt to write cache lines back to SDRAM
163 * which will cause the system to hang.
164 */
165 cached = 0;
166 }
167
168 omap_map_sram(omap_sram_start, omap_sram_size,
169 omap_sram_skip, cached);
170}
171
172static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
173 u32 base_cs, u32 force_unlock);
174
175void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
176 u32 base_cs, u32 force_unlock)
177{
178 BUG_ON(!_omap2_sram_ddr_init);
179 _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
180 base_cs, force_unlock);
181}
182
183static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
184 u32 mem_type);
185
186void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
187{
188 BUG_ON(!_omap2_sram_reprogram_sdrc);
189 _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
190}
191
192static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
193
194u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
195{
196 BUG_ON(!_omap2_set_prcm);
197 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
198}
199
200#ifdef CONFIG_SOC_OMAP2420
201static int __init omap242x_sram_init(void)
202{
203 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
204 omap242x_sram_ddr_init_sz);
205
206 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
207 omap242x_sram_reprogram_sdrc_sz);
208
209 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
210 omap242x_sram_set_prcm_sz);
211
212 return 0;
213}
214#else
215static inline int omap242x_sram_init(void)
216{
217 return 0;
218}
219#endif
220
221#ifdef CONFIG_SOC_OMAP2430
222static int __init omap243x_sram_init(void)
223{
224 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
225 omap243x_sram_ddr_init_sz);
226
227 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
228 omap243x_sram_reprogram_sdrc_sz);
229
230 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
231 omap243x_sram_set_prcm_sz);
232
233 return 0;
234}
235#else
236static inline int omap243x_sram_init(void)
237{
238 return 0;
239}
240#endif
241
242#ifdef CONFIG_ARCH_OMAP3
243
244static u32 (*_omap3_sram_configure_core_dpll)(
245 u32 m2, u32 unlock_dll, u32 f, u32 inc,
246 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
247 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
248 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
249 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
250
251u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
252 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
253 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
254 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
255 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
256{
257 BUG_ON(!_omap3_sram_configure_core_dpll);
258 return _omap3_sram_configure_core_dpll(
259 m2, unlock_dll, f, inc,
260 sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
261 sdrc_actim_ctrl_b_0, sdrc_mr_0,
262 sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
263 sdrc_actim_ctrl_b_1, sdrc_mr_1);
264}
265
266void omap3_sram_restore_context(void)
267{
268 omap_sram_reset();
269
270 _omap3_sram_configure_core_dpll =
271 omap_sram_push(omap3_sram_configure_core_dpll,
272 omap3_sram_configure_core_dpll_sz);
273 omap_push_sram_idle();
274}
275
276static inline int omap34xx_sram_init(void)
277{
278 omap3_sram_restore_context();
279 return 0;
280}
281#else
282static inline int omap34xx_sram_init(void)
283{
284 return 0;
285}
286#endif /* CONFIG_ARCH_OMAP3 */
287
288static inline int am33xx_sram_init(void)
289{
290 return 0;
291}
292
293int __init omap_sram_init(void)
294{
295 omap_detect_sram();
296 omap2_map_sram();
297
298 if (cpu_is_omap242x())
299 omap242x_sram_init();
300 else if (cpu_is_omap2430())
301 omap243x_sram_init();
302 else if (soc_is_am33xx())
303 am33xx_sram_init();
304 else if (cpu_is_omap34xx())
305 omap34xx_sram_init();
306
307 return 0;
308}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * OMAP SRAM detection and management
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
8 *
9 * Copyright (C) 2009-2012 Texas Instruments
10 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/set_memory.h>
18
19#include <asm/fncpy.h>
20#include <asm/tlb.h>
21#include <asm/cacheflush.h>
22
23#include <asm/mach/map.h>
24
25#include "soc.h"
26#include "iomap.h"
27#include "prm2xxx_3xxx.h"
28#include "sdrc.h"
29#include "sram.h"
30
31#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
32#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
33
34#define SRAM_BOOTLOADER_SZ 0x00
35
36#define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
37#define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
38#define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
39
40#define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
41#define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
42#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
43#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
44#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
45
46#define GP_DEVICE 0x300
47
48#define ROUND_DOWN(value, boundary) ((value) & (~((boundary) - 1)))
49
50static unsigned long omap_sram_start;
51static unsigned long omap_sram_size;
52static void __iomem *omap_sram_base;
53static unsigned long omap_sram_skip;
54static void __iomem *omap_sram_ceil;
55
56/*
57 * Memory allocator for SRAM: calculates the new ceiling address
58 * for pushing a function using the fncpy API.
59 *
60 * Note that fncpy requires the returned address to be aligned
61 * to an 8-byte boundary.
62 */
63static void *omap_sram_push_address(unsigned long size)
64{
65 unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
66
67 available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);
68
69 if (size > available) {
70 pr_err("Not enough space in SRAM\n");
71 return NULL;
72 }
73
74 new_ceil -= size;
75 new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
76 omap_sram_ceil = IOMEM(new_ceil);
77
78 return (void __force *)omap_sram_ceil;
79}
80
81void *omap_sram_push(void *funcp, unsigned long size)
82{
83 void *sram;
84 unsigned long base;
85 int pages;
86 void *dst = NULL;
87
88 sram = omap_sram_push_address(size);
89 if (!sram)
90 return NULL;
91
92 base = (unsigned long)sram & PAGE_MASK;
93 pages = PAGE_ALIGN(size) / PAGE_SIZE;
94
95 set_memory_rw(base, pages);
96
97 dst = fncpy(sram, funcp, size);
98
99 set_memory_rox(base, pages);
100
101 return dst;
102}
103
104/*
105 * The SRAM context is lost during off-idle and stack
106 * needs to be reset.
107 */
108static void omap_sram_reset(void)
109{
110 omap_sram_ceil = omap_sram_base + omap_sram_size;
111}
112
113/*
114 * Depending on the target RAMFS firewall setup, the public usable amount of
115 * SRAM varies. The default accessible size for all device types is 2k. A GP
116 * device allows ARM11 but not other initiators for full size. This
117 * functionality seems ok until some nice security API happens.
118 */
119static int is_sram_locked(void)
120{
121 if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
122 /* RAMFW: R/W access to all initiators for all qualifier sets */
123 if (cpu_is_omap242x()) {
124 writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
125 writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
126 writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
127 }
128 if (cpu_is_omap34xx()) {
129 writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
130 writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
131 writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
132 writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
133 writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
134 }
135 return 0;
136 } else
137 return 1; /* assume locked with no PPA or security driver */
138}
139
140/*
141 * The amount of SRAM depends on the core type.
142 * Note that we cannot try to test for SRAM here because writes
143 * to secure SRAM will hang the system. Also the SRAM is not
144 * yet mapped at this point.
145 */
146static void __init omap_detect_sram(void)
147{
148 omap_sram_skip = SRAM_BOOTLOADER_SZ;
149 if (is_sram_locked()) {
150 if (cpu_is_omap34xx()) {
151 omap_sram_start = OMAP3_SRAM_PUB_PA;
152 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
153 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
154 omap_sram_size = 0x7000; /* 28K */
155 omap_sram_skip += SZ_16K;
156 } else {
157 omap_sram_size = 0x8000; /* 32K */
158 }
159 } else {
160 omap_sram_start = OMAP2_SRAM_PUB_PA;
161 omap_sram_size = 0x800; /* 2K */
162 }
163 } else {
164 if (cpu_is_omap34xx()) {
165 omap_sram_start = OMAP3_SRAM_PA;
166 omap_sram_size = 0x10000; /* 64K */
167 } else {
168 omap_sram_start = OMAP2_SRAM_PA;
169 if (cpu_is_omap242x())
170 omap_sram_size = 0xa0000; /* 640K */
171 else if (cpu_is_omap243x())
172 omap_sram_size = 0x10000; /* 64K */
173 }
174 }
175}
176
177/*
178 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
179 */
180static void __init omap2_map_sram(void)
181{
182 unsigned long base;
183 int pages;
184 int cached = 1;
185
186 if (cpu_is_omap34xx()) {
187 /*
188 * SRAM must be marked as non-cached on OMAP3 since the
189 * CORE DPLL M2 divider change code (in SRAM) runs with the
190 * SDRAM controller disabled, and if it is marked cached,
191 * the ARM may attempt to write cache lines back to SDRAM
192 * which will cause the system to hang.
193 */
194 cached = 0;
195 }
196
197 if (omap_sram_size == 0)
198 return;
199
200 omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
201 omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size, cached);
202 if (!omap_sram_base) {
203 pr_err("SRAM: Could not map\n");
204 return;
205 }
206
207 omap_sram_reset();
208
209 /*
210 * Looks like we need to preserve some bootloader code at the
211 * beginning of SRAM for jumping to flash for reboot to work...
212 */
213 memset_io(omap_sram_base + omap_sram_skip, 0,
214 omap_sram_size - omap_sram_skip);
215
216 base = (unsigned long)omap_sram_base;
217 pages = PAGE_ALIGN(omap_sram_size) / PAGE_SIZE;
218
219 set_memory_rox(base, pages);
220}
221
222static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
223 u32 base_cs, u32 force_unlock);
224
225void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
226 u32 base_cs, u32 force_unlock)
227{
228 BUG_ON(!_omap2_sram_ddr_init);
229 _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
230 base_cs, force_unlock);
231}
232
233static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
234 u32 mem_type);
235
236void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
237{
238 BUG_ON(!_omap2_sram_reprogram_sdrc);
239 _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
240}
241
242static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
243
244u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
245{
246 BUG_ON(!_omap2_set_prcm);
247 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
248}
249
250#ifdef CONFIG_SOC_OMAP2420
251static int __init omap242x_sram_init(void)
252{
253 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
254 omap242x_sram_ddr_init_sz);
255
256 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
257 omap242x_sram_reprogram_sdrc_sz);
258
259 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
260 omap242x_sram_set_prcm_sz);
261
262 return 0;
263}
264#else
265static inline int omap242x_sram_init(void)
266{
267 return 0;
268}
269#endif
270
271#ifdef CONFIG_SOC_OMAP2430
272static int __init omap243x_sram_init(void)
273{
274 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
275 omap243x_sram_ddr_init_sz);
276
277 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
278 omap243x_sram_reprogram_sdrc_sz);
279
280 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
281 omap243x_sram_set_prcm_sz);
282
283 return 0;
284}
285#else
286static inline int omap243x_sram_init(void)
287{
288 return 0;
289}
290#endif
291
292#ifdef CONFIG_ARCH_OMAP3
293
294void omap3_sram_restore_context(void)
295{
296 omap_sram_reset();
297
298 omap_push_sram_idle();
299}
300
301static inline int omap34xx_sram_init(void)
302{
303 omap3_sram_restore_context();
304 return 0;
305}
306#else
307static inline int omap34xx_sram_init(void)
308{
309 return 0;
310}
311#endif /* CONFIG_ARCH_OMAP3 */
312
313int __init omap_sram_init(void)
314{
315 omap_detect_sram();
316 omap2_map_sram();
317
318 if (cpu_is_omap242x())
319 omap242x_sram_init();
320 else if (cpu_is_omap2430())
321 omap243x_sram_init();
322 else if (cpu_is_omap34xx())
323 omap34xx_sram_init();
324
325 return 0;
326}