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1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 Intel Deutschland GmbH
11 * Copyright(c) 2018 - 2019 Intel Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING.
24 *
25 * Contact Information:
26 * Intel Linux Wireless <linuxwifi@intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *
29 * BSD LICENSE
30 *
31 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
33 * Copyright(c) 2018 - 2019 Intel Corporation
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************/
63#ifndef __iwl_csr_h__
64#define __iwl_csr_h__
65/*
66 * CSR (control and status registers)
67 *
68 * CSR registers are mapped directly into PCI bus space, and are accessible
69 * whenever platform supplies power to device, even when device is in
70 * low power states due to driver-invoked device resets
71 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
72 *
73 * Use iwl_write32() and iwl_read32() family to access these registers;
74 * these provide simple PCI bus access, without waking up the MAC.
75 * Do not use iwl_write_direct32() family for these registers;
76 * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
77 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
78 * the CSR registers.
79 *
80 * NOTE: Device does need to be awake in order to read this memory
81 * via CSR_EEPROM and CSR_OTP registers
82 */
83#define CSR_BASE (0x000)
84
85#define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
86#define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
87#define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
88#define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
89#define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
90#define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
91#define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
92#define CSR_GP_CNTRL (CSR_BASE+0x024)
93
94/* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
95#define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
96
97/*
98 * Hardware revision info
99 * Bit fields:
100 * 31-16: Reserved
101 * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
102 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
103 * 1-0: "Dash" (-) value, as in A-1, etc.
104 */
105#define CSR_HW_REV (CSR_BASE+0x028)
106
107/*
108 * RF ID revision info
109 * Bit fields:
110 * 31:24: Reserved (set to 0x0)
111 * 23:12: Type
112 * 11:8: Step (A - 0x0, B - 0x1, etc)
113 * 7:4: Dash
114 * 3:0: Flavor
115 */
116#define CSR_HW_RF_ID (CSR_BASE+0x09c)
117
118/*
119 * EEPROM and OTP (one-time-programmable) memory reads
120 *
121 * NOTE: Device must be awake, initialized via apm_ops.init(),
122 * in order to read.
123 */
124#define CSR_EEPROM_REG (CSR_BASE+0x02c)
125#define CSR_EEPROM_GP (CSR_BASE+0x030)
126#define CSR_OTP_GP_REG (CSR_BASE+0x034)
127
128#define CSR_GIO_REG (CSR_BASE+0x03C)
129#define CSR_GP_UCODE_REG (CSR_BASE+0x048)
130#define CSR_GP_DRIVER_REG (CSR_BASE+0x050)
131
132/*
133 * UCODE-DRIVER GP (general purpose) mailbox registers.
134 * SET/CLR registers set/clear bit(s) if "1" is written.
135 */
136#define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
137#define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
138#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
139#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
140
141#define CSR_MBOX_SET_REG (CSR_BASE + 0x88)
142
143#define CSR_LED_REG (CSR_BASE+0x094)
144#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
145#define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE + 0x0A8) /* 6000 and up */
146#define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE BIT(20)
147#define CSR_MAC_SHADOW_REG_CTL2 (CSR_BASE + 0x0AC)
148#define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE 0xFFFF
149
150/* GIO Chicken Bits (PCI Express bus link power management) */
151#define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
152
153/* host chicken bits */
154#define CSR_HOST_CHICKEN (CSR_BASE + 0x204)
155#define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME BIT(19)
156
157/* Analog phase-lock-loop configuration */
158#define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
159
160/*
161 * CSR HW resources monitor registers
162 */
163#define CSR_MONITOR_CFG_REG (CSR_BASE+0x214)
164#define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228)
165#define CSR_MONITOR_XTAL_RESOURCES (0x00000010)
166
167/*
168 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
169 * "step" determines CCK backoff for txpower calculation.
170 * See also CSR_HW_REV register.
171 * Bit fields:
172 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
173 * 1-0: "Dash" (-) value, as in C-1, etc.
174 */
175#define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
176
177#define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
178#define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
179
180/* Bits for CSR_HW_IF_CONFIG_REG */
181#define CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
182#define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
183#define CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM (0x00000080)
184#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
185#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
186#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
187#define CSR_HW_IF_CONFIG_REG_D3_DEBUG (0x00000200)
188#define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
189#define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
190#define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
191
192#define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
193#define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
194#define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
195#define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
196#define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
197#define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
198
199#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
200#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
201#define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
202#define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
203#define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
204#define CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
205#define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
206
207#define CSR_MBOX_SET_REG_OS_ALIVE BIT(5)
208
209#define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
210#define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
211
212/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
213 * acknowledged (reset) by host writing "1" to flagged bits. */
214#define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
215#define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
216#define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
217#define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
218#define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
219#define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
220#define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
221#define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
222#define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
223#define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
224#define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
225
226#define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
227 CSR_INT_BIT_HW_ERR | \
228 CSR_INT_BIT_FH_TX | \
229 CSR_INT_BIT_SW_ERR | \
230 CSR_INT_BIT_RF_KILL | \
231 CSR_INT_BIT_SW_RX | \
232 CSR_INT_BIT_WAKEUP | \
233 CSR_INT_BIT_ALIVE | \
234 CSR_INT_BIT_RX_PERIODIC)
235
236/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
237#define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
238#define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
239#define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
240#define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
241#define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
242#define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
243
244#define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
245 CSR_FH_INT_BIT_RX_CHNL1 | \
246 CSR_FH_INT_BIT_RX_CHNL0)
247
248#define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \
249 CSR_FH_INT_BIT_TX_CHNL0)
250
251/* GPIO */
252#define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
253#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
254#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
255
256/* RESET */
257#define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
258#define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
259#define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
260#define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
261#define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
262#define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
263
264/*
265 * GP (general purpose) CONTROL REGISTER
266 * Bit fields:
267 * 27: HW_RF_KILL_SW
268 * Indicates state of (platform's) hardware RF-Kill switch
269 * 26-24: POWER_SAVE_TYPE
270 * Indicates current power-saving mode:
271 * 000 -- No power saving
272 * 001 -- MAC power-down
273 * 010 -- PHY (radio) power-down
274 * 011 -- Error
275 * 10: XTAL ON request
276 * 9-6: SYS_CONFIG
277 * Indicates current system configuration, reflecting pins on chip
278 * as forced high/low by device circuit board.
279 * 4: GOING_TO_SLEEP
280 * Indicates MAC is entering a power-saving sleep power-down.
281 * Not a good time to access device-internal resources.
282 * 3: MAC_ACCESS_REQ
283 * Host sets this to request and maintain MAC wakeup, to allow host
284 * access to device-internal resources. Host must wait for
285 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
286 * device registers.
287 * 2: INIT_DONE
288 * Host sets this to put device into fully operational D0 power mode.
289 * Host resets this after SW_RESET to put device into low power mode.
290 * 0: MAC_CLOCK_READY
291 * Indicates MAC (ucode processor, etc.) is powered up and can run.
292 * Internal resources are accessible.
293 * NOTE: This does not indicate that the processor is actually running.
294 * NOTE: This does not indicate that device has completed
295 * init or post-power-down restore of internal SRAM memory.
296 * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
297 * SRAM is restored and uCode is in normal operation mode.
298 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
299 * do not need to save/restore it.
300 * NOTE: After device reset, this bit remains "0" until host sets
301 * INIT_DONE
302 */
303#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
304#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
305#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
306#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
307#define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400)
308
309#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
310
311#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
312#define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000)
313#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
314
315
316/* HW REV */
317#define CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
318#define CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
319#define CSR_HW_REV_TYPE(_val) (((_val) & 0x000FFF0) >> 4)
320
321/* HW RFID */
322#define CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0)
323#define CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4)
324#define CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8)
325#define CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12)
326
327/**
328 * hw_rev values
329 */
330enum {
331 SILICON_A_STEP = 0,
332 SILICON_B_STEP,
333 SILICON_C_STEP,
334};
335
336
337#define CSR_HW_REV_TYPE_MSK (0x000FFF0)
338#define CSR_HW_REV_TYPE_5300 (0x0000020)
339#define CSR_HW_REV_TYPE_5350 (0x0000030)
340#define CSR_HW_REV_TYPE_5100 (0x0000050)
341#define CSR_HW_REV_TYPE_5150 (0x0000040)
342#define CSR_HW_REV_TYPE_1000 (0x0000060)
343#define CSR_HW_REV_TYPE_6x00 (0x0000070)
344#define CSR_HW_REV_TYPE_6x50 (0x0000080)
345#define CSR_HW_REV_TYPE_6150 (0x0000084)
346#define CSR_HW_REV_TYPE_6x05 (0x00000B0)
347#define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05
348#define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05
349#define CSR_HW_REV_TYPE_2x30 (0x00000C0)
350#define CSR_HW_REV_TYPE_2x00 (0x0000100)
351#define CSR_HW_REV_TYPE_105 (0x0000110)
352#define CSR_HW_REV_TYPE_135 (0x0000120)
353#define CSR_HW_REV_TYPE_7265D (0x0000210)
354#define CSR_HW_REV_TYPE_NONE (0x00001F0)
355#define CSR_HW_REV_TYPE_QNJ (0x0000360)
356#define CSR_HW_REV_TYPE_QNJ_B0 (0x0000364)
357#define CSR_HW_REV_TYPE_QU_B0 (0x0000334)
358#define CSR_HW_REV_TYPE_QU_C0 (0x0000338)
359#define CSR_HW_REV_TYPE_QUZ (0x0000354)
360#define CSR_HW_REV_TYPE_HR_CDB (0x0000340)
361#define CSR_HW_REV_TYPE_SO (0x0000370)
362#define CSR_HW_REV_TYPE_TY (0x0000420)
363
364/* RF_ID value */
365#define CSR_HW_RF_ID_TYPE_JF (0x00105100)
366#define CSR_HW_RF_ID_TYPE_HR (0x0010A000)
367#define CSR_HW_RF_ID_TYPE_HR1 (0x0010c100)
368#define CSR_HW_RF_ID_TYPE_HRCDB (0x00109F00)
369#define CSR_HW_RF_ID_TYPE_GF (0x0010D000)
370#define CSR_HW_RF_ID_TYPE_GF4 (0x0010E000)
371
372/* HW_RF CHIP ID */
373#define CSR_HW_RF_ID_TYPE_CHIP_ID(_val) (((_val) >> 12) & 0xFFF)
374
375/* HW_RF CHIP STEP */
376#define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF)
377
378/* EEPROM REG */
379#define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
380#define CSR_EEPROM_REG_BIT_CMD (0x00000002)
381#define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
382#define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
383
384/* EEPROM GP */
385#define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
386#define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
387#define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
388#define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
389#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
390#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
391
392/* One-time-programmable memory general purpose reg */
393#define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
394#define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
395#define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
396#define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
397
398/* GP REG */
399#define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
400#define CSR_GP_REG_NO_POWER_SAVE (0x00000000)
401#define CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
402#define CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
403#define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
404
405
406/* CSR GIO */
407#define CSR_GIO_REG_VAL_L0S_DISABLED (0x00000002)
408
409/*
410 * UCODE-DRIVER GP (general purpose) mailbox register 1
411 * Host driver and uCode write and/or read this register to communicate with
412 * each other.
413 * Bit fields:
414 * 4: UCODE_DISABLE
415 * Host sets this to request permanent halt of uCode, same as
416 * sending CARD_STATE command with "halt" bit set.
417 * 3: CT_KILL_EXIT
418 * Host sets this to request exit from CT_KILL state, i.e. host thinks
419 * device temperature is low enough to continue normal operation.
420 * 2: CMD_BLOCKED
421 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
422 * to release uCode to clear all Tx and command queues, enter
423 * unassociated mode, and power down.
424 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
425 * 1: SW_BIT_RFKILL
426 * Host sets this when issuing CARD_STATE command to request
427 * device sleep.
428 * 0: MAC_SLEEP
429 * uCode sets this when preparing a power-saving power-down.
430 * uCode resets this when power-up is complete and SRAM is sane.
431 * NOTE: device saves internal SRAM data to host when powering down,
432 * and must restore this data after powering back up.
433 * MAC_SLEEP is the best indication that restore is complete.
434 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
435 * do not need to save/restore it.
436 */
437#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
438#define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
439#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
440#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
441#define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
442
443/* GP Driver */
444#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
445#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
446#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
447#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
448#define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
449#define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
450
451#define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
452
453/* GIO Chicken Bits (PCI Express bus link power management) */
454#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
455#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
456
457/* LED */
458#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
459#define CSR_LED_REG_TURN_ON (0x60)
460#define CSR_LED_REG_TURN_OFF (0x20)
461
462/* ANA_PLL */
463#define CSR50_ANA_PLL_CFG_VAL (0x00880300)
464
465/* HPET MEM debug */
466#define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
467
468/* DRAM INT TABLE */
469#define CSR_DRAM_INT_TBL_ENABLE (1 << 31)
470#define CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
471#define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
472
473/*
474 * SHR target access (Shared block memory space)
475 *
476 * Shared internal registers can be accessed directly from PCI bus through SHR
477 * arbiter without need for the MAC HW to be powered up. This is possible due to
478 * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and
479 * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers.
480 *
481 * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
482 * need not be powered up so no "grab inc access" is required.
483 */
484
485/*
486 * Registers for accessing shared registers (e.g. SHR_APMG_GP1,
487 * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC),
488 * first, write to the control register:
489 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
490 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
491 * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
492 *
493 * To write the register, first, write to the data register
494 * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
495 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
496 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
497 */
498#define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec)
499#define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4)
500
501/*
502 * HBUS (Host-side Bus)
503 *
504 * HBUS registers are mapped directly into PCI bus space, but are used
505 * to indirectly access device's internal memory or registers that
506 * may be powered-down.
507 *
508 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
509 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
510 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
511 * internal resources.
512 *
513 * Do not use iwl_write32()/iwl_read32() family to access these registers;
514 * these provide only simple PCI bus access, without waking up the MAC.
515 */
516#define HBUS_BASE (0x400)
517
518/*
519 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
520 * structures, error log, event log, verifying uCode load).
521 * First write to address register, then read from or write to data register
522 * to complete the job. Once the address register is set up, accesses to
523 * data registers auto-increment the address by one dword.
524 * Bit usage for address registers (read or write):
525 * 0-31: memory address within device
526 */
527#define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
528#define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
529#define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
530#define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
531
532/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
533#define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
534#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
535
536/*
537 * Registers for accessing device's internal peripheral registers
538 * (e.g. SCD, BSM, etc.). First write to address register,
539 * then read from or write to data register to complete the job.
540 * Bit usage for address registers (read or write):
541 * 0-15: register address (offset) within device
542 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
543 */
544#define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
545#define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
546#define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
547#define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
548
549/* Used to enable DBGM */
550#define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c)
551
552/*
553 * Per-Tx-queue write pointer (index, really!)
554 * Indicates index to next TFD that driver will fill (1 past latest filled).
555 * Bit usage:
556 * 0-7: queue write index
557 * 11-8: queue selector
558 */
559#define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
560
561/**********************************************************
562 * CSR values
563 **********************************************************/
564 /*
565 * host interrupt timeout value
566 * used with setting interrupt coalescing timer
567 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
568 *
569 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
570 */
571#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
572#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
573#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
574#define IWL_HOST_INT_OPER_MODE BIT(31)
575
576/*****************************************************************************
577 * 7000/3000 series SHR DTS addresses *
578 *****************************************************************************/
579
580/* Diode Results Register Structure: */
581enum dtd_diode_reg {
582 DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
583 DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
584 DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
585 DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
586 DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
587 DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
588/* Those are the masks INSIDE the flags bit-field: */
589 DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
590 DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
591 DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
592 DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
593};
594
595/*****************************************************************************
596 * MSIX related registers *
597 *****************************************************************************/
598
599#define CSR_MSIX_BASE (0x2000)
600#define CSR_MSIX_FH_INT_CAUSES_AD (CSR_MSIX_BASE + 0x800)
601#define CSR_MSIX_FH_INT_MASK_AD (CSR_MSIX_BASE + 0x804)
602#define CSR_MSIX_HW_INT_CAUSES_AD (CSR_MSIX_BASE + 0x808)
603#define CSR_MSIX_HW_INT_MASK_AD (CSR_MSIX_BASE + 0x80C)
604#define CSR_MSIX_AUTOMASK_ST_AD (CSR_MSIX_BASE + 0x810)
605#define CSR_MSIX_RX_IVAR_AD_REG (CSR_MSIX_BASE + 0x880)
606#define CSR_MSIX_IVAR_AD_REG (CSR_MSIX_BASE + 0x890)
607#define CSR_MSIX_PENDING_PBA_AD (CSR_MSIX_BASE + 0x1000)
608#define CSR_MSIX_RX_IVAR(cause) (CSR_MSIX_RX_IVAR_AD_REG + (cause))
609#define CSR_MSIX_IVAR(cause) (CSR_MSIX_IVAR_AD_REG + (cause))
610
611#define MSIX_FH_INT_CAUSES_Q(q) (q)
612
613/*
614 * Causes for the FH register interrupts
615 */
616enum msix_fh_int_causes {
617 MSIX_FH_INT_CAUSES_Q0 = BIT(0),
618 MSIX_FH_INT_CAUSES_Q1 = BIT(1),
619 MSIX_FH_INT_CAUSES_D2S_CH0_NUM = BIT(16),
620 MSIX_FH_INT_CAUSES_D2S_CH1_NUM = BIT(17),
621 MSIX_FH_INT_CAUSES_S2D = BIT(19),
622 MSIX_FH_INT_CAUSES_FH_ERR = BIT(21),
623};
624
625/*
626 * Causes for the HW register interrupts
627 */
628enum msix_hw_int_causes {
629 MSIX_HW_INT_CAUSES_REG_ALIVE = BIT(0),
630 MSIX_HW_INT_CAUSES_REG_WAKEUP = BIT(1),
631 MSIX_HW_INT_CAUSES_REG_IML = BIT(2),
632 MSIX_HW_INT_CAUSES_REG_CT_KILL = BIT(6),
633 MSIX_HW_INT_CAUSES_REG_RF_KILL = BIT(7),
634 MSIX_HW_INT_CAUSES_REG_PERIODIC = BIT(8),
635 MSIX_HW_INT_CAUSES_REG_SW_ERR = BIT(25),
636 MSIX_HW_INT_CAUSES_REG_SCD = BIT(26),
637 MSIX_HW_INT_CAUSES_REG_FH_TX = BIT(27),
638 MSIX_HW_INT_CAUSES_REG_HW_ERR = BIT(29),
639 MSIX_HW_INT_CAUSES_REG_HAP = BIT(30),
640};
641
642#define MSIX_MIN_INTERRUPT_VECTORS 2
643#define MSIX_AUTO_CLEAR_CAUSE 0
644#define MSIX_NON_AUTO_CLEAR_CAUSE BIT(7)
645
646/*****************************************************************************
647 * HW address related registers *
648 *****************************************************************************/
649
650#define CSR_ADDR_BASE (0x380)
651#define CSR_MAC_ADDR0_OTP (CSR_ADDR_BASE)
652#define CSR_MAC_ADDR1_OTP (CSR_ADDR_BASE + 4)
653#define CSR_MAC_ADDR0_STRAP (CSR_ADDR_BASE + 8)
654#define CSR_MAC_ADDR1_STRAP (CSR_ADDR_BASE + 0xC)
655
656#endif /* !__iwl_csr_h__ */