1/*
  2 * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
  3 * Copyright (c) 2008-2009 Marvell Semiconductor
  4 *
  5 * This program is free software; you can redistribute it and/or modify
  6 * it under the terms of the GNU General Public License as published by
  7 * the Free Software Foundation; either version 2 of the License, or
  8 * (at your option) any later version.
  9 */
 10
 11#include <linux/delay.h>
 12#include <linux/jiffies.h>
 13#include <linux/list.h>
 14#include <linux/module.h>
 15#include <linux/netdevice.h>
 16#include <linux/phy.h>
 17#include <net/dsa.h>
 18#include "mv88e6xxx.h"
 19
 20/* Switch product IDs */
 21#define ID_6085		0x04a0
 22#define ID_6095		0x0950
 23#define ID_6131		0x1060
 24
 25static char *mv88e6131_probe(struct mii_bus *bus, int sw_addr)
 26{
 27	int ret;
 28
 29	ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
 30	if (ret >= 0) {
 31		ret &= 0xfff0;
 32		if (ret == ID_6085)
 33			return "Marvell 88E6085";
 34		if (ret == ID_6095)
 35			return "Marvell 88E6095/88E6095F";
 36		if (ret == ID_6131)
 37			return "Marvell 88E6131";
 38	}
 39
 40	return NULL;
 41}
 42
 43static int mv88e6131_switch_reset(struct dsa_switch *ds)
 44{
 45	int i;
 46	int ret;
 47	unsigned long timeout;
 48
 49	/* Set all ports to the disabled state. */
 50	for (i = 0; i < 11; i++) {
 51		ret = REG_READ(REG_PORT(i), 0x04);
 52		REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
 53	}
 54
 55	/* Wait for transmit queues to drain. */
 56	usleep_range(2000, 4000);
 57
 58	/* Reset the switch. */
 59	REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
 60
 61	/* Wait up to one second for reset to complete. */
 62	timeout = jiffies + 1 * HZ;
 63	while (time_before(jiffies, timeout)) {
 64		ret = REG_READ(REG_GLOBAL, 0x00);
 65		if ((ret & 0xc800) == 0xc800)
 66			break;
 67
 68		usleep_range(1000, 2000);
 69	}
 70	if (time_after(jiffies, timeout))
 71		return -ETIMEDOUT;
 72
 73	return 0;
 74}
 75
 76static int mv88e6131_setup_global(struct dsa_switch *ds)
 77{
 78	int ret;
 79	int i;
 80
 81	/* Enable the PHY polling unit, don't discard packets with
 82	 * excessive collisions, use a weighted fair queueing scheme
 83	 * to arbitrate between packet queues, set the maximum frame
 84	 * size to 1632, and mask all interrupt sources.
 85	 */
 86	REG_WRITE(REG_GLOBAL, 0x04, 0x4400);
 87
 88	/* Set the default address aging time to 5 minutes, and
 89	 * enable address learn messages to be sent to all message
 90	 * ports.
 91	 */
 92	REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
 93
 94	/* Configure the priority mapping registers. */
 95	ret = mv88e6xxx_config_prio(ds);
 96	if (ret < 0)
 97		return ret;
 98
 99	/* Set the VLAN ethertype to 0x8100. */
100	REG_WRITE(REG_GLOBAL, 0x19, 0x8100);
101
102	/* Disable ARP mirroring, and configure the upstream port as
103	 * the port to which ingress and egress monitor frames are to
104	 * be sent.
105	 */
106	REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0);
107
108	/* Disable cascade port functionality unless this device
109	 * is used in a cascade configuration, and set the switch's
110	 * DSA device number.
111	 */
112	if (ds->dst->pd->nr_chips > 1)
113		REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 | (ds->index & 0x1f));
114	else
115		REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f));
116
117	/* Send all frames with destination addresses matching
118	 * 01:80:c2:00:00:0x to the CPU port.
119	 */
120	REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
121
122	/* Ignore removed tag data on doubly tagged packets, disable
123	 * flow control messages, force flow control priority to the
124	 * highest, and send all special multicast frames to the CPU
125	 * port at the highest priority.
126	 */
127	REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
128
129	/* Program the DSA routing table. */
130	for (i = 0; i < 32; i++) {
131		int nexthop;
132
133		nexthop = 0x1f;
134		if (i != ds->index && i < ds->dst->pd->nr_chips)
135			nexthop = ds->pd->rtable[i] & 0x1f;
136
137		REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
138	}
139
140	/* Clear all trunk masks. */
141	for (i = 0; i < 8; i++)
142		REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7ff);
143
144	/* Clear all trunk mappings. */
145	for (i = 0; i < 16; i++)
146		REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));
147
148	/* Force the priority of IGMP/MLD snoop frames and ARP frames
149	 * to the highest setting.
150	 */
151	REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff);
152
153	return 0;
154}
155
156static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
157{
158	struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
159	int addr = REG_PORT(p);
160	u16 val;
161
162	/* MAC Forcing register: don't force link, speed, duplex
163	 * or flow control state to any particular values on physical
164	 * ports, but force the CPU port and all DSA ports to 1000 Mb/s
165	 * (100 Mb/s on 6085) full duplex.
166	 */
167	if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
168		if (ps->id == ID_6085)
169			REG_WRITE(addr, 0x01, 0x003d); /* 100 Mb/s */
170		else
171			REG_WRITE(addr, 0x01, 0x003e); /* 1000 Mb/s */
172	else
173		REG_WRITE(addr, 0x01, 0x0003);
174
175	/* Port Control: disable Core Tag, disable Drop-on-Lock,
176	 * transmit frames unmodified, disable Header mode,
177	 * enable IGMP/MLD snoop, disable DoubleTag, disable VLAN
178	 * tunneling, determine priority by looking at 802.1p and
179	 * IP priority fields (IP prio has precedence), and set STP
180	 * state to Forwarding.
181	 *
182	 * If this is the upstream port for this switch, enable
183	 * forwarding of unknown unicasts, and enable DSA tagging
184	 * mode.
185	 *
186	 * If this is the link to another switch, use DSA tagging
187	 * mode, but do not enable forwarding of unknown unicasts.
188	 */
189	val = 0x0433;
190	if (p == dsa_upstream_port(ds)) {
191		val |= 0x0104;
192		/* On 6085, unknown multicast forward is controlled
193		 * here rather than in Port Control 2 register.
194		 */
195		if (ps->id == ID_6085)
196			val |= 0x0008;
197	}
198	if (ds->dsa_port_mask & (1 << p))
199		val |= 0x0100;
200	REG_WRITE(addr, 0x04, val);
201
202	/* Port Control 1: disable trunking.  Also, if this is the
203	 * CPU port, enable learn messages to be sent to this port.
204	 */
205	REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
206
207	/* Port based VLAN map: give each port its own address
208	 * database, allow the CPU port to talk to each of the 'real'
209	 * ports, and allow each of the 'real' ports to only talk to
210	 * the upstream port.
211	 */
212	val = (p & 0xf) << 12;
213	if (dsa_is_cpu_port(ds, p))
214		val |= ds->phys_port_mask;
215	else
216		val |= 1 << dsa_upstream_port(ds);
217	REG_WRITE(addr, 0x06, val);
218
219	/* Default VLAN ID and priority: don't set a default VLAN
220	 * ID, and set the default packet priority to zero.
221	 */
222	REG_WRITE(addr, 0x07, 0x0000);
223
224	/* Port Control 2: don't force a good FCS, don't use
225	 * VLAN-based, source address-based or destination
226	 * address-based priority overrides, don't let the switch
227	 * add or strip 802.1q tags, don't discard tagged or
228	 * untagged frames on this port, do a destination address
229	 * lookup on received packets as usual, don't send a copy
230	 * of all transmitted/received frames on this port to the
231	 * CPU, and configure the upstream port number.
232	 *
233	 * If this is the upstream port for this switch, enable
234	 * forwarding of unknown multicast addresses.
235	 */
236	if (ps->id == ID_6085)
237		/* on 6085, bits 3:0 are reserved, bit 6 control ARP
238		 * mirroring, and multicast forward is handled in
239		 * Port Control register.
240		 */
241		REG_WRITE(addr, 0x08, 0x0080);
242	else {
243		val = 0x0080 | dsa_upstream_port(ds);
244		if (p == dsa_upstream_port(ds))
245			val |= 0x0040;
246		REG_WRITE(addr, 0x08, val);
247	}
248
249	/* Rate Control: disable ingress rate limiting. */
250	REG_WRITE(addr, 0x09, 0x0000);
251
252	/* Rate Control 2: disable egress rate limiting. */
253	REG_WRITE(addr, 0x0a, 0x0000);
254
255	/* Port Association Vector: when learning source addresses
256	 * of packets, add the address to the address database using
257	 * a port bitmap that has only the bit for this port set and
258	 * the other bits clear.
259	 */
260	REG_WRITE(addr, 0x0b, 1 << p);
261
262	/* Tag Remap: use an identity 802.1p prio -> switch prio
263	 * mapping.
264	 */
265	REG_WRITE(addr, 0x18, 0x3210);
266
267	/* Tag Remap 2: use an identity 802.1p prio -> switch prio
268	 * mapping.
269	 */
270	REG_WRITE(addr, 0x19, 0x7654);
271
272	return 0;
273}
274
275static int mv88e6131_setup(struct dsa_switch *ds)
276{
277	struct mv88e6xxx_priv_state *ps = (void *)(ds + 1);
278	int i;
279	int ret;
280
281	mutex_init(&ps->smi_mutex);
282	mv88e6xxx_ppu_state_init(ds);
283	mutex_init(&ps->stats_mutex);
284
285	ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;
286
287	ret = mv88e6131_switch_reset(ds);
288	if (ret < 0)
289		return ret;
290
291	/* @@@ initialise vtu and atu */
292
293	ret = mv88e6131_setup_global(ds);
294	if (ret < 0)
295		return ret;
296
297	for (i = 0; i < 11; i++) {
298		ret = mv88e6131_setup_port(ds, i);
299		if (ret < 0)
300			return ret;
301	}
302
303	return 0;
304}
305
306static int mv88e6131_port_to_phy_addr(int port)
307{
308	if (port >= 0 && port <= 11)
309		return port;
310	return -1;
311}
312
313static int
314mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum)
315{
316	int addr = mv88e6131_port_to_phy_addr(port);
317	return mv88e6xxx_phy_read_ppu(ds, addr, regnum);
318}
319
320static int
321mv88e6131_phy_write(struct dsa_switch *ds,
322			      int port, int regnum, u16 val)
323{
324	int addr = mv88e6131_port_to_phy_addr(port);
325	return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val);
326}
327
328static struct mv88e6xxx_hw_stat mv88e6131_hw_stats[] = {
329	{ "in_good_octets", 8, 0x00, },
330	{ "in_bad_octets", 4, 0x02, },
331	{ "in_unicast", 4, 0x04, },
332	{ "in_broadcasts", 4, 0x06, },
333	{ "in_multicasts", 4, 0x07, },
334	{ "in_pause", 4, 0x16, },
335	{ "in_undersize", 4, 0x18, },
336	{ "in_fragments", 4, 0x19, },
337	{ "in_oversize", 4, 0x1a, },
338	{ "in_jabber", 4, 0x1b, },
339	{ "in_rx_error", 4, 0x1c, },
340	{ "in_fcs_error", 4, 0x1d, },
341	{ "out_octets", 8, 0x0e, },
342	{ "out_unicast", 4, 0x10, },
343	{ "out_broadcasts", 4, 0x13, },
344	{ "out_multicasts", 4, 0x12, },
345	{ "out_pause", 4, 0x15, },
346	{ "excessive", 4, 0x11, },
347	{ "collisions", 4, 0x1e, },
348	{ "deferred", 4, 0x05, },
349	{ "single", 4, 0x14, },
350	{ "multiple", 4, 0x17, },
351	{ "out_fcs_error", 4, 0x03, },
352	{ "late", 4, 0x1f, },
353	{ "hist_64bytes", 4, 0x08, },
354	{ "hist_65_127bytes", 4, 0x09, },
355	{ "hist_128_255bytes", 4, 0x0a, },
356	{ "hist_256_511bytes", 4, 0x0b, },
357	{ "hist_512_1023bytes", 4, 0x0c, },
358	{ "hist_1024_max_bytes", 4, 0x0d, },
359};
360
361static void
362mv88e6131_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
363{
364	mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6131_hw_stats),
365			      mv88e6131_hw_stats, port, data);
366}
367
368static void
369mv88e6131_get_ethtool_stats(struct dsa_switch *ds,
370				  int port, uint64_t *data)
371{
372	mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6131_hw_stats),
373				    mv88e6131_hw_stats, port, data);
374}
375
376static int mv88e6131_get_sset_count(struct dsa_switch *ds)
377{
378	return ARRAY_SIZE(mv88e6131_hw_stats);
379}
380
381struct dsa_switch_driver mv88e6131_switch_driver = {
382	.tag_protocol		= cpu_to_be16(ETH_P_DSA),
383	.priv_size		= sizeof(struct mv88e6xxx_priv_state),
384	.probe			= mv88e6131_probe,
385	.setup			= mv88e6131_setup,
386	.set_addr		= mv88e6xxx_set_addr_direct,
387	.phy_read		= mv88e6131_phy_read,
388	.phy_write		= mv88e6131_phy_write,
389	.poll_link		= mv88e6xxx_poll_link,
390	.get_strings		= mv88e6131_get_strings,
391	.get_ethtool_stats	= mv88e6131_get_ethtool_stats,
392	.get_sset_count		= mv88e6131_get_sset_count,
393};
394
395MODULE_ALIAS("platform:mv88e6085");
396MODULE_ALIAS("platform:mv88e6095");
397MODULE_ALIAS("platform:mv88e6095f");
398MODULE_ALIAS("platform:mv88e6131");