Loading...
Note: File does not exist in v3.15.
1// SPDX-License-Identifier: GPL-2.0
2//
3// Secure Digital Host Controller
4//
5// Copyright (C) 2018 Spreadtrum, Inc.
6// Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
7
8#include <linux/delay.h>
9#include <linux/dma-mapping.h>
10#include <linux/highmem.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
14#include <linux/of_gpio.h>
15#include <linux/pinctrl/consumer.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/regulator/consumer.h>
19#include <linux/slab.h>
20
21#include "sdhci-pltfm.h"
22#include "mmc_hsq.h"
23
24/* SDHCI_ARGUMENT2 register high 16bit */
25#define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16)
26
27#define SDHCI_SPRD_REG_32_DLL_CFG 0x200
28#define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
29#define SDHCI_SPRD_DLL_EN BIT(21)
30#define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16)
31#define SDHCI_SPRD_DLL_INIT_COUNT 0xc00
32#define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3
33
34#define SDHCI_SPRD_REG_32_DLL_DLY 0x204
35
36#define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208
37#define SDHCIBSPRD_IT_WR_DLY_INV BIT(5)
38#define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13)
39#define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21)
40#define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29)
41
42#define SDHCI_SPRD_REG_32_BUSY_POSI 0x250
43#define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25)
44#define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24)
45
46#define SDHCI_SPRD_REG_DEBOUNCE 0x28C
47#define SDHCI_SPRD_BIT_DLL_BAK BIT(0)
48#define SDHCI_SPRD_BIT_DLL_VAL BIT(1)
49
50#define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B
51
52/* SDHCI_HOST_CONTROL2 */
53#define SDHCI_SPRD_CTRL_HS200 0x0005
54#define SDHCI_SPRD_CTRL_HS400 0x0006
55#define SDHCI_SPRD_CTRL_HS400ES 0x0007
56
57/*
58 * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
59 * reserved, and only used on Spreadtrum's design, the hardware cannot work
60 * if this bit is cleared.
61 * 1 : normal work
62 * 0 : hardware reset
63 */
64#define SDHCI_HW_RESET_CARD BIT(3)
65
66#define SDHCI_SPRD_MAX_CUR 0xFFFFFF
67#define SDHCI_SPRD_CLK_MAX_DIV 1023
68
69#define SDHCI_SPRD_CLK_DEF_RATE 26000000
70#define SDHCI_SPRD_PHY_DLL_CLK 52000000
71
72struct sdhci_sprd_host {
73 u32 version;
74 struct clk *clk_sdio;
75 struct clk *clk_enable;
76 struct clk *clk_2x_enable;
77 struct pinctrl *pinctrl;
78 struct pinctrl_state *pins_uhs;
79 struct pinctrl_state *pins_default;
80 u32 base_rate;
81 int flags; /* backup of host attribute */
82 u32 phy_delay[MMC_TIMING_MMC_HS400 + 2];
83};
84
85struct sdhci_sprd_phy_cfg {
86 const char *property;
87 u8 timing;
88};
89
90static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = {
91 { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
92 { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
93 { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
94 { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
95 { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
96 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
97 { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, },
98 { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, },
99 { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, },
100};
101
102#define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
103
104static void sdhci_sprd_init_config(struct sdhci_host *host)
105{
106 u16 val;
107
108 /* set dll backup mode */
109 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
110 val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
111 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
112}
113
114static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
115{
116 if (unlikely(reg == SDHCI_MAX_CURRENT))
117 return SDHCI_SPRD_MAX_CUR;
118
119 return readl_relaxed(host->ioaddr + reg);
120}
121
122static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
123{
124 /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
125 if (unlikely(reg == SDHCI_MAX_CURRENT))
126 return;
127
128 if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
129 val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
130
131 writel_relaxed(val, host->ioaddr + reg);
132}
133
134static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg)
135{
136 /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */
137 if (unlikely(reg == SDHCI_BLOCK_COUNT))
138 return;
139
140 writew_relaxed(val, host->ioaddr + reg);
141}
142
143static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg)
144{
145 /*
146 * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the
147 * standard specification, sdhci_reset() write this register directly
148 * without checking other reserved bits, that will clear BIT(3) which
149 * is defined as hardware reset on Spreadtrum's platform and clearing
150 * it by mistake will lead the card not work. So here we need to work
151 * around it.
152 */
153 if (unlikely(reg == SDHCI_SOFTWARE_RESET)) {
154 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
155 val |= SDHCI_HW_RESET_CARD;
156 }
157
158 writeb_relaxed(val, host->ioaddr + reg);
159}
160
161static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host)
162{
163 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
164
165 ctrl &= ~SDHCI_CLOCK_CARD_EN;
166 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
167}
168
169static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host)
170{
171 u16 ctrl;
172
173 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
174 ctrl |= SDHCI_CLOCK_CARD_EN;
175 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
176}
177
178static inline void
179sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en)
180{
181 u32 dll_dly_offset;
182
183 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
184 if (en)
185 dll_dly_offset |= mask;
186 else
187 dll_dly_offset &= ~mask;
188 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
189}
190
191static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk)
192{
193 u32 div;
194
195 /* select 2x clock source */
196 if (base_clk <= clk * 2)
197 return 0;
198
199 div = (u32) (base_clk / (clk * 2));
200
201 if ((base_clk / div) > (clk * 2))
202 div++;
203
204 if (div > SDHCI_SPRD_CLK_MAX_DIV)
205 div = SDHCI_SPRD_CLK_MAX_DIV;
206
207 if (div % 2)
208 div = (div + 1) / 2;
209 else
210 div = div / 2;
211
212 return div;
213}
214
215static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
216 unsigned int clk)
217{
218 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
219 u32 div, val, mask;
220
221 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
222
223 div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
224 div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
225 sdhci_enable_clk(host, div);
226
227 /* enable auto gate sdhc_enable_auto_gate */
228 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
229 mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN |
230 SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
231 if (mask != (val & mask)) {
232 val |= mask;
233 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
234 }
235}
236
237static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host)
238{
239 u32 tmp;
240
241 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
242 tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN);
243 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
244 /* wait 1ms */
245 usleep_range(1000, 1250);
246
247 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
248 tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE |
249 SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL;
250 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
251 /* wait 1ms */
252 usleep_range(1000, 1250);
253
254 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
255 tmp |= SDHCI_SPRD_DLL_EN;
256 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
257 /* wait 1ms */
258 usleep_range(1000, 1250);
259}
260
261static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock)
262{
263 bool en = false, clk_changed = false;
264
265 if (clock == 0) {
266 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
267 } else if (clock != host->clock) {
268 sdhci_sprd_sd_clk_off(host);
269 _sdhci_sprd_set_clock(host, clock);
270
271 if (clock <= 400000)
272 en = true;
273 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV |
274 SDHCI_SPRD_BIT_POSRD_DLY_INV, en);
275 clk_changed = true;
276 } else {
277 _sdhci_sprd_set_clock(host, clock);
278 }
279
280 /*
281 * According to the Spreadtrum SD host specification, when we changed
282 * the clock to be more than 52M, we should enable the PHY DLL which
283 * is used to track the clock frequency to make the clock work more
284 * stable. Otherwise deviation may occur of the higher clock.
285 */
286 if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK)
287 sdhci_sprd_enable_phy_dll(host);
288}
289
290static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host)
291{
292 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
293
294 return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX);
295}
296
297static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host)
298{
299 return 400000;
300}
301
302static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host,
303 unsigned int timing)
304{
305 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
306 struct mmc_host *mmc = host->mmc;
307 u32 *p = sprd_host->phy_delay;
308 u16 ctrl_2;
309
310 if (timing == host->timing)
311 return;
312
313 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
314 /* Select Bus Speed Mode for host */
315 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
316 switch (timing) {
317 case MMC_TIMING_UHS_SDR12:
318 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
319 break;
320 case MMC_TIMING_MMC_HS:
321 case MMC_TIMING_SD_HS:
322 case MMC_TIMING_UHS_SDR25:
323 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
324 break;
325 case MMC_TIMING_UHS_SDR50:
326 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
327 break;
328 case MMC_TIMING_UHS_SDR104:
329 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
330 break;
331 case MMC_TIMING_UHS_DDR50:
332 case MMC_TIMING_MMC_DDR52:
333 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
334 break;
335 case MMC_TIMING_MMC_HS200:
336 ctrl_2 |= SDHCI_SPRD_CTRL_HS200;
337 break;
338 case MMC_TIMING_MMC_HS400:
339 ctrl_2 |= SDHCI_SPRD_CTRL_HS400;
340 break;
341 default:
342 break;
343 }
344
345 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
346
347 if (!mmc->ios.enhanced_strobe)
348 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY);
349}
350
351static void sdhci_sprd_hw_reset(struct sdhci_host *host)
352{
353 int val;
354
355 /*
356 * Note: don't use sdhci_writeb() API here since it is redirected to
357 * sdhci_sprd_writeb() in which we have a workaround for
358 * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can
359 * not be cleared.
360 */
361 val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
362 val &= ~SDHCI_HW_RESET_CARD;
363 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
364 /* wait for 10 us */
365 usleep_range(10, 20);
366
367 val |= SDHCI_HW_RESET_CARD;
368 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
369 usleep_range(300, 500);
370}
371
372static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host)
373{
374 /* The Spredtrum controller actual maximum timeout count is 1 << 31 */
375 return 1 << 31;
376}
377
378static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host)
379{
380 return 0;
381}
382
383static void sdhci_sprd_request_done(struct sdhci_host *host,
384 struct mmc_request *mrq)
385{
386 /* Validate if the request was from software queue firstly. */
387 if (mmc_hsq_finalize_request(host->mmc, mrq))
388 return;
389
390 mmc_request_done(host->mmc, mrq);
391}
392
393static struct sdhci_ops sdhci_sprd_ops = {
394 .read_l = sdhci_sprd_readl,
395 .write_l = sdhci_sprd_writel,
396 .write_b = sdhci_sprd_writeb,
397 .set_clock = sdhci_sprd_set_clock,
398 .get_max_clock = sdhci_sprd_get_max_clock,
399 .get_min_clock = sdhci_sprd_get_min_clock,
400 .set_bus_width = sdhci_set_bus_width,
401 .reset = sdhci_reset,
402 .set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
403 .hw_reset = sdhci_sprd_hw_reset,
404 .get_max_timeout_count = sdhci_sprd_get_max_timeout_count,
405 .get_ro = sdhci_sprd_get_ro,
406 .request_done = sdhci_sprd_request_done,
407};
408
409static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc,
410 struct mmc_request *mrq)
411{
412 struct sdhci_host *host = mmc_priv(mmc);
413 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
414
415 host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23;
416
417 /*
418 * From version 4.10 onward, ARGUMENT2 register is also as 32-bit
419 * block count register which doesn't support stuff bits of
420 * CMD23 argument on Spreadtrum's sd host controller.
421 */
422 if (host->version >= SDHCI_SPEC_410 &&
423 mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) &&
424 (host->flags & SDHCI_AUTO_CMD23))
425 host->flags &= ~SDHCI_AUTO_CMD23;
426}
427
428static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
429{
430 sdhci_sprd_check_auto_cmd23(mmc, mrq);
431
432 sdhci_request(mmc, mrq);
433}
434
435static int sdhci_sprd_request_atomic(struct mmc_host *mmc,
436 struct mmc_request *mrq)
437{
438 sdhci_sprd_check_auto_cmd23(mmc, mrq);
439
440 return sdhci_request_atomic(mmc, mrq);
441}
442
443static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
444{
445 struct sdhci_host *host = mmc_priv(mmc);
446 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
447 int ret;
448
449 if (!IS_ERR(mmc->supply.vqmmc)) {
450 ret = mmc_regulator_set_vqmmc(mmc, ios);
451 if (ret < 0) {
452 pr_err("%s: Switching signalling voltage failed\n",
453 mmc_hostname(mmc));
454 return ret;
455 }
456 }
457
458 if (IS_ERR(sprd_host->pinctrl))
459 return 0;
460
461 switch (ios->signal_voltage) {
462 case MMC_SIGNAL_VOLTAGE_180:
463 ret = pinctrl_select_state(sprd_host->pinctrl,
464 sprd_host->pins_uhs);
465 if (ret) {
466 pr_err("%s: failed to select uhs pin state\n",
467 mmc_hostname(mmc));
468 return ret;
469 }
470 break;
471
472 default:
473 fallthrough;
474 case MMC_SIGNAL_VOLTAGE_330:
475 ret = pinctrl_select_state(sprd_host->pinctrl,
476 sprd_host->pins_default);
477 if (ret) {
478 pr_err("%s: failed to select default pin state\n",
479 mmc_hostname(mmc));
480 return ret;
481 }
482 break;
483 }
484
485 /* Wait for 300 ~ 500 us for pin state stable */
486 usleep_range(300, 500);
487 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
488
489 return 0;
490}
491
492static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc,
493 struct mmc_ios *ios)
494{
495 struct sdhci_host *host = mmc_priv(mmc);
496 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
497 u32 *p = sprd_host->phy_delay;
498 u16 ctrl_2;
499
500 if (!ios->enhanced_strobe)
501 return;
502
503 sdhci_sprd_sd_clk_off(host);
504
505 /* Set HS400 enhanced strobe mode */
506 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
507 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
508 ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES;
509 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
510
511 sdhci_sprd_sd_clk_on(host);
512
513 /* Set the PHY DLL delay value for HS400 enhanced strobe mode */
514 sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1],
515 SDHCI_SPRD_REG_32_DLL_DLY);
516}
517
518static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host,
519 struct device_node *np)
520{
521 u32 *p = sprd_host->phy_delay;
522 int ret, i, index;
523 u32 val[4];
524
525 for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) {
526 ret = of_property_read_u32_array(np,
527 sdhci_sprd_phy_cfgs[i].property, val, 4);
528 if (ret)
529 continue;
530
531 index = sdhci_sprd_phy_cfgs[i].timing;
532 p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24);
533 }
534}
535
536static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
537 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
538 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
539 SDHCI_QUIRK_MISSING_CAPS,
540 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
541 SDHCI_QUIRK2_USE_32BIT_BLK_CNT |
542 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
543 .ops = &sdhci_sprd_ops,
544};
545
546static int sdhci_sprd_probe(struct platform_device *pdev)
547{
548 struct sdhci_host *host;
549 struct sdhci_sprd_host *sprd_host;
550 struct mmc_hsq *hsq;
551 struct clk *clk;
552 int ret = 0;
553
554 host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host));
555 if (IS_ERR(host))
556 return PTR_ERR(host);
557
558 host->dma_mask = DMA_BIT_MASK(64);
559 pdev->dev.dma_mask = &host->dma_mask;
560 host->mmc_host_ops.request = sdhci_sprd_request;
561 host->mmc_host_ops.hs400_enhanced_strobe =
562 sdhci_sprd_hs400_enhanced_strobe;
563 /*
564 * We can not use the standard ops to change and detect the voltage
565 * signal for Spreadtrum SD host controller, since our voltage regulator
566 * for I/O is fixed in hardware, that means we do not need control
567 * the standard SD host controller to change the I/O voltage.
568 */
569 host->mmc_host_ops.start_signal_voltage_switch =
570 sdhci_sprd_voltage_switch;
571
572 host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
573 MMC_CAP_WAIT_WHILE_BUSY;
574
575 ret = mmc_of_parse(host->mmc);
576 if (ret)
577 goto pltfm_free;
578
579 if (!mmc_card_is_removable(host->mmc))
580 host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic;
581 else
582 host->always_defer_done = true;
583
584 sprd_host = TO_SPRD_HOST(host);
585 sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node);
586
587 sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev);
588 if (!IS_ERR(sprd_host->pinctrl)) {
589 sprd_host->pins_uhs =
590 pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs");
591 if (IS_ERR(sprd_host->pins_uhs)) {
592 ret = PTR_ERR(sprd_host->pins_uhs);
593 goto pltfm_free;
594 }
595
596 sprd_host->pins_default =
597 pinctrl_lookup_state(sprd_host->pinctrl, "default");
598 if (IS_ERR(sprd_host->pins_default)) {
599 ret = PTR_ERR(sprd_host->pins_default);
600 goto pltfm_free;
601 }
602 }
603
604 clk = devm_clk_get(&pdev->dev, "sdio");
605 if (IS_ERR(clk)) {
606 ret = PTR_ERR(clk);
607 goto pltfm_free;
608 }
609 sprd_host->clk_sdio = clk;
610 sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio);
611 if (!sprd_host->base_rate)
612 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE;
613
614 clk = devm_clk_get(&pdev->dev, "enable");
615 if (IS_ERR(clk)) {
616 ret = PTR_ERR(clk);
617 goto pltfm_free;
618 }
619 sprd_host->clk_enable = clk;
620
621 clk = devm_clk_get(&pdev->dev, "2x_enable");
622 if (!IS_ERR(clk))
623 sprd_host->clk_2x_enable = clk;
624
625 ret = clk_prepare_enable(sprd_host->clk_sdio);
626 if (ret)
627 goto pltfm_free;
628
629 ret = clk_prepare_enable(sprd_host->clk_enable);
630 if (ret)
631 goto clk_disable;
632
633 ret = clk_prepare_enable(sprd_host->clk_2x_enable);
634 if (ret)
635 goto clk_disable2;
636
637 sdhci_sprd_init_config(host);
638 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
639 sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >>
640 SDHCI_VENDOR_VER_SHIFT);
641
642 pm_runtime_get_noresume(&pdev->dev);
643 pm_runtime_set_active(&pdev->dev);
644 pm_runtime_enable(&pdev->dev);
645 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
646 pm_runtime_use_autosuspend(&pdev->dev);
647 pm_suspend_ignore_children(&pdev->dev, 1);
648
649 sdhci_enable_v4_mode(host);
650
651 /*
652 * Supply the existing CAPS, but clear the UHS-I modes. This
653 * will allow these modes to be specified only by device
654 * tree properties through mmc_of_parse().
655 */
656 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
657 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
658 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
659 SDHCI_SUPPORT_DDR50);
660
661 ret = sdhci_setup_host(host);
662 if (ret)
663 goto pm_runtime_disable;
664
665 sprd_host->flags = host->flags;
666
667 hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
668 if (!hsq) {
669 ret = -ENOMEM;
670 goto err_cleanup_host;
671 }
672
673 ret = mmc_hsq_init(hsq, host->mmc);
674 if (ret)
675 goto err_cleanup_host;
676
677 ret = __sdhci_add_host(host);
678 if (ret)
679 goto err_cleanup_host;
680
681 pm_runtime_mark_last_busy(&pdev->dev);
682 pm_runtime_put_autosuspend(&pdev->dev);
683
684 return 0;
685
686err_cleanup_host:
687 sdhci_cleanup_host(host);
688
689pm_runtime_disable:
690 pm_runtime_put_noidle(&pdev->dev);
691 pm_runtime_disable(&pdev->dev);
692 pm_runtime_set_suspended(&pdev->dev);
693
694 clk_disable_unprepare(sprd_host->clk_2x_enable);
695
696clk_disable2:
697 clk_disable_unprepare(sprd_host->clk_enable);
698
699clk_disable:
700 clk_disable_unprepare(sprd_host->clk_sdio);
701
702pltfm_free:
703 sdhci_pltfm_free(pdev);
704 return ret;
705}
706
707static int sdhci_sprd_remove(struct platform_device *pdev)
708{
709 struct sdhci_host *host = platform_get_drvdata(pdev);
710 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
711 struct mmc_host *mmc = host->mmc;
712
713 mmc_remove_host(mmc);
714 clk_disable_unprepare(sprd_host->clk_sdio);
715 clk_disable_unprepare(sprd_host->clk_enable);
716 clk_disable_unprepare(sprd_host->clk_2x_enable);
717
718 mmc_free_host(mmc);
719
720 return 0;
721}
722
723static const struct of_device_id sdhci_sprd_of_match[] = {
724 { .compatible = "sprd,sdhci-r11", },
725 { }
726};
727MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match);
728
729#ifdef CONFIG_PM
730static int sdhci_sprd_runtime_suspend(struct device *dev)
731{
732 struct sdhci_host *host = dev_get_drvdata(dev);
733 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
734
735 mmc_hsq_suspend(host->mmc);
736 sdhci_runtime_suspend_host(host);
737
738 clk_disable_unprepare(sprd_host->clk_sdio);
739 clk_disable_unprepare(sprd_host->clk_enable);
740 clk_disable_unprepare(sprd_host->clk_2x_enable);
741
742 return 0;
743}
744
745static int sdhci_sprd_runtime_resume(struct device *dev)
746{
747 struct sdhci_host *host = dev_get_drvdata(dev);
748 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
749 int ret;
750
751 ret = clk_prepare_enable(sprd_host->clk_2x_enable);
752 if (ret)
753 return ret;
754
755 ret = clk_prepare_enable(sprd_host->clk_enable);
756 if (ret)
757 goto clk_2x_disable;
758
759 ret = clk_prepare_enable(sprd_host->clk_sdio);
760 if (ret)
761 goto clk_disable;
762
763 sdhci_runtime_resume_host(host, 1);
764 mmc_hsq_resume(host->mmc);
765
766 return 0;
767
768clk_disable:
769 clk_disable_unprepare(sprd_host->clk_enable);
770
771clk_2x_disable:
772 clk_disable_unprepare(sprd_host->clk_2x_enable);
773
774 return ret;
775}
776#endif
777
778static const struct dev_pm_ops sdhci_sprd_pm_ops = {
779 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
780 pm_runtime_force_resume)
781 SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend,
782 sdhci_sprd_runtime_resume, NULL)
783};
784
785static struct platform_driver sdhci_sprd_driver = {
786 .probe = sdhci_sprd_probe,
787 .remove = sdhci_sprd_remove,
788 .driver = {
789 .name = "sdhci_sprd_r11",
790 .of_match_table = of_match_ptr(sdhci_sprd_of_match),
791 .pm = &sdhci_sprd_pm_ops,
792 },
793};
794module_platform_driver(sdhci_sprd_driver);
795
796MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver");
797MODULE_LICENSE("GPL v2");
798MODULE_ALIAS("platform:sdhci-sprd-r11");