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1/*
2 * Freescale eSDHC controller driver generics for OF and pltfm.
3 *
4 * Copyright (c) 2007 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 MontaVista Software, Inc.
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <w.sang@pengutronix.de>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
15#define _DRIVERS_MMC_SDHCI_ESDHC_H
16
17/*
18 * Ops and quirks for the Freescale eSDHC controller.
19 */
20
21#define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
22 SDHCI_QUIRK_NO_BUSY_IRQ | \
23 SDHCI_QUIRK_NONSTANDARD_CLOCK | \
24 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
25 SDHCI_QUIRK_PIO_NEEDS_DELAY | \
26 SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
27
28#define ESDHC_SYSTEM_CONTROL 0x2c
29#define ESDHC_CLOCK_MASK 0x0000fff0
30#define ESDHC_PREDIV_SHIFT 8
31#define ESDHC_DIVIDER_SHIFT 4
32#define ESDHC_CLOCK_PEREN 0x00000004
33#define ESDHC_CLOCK_HCKEN 0x00000002
34#define ESDHC_CLOCK_IPGEN 0x00000001
35
36/* pltfm-specific */
37#define ESDHC_HOST_CONTROL_LE 0x20
38
39/*
40 * P2020 interpretation of the SDHCI_HOST_CONTROL register
41 */
42#define ESDHC_CTRL_4BITBUS (0x1 << 1)
43#define ESDHC_CTRL_8BITBUS (0x2 << 1)
44#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
45
46/* OF-specific */
47#define ESDHC_DMA_SYSCTL 0x40c
48#define ESDHC_DMA_SNOOP 0x00000040
49
50#define ESDHC_HOST_CONTROL_RES 0x05
51
52#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Freescale eSDHC controller driver generics for OF and pltfm.
4 *
5 * Copyright (c) 2007 Freescale Semiconductor, Inc.
6 * Copyright (c) 2009 MontaVista Software, Inc.
7 * Copyright (c) 2010 Pengutronix e.K.
8 * Author: Wolfram Sang <kernel@pengutronix.de>
9 */
10
11#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
12#define _DRIVERS_MMC_SDHCI_ESDHC_H
13
14/*
15 * Ops and quirks for the Freescale eSDHC controller.
16 */
17
18#define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
19 SDHCI_QUIRK_32BIT_DMA_ADDR | \
20 SDHCI_QUIRK_NO_BUSY_IRQ | \
21 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
22 SDHCI_QUIRK_PIO_NEEDS_DELAY | \
23 SDHCI_QUIRK_NO_HISPD_BIT)
24
25/* pltfm-specific */
26#define ESDHC_HOST_CONTROL_LE 0x20
27
28/*
29 * eSDHC register definition
30 */
31
32/* Present State Register */
33#define ESDHC_PRSSTAT 0x24
34#define ESDHC_CLOCK_GATE_OFF 0x00000080
35#define ESDHC_CLOCK_STABLE 0x00000008
36
37/* Protocol Control Register */
38#define ESDHC_PROCTL 0x28
39#define ESDHC_VOLT_SEL 0x00000400
40#define ESDHC_CTRL_4BITBUS (0x1 << 1)
41#define ESDHC_CTRL_8BITBUS (0x2 << 1)
42#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
43#define ESDHC_HOST_CONTROL_RES 0x01
44
45/* System Control Register */
46#define ESDHC_SYSTEM_CONTROL 0x2c
47#define ESDHC_CLOCK_MASK 0x0000fff0
48#define ESDHC_PREDIV_SHIFT 8
49#define ESDHC_DIVIDER_SHIFT 4
50#define ESDHC_CLOCK_SDCLKEN 0x00000008
51#define ESDHC_CLOCK_PEREN 0x00000004
52#define ESDHC_CLOCK_HCKEN 0x00000002
53#define ESDHC_CLOCK_IPGEN 0x00000001
54
55/* System Control 2 Register */
56#define ESDHC_SYSTEM_CONTROL_2 0x3c
57#define ESDHC_SMPCLKSEL 0x00800000
58#define ESDHC_EXTN 0x00400000
59
60/* Host Controller Capabilities Register 2 */
61#define ESDHC_CAPABILITIES_1 0x114
62
63/* Tuning Block Control Register */
64#define ESDHC_TBCTL 0x120
65#define ESDHC_HS400_WNDW_ADJUST 0x00000040
66#define ESDHC_HS400_MODE 0x00000010
67#define ESDHC_TB_EN 0x00000004
68#define ESDHC_TB_MODE_MASK 0x00000003
69#define ESDHC_TB_MODE_SW 0x00000003
70#define ESDHC_TB_MODE_3 0x00000002
71
72#define ESDHC_TBSTAT 0x124
73
74#define ESDHC_TBPTR 0x128
75#define ESDHC_WNDW_STRT_PTR_SHIFT 8
76#define ESDHC_WNDW_STRT_PTR_MASK (0x7f << 8)
77#define ESDHC_WNDW_END_PTR_MASK 0x7f
78
79/* SD Clock Control Register */
80#define ESDHC_SDCLKCTL 0x144
81#define ESDHC_LPBK_CLK_SEL 0x80000000
82#define ESDHC_CMD_CLK_CTL 0x00008000
83
84/* SD Timing Control Register */
85#define ESDHC_SDTIMNGCTL 0x148
86#define ESDHC_FLW_CTL_BG 0x00008000
87
88/* DLL Config 0 Register */
89#define ESDHC_DLLCFG0 0x160
90#define ESDHC_DLL_ENABLE 0x80000000
91#define ESDHC_DLL_FREQ_SEL 0x08000000
92
93/* DLL Config 1 Register */
94#define ESDHC_DLLCFG1 0x164
95#define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x80000000
96
97/* DLL Status 0 Register */
98#define ESDHC_DLLSTAT0 0x170
99#define ESDHC_DLL_STS_SLV_LOCK 0x08000000
100
101/* Control Register for DMA transfer */
102#define ESDHC_DMA_SYSCTL 0x40c
103#define ESDHC_PERIPHERAL_CLK_SEL 0x00080000
104#define ESDHC_FLUSH_ASYNC_FIFO 0x00040000
105#define ESDHC_DMA_SNOOP 0x00000040
106
107#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */