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1/*
2 * linux/drivers/mmc/host/omap.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/ioport.h>
18#include <linux/platform_device.h>
19#include <linux/interrupt.h>
20#include <linux/dmaengine.h>
21#include <linux/dma-mapping.h>
22#include <linux/delay.h>
23#include <linux/spinlock.h>
24#include <linux/timer.h>
25#include <linux/of.h>
26#include <linux/omap-dma.h>
27#include <linux/mmc/host.h>
28#include <linux/mmc/card.h>
29#include <linux/mmc/mmc.h>
30#include <linux/clk.h>
31#include <linux/scatterlist.h>
32#include <linux/slab.h>
33#include <linux/platform_data/mmc-omap.h>
34
35
36#define OMAP_MMC_REG_CMD 0x00
37#define OMAP_MMC_REG_ARGL 0x01
38#define OMAP_MMC_REG_ARGH 0x02
39#define OMAP_MMC_REG_CON 0x03
40#define OMAP_MMC_REG_STAT 0x04
41#define OMAP_MMC_REG_IE 0x05
42#define OMAP_MMC_REG_CTO 0x06
43#define OMAP_MMC_REG_DTO 0x07
44#define OMAP_MMC_REG_DATA 0x08
45#define OMAP_MMC_REG_BLEN 0x09
46#define OMAP_MMC_REG_NBLK 0x0a
47#define OMAP_MMC_REG_BUF 0x0b
48#define OMAP_MMC_REG_SDIO 0x0d
49#define OMAP_MMC_REG_REV 0x0f
50#define OMAP_MMC_REG_RSP0 0x10
51#define OMAP_MMC_REG_RSP1 0x11
52#define OMAP_MMC_REG_RSP2 0x12
53#define OMAP_MMC_REG_RSP3 0x13
54#define OMAP_MMC_REG_RSP4 0x14
55#define OMAP_MMC_REG_RSP5 0x15
56#define OMAP_MMC_REG_RSP6 0x16
57#define OMAP_MMC_REG_RSP7 0x17
58#define OMAP_MMC_REG_IOSR 0x18
59#define OMAP_MMC_REG_SYSC 0x19
60#define OMAP_MMC_REG_SYSS 0x1a
61
62#define OMAP_MMC_STAT_CARD_ERR (1 << 14)
63#define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
64#define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
65#define OMAP_MMC_STAT_A_EMPTY (1 << 11)
66#define OMAP_MMC_STAT_A_FULL (1 << 10)
67#define OMAP_MMC_STAT_CMD_CRC (1 << 8)
68#define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
69#define OMAP_MMC_STAT_DATA_CRC (1 << 6)
70#define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
71#define OMAP_MMC_STAT_END_BUSY (1 << 4)
72#define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
73#define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
74#define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
75
76#define mmc_omap7xx() (host->features & MMC_OMAP7XX)
77#define mmc_omap15xx() (host->features & MMC_OMAP15XX)
78#define mmc_omap16xx() (host->features & MMC_OMAP16XX)
79#define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
80#define mmc_omap1() (host->features & MMC_OMAP1_MASK)
81#define mmc_omap2() (!mmc_omap1())
82
83#define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
84#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
85#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
86
87/*
88 * Command types
89 */
90#define OMAP_MMC_CMDTYPE_BC 0
91#define OMAP_MMC_CMDTYPE_BCR 1
92#define OMAP_MMC_CMDTYPE_AC 2
93#define OMAP_MMC_CMDTYPE_ADTC 3
94
95#define DRIVER_NAME "mmci-omap"
96
97/* Specifies how often in millisecs to poll for card status changes
98 * when the cover switch is open */
99#define OMAP_MMC_COVER_POLL_DELAY 500
100
101struct mmc_omap_host;
102
103struct mmc_omap_slot {
104 int id;
105 unsigned int vdd;
106 u16 saved_con;
107 u16 bus_mode;
108 unsigned int fclk_freq;
109
110 struct tasklet_struct cover_tasklet;
111 struct timer_list cover_timer;
112 unsigned cover_open;
113
114 struct mmc_request *mrq;
115 struct mmc_omap_host *host;
116 struct mmc_host *mmc;
117 struct omap_mmc_slot_data *pdata;
118};
119
120struct mmc_omap_host {
121 int initialized;
122 struct mmc_request * mrq;
123 struct mmc_command * cmd;
124 struct mmc_data * data;
125 struct mmc_host * mmc;
126 struct device * dev;
127 unsigned char id; /* 16xx chips have 2 MMC blocks */
128 struct clk * iclk;
129 struct clk * fclk;
130 struct dma_chan *dma_rx;
131 u32 dma_rx_burst;
132 struct dma_chan *dma_tx;
133 u32 dma_tx_burst;
134 void __iomem *virt_base;
135 unsigned int phys_base;
136 int irq;
137 unsigned char bus_mode;
138 unsigned int reg_shift;
139
140 struct work_struct cmd_abort_work;
141 unsigned abort:1;
142 struct timer_list cmd_abort_timer;
143
144 struct work_struct slot_release_work;
145 struct mmc_omap_slot *next_slot;
146 struct work_struct send_stop_work;
147 struct mmc_data *stop_data;
148
149 unsigned int sg_len;
150 int sg_idx;
151 u16 * buffer;
152 u32 buffer_bytes_left;
153 u32 total_bytes_left;
154
155 unsigned features;
156 unsigned brs_received:1, dma_done:1;
157 unsigned dma_in_use:1;
158 spinlock_t dma_lock;
159
160 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
161 struct mmc_omap_slot *current_slot;
162 spinlock_t slot_lock;
163 wait_queue_head_t slot_wq;
164 int nr_slots;
165
166 struct timer_list clk_timer;
167 spinlock_t clk_lock; /* for changing enabled state */
168 unsigned int fclk_enabled:1;
169 struct workqueue_struct *mmc_omap_wq;
170
171 struct omap_mmc_platform_data *pdata;
172};
173
174
175static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
176{
177 unsigned long tick_ns;
178
179 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
180 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
181 ndelay(8 * tick_ns);
182 }
183}
184
185static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
186{
187 unsigned long flags;
188
189 spin_lock_irqsave(&host->clk_lock, flags);
190 if (host->fclk_enabled != enable) {
191 host->fclk_enabled = enable;
192 if (enable)
193 clk_enable(host->fclk);
194 else
195 clk_disable(host->fclk);
196 }
197 spin_unlock_irqrestore(&host->clk_lock, flags);
198}
199
200static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
201{
202 struct mmc_omap_host *host = slot->host;
203 unsigned long flags;
204
205 if (claimed)
206 goto no_claim;
207 spin_lock_irqsave(&host->slot_lock, flags);
208 while (host->mmc != NULL) {
209 spin_unlock_irqrestore(&host->slot_lock, flags);
210 wait_event(host->slot_wq, host->mmc == NULL);
211 spin_lock_irqsave(&host->slot_lock, flags);
212 }
213 host->mmc = slot->mmc;
214 spin_unlock_irqrestore(&host->slot_lock, flags);
215no_claim:
216 del_timer(&host->clk_timer);
217 if (host->current_slot != slot || !claimed)
218 mmc_omap_fclk_offdelay(host->current_slot);
219
220 if (host->current_slot != slot) {
221 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
222 if (host->pdata->switch_slot != NULL)
223 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
224 host->current_slot = slot;
225 }
226
227 if (claimed) {
228 mmc_omap_fclk_enable(host, 1);
229
230 /* Doing the dummy read here seems to work around some bug
231 * at least in OMAP24xx silicon where the command would not
232 * start after writing the CMD register. Sigh. */
233 OMAP_MMC_READ(host, CON);
234
235 OMAP_MMC_WRITE(host, CON, slot->saved_con);
236 } else
237 mmc_omap_fclk_enable(host, 0);
238}
239
240static void mmc_omap_start_request(struct mmc_omap_host *host,
241 struct mmc_request *req);
242
243static void mmc_omap_slot_release_work(struct work_struct *work)
244{
245 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
246 slot_release_work);
247 struct mmc_omap_slot *next_slot = host->next_slot;
248 struct mmc_request *rq;
249
250 host->next_slot = NULL;
251 mmc_omap_select_slot(next_slot, 1);
252
253 rq = next_slot->mrq;
254 next_slot->mrq = NULL;
255 mmc_omap_start_request(host, rq);
256}
257
258static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
259{
260 struct mmc_omap_host *host = slot->host;
261 unsigned long flags;
262 int i;
263
264 BUG_ON(slot == NULL || host->mmc == NULL);
265
266 if (clk_enabled)
267 /* Keeps clock running for at least 8 cycles on valid freq */
268 mod_timer(&host->clk_timer, jiffies + HZ/10);
269 else {
270 del_timer(&host->clk_timer);
271 mmc_omap_fclk_offdelay(slot);
272 mmc_omap_fclk_enable(host, 0);
273 }
274
275 spin_lock_irqsave(&host->slot_lock, flags);
276 /* Check for any pending requests */
277 for (i = 0; i < host->nr_slots; i++) {
278 struct mmc_omap_slot *new_slot;
279
280 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
281 continue;
282
283 BUG_ON(host->next_slot != NULL);
284 new_slot = host->slots[i];
285 /* The current slot should not have a request in queue */
286 BUG_ON(new_slot == host->current_slot);
287
288 host->next_slot = new_slot;
289 host->mmc = new_slot->mmc;
290 spin_unlock_irqrestore(&host->slot_lock, flags);
291 queue_work(host->mmc_omap_wq, &host->slot_release_work);
292 return;
293 }
294
295 host->mmc = NULL;
296 wake_up(&host->slot_wq);
297 spin_unlock_irqrestore(&host->slot_lock, flags);
298}
299
300static inline
301int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
302{
303 if (slot->pdata->get_cover_state)
304 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
305 slot->id);
306 return 0;
307}
308
309static ssize_t
310mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
311 char *buf)
312{
313 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
314 struct mmc_omap_slot *slot = mmc_priv(mmc);
315
316 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
317 "closed");
318}
319
320static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
321
322static ssize_t
323mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
324 char *buf)
325{
326 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
327 struct mmc_omap_slot *slot = mmc_priv(mmc);
328
329 return sprintf(buf, "%s\n", slot->pdata->name);
330}
331
332static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
333
334static void
335mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
336{
337 u32 cmdreg;
338 u32 resptype;
339 u32 cmdtype;
340 u16 irq_mask;
341
342 host->cmd = cmd;
343
344 resptype = 0;
345 cmdtype = 0;
346
347 /* Our hardware needs to know exact type */
348 switch (mmc_resp_type(cmd)) {
349 case MMC_RSP_NONE:
350 break;
351 case MMC_RSP_R1:
352 case MMC_RSP_R1B:
353 /* resp 1, 1b, 6, 7 */
354 resptype = 1;
355 break;
356 case MMC_RSP_R2:
357 resptype = 2;
358 break;
359 case MMC_RSP_R3:
360 resptype = 3;
361 break;
362 default:
363 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
364 break;
365 }
366
367 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
368 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
369 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
370 cmdtype = OMAP_MMC_CMDTYPE_BC;
371 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
372 cmdtype = OMAP_MMC_CMDTYPE_BCR;
373 } else {
374 cmdtype = OMAP_MMC_CMDTYPE_AC;
375 }
376
377 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
378
379 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
380 cmdreg |= 1 << 6;
381
382 if (cmd->flags & MMC_RSP_BUSY)
383 cmdreg |= 1 << 11;
384
385 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
386 cmdreg |= 1 << 15;
387
388 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
389
390 OMAP_MMC_WRITE(host, CTO, 200);
391 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
392 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
393 irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
394 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
395 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
396 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
397 OMAP_MMC_STAT_END_OF_DATA;
398 if (cmd->opcode == MMC_ERASE)
399 irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;
400 OMAP_MMC_WRITE(host, IE, irq_mask);
401 OMAP_MMC_WRITE(host, CMD, cmdreg);
402}
403
404static void
405mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
406 int abort)
407{
408 enum dma_data_direction dma_data_dir;
409 struct device *dev = mmc_dev(host->mmc);
410 struct dma_chan *c;
411
412 if (data->flags & MMC_DATA_WRITE) {
413 dma_data_dir = DMA_TO_DEVICE;
414 c = host->dma_tx;
415 } else {
416 dma_data_dir = DMA_FROM_DEVICE;
417 c = host->dma_rx;
418 }
419 if (c) {
420 if (data->error) {
421 dmaengine_terminate_all(c);
422 /* Claim nothing transferred on error... */
423 data->bytes_xfered = 0;
424 }
425 dev = c->device->dev;
426 }
427 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
428}
429
430static void mmc_omap_send_stop_work(struct work_struct *work)
431{
432 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
433 send_stop_work);
434 struct mmc_omap_slot *slot = host->current_slot;
435 struct mmc_data *data = host->stop_data;
436 unsigned long tick_ns;
437
438 tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
439 ndelay(8*tick_ns);
440
441 mmc_omap_start_command(host, data->stop);
442}
443
444static void
445mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
446{
447 if (host->dma_in_use)
448 mmc_omap_release_dma(host, data, data->error);
449
450 host->data = NULL;
451 host->sg_len = 0;
452
453 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
454 * dozens of requests until the card finishes writing data.
455 * It'd be cheaper to just wait till an EOFB interrupt arrives...
456 */
457
458 if (!data->stop) {
459 struct mmc_host *mmc;
460
461 host->mrq = NULL;
462 mmc = host->mmc;
463 mmc_omap_release_slot(host->current_slot, 1);
464 mmc_request_done(mmc, data->mrq);
465 return;
466 }
467
468 host->stop_data = data;
469 queue_work(host->mmc_omap_wq, &host->send_stop_work);
470}
471
472static void
473mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
474{
475 struct mmc_omap_slot *slot = host->current_slot;
476 unsigned int restarts, passes, timeout;
477 u16 stat = 0;
478
479 /* Sending abort takes 80 clocks. Have some extra and round up */
480 timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
481 restarts = 0;
482 while (restarts < maxloops) {
483 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
484 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
485
486 passes = 0;
487 while (passes < timeout) {
488 stat = OMAP_MMC_READ(host, STAT);
489 if (stat & OMAP_MMC_STAT_END_OF_CMD)
490 goto out;
491 udelay(1);
492 passes++;
493 }
494
495 restarts++;
496 }
497out:
498 OMAP_MMC_WRITE(host, STAT, stat);
499}
500
501static void
502mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
503{
504 if (host->dma_in_use)
505 mmc_omap_release_dma(host, data, 1);
506
507 host->data = NULL;
508 host->sg_len = 0;
509
510 mmc_omap_send_abort(host, 10000);
511}
512
513static void
514mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
515{
516 unsigned long flags;
517 int done;
518
519 if (!host->dma_in_use) {
520 mmc_omap_xfer_done(host, data);
521 return;
522 }
523 done = 0;
524 spin_lock_irqsave(&host->dma_lock, flags);
525 if (host->dma_done)
526 done = 1;
527 else
528 host->brs_received = 1;
529 spin_unlock_irqrestore(&host->dma_lock, flags);
530 if (done)
531 mmc_omap_xfer_done(host, data);
532}
533
534static void
535mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
536{
537 unsigned long flags;
538 int done;
539
540 done = 0;
541 spin_lock_irqsave(&host->dma_lock, flags);
542 if (host->brs_received)
543 done = 1;
544 else
545 host->dma_done = 1;
546 spin_unlock_irqrestore(&host->dma_lock, flags);
547 if (done)
548 mmc_omap_xfer_done(host, data);
549}
550
551static void
552mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
553{
554 host->cmd = NULL;
555
556 del_timer(&host->cmd_abort_timer);
557
558 if (cmd->flags & MMC_RSP_PRESENT) {
559 if (cmd->flags & MMC_RSP_136) {
560 /* response type 2 */
561 cmd->resp[3] =
562 OMAP_MMC_READ(host, RSP0) |
563 (OMAP_MMC_READ(host, RSP1) << 16);
564 cmd->resp[2] =
565 OMAP_MMC_READ(host, RSP2) |
566 (OMAP_MMC_READ(host, RSP3) << 16);
567 cmd->resp[1] =
568 OMAP_MMC_READ(host, RSP4) |
569 (OMAP_MMC_READ(host, RSP5) << 16);
570 cmd->resp[0] =
571 OMAP_MMC_READ(host, RSP6) |
572 (OMAP_MMC_READ(host, RSP7) << 16);
573 } else {
574 /* response types 1, 1b, 3, 4, 5, 6 */
575 cmd->resp[0] =
576 OMAP_MMC_READ(host, RSP6) |
577 (OMAP_MMC_READ(host, RSP7) << 16);
578 }
579 }
580
581 if (host->data == NULL || cmd->error) {
582 struct mmc_host *mmc;
583
584 if (host->data != NULL)
585 mmc_omap_abort_xfer(host, host->data);
586 host->mrq = NULL;
587 mmc = host->mmc;
588 mmc_omap_release_slot(host->current_slot, 1);
589 mmc_request_done(mmc, cmd->mrq);
590 }
591}
592
593/*
594 * Abort stuck command. Can occur when card is removed while it is being
595 * read.
596 */
597static void mmc_omap_abort_command(struct work_struct *work)
598{
599 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
600 cmd_abort_work);
601 BUG_ON(!host->cmd);
602
603 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
604 host->cmd->opcode);
605
606 if (host->cmd->error == 0)
607 host->cmd->error = -ETIMEDOUT;
608
609 if (host->data == NULL) {
610 struct mmc_command *cmd;
611 struct mmc_host *mmc;
612
613 cmd = host->cmd;
614 host->cmd = NULL;
615 mmc_omap_send_abort(host, 10000);
616
617 host->mrq = NULL;
618 mmc = host->mmc;
619 mmc_omap_release_slot(host->current_slot, 1);
620 mmc_request_done(mmc, cmd->mrq);
621 } else
622 mmc_omap_cmd_done(host, host->cmd);
623
624 host->abort = 0;
625 enable_irq(host->irq);
626}
627
628static void
629mmc_omap_cmd_timer(unsigned long data)
630{
631 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
632 unsigned long flags;
633
634 spin_lock_irqsave(&host->slot_lock, flags);
635 if (host->cmd != NULL && !host->abort) {
636 OMAP_MMC_WRITE(host, IE, 0);
637 disable_irq(host->irq);
638 host->abort = 1;
639 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
640 }
641 spin_unlock_irqrestore(&host->slot_lock, flags);
642}
643
644/* PIO only */
645static void
646mmc_omap_sg_to_buf(struct mmc_omap_host *host)
647{
648 struct scatterlist *sg;
649
650 sg = host->data->sg + host->sg_idx;
651 host->buffer_bytes_left = sg->length;
652 host->buffer = sg_virt(sg);
653 if (host->buffer_bytes_left > host->total_bytes_left)
654 host->buffer_bytes_left = host->total_bytes_left;
655}
656
657static void
658mmc_omap_clk_timer(unsigned long data)
659{
660 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
661
662 mmc_omap_fclk_enable(host, 0);
663}
664
665/* PIO only */
666static void
667mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
668{
669 int n, nwords;
670
671 if (host->buffer_bytes_left == 0) {
672 host->sg_idx++;
673 BUG_ON(host->sg_idx == host->sg_len);
674 mmc_omap_sg_to_buf(host);
675 }
676 n = 64;
677 if (n > host->buffer_bytes_left)
678 n = host->buffer_bytes_left;
679
680 nwords = n / 2;
681 nwords += n & 1; /* handle odd number of bytes to transfer */
682
683 host->buffer_bytes_left -= n;
684 host->total_bytes_left -= n;
685 host->data->bytes_xfered += n;
686
687 if (write) {
688 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
689 host->buffer, nwords);
690 } else {
691 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
692 host->buffer, nwords);
693 }
694
695 host->buffer += nwords;
696}
697
698#ifdef CONFIG_MMC_DEBUG
699static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
700{
701 static const char *mmc_omap_status_bits[] = {
702 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
703 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
704 };
705 int i;
706 char res[64], *buf = res;
707
708 buf += sprintf(buf, "MMC IRQ 0x%x:", status);
709
710 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
711 if (status & (1 << i))
712 buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
713 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
714}
715#else
716static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
717{
718}
719#endif
720
721
722static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
723{
724 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
725 u16 status;
726 int end_command;
727 int end_transfer;
728 int transfer_error, cmd_error;
729
730 if (host->cmd == NULL && host->data == NULL) {
731 status = OMAP_MMC_READ(host, STAT);
732 dev_info(mmc_dev(host->slots[0]->mmc),
733 "Spurious IRQ 0x%04x\n", status);
734 if (status != 0) {
735 OMAP_MMC_WRITE(host, STAT, status);
736 OMAP_MMC_WRITE(host, IE, 0);
737 }
738 return IRQ_HANDLED;
739 }
740
741 end_command = 0;
742 end_transfer = 0;
743 transfer_error = 0;
744 cmd_error = 0;
745
746 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
747 int cmd;
748
749 OMAP_MMC_WRITE(host, STAT, status);
750 if (host->cmd != NULL)
751 cmd = host->cmd->opcode;
752 else
753 cmd = -1;
754 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
755 status, cmd);
756 mmc_omap_report_irq(host, status);
757
758 if (host->total_bytes_left) {
759 if ((status & OMAP_MMC_STAT_A_FULL) ||
760 (status & OMAP_MMC_STAT_END_OF_DATA))
761 mmc_omap_xfer_data(host, 0);
762 if (status & OMAP_MMC_STAT_A_EMPTY)
763 mmc_omap_xfer_data(host, 1);
764 }
765
766 if (status & OMAP_MMC_STAT_END_OF_DATA)
767 end_transfer = 1;
768
769 if (status & OMAP_MMC_STAT_DATA_TOUT) {
770 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
771 cmd);
772 if (host->data) {
773 host->data->error = -ETIMEDOUT;
774 transfer_error = 1;
775 }
776 }
777
778 if (status & OMAP_MMC_STAT_DATA_CRC) {
779 if (host->data) {
780 host->data->error = -EILSEQ;
781 dev_dbg(mmc_dev(host->mmc),
782 "data CRC error, bytes left %d\n",
783 host->total_bytes_left);
784 transfer_error = 1;
785 } else {
786 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
787 }
788 }
789
790 if (status & OMAP_MMC_STAT_CMD_TOUT) {
791 /* Timeouts are routine with some commands */
792 if (host->cmd) {
793 struct mmc_omap_slot *slot =
794 host->current_slot;
795 if (slot == NULL ||
796 !mmc_omap_cover_is_open(slot))
797 dev_err(mmc_dev(host->mmc),
798 "command timeout (CMD%d)\n",
799 cmd);
800 host->cmd->error = -ETIMEDOUT;
801 end_command = 1;
802 cmd_error = 1;
803 }
804 }
805
806 if (status & OMAP_MMC_STAT_CMD_CRC) {
807 if (host->cmd) {
808 dev_err(mmc_dev(host->mmc),
809 "command CRC error (CMD%d, arg 0x%08x)\n",
810 cmd, host->cmd->arg);
811 host->cmd->error = -EILSEQ;
812 end_command = 1;
813 cmd_error = 1;
814 } else
815 dev_err(mmc_dev(host->mmc),
816 "command CRC error without cmd?\n");
817 }
818
819 if (status & OMAP_MMC_STAT_CARD_ERR) {
820 dev_dbg(mmc_dev(host->mmc),
821 "ignoring card status error (CMD%d)\n",
822 cmd);
823 end_command = 1;
824 }
825
826 /*
827 * NOTE: On 1610 the END_OF_CMD may come too early when
828 * starting a write
829 */
830 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
831 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
832 end_command = 1;
833 }
834 }
835
836 if (cmd_error && host->data) {
837 del_timer(&host->cmd_abort_timer);
838 host->abort = 1;
839 OMAP_MMC_WRITE(host, IE, 0);
840 disable_irq_nosync(host->irq);
841 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
842 return IRQ_HANDLED;
843 }
844
845 if (end_command && host->cmd)
846 mmc_omap_cmd_done(host, host->cmd);
847 if (host->data != NULL) {
848 if (transfer_error)
849 mmc_omap_xfer_done(host, host->data);
850 else if (end_transfer)
851 mmc_omap_end_of_data(host, host->data);
852 }
853
854 return IRQ_HANDLED;
855}
856
857void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
858{
859 int cover_open;
860 struct mmc_omap_host *host = dev_get_drvdata(dev);
861 struct mmc_omap_slot *slot = host->slots[num];
862
863 BUG_ON(num >= host->nr_slots);
864
865 /* Other subsystems can call in here before we're initialised. */
866 if (host->nr_slots == 0 || !host->slots[num])
867 return;
868
869 cover_open = mmc_omap_cover_is_open(slot);
870 if (cover_open != slot->cover_open) {
871 slot->cover_open = cover_open;
872 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
873 }
874
875 tasklet_hi_schedule(&slot->cover_tasklet);
876}
877
878static void mmc_omap_cover_timer(unsigned long arg)
879{
880 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
881 tasklet_schedule(&slot->cover_tasklet);
882}
883
884static void mmc_omap_cover_handler(unsigned long param)
885{
886 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
887 int cover_open = mmc_omap_cover_is_open(slot);
888
889 mmc_detect_change(slot->mmc, 0);
890 if (!cover_open)
891 return;
892
893 /*
894 * If no card is inserted, we postpone polling until
895 * the cover has been closed.
896 */
897 if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
898 return;
899
900 mod_timer(&slot->cover_timer,
901 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
902}
903
904static void mmc_omap_dma_callback(void *priv)
905{
906 struct mmc_omap_host *host = priv;
907 struct mmc_data *data = host->data;
908
909 /* If we got to the end of DMA, assume everything went well */
910 data->bytes_xfered += data->blocks * data->blksz;
911
912 mmc_omap_dma_done(host, data);
913}
914
915static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
916{
917 u16 reg;
918
919 reg = OMAP_MMC_READ(host, SDIO);
920 reg &= ~(1 << 5);
921 OMAP_MMC_WRITE(host, SDIO, reg);
922 /* Set maximum timeout */
923 OMAP_MMC_WRITE(host, CTO, 0xff);
924}
925
926static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
927{
928 unsigned int timeout, cycle_ns;
929 u16 reg;
930
931 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
932 timeout = req->data->timeout_ns / cycle_ns;
933 timeout += req->data->timeout_clks;
934
935 /* Check if we need to use timeout multiplier register */
936 reg = OMAP_MMC_READ(host, SDIO);
937 if (timeout > 0xffff) {
938 reg |= (1 << 5);
939 timeout /= 1024;
940 } else
941 reg &= ~(1 << 5);
942 OMAP_MMC_WRITE(host, SDIO, reg);
943 OMAP_MMC_WRITE(host, DTO, timeout);
944}
945
946static void
947mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
948{
949 struct mmc_data *data = req->data;
950 int i, use_dma = 1, block_size;
951 unsigned sg_len;
952
953 host->data = data;
954 if (data == NULL) {
955 OMAP_MMC_WRITE(host, BLEN, 0);
956 OMAP_MMC_WRITE(host, NBLK, 0);
957 OMAP_MMC_WRITE(host, BUF, 0);
958 host->dma_in_use = 0;
959 set_cmd_timeout(host, req);
960 return;
961 }
962
963 block_size = data->blksz;
964
965 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
966 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
967 set_data_timeout(host, req);
968
969 /* cope with calling layer confusion; it issues "single
970 * block" writes using multi-block scatterlists.
971 */
972 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
973
974 /* Only do DMA for entire blocks */
975 for (i = 0; i < sg_len; i++) {
976 if ((data->sg[i].length % block_size) != 0) {
977 use_dma = 0;
978 break;
979 }
980 }
981
982 host->sg_idx = 0;
983 if (use_dma) {
984 enum dma_data_direction dma_data_dir;
985 struct dma_async_tx_descriptor *tx;
986 struct dma_chan *c;
987 u32 burst, *bp;
988 u16 buf;
989
990 /*
991 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
992 * and 24xx. Use 16 or 32 word frames when the
993 * blocksize is at least that large. Blocksize is
994 * usually 512 bytes; but not for some SD reads.
995 */
996 burst = mmc_omap15xx() ? 32 : 64;
997 if (burst > data->blksz)
998 burst = data->blksz;
999
1000 burst >>= 1;
1001
1002 if (data->flags & MMC_DATA_WRITE) {
1003 c = host->dma_tx;
1004 bp = &host->dma_tx_burst;
1005 buf = 0x0f80 | (burst - 1) << 0;
1006 dma_data_dir = DMA_TO_DEVICE;
1007 } else {
1008 c = host->dma_rx;
1009 bp = &host->dma_rx_burst;
1010 buf = 0x800f | (burst - 1) << 8;
1011 dma_data_dir = DMA_FROM_DEVICE;
1012 }
1013
1014 if (!c)
1015 goto use_pio;
1016
1017 /* Only reconfigure if we have a different burst size */
1018 if (*bp != burst) {
1019 struct dma_slave_config cfg;
1020
1021 cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1022 cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1023 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1024 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1025 cfg.src_maxburst = burst;
1026 cfg.dst_maxburst = burst;
1027
1028 if (dmaengine_slave_config(c, &cfg))
1029 goto use_pio;
1030
1031 *bp = burst;
1032 }
1033
1034 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1035 dma_data_dir);
1036 if (host->sg_len == 0)
1037 goto use_pio;
1038
1039 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1040 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1041 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1042 if (!tx)
1043 goto use_pio;
1044
1045 OMAP_MMC_WRITE(host, BUF, buf);
1046
1047 tx->callback = mmc_omap_dma_callback;
1048 tx->callback_param = host;
1049 dmaengine_submit(tx);
1050 host->brs_received = 0;
1051 host->dma_done = 0;
1052 host->dma_in_use = 1;
1053 return;
1054 }
1055 use_pio:
1056
1057 /* Revert to PIO? */
1058 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1059 host->total_bytes_left = data->blocks * block_size;
1060 host->sg_len = sg_len;
1061 mmc_omap_sg_to_buf(host);
1062 host->dma_in_use = 0;
1063}
1064
1065static void mmc_omap_start_request(struct mmc_omap_host *host,
1066 struct mmc_request *req)
1067{
1068 BUG_ON(host->mrq != NULL);
1069
1070 host->mrq = req;
1071
1072 /* only touch fifo AFTER the controller readies it */
1073 mmc_omap_prepare_data(host, req);
1074 mmc_omap_start_command(host, req->cmd);
1075 if (host->dma_in_use) {
1076 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1077 host->dma_tx : host->dma_rx;
1078
1079 dma_async_issue_pending(c);
1080 }
1081}
1082
1083static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1084{
1085 struct mmc_omap_slot *slot = mmc_priv(mmc);
1086 struct mmc_omap_host *host = slot->host;
1087 unsigned long flags;
1088
1089 spin_lock_irqsave(&host->slot_lock, flags);
1090 if (host->mmc != NULL) {
1091 BUG_ON(slot->mrq != NULL);
1092 slot->mrq = req;
1093 spin_unlock_irqrestore(&host->slot_lock, flags);
1094 return;
1095 } else
1096 host->mmc = mmc;
1097 spin_unlock_irqrestore(&host->slot_lock, flags);
1098 mmc_omap_select_slot(slot, 1);
1099 mmc_omap_start_request(host, req);
1100}
1101
1102static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1103 int vdd)
1104{
1105 struct mmc_omap_host *host;
1106
1107 host = slot->host;
1108
1109 if (slot->pdata->set_power != NULL)
1110 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1111 vdd);
1112 if (mmc_omap2()) {
1113 u16 w;
1114
1115 if (power_on) {
1116 w = OMAP_MMC_READ(host, CON);
1117 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1118 } else {
1119 w = OMAP_MMC_READ(host, CON);
1120 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1121 }
1122 }
1123}
1124
1125static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1126{
1127 struct mmc_omap_slot *slot = mmc_priv(mmc);
1128 struct mmc_omap_host *host = slot->host;
1129 int func_clk_rate = clk_get_rate(host->fclk);
1130 int dsor;
1131
1132 if (ios->clock == 0)
1133 return 0;
1134
1135 dsor = func_clk_rate / ios->clock;
1136 if (dsor < 1)
1137 dsor = 1;
1138
1139 if (func_clk_rate / dsor > ios->clock)
1140 dsor++;
1141
1142 if (dsor > 250)
1143 dsor = 250;
1144
1145 slot->fclk_freq = func_clk_rate / dsor;
1146
1147 if (ios->bus_width == MMC_BUS_WIDTH_4)
1148 dsor |= 1 << 15;
1149
1150 return dsor;
1151}
1152
1153static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1154{
1155 struct mmc_omap_slot *slot = mmc_priv(mmc);
1156 struct mmc_omap_host *host = slot->host;
1157 int i, dsor;
1158 int clk_enabled;
1159
1160 mmc_omap_select_slot(slot, 0);
1161
1162 dsor = mmc_omap_calc_divisor(mmc, ios);
1163
1164 if (ios->vdd != slot->vdd)
1165 slot->vdd = ios->vdd;
1166
1167 clk_enabled = 0;
1168 switch (ios->power_mode) {
1169 case MMC_POWER_OFF:
1170 mmc_omap_set_power(slot, 0, ios->vdd);
1171 break;
1172 case MMC_POWER_UP:
1173 /* Cannot touch dsor yet, just power up MMC */
1174 mmc_omap_set_power(slot, 1, ios->vdd);
1175 goto exit;
1176 case MMC_POWER_ON:
1177 mmc_omap_fclk_enable(host, 1);
1178 clk_enabled = 1;
1179 dsor |= 1 << 11;
1180 break;
1181 }
1182
1183 if (slot->bus_mode != ios->bus_mode) {
1184 if (slot->pdata->set_bus_mode != NULL)
1185 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1186 ios->bus_mode);
1187 slot->bus_mode = ios->bus_mode;
1188 }
1189
1190 /* On insanely high arm_per frequencies something sometimes
1191 * goes somehow out of sync, and the POW bit is not being set,
1192 * which results in the while loop below getting stuck.
1193 * Writing to the CON register twice seems to do the trick. */
1194 for (i = 0; i < 2; i++)
1195 OMAP_MMC_WRITE(host, CON, dsor);
1196 slot->saved_con = dsor;
1197 if (ios->power_mode == MMC_POWER_ON) {
1198 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1199 int usecs = 250;
1200
1201 /* Send clock cycles, poll completion */
1202 OMAP_MMC_WRITE(host, IE, 0);
1203 OMAP_MMC_WRITE(host, STAT, 0xffff);
1204 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1205 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1206 udelay(1);
1207 usecs--;
1208 }
1209 OMAP_MMC_WRITE(host, STAT, 1);
1210 }
1211
1212exit:
1213 mmc_omap_release_slot(slot, clk_enabled);
1214}
1215
1216static const struct mmc_host_ops mmc_omap_ops = {
1217 .request = mmc_omap_request,
1218 .set_ios = mmc_omap_set_ios,
1219};
1220
1221static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1222{
1223 struct mmc_omap_slot *slot = NULL;
1224 struct mmc_host *mmc;
1225 int r;
1226
1227 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1228 if (mmc == NULL)
1229 return -ENOMEM;
1230
1231 slot = mmc_priv(mmc);
1232 slot->host = host;
1233 slot->mmc = mmc;
1234 slot->id = id;
1235 slot->pdata = &host->pdata->slots[id];
1236
1237 host->slots[id] = slot;
1238
1239 mmc->caps = 0;
1240 if (host->pdata->slots[id].wires >= 4)
1241 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_ERASE;
1242
1243 mmc->ops = &mmc_omap_ops;
1244 mmc->f_min = 400000;
1245
1246 if (mmc_omap2())
1247 mmc->f_max = 48000000;
1248 else
1249 mmc->f_max = 24000000;
1250 if (host->pdata->max_freq)
1251 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1252 mmc->ocr_avail = slot->pdata->ocr_mask;
1253
1254 /* Use scatterlist DMA to reduce per-transfer costs.
1255 * NOTE max_seg_size assumption that small blocks aren't
1256 * normally used (except e.g. for reading SD registers).
1257 */
1258 mmc->max_segs = 32;
1259 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1260 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1261 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1262 mmc->max_seg_size = mmc->max_req_size;
1263
1264 if (slot->pdata->get_cover_state != NULL) {
1265 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1266 (unsigned long)slot);
1267 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1268 (unsigned long)slot);
1269 }
1270
1271 r = mmc_add_host(mmc);
1272 if (r < 0)
1273 goto err_remove_host;
1274
1275 if (slot->pdata->name != NULL) {
1276 r = device_create_file(&mmc->class_dev,
1277 &dev_attr_slot_name);
1278 if (r < 0)
1279 goto err_remove_host;
1280 }
1281
1282 if (slot->pdata->get_cover_state != NULL) {
1283 r = device_create_file(&mmc->class_dev,
1284 &dev_attr_cover_switch);
1285 if (r < 0)
1286 goto err_remove_slot_name;
1287 tasklet_schedule(&slot->cover_tasklet);
1288 }
1289
1290 return 0;
1291
1292err_remove_slot_name:
1293 if (slot->pdata->name != NULL)
1294 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1295err_remove_host:
1296 mmc_remove_host(mmc);
1297 mmc_free_host(mmc);
1298 return r;
1299}
1300
1301static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1302{
1303 struct mmc_host *mmc = slot->mmc;
1304
1305 if (slot->pdata->name != NULL)
1306 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1307 if (slot->pdata->get_cover_state != NULL)
1308 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1309
1310 tasklet_kill(&slot->cover_tasklet);
1311 del_timer_sync(&slot->cover_timer);
1312 flush_workqueue(slot->host->mmc_omap_wq);
1313
1314 mmc_remove_host(mmc);
1315 mmc_free_host(mmc);
1316}
1317
1318static int mmc_omap_probe(struct platform_device *pdev)
1319{
1320 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1321 struct mmc_omap_host *host = NULL;
1322 struct resource *res;
1323 dma_cap_mask_t mask;
1324 unsigned sig = 0;
1325 int i, ret = 0;
1326 int irq;
1327
1328 if (pdata == NULL) {
1329 dev_err(&pdev->dev, "platform data missing\n");
1330 return -ENXIO;
1331 }
1332 if (pdata->nr_slots == 0) {
1333 dev_err(&pdev->dev, "no slots\n");
1334 return -EPROBE_DEFER;
1335 }
1336
1337 host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),
1338 GFP_KERNEL);
1339 if (host == NULL)
1340 return -ENOMEM;
1341
1342 irq = platform_get_irq(pdev, 0);
1343 if (irq < 0)
1344 return -ENXIO;
1345
1346 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1347 host->virt_base = devm_ioremap_resource(&pdev->dev, res);
1348 if (IS_ERR(host->virt_base))
1349 return PTR_ERR(host->virt_base);
1350
1351 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1352 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1353
1354 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1355 setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1356 (unsigned long) host);
1357
1358 spin_lock_init(&host->clk_lock);
1359 setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1360
1361 spin_lock_init(&host->dma_lock);
1362 spin_lock_init(&host->slot_lock);
1363 init_waitqueue_head(&host->slot_wq);
1364
1365 host->pdata = pdata;
1366 host->features = host->pdata->slots[0].features;
1367 host->dev = &pdev->dev;
1368 platform_set_drvdata(pdev, host);
1369
1370 host->id = pdev->id;
1371 host->irq = irq;
1372 host->phys_base = res->start;
1373 host->iclk = clk_get(&pdev->dev, "ick");
1374 if (IS_ERR(host->iclk))
1375 return PTR_ERR(host->iclk);
1376 clk_enable(host->iclk);
1377
1378 host->fclk = clk_get(&pdev->dev, "fck");
1379 if (IS_ERR(host->fclk)) {
1380 ret = PTR_ERR(host->fclk);
1381 goto err_free_iclk;
1382 }
1383
1384 dma_cap_zero(mask);
1385 dma_cap_set(DMA_SLAVE, mask);
1386
1387 host->dma_tx_burst = -1;
1388 host->dma_rx_burst = -1;
1389
1390 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1391 if (res)
1392 sig = res->start;
1393 host->dma_tx = dma_request_slave_channel_compat(mask,
1394 omap_dma_filter_fn, &sig, &pdev->dev, "tx");
1395 if (!host->dma_tx)
1396 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
1397 sig);
1398
1399 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1400 if (res)
1401 sig = res->start;
1402 host->dma_rx = dma_request_slave_channel_compat(mask,
1403 omap_dma_filter_fn, &sig, &pdev->dev, "rx");
1404 if (!host->dma_rx)
1405 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
1406 sig);
1407
1408 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1409 if (ret)
1410 goto err_free_dma;
1411
1412 if (pdata->init != NULL) {
1413 ret = pdata->init(&pdev->dev);
1414 if (ret < 0)
1415 goto err_free_irq;
1416 }
1417
1418 host->nr_slots = pdata->nr_slots;
1419 host->reg_shift = (mmc_omap7xx() ? 1 : 2);
1420
1421 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1422 if (!host->mmc_omap_wq)
1423 goto err_plat_cleanup;
1424
1425 for (i = 0; i < pdata->nr_slots; i++) {
1426 ret = mmc_omap_new_slot(host, i);
1427 if (ret < 0) {
1428 while (--i >= 0)
1429 mmc_omap_remove_slot(host->slots[i]);
1430
1431 goto err_destroy_wq;
1432 }
1433 }
1434
1435 return 0;
1436
1437err_destroy_wq:
1438 destroy_workqueue(host->mmc_omap_wq);
1439err_plat_cleanup:
1440 if (pdata->cleanup)
1441 pdata->cleanup(&pdev->dev);
1442err_free_irq:
1443 free_irq(host->irq, host);
1444err_free_dma:
1445 if (host->dma_tx)
1446 dma_release_channel(host->dma_tx);
1447 if (host->dma_rx)
1448 dma_release_channel(host->dma_rx);
1449 clk_put(host->fclk);
1450err_free_iclk:
1451 clk_disable(host->iclk);
1452 clk_put(host->iclk);
1453 return ret;
1454}
1455
1456static int mmc_omap_remove(struct platform_device *pdev)
1457{
1458 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1459 int i;
1460
1461 BUG_ON(host == NULL);
1462
1463 for (i = 0; i < host->nr_slots; i++)
1464 mmc_omap_remove_slot(host->slots[i]);
1465
1466 if (host->pdata->cleanup)
1467 host->pdata->cleanup(&pdev->dev);
1468
1469 mmc_omap_fclk_enable(host, 0);
1470 free_irq(host->irq, host);
1471 clk_put(host->fclk);
1472 clk_disable(host->iclk);
1473 clk_put(host->iclk);
1474
1475 if (host->dma_tx)
1476 dma_release_channel(host->dma_tx);
1477 if (host->dma_rx)
1478 dma_release_channel(host->dma_rx);
1479
1480 destroy_workqueue(host->mmc_omap_wq);
1481
1482 return 0;
1483}
1484
1485#if IS_BUILTIN(CONFIG_OF)
1486static const struct of_device_id mmc_omap_match[] = {
1487 { .compatible = "ti,omap2420-mmc", },
1488 { },
1489};
1490#endif
1491
1492static struct platform_driver mmc_omap_driver = {
1493 .probe = mmc_omap_probe,
1494 .remove = mmc_omap_remove,
1495 .driver = {
1496 .name = DRIVER_NAME,
1497 .owner = THIS_MODULE,
1498 .of_match_table = of_match_ptr(mmc_omap_match),
1499 },
1500};
1501
1502module_platform_driver(mmc_omap_driver);
1503MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1504MODULE_LICENSE("GPL");
1505MODULE_ALIAS("platform:" DRIVER_NAME);
1506MODULE_AUTHOR("Juha Yrjölä");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/drivers/mmc/host/omap.c
4 *
5 * Copyright (C) 2004 Nokia Corporation
6 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
7 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
8 * Other hacks (DMA, SD, etc) by David Brownell
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/platform_device.h>
16#include <linux/interrupt.h>
17#include <linux/dmaengine.h>
18#include <linux/dma-mapping.h>
19#include <linux/delay.h>
20#include <linux/spinlock.h>
21#include <linux/timer.h>
22#include <linux/of.h>
23#include <linux/mmc/host.h>
24#include <linux/mmc/card.h>
25#include <linux/mmc/mmc.h>
26#include <linux/clk.h>
27#include <linux/scatterlist.h>
28#include <linux/slab.h>
29#include <linux/platform_data/mmc-omap.h>
30
31
32#define OMAP_MMC_REG_CMD 0x00
33#define OMAP_MMC_REG_ARGL 0x01
34#define OMAP_MMC_REG_ARGH 0x02
35#define OMAP_MMC_REG_CON 0x03
36#define OMAP_MMC_REG_STAT 0x04
37#define OMAP_MMC_REG_IE 0x05
38#define OMAP_MMC_REG_CTO 0x06
39#define OMAP_MMC_REG_DTO 0x07
40#define OMAP_MMC_REG_DATA 0x08
41#define OMAP_MMC_REG_BLEN 0x09
42#define OMAP_MMC_REG_NBLK 0x0a
43#define OMAP_MMC_REG_BUF 0x0b
44#define OMAP_MMC_REG_SDIO 0x0d
45#define OMAP_MMC_REG_REV 0x0f
46#define OMAP_MMC_REG_RSP0 0x10
47#define OMAP_MMC_REG_RSP1 0x11
48#define OMAP_MMC_REG_RSP2 0x12
49#define OMAP_MMC_REG_RSP3 0x13
50#define OMAP_MMC_REG_RSP4 0x14
51#define OMAP_MMC_REG_RSP5 0x15
52#define OMAP_MMC_REG_RSP6 0x16
53#define OMAP_MMC_REG_RSP7 0x17
54#define OMAP_MMC_REG_IOSR 0x18
55#define OMAP_MMC_REG_SYSC 0x19
56#define OMAP_MMC_REG_SYSS 0x1a
57
58#define OMAP_MMC_STAT_CARD_ERR (1 << 14)
59#define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
60#define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
61#define OMAP_MMC_STAT_A_EMPTY (1 << 11)
62#define OMAP_MMC_STAT_A_FULL (1 << 10)
63#define OMAP_MMC_STAT_CMD_CRC (1 << 8)
64#define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
65#define OMAP_MMC_STAT_DATA_CRC (1 << 6)
66#define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
67#define OMAP_MMC_STAT_END_BUSY (1 << 4)
68#define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
69#define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
70#define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
71
72#define mmc_omap7xx() (host->features & MMC_OMAP7XX)
73#define mmc_omap15xx() (host->features & MMC_OMAP15XX)
74#define mmc_omap16xx() (host->features & MMC_OMAP16XX)
75#define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
76#define mmc_omap1() (host->features & MMC_OMAP1_MASK)
77#define mmc_omap2() (!mmc_omap1())
78
79#define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
80#define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
81#define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
82
83/*
84 * Command types
85 */
86#define OMAP_MMC_CMDTYPE_BC 0
87#define OMAP_MMC_CMDTYPE_BCR 1
88#define OMAP_MMC_CMDTYPE_AC 2
89#define OMAP_MMC_CMDTYPE_ADTC 3
90
91#define DRIVER_NAME "mmci-omap"
92
93/* Specifies how often in millisecs to poll for card status changes
94 * when the cover switch is open */
95#define OMAP_MMC_COVER_POLL_DELAY 500
96
97struct mmc_omap_host;
98
99struct mmc_omap_slot {
100 int id;
101 unsigned int vdd;
102 u16 saved_con;
103 u16 bus_mode;
104 u16 power_mode;
105 unsigned int fclk_freq;
106
107 struct tasklet_struct cover_tasklet;
108 struct timer_list cover_timer;
109 unsigned cover_open;
110
111 struct mmc_request *mrq;
112 struct mmc_omap_host *host;
113 struct mmc_host *mmc;
114 struct omap_mmc_slot_data *pdata;
115};
116
117struct mmc_omap_host {
118 int initialized;
119 struct mmc_request * mrq;
120 struct mmc_command * cmd;
121 struct mmc_data * data;
122 struct mmc_host * mmc;
123 struct device * dev;
124 unsigned char id; /* 16xx chips have 2 MMC blocks */
125 struct clk * iclk;
126 struct clk * fclk;
127 struct dma_chan *dma_rx;
128 u32 dma_rx_burst;
129 struct dma_chan *dma_tx;
130 u32 dma_tx_burst;
131 void __iomem *virt_base;
132 unsigned int phys_base;
133 int irq;
134 unsigned char bus_mode;
135 unsigned int reg_shift;
136
137 struct work_struct cmd_abort_work;
138 unsigned abort:1;
139 struct timer_list cmd_abort_timer;
140
141 struct work_struct slot_release_work;
142 struct mmc_omap_slot *next_slot;
143 struct work_struct send_stop_work;
144 struct mmc_data *stop_data;
145
146 unsigned int sg_len;
147 int sg_idx;
148 u16 * buffer;
149 u32 buffer_bytes_left;
150 u32 total_bytes_left;
151
152 unsigned features;
153 unsigned brs_received:1, dma_done:1;
154 unsigned dma_in_use:1;
155 spinlock_t dma_lock;
156
157 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
158 struct mmc_omap_slot *current_slot;
159 spinlock_t slot_lock;
160 wait_queue_head_t slot_wq;
161 int nr_slots;
162
163 struct timer_list clk_timer;
164 spinlock_t clk_lock; /* for changing enabled state */
165 unsigned int fclk_enabled:1;
166 struct workqueue_struct *mmc_omap_wq;
167
168 struct omap_mmc_platform_data *pdata;
169};
170
171
172static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
173{
174 unsigned long tick_ns;
175
176 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
177 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
178 ndelay(8 * tick_ns);
179 }
180}
181
182static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
183{
184 unsigned long flags;
185
186 spin_lock_irqsave(&host->clk_lock, flags);
187 if (host->fclk_enabled != enable) {
188 host->fclk_enabled = enable;
189 if (enable)
190 clk_enable(host->fclk);
191 else
192 clk_disable(host->fclk);
193 }
194 spin_unlock_irqrestore(&host->clk_lock, flags);
195}
196
197static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
198{
199 struct mmc_omap_host *host = slot->host;
200 unsigned long flags;
201
202 if (claimed)
203 goto no_claim;
204 spin_lock_irqsave(&host->slot_lock, flags);
205 while (host->mmc != NULL) {
206 spin_unlock_irqrestore(&host->slot_lock, flags);
207 wait_event(host->slot_wq, host->mmc == NULL);
208 spin_lock_irqsave(&host->slot_lock, flags);
209 }
210 host->mmc = slot->mmc;
211 spin_unlock_irqrestore(&host->slot_lock, flags);
212no_claim:
213 del_timer(&host->clk_timer);
214 if (host->current_slot != slot || !claimed)
215 mmc_omap_fclk_offdelay(host->current_slot);
216
217 if (host->current_slot != slot) {
218 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
219 if (host->pdata->switch_slot != NULL)
220 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
221 host->current_slot = slot;
222 }
223
224 if (claimed) {
225 mmc_omap_fclk_enable(host, 1);
226
227 /* Doing the dummy read here seems to work around some bug
228 * at least in OMAP24xx silicon where the command would not
229 * start after writing the CMD register. Sigh. */
230 OMAP_MMC_READ(host, CON);
231
232 OMAP_MMC_WRITE(host, CON, slot->saved_con);
233 } else
234 mmc_omap_fclk_enable(host, 0);
235}
236
237static void mmc_omap_start_request(struct mmc_omap_host *host,
238 struct mmc_request *req);
239
240static void mmc_omap_slot_release_work(struct work_struct *work)
241{
242 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
243 slot_release_work);
244 struct mmc_omap_slot *next_slot = host->next_slot;
245 struct mmc_request *rq;
246
247 host->next_slot = NULL;
248 mmc_omap_select_slot(next_slot, 1);
249
250 rq = next_slot->mrq;
251 next_slot->mrq = NULL;
252 mmc_omap_start_request(host, rq);
253}
254
255static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
256{
257 struct mmc_omap_host *host = slot->host;
258 unsigned long flags;
259 int i;
260
261 BUG_ON(slot == NULL || host->mmc == NULL);
262
263 if (clk_enabled)
264 /* Keeps clock running for at least 8 cycles on valid freq */
265 mod_timer(&host->clk_timer, jiffies + HZ/10);
266 else {
267 del_timer(&host->clk_timer);
268 mmc_omap_fclk_offdelay(slot);
269 mmc_omap_fclk_enable(host, 0);
270 }
271
272 spin_lock_irqsave(&host->slot_lock, flags);
273 /* Check for any pending requests */
274 for (i = 0; i < host->nr_slots; i++) {
275 struct mmc_omap_slot *new_slot;
276
277 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
278 continue;
279
280 BUG_ON(host->next_slot != NULL);
281 new_slot = host->slots[i];
282 /* The current slot should not have a request in queue */
283 BUG_ON(new_slot == host->current_slot);
284
285 host->next_slot = new_slot;
286 host->mmc = new_slot->mmc;
287 spin_unlock_irqrestore(&host->slot_lock, flags);
288 queue_work(host->mmc_omap_wq, &host->slot_release_work);
289 return;
290 }
291
292 host->mmc = NULL;
293 wake_up(&host->slot_wq);
294 spin_unlock_irqrestore(&host->slot_lock, flags);
295}
296
297static inline
298int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
299{
300 if (slot->pdata->get_cover_state)
301 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
302 slot->id);
303 return 0;
304}
305
306static ssize_t
307mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
308 char *buf)
309{
310 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
311 struct mmc_omap_slot *slot = mmc_priv(mmc);
312
313 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
314 "closed");
315}
316
317static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
318
319static ssize_t
320mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
321 char *buf)
322{
323 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
324 struct mmc_omap_slot *slot = mmc_priv(mmc);
325
326 return sprintf(buf, "%s\n", slot->pdata->name);
327}
328
329static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
330
331static void
332mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
333{
334 u32 cmdreg;
335 u32 resptype;
336 u32 cmdtype;
337 u16 irq_mask;
338
339 host->cmd = cmd;
340
341 resptype = 0;
342 cmdtype = 0;
343
344 /* Our hardware needs to know exact type */
345 switch (mmc_resp_type(cmd)) {
346 case MMC_RSP_NONE:
347 break;
348 case MMC_RSP_R1:
349 case MMC_RSP_R1B:
350 /* resp 1, 1b, 6, 7 */
351 resptype = 1;
352 break;
353 case MMC_RSP_R2:
354 resptype = 2;
355 break;
356 case MMC_RSP_R3:
357 resptype = 3;
358 break;
359 default:
360 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
361 break;
362 }
363
364 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
365 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
366 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
367 cmdtype = OMAP_MMC_CMDTYPE_BC;
368 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
369 cmdtype = OMAP_MMC_CMDTYPE_BCR;
370 } else {
371 cmdtype = OMAP_MMC_CMDTYPE_AC;
372 }
373
374 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
375
376 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
377 cmdreg |= 1 << 6;
378
379 if (cmd->flags & MMC_RSP_BUSY)
380 cmdreg |= 1 << 11;
381
382 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
383 cmdreg |= 1 << 15;
384
385 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
386
387 OMAP_MMC_WRITE(host, CTO, 200);
388 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
389 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
390 irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
391 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
392 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
393 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
394 OMAP_MMC_STAT_END_OF_DATA;
395 if (cmd->opcode == MMC_ERASE)
396 irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;
397 OMAP_MMC_WRITE(host, IE, irq_mask);
398 OMAP_MMC_WRITE(host, CMD, cmdreg);
399}
400
401static void
402mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
403 int abort)
404{
405 enum dma_data_direction dma_data_dir;
406 struct device *dev = mmc_dev(host->mmc);
407 struct dma_chan *c;
408
409 if (data->flags & MMC_DATA_WRITE) {
410 dma_data_dir = DMA_TO_DEVICE;
411 c = host->dma_tx;
412 } else {
413 dma_data_dir = DMA_FROM_DEVICE;
414 c = host->dma_rx;
415 }
416 if (c) {
417 if (data->error) {
418 dmaengine_terminate_all(c);
419 /* Claim nothing transferred on error... */
420 data->bytes_xfered = 0;
421 }
422 dev = c->device->dev;
423 }
424 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
425}
426
427static void mmc_omap_send_stop_work(struct work_struct *work)
428{
429 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
430 send_stop_work);
431 struct mmc_omap_slot *slot = host->current_slot;
432 struct mmc_data *data = host->stop_data;
433 unsigned long tick_ns;
434
435 tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
436 ndelay(8*tick_ns);
437
438 mmc_omap_start_command(host, data->stop);
439}
440
441static void
442mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
443{
444 if (host->dma_in_use)
445 mmc_omap_release_dma(host, data, data->error);
446
447 host->data = NULL;
448 host->sg_len = 0;
449
450 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
451 * dozens of requests until the card finishes writing data.
452 * It'd be cheaper to just wait till an EOFB interrupt arrives...
453 */
454
455 if (!data->stop) {
456 struct mmc_host *mmc;
457
458 host->mrq = NULL;
459 mmc = host->mmc;
460 mmc_omap_release_slot(host->current_slot, 1);
461 mmc_request_done(mmc, data->mrq);
462 return;
463 }
464
465 host->stop_data = data;
466 queue_work(host->mmc_omap_wq, &host->send_stop_work);
467}
468
469static void
470mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
471{
472 struct mmc_omap_slot *slot = host->current_slot;
473 unsigned int restarts, passes, timeout;
474 u16 stat = 0;
475
476 /* Sending abort takes 80 clocks. Have some extra and round up */
477 timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq);
478 restarts = 0;
479 while (restarts < maxloops) {
480 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
481 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
482
483 passes = 0;
484 while (passes < timeout) {
485 stat = OMAP_MMC_READ(host, STAT);
486 if (stat & OMAP_MMC_STAT_END_OF_CMD)
487 goto out;
488 udelay(1);
489 passes++;
490 }
491
492 restarts++;
493 }
494out:
495 OMAP_MMC_WRITE(host, STAT, stat);
496}
497
498static void
499mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
500{
501 if (host->dma_in_use)
502 mmc_omap_release_dma(host, data, 1);
503
504 host->data = NULL;
505 host->sg_len = 0;
506
507 mmc_omap_send_abort(host, 10000);
508}
509
510static void
511mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
512{
513 unsigned long flags;
514 int done;
515
516 if (!host->dma_in_use) {
517 mmc_omap_xfer_done(host, data);
518 return;
519 }
520 done = 0;
521 spin_lock_irqsave(&host->dma_lock, flags);
522 if (host->dma_done)
523 done = 1;
524 else
525 host->brs_received = 1;
526 spin_unlock_irqrestore(&host->dma_lock, flags);
527 if (done)
528 mmc_omap_xfer_done(host, data);
529}
530
531static void
532mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
533{
534 unsigned long flags;
535 int done;
536
537 done = 0;
538 spin_lock_irqsave(&host->dma_lock, flags);
539 if (host->brs_received)
540 done = 1;
541 else
542 host->dma_done = 1;
543 spin_unlock_irqrestore(&host->dma_lock, flags);
544 if (done)
545 mmc_omap_xfer_done(host, data);
546}
547
548static void
549mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
550{
551 host->cmd = NULL;
552
553 del_timer(&host->cmd_abort_timer);
554
555 if (cmd->flags & MMC_RSP_PRESENT) {
556 if (cmd->flags & MMC_RSP_136) {
557 /* response type 2 */
558 cmd->resp[3] =
559 OMAP_MMC_READ(host, RSP0) |
560 (OMAP_MMC_READ(host, RSP1) << 16);
561 cmd->resp[2] =
562 OMAP_MMC_READ(host, RSP2) |
563 (OMAP_MMC_READ(host, RSP3) << 16);
564 cmd->resp[1] =
565 OMAP_MMC_READ(host, RSP4) |
566 (OMAP_MMC_READ(host, RSP5) << 16);
567 cmd->resp[0] =
568 OMAP_MMC_READ(host, RSP6) |
569 (OMAP_MMC_READ(host, RSP7) << 16);
570 } else {
571 /* response types 1, 1b, 3, 4, 5, 6 */
572 cmd->resp[0] =
573 OMAP_MMC_READ(host, RSP6) |
574 (OMAP_MMC_READ(host, RSP7) << 16);
575 }
576 }
577
578 if (host->data == NULL || cmd->error) {
579 struct mmc_host *mmc;
580
581 if (host->data != NULL)
582 mmc_omap_abort_xfer(host, host->data);
583 host->mrq = NULL;
584 mmc = host->mmc;
585 mmc_omap_release_slot(host->current_slot, 1);
586 mmc_request_done(mmc, cmd->mrq);
587 }
588}
589
590/*
591 * Abort stuck command. Can occur when card is removed while it is being
592 * read.
593 */
594static void mmc_omap_abort_command(struct work_struct *work)
595{
596 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
597 cmd_abort_work);
598 BUG_ON(!host->cmd);
599
600 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
601 host->cmd->opcode);
602
603 if (host->cmd->error == 0)
604 host->cmd->error = -ETIMEDOUT;
605
606 if (host->data == NULL) {
607 struct mmc_command *cmd;
608 struct mmc_host *mmc;
609
610 cmd = host->cmd;
611 host->cmd = NULL;
612 mmc_omap_send_abort(host, 10000);
613
614 host->mrq = NULL;
615 mmc = host->mmc;
616 mmc_omap_release_slot(host->current_slot, 1);
617 mmc_request_done(mmc, cmd->mrq);
618 } else
619 mmc_omap_cmd_done(host, host->cmd);
620
621 host->abort = 0;
622 enable_irq(host->irq);
623}
624
625static void
626mmc_omap_cmd_timer(struct timer_list *t)
627{
628 struct mmc_omap_host *host = from_timer(host, t, cmd_abort_timer);
629 unsigned long flags;
630
631 spin_lock_irqsave(&host->slot_lock, flags);
632 if (host->cmd != NULL && !host->abort) {
633 OMAP_MMC_WRITE(host, IE, 0);
634 disable_irq(host->irq);
635 host->abort = 1;
636 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
637 }
638 spin_unlock_irqrestore(&host->slot_lock, flags);
639}
640
641/* PIO only */
642static void
643mmc_omap_sg_to_buf(struct mmc_omap_host *host)
644{
645 struct scatterlist *sg;
646
647 sg = host->data->sg + host->sg_idx;
648 host->buffer_bytes_left = sg->length;
649 host->buffer = sg_virt(sg);
650 if (host->buffer_bytes_left > host->total_bytes_left)
651 host->buffer_bytes_left = host->total_bytes_left;
652}
653
654static void
655mmc_omap_clk_timer(struct timer_list *t)
656{
657 struct mmc_omap_host *host = from_timer(host, t, clk_timer);
658
659 mmc_omap_fclk_enable(host, 0);
660}
661
662/* PIO only */
663static void
664mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
665{
666 int n, nwords;
667
668 if (host->buffer_bytes_left == 0) {
669 host->sg_idx++;
670 BUG_ON(host->sg_idx == host->sg_len);
671 mmc_omap_sg_to_buf(host);
672 }
673 n = 64;
674 if (n > host->buffer_bytes_left)
675 n = host->buffer_bytes_left;
676
677 /* Round up to handle odd number of bytes to transfer */
678 nwords = DIV_ROUND_UP(n, 2);
679
680 host->buffer_bytes_left -= n;
681 host->total_bytes_left -= n;
682 host->data->bytes_xfered += n;
683
684 if (write) {
685 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
686 host->buffer, nwords);
687 } else {
688 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
689 host->buffer, nwords);
690 }
691
692 host->buffer += nwords;
693}
694
695#ifdef CONFIG_MMC_DEBUG
696static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
697{
698 static const char *mmc_omap_status_bits[] = {
699 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
700 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
701 };
702 int i;
703 char res[64], *buf = res;
704
705 buf += sprintf(buf, "MMC IRQ 0x%x:", status);
706
707 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
708 if (status & (1 << i))
709 buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
710 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
711}
712#else
713static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
714{
715}
716#endif
717
718
719static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
720{
721 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
722 u16 status;
723 int end_command;
724 int end_transfer;
725 int transfer_error, cmd_error;
726
727 if (host->cmd == NULL && host->data == NULL) {
728 status = OMAP_MMC_READ(host, STAT);
729 dev_info(mmc_dev(host->slots[0]->mmc),
730 "Spurious IRQ 0x%04x\n", status);
731 if (status != 0) {
732 OMAP_MMC_WRITE(host, STAT, status);
733 OMAP_MMC_WRITE(host, IE, 0);
734 }
735 return IRQ_HANDLED;
736 }
737
738 end_command = 0;
739 end_transfer = 0;
740 transfer_error = 0;
741 cmd_error = 0;
742
743 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
744 int cmd;
745
746 OMAP_MMC_WRITE(host, STAT, status);
747 if (host->cmd != NULL)
748 cmd = host->cmd->opcode;
749 else
750 cmd = -1;
751 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
752 status, cmd);
753 mmc_omap_report_irq(host, status);
754
755 if (host->total_bytes_left) {
756 if ((status & OMAP_MMC_STAT_A_FULL) ||
757 (status & OMAP_MMC_STAT_END_OF_DATA))
758 mmc_omap_xfer_data(host, 0);
759 if (status & OMAP_MMC_STAT_A_EMPTY)
760 mmc_omap_xfer_data(host, 1);
761 }
762
763 if (status & OMAP_MMC_STAT_END_OF_DATA)
764 end_transfer = 1;
765
766 if (status & OMAP_MMC_STAT_DATA_TOUT) {
767 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
768 cmd);
769 if (host->data) {
770 host->data->error = -ETIMEDOUT;
771 transfer_error = 1;
772 }
773 }
774
775 if (status & OMAP_MMC_STAT_DATA_CRC) {
776 if (host->data) {
777 host->data->error = -EILSEQ;
778 dev_dbg(mmc_dev(host->mmc),
779 "data CRC error, bytes left %d\n",
780 host->total_bytes_left);
781 transfer_error = 1;
782 } else {
783 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
784 }
785 }
786
787 if (status & OMAP_MMC_STAT_CMD_TOUT) {
788 /* Timeouts are routine with some commands */
789 if (host->cmd) {
790 struct mmc_omap_slot *slot =
791 host->current_slot;
792 if (slot == NULL ||
793 !mmc_omap_cover_is_open(slot))
794 dev_err(mmc_dev(host->mmc),
795 "command timeout (CMD%d)\n",
796 cmd);
797 host->cmd->error = -ETIMEDOUT;
798 end_command = 1;
799 cmd_error = 1;
800 }
801 }
802
803 if (status & OMAP_MMC_STAT_CMD_CRC) {
804 if (host->cmd) {
805 dev_err(mmc_dev(host->mmc),
806 "command CRC error (CMD%d, arg 0x%08x)\n",
807 cmd, host->cmd->arg);
808 host->cmd->error = -EILSEQ;
809 end_command = 1;
810 cmd_error = 1;
811 } else
812 dev_err(mmc_dev(host->mmc),
813 "command CRC error without cmd?\n");
814 }
815
816 if (status & OMAP_MMC_STAT_CARD_ERR) {
817 dev_dbg(mmc_dev(host->mmc),
818 "ignoring card status error (CMD%d)\n",
819 cmd);
820 end_command = 1;
821 }
822
823 /*
824 * NOTE: On 1610 the END_OF_CMD may come too early when
825 * starting a write
826 */
827 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
828 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
829 end_command = 1;
830 }
831 }
832
833 if (cmd_error && host->data) {
834 del_timer(&host->cmd_abort_timer);
835 host->abort = 1;
836 OMAP_MMC_WRITE(host, IE, 0);
837 disable_irq_nosync(host->irq);
838 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
839 return IRQ_HANDLED;
840 }
841
842 if (end_command && host->cmd)
843 mmc_omap_cmd_done(host, host->cmd);
844 if (host->data != NULL) {
845 if (transfer_error)
846 mmc_omap_xfer_done(host, host->data);
847 else if (end_transfer)
848 mmc_omap_end_of_data(host, host->data);
849 }
850
851 return IRQ_HANDLED;
852}
853
854void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
855{
856 int cover_open;
857 struct mmc_omap_host *host = dev_get_drvdata(dev);
858 struct mmc_omap_slot *slot = host->slots[num];
859
860 BUG_ON(num >= host->nr_slots);
861
862 /* Other subsystems can call in here before we're initialised. */
863 if (host->nr_slots == 0 || !host->slots[num])
864 return;
865
866 cover_open = mmc_omap_cover_is_open(slot);
867 if (cover_open != slot->cover_open) {
868 slot->cover_open = cover_open;
869 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
870 }
871
872 tasklet_hi_schedule(&slot->cover_tasklet);
873}
874
875static void mmc_omap_cover_timer(struct timer_list *t)
876{
877 struct mmc_omap_slot *slot = from_timer(slot, t, cover_timer);
878 tasklet_schedule(&slot->cover_tasklet);
879}
880
881static void mmc_omap_cover_handler(unsigned long param)
882{
883 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
884 int cover_open = mmc_omap_cover_is_open(slot);
885
886 mmc_detect_change(slot->mmc, 0);
887 if (!cover_open)
888 return;
889
890 /*
891 * If no card is inserted, we postpone polling until
892 * the cover has been closed.
893 */
894 if (slot->mmc->card == NULL)
895 return;
896
897 mod_timer(&slot->cover_timer,
898 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
899}
900
901static void mmc_omap_dma_callback(void *priv)
902{
903 struct mmc_omap_host *host = priv;
904 struct mmc_data *data = host->data;
905
906 /* If we got to the end of DMA, assume everything went well */
907 data->bytes_xfered += data->blocks * data->blksz;
908
909 mmc_omap_dma_done(host, data);
910}
911
912static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
913{
914 u16 reg;
915
916 reg = OMAP_MMC_READ(host, SDIO);
917 reg &= ~(1 << 5);
918 OMAP_MMC_WRITE(host, SDIO, reg);
919 /* Set maximum timeout */
920 OMAP_MMC_WRITE(host, CTO, 0xfd);
921}
922
923static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
924{
925 unsigned int timeout, cycle_ns;
926 u16 reg;
927
928 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
929 timeout = req->data->timeout_ns / cycle_ns;
930 timeout += req->data->timeout_clks;
931
932 /* Check if we need to use timeout multiplier register */
933 reg = OMAP_MMC_READ(host, SDIO);
934 if (timeout > 0xffff) {
935 reg |= (1 << 5);
936 timeout /= 1024;
937 } else
938 reg &= ~(1 << 5);
939 OMAP_MMC_WRITE(host, SDIO, reg);
940 OMAP_MMC_WRITE(host, DTO, timeout);
941}
942
943static void
944mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
945{
946 struct mmc_data *data = req->data;
947 int i, use_dma = 1, block_size;
948 struct scatterlist *sg;
949 unsigned sg_len;
950
951 host->data = data;
952 if (data == NULL) {
953 OMAP_MMC_WRITE(host, BLEN, 0);
954 OMAP_MMC_WRITE(host, NBLK, 0);
955 OMAP_MMC_WRITE(host, BUF, 0);
956 host->dma_in_use = 0;
957 set_cmd_timeout(host, req);
958 return;
959 }
960
961 block_size = data->blksz;
962
963 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
964 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
965 set_data_timeout(host, req);
966
967 /* cope with calling layer confusion; it issues "single
968 * block" writes using multi-block scatterlists.
969 */
970 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
971
972 /* Only do DMA for entire blocks */
973 for_each_sg(data->sg, sg, sg_len, i) {
974 if ((sg->length % block_size) != 0) {
975 use_dma = 0;
976 break;
977 }
978 }
979
980 host->sg_idx = 0;
981 if (use_dma) {
982 enum dma_data_direction dma_data_dir;
983 struct dma_async_tx_descriptor *tx;
984 struct dma_chan *c;
985 u32 burst, *bp;
986 u16 buf;
987
988 /*
989 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
990 * and 24xx. Use 16 or 32 word frames when the
991 * blocksize is at least that large. Blocksize is
992 * usually 512 bytes; but not for some SD reads.
993 */
994 burst = mmc_omap15xx() ? 32 : 64;
995 if (burst > data->blksz)
996 burst = data->blksz;
997
998 burst >>= 1;
999
1000 if (data->flags & MMC_DATA_WRITE) {
1001 c = host->dma_tx;
1002 bp = &host->dma_tx_burst;
1003 buf = 0x0f80 | (burst - 1) << 0;
1004 dma_data_dir = DMA_TO_DEVICE;
1005 } else {
1006 c = host->dma_rx;
1007 bp = &host->dma_rx_burst;
1008 buf = 0x800f | (burst - 1) << 8;
1009 dma_data_dir = DMA_FROM_DEVICE;
1010 }
1011
1012 if (!c)
1013 goto use_pio;
1014
1015 /* Only reconfigure if we have a different burst size */
1016 if (*bp != burst) {
1017 struct dma_slave_config cfg = {
1018 .src_addr = host->phys_base +
1019 OMAP_MMC_REG(host, DATA),
1020 .dst_addr = host->phys_base +
1021 OMAP_MMC_REG(host, DATA),
1022 .src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1023 .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1024 .src_maxburst = burst,
1025 .dst_maxburst = burst,
1026 };
1027
1028 if (dmaengine_slave_config(c, &cfg))
1029 goto use_pio;
1030
1031 *bp = burst;
1032 }
1033
1034 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1035 dma_data_dir);
1036 if (host->sg_len == 0)
1037 goto use_pio;
1038
1039 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1040 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1041 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1042 if (!tx)
1043 goto use_pio;
1044
1045 OMAP_MMC_WRITE(host, BUF, buf);
1046
1047 tx->callback = mmc_omap_dma_callback;
1048 tx->callback_param = host;
1049 dmaengine_submit(tx);
1050 host->brs_received = 0;
1051 host->dma_done = 0;
1052 host->dma_in_use = 1;
1053 return;
1054 }
1055 use_pio:
1056
1057 /* Revert to PIO? */
1058 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1059 host->total_bytes_left = data->blocks * block_size;
1060 host->sg_len = sg_len;
1061 mmc_omap_sg_to_buf(host);
1062 host->dma_in_use = 0;
1063}
1064
1065static void mmc_omap_start_request(struct mmc_omap_host *host,
1066 struct mmc_request *req)
1067{
1068 BUG_ON(host->mrq != NULL);
1069
1070 host->mrq = req;
1071
1072 /* only touch fifo AFTER the controller readies it */
1073 mmc_omap_prepare_data(host, req);
1074 mmc_omap_start_command(host, req->cmd);
1075 if (host->dma_in_use) {
1076 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1077 host->dma_tx : host->dma_rx;
1078
1079 dma_async_issue_pending(c);
1080 }
1081}
1082
1083static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1084{
1085 struct mmc_omap_slot *slot = mmc_priv(mmc);
1086 struct mmc_omap_host *host = slot->host;
1087 unsigned long flags;
1088
1089 spin_lock_irqsave(&host->slot_lock, flags);
1090 if (host->mmc != NULL) {
1091 BUG_ON(slot->mrq != NULL);
1092 slot->mrq = req;
1093 spin_unlock_irqrestore(&host->slot_lock, flags);
1094 return;
1095 } else
1096 host->mmc = mmc;
1097 spin_unlock_irqrestore(&host->slot_lock, flags);
1098 mmc_omap_select_slot(slot, 1);
1099 mmc_omap_start_request(host, req);
1100}
1101
1102static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1103 int vdd)
1104{
1105 struct mmc_omap_host *host;
1106
1107 host = slot->host;
1108
1109 if (slot->pdata->set_power != NULL)
1110 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1111 vdd);
1112 if (mmc_omap2()) {
1113 u16 w;
1114
1115 if (power_on) {
1116 w = OMAP_MMC_READ(host, CON);
1117 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1118 } else {
1119 w = OMAP_MMC_READ(host, CON);
1120 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1121 }
1122 }
1123}
1124
1125static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1126{
1127 struct mmc_omap_slot *slot = mmc_priv(mmc);
1128 struct mmc_omap_host *host = slot->host;
1129 int func_clk_rate = clk_get_rate(host->fclk);
1130 int dsor;
1131
1132 if (ios->clock == 0)
1133 return 0;
1134
1135 dsor = func_clk_rate / ios->clock;
1136 if (dsor < 1)
1137 dsor = 1;
1138
1139 if (func_clk_rate / dsor > ios->clock)
1140 dsor++;
1141
1142 if (dsor > 250)
1143 dsor = 250;
1144
1145 slot->fclk_freq = func_clk_rate / dsor;
1146
1147 if (ios->bus_width == MMC_BUS_WIDTH_4)
1148 dsor |= 1 << 15;
1149
1150 return dsor;
1151}
1152
1153static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1154{
1155 struct mmc_omap_slot *slot = mmc_priv(mmc);
1156 struct mmc_omap_host *host = slot->host;
1157 int i, dsor;
1158 int clk_enabled, init_stream;
1159
1160 mmc_omap_select_slot(slot, 0);
1161
1162 dsor = mmc_omap_calc_divisor(mmc, ios);
1163
1164 if (ios->vdd != slot->vdd)
1165 slot->vdd = ios->vdd;
1166
1167 clk_enabled = 0;
1168 init_stream = 0;
1169 switch (ios->power_mode) {
1170 case MMC_POWER_OFF:
1171 mmc_omap_set_power(slot, 0, ios->vdd);
1172 break;
1173 case MMC_POWER_UP:
1174 /* Cannot touch dsor yet, just power up MMC */
1175 mmc_omap_set_power(slot, 1, ios->vdd);
1176 slot->power_mode = ios->power_mode;
1177 goto exit;
1178 case MMC_POWER_ON:
1179 mmc_omap_fclk_enable(host, 1);
1180 clk_enabled = 1;
1181 dsor |= 1 << 11;
1182 if (slot->power_mode != MMC_POWER_ON)
1183 init_stream = 1;
1184 break;
1185 }
1186 slot->power_mode = ios->power_mode;
1187
1188 if (slot->bus_mode != ios->bus_mode) {
1189 if (slot->pdata->set_bus_mode != NULL)
1190 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1191 ios->bus_mode);
1192 slot->bus_mode = ios->bus_mode;
1193 }
1194
1195 /* On insanely high arm_per frequencies something sometimes
1196 * goes somehow out of sync, and the POW bit is not being set,
1197 * which results in the while loop below getting stuck.
1198 * Writing to the CON register twice seems to do the trick. */
1199 for (i = 0; i < 2; i++)
1200 OMAP_MMC_WRITE(host, CON, dsor);
1201 slot->saved_con = dsor;
1202 if (init_stream) {
1203 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1204 int usecs = 250;
1205
1206 /* Send clock cycles, poll completion */
1207 OMAP_MMC_WRITE(host, IE, 0);
1208 OMAP_MMC_WRITE(host, STAT, 0xffff);
1209 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1210 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1211 udelay(1);
1212 usecs--;
1213 }
1214 OMAP_MMC_WRITE(host, STAT, 1);
1215 }
1216
1217exit:
1218 mmc_omap_release_slot(slot, clk_enabled);
1219}
1220
1221static const struct mmc_host_ops mmc_omap_ops = {
1222 .request = mmc_omap_request,
1223 .set_ios = mmc_omap_set_ios,
1224};
1225
1226static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1227{
1228 struct mmc_omap_slot *slot = NULL;
1229 struct mmc_host *mmc;
1230 int r;
1231
1232 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1233 if (mmc == NULL)
1234 return -ENOMEM;
1235
1236 slot = mmc_priv(mmc);
1237 slot->host = host;
1238 slot->mmc = mmc;
1239 slot->id = id;
1240 slot->power_mode = MMC_POWER_UNDEFINED;
1241 slot->pdata = &host->pdata->slots[id];
1242
1243 host->slots[id] = slot;
1244
1245 mmc->caps = 0;
1246 if (host->pdata->slots[id].wires >= 4)
1247 mmc->caps |= MMC_CAP_4_BIT_DATA;
1248
1249 mmc->ops = &mmc_omap_ops;
1250 mmc->f_min = 400000;
1251
1252 if (mmc_omap2())
1253 mmc->f_max = 48000000;
1254 else
1255 mmc->f_max = 24000000;
1256 if (host->pdata->max_freq)
1257 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1258 mmc->ocr_avail = slot->pdata->ocr_mask;
1259
1260 /* Use scatterlist DMA to reduce per-transfer costs.
1261 * NOTE max_seg_size assumption that small blocks aren't
1262 * normally used (except e.g. for reading SD registers).
1263 */
1264 mmc->max_segs = 32;
1265 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1266 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1267 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1268 mmc->max_seg_size = mmc->max_req_size;
1269
1270 if (slot->pdata->get_cover_state != NULL) {
1271 timer_setup(&slot->cover_timer, mmc_omap_cover_timer, 0);
1272 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1273 (unsigned long)slot);
1274 }
1275
1276 r = mmc_add_host(mmc);
1277 if (r < 0)
1278 goto err_remove_host;
1279
1280 if (slot->pdata->name != NULL) {
1281 r = device_create_file(&mmc->class_dev,
1282 &dev_attr_slot_name);
1283 if (r < 0)
1284 goto err_remove_host;
1285 }
1286
1287 if (slot->pdata->get_cover_state != NULL) {
1288 r = device_create_file(&mmc->class_dev,
1289 &dev_attr_cover_switch);
1290 if (r < 0)
1291 goto err_remove_slot_name;
1292 tasklet_schedule(&slot->cover_tasklet);
1293 }
1294
1295 return 0;
1296
1297err_remove_slot_name:
1298 if (slot->pdata->name != NULL)
1299 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1300err_remove_host:
1301 mmc_remove_host(mmc);
1302 mmc_free_host(mmc);
1303 return r;
1304}
1305
1306static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1307{
1308 struct mmc_host *mmc = slot->mmc;
1309
1310 if (slot->pdata->name != NULL)
1311 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1312 if (slot->pdata->get_cover_state != NULL)
1313 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1314
1315 tasklet_kill(&slot->cover_tasklet);
1316 del_timer_sync(&slot->cover_timer);
1317 flush_workqueue(slot->host->mmc_omap_wq);
1318
1319 mmc_remove_host(mmc);
1320 mmc_free_host(mmc);
1321}
1322
1323static int mmc_omap_probe(struct platform_device *pdev)
1324{
1325 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1326 struct mmc_omap_host *host = NULL;
1327 struct resource *res;
1328 int i, ret = 0;
1329 int irq;
1330
1331 if (pdata == NULL) {
1332 dev_err(&pdev->dev, "platform data missing\n");
1333 return -ENXIO;
1334 }
1335 if (pdata->nr_slots == 0) {
1336 dev_err(&pdev->dev, "no slots\n");
1337 return -EPROBE_DEFER;
1338 }
1339
1340 host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),
1341 GFP_KERNEL);
1342 if (host == NULL)
1343 return -ENOMEM;
1344
1345 irq = platform_get_irq(pdev, 0);
1346 if (irq < 0)
1347 return -ENXIO;
1348
1349 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1350 host->virt_base = devm_ioremap_resource(&pdev->dev, res);
1351 if (IS_ERR(host->virt_base))
1352 return PTR_ERR(host->virt_base);
1353
1354 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1355 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1356
1357 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1358 timer_setup(&host->cmd_abort_timer, mmc_omap_cmd_timer, 0);
1359
1360 spin_lock_init(&host->clk_lock);
1361 timer_setup(&host->clk_timer, mmc_omap_clk_timer, 0);
1362
1363 spin_lock_init(&host->dma_lock);
1364 spin_lock_init(&host->slot_lock);
1365 init_waitqueue_head(&host->slot_wq);
1366
1367 host->pdata = pdata;
1368 host->features = host->pdata->slots[0].features;
1369 host->dev = &pdev->dev;
1370 platform_set_drvdata(pdev, host);
1371
1372 host->id = pdev->id;
1373 host->irq = irq;
1374 host->phys_base = res->start;
1375 host->iclk = clk_get(&pdev->dev, "ick");
1376 if (IS_ERR(host->iclk))
1377 return PTR_ERR(host->iclk);
1378 clk_enable(host->iclk);
1379
1380 host->fclk = clk_get(&pdev->dev, "fck");
1381 if (IS_ERR(host->fclk)) {
1382 ret = PTR_ERR(host->fclk);
1383 goto err_free_iclk;
1384 }
1385
1386 host->dma_tx_burst = -1;
1387 host->dma_rx_burst = -1;
1388
1389 host->dma_tx = dma_request_chan(&pdev->dev, "tx");
1390 if (IS_ERR(host->dma_tx)) {
1391 ret = PTR_ERR(host->dma_tx);
1392 if (ret == -EPROBE_DEFER) {
1393 clk_put(host->fclk);
1394 goto err_free_iclk;
1395 }
1396
1397 host->dma_tx = NULL;
1398 dev_warn(host->dev, "TX DMA channel request failed\n");
1399 }
1400
1401 host->dma_rx = dma_request_chan(&pdev->dev, "rx");
1402 if (IS_ERR(host->dma_rx)) {
1403 ret = PTR_ERR(host->dma_rx);
1404 if (ret == -EPROBE_DEFER) {
1405 if (host->dma_tx)
1406 dma_release_channel(host->dma_tx);
1407 clk_put(host->fclk);
1408 goto err_free_iclk;
1409 }
1410
1411 host->dma_rx = NULL;
1412 dev_warn(host->dev, "RX DMA channel request failed\n");
1413 }
1414
1415 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1416 if (ret)
1417 goto err_free_dma;
1418
1419 if (pdata->init != NULL) {
1420 ret = pdata->init(&pdev->dev);
1421 if (ret < 0)
1422 goto err_free_irq;
1423 }
1424
1425 host->nr_slots = pdata->nr_slots;
1426 host->reg_shift = (mmc_omap7xx() ? 1 : 2);
1427
1428 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1429 if (!host->mmc_omap_wq) {
1430 ret = -ENOMEM;
1431 goto err_plat_cleanup;
1432 }
1433
1434 for (i = 0; i < pdata->nr_slots; i++) {
1435 ret = mmc_omap_new_slot(host, i);
1436 if (ret < 0) {
1437 while (--i >= 0)
1438 mmc_omap_remove_slot(host->slots[i]);
1439
1440 goto err_destroy_wq;
1441 }
1442 }
1443
1444 return 0;
1445
1446err_destroy_wq:
1447 destroy_workqueue(host->mmc_omap_wq);
1448err_plat_cleanup:
1449 if (pdata->cleanup)
1450 pdata->cleanup(&pdev->dev);
1451err_free_irq:
1452 free_irq(host->irq, host);
1453err_free_dma:
1454 if (host->dma_tx)
1455 dma_release_channel(host->dma_tx);
1456 if (host->dma_rx)
1457 dma_release_channel(host->dma_rx);
1458 clk_put(host->fclk);
1459err_free_iclk:
1460 clk_disable(host->iclk);
1461 clk_put(host->iclk);
1462 return ret;
1463}
1464
1465static int mmc_omap_remove(struct platform_device *pdev)
1466{
1467 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1468 int i;
1469
1470 BUG_ON(host == NULL);
1471
1472 for (i = 0; i < host->nr_slots; i++)
1473 mmc_omap_remove_slot(host->slots[i]);
1474
1475 if (host->pdata->cleanup)
1476 host->pdata->cleanup(&pdev->dev);
1477
1478 mmc_omap_fclk_enable(host, 0);
1479 free_irq(host->irq, host);
1480 clk_put(host->fclk);
1481 clk_disable(host->iclk);
1482 clk_put(host->iclk);
1483
1484 if (host->dma_tx)
1485 dma_release_channel(host->dma_tx);
1486 if (host->dma_rx)
1487 dma_release_channel(host->dma_rx);
1488
1489 destroy_workqueue(host->mmc_omap_wq);
1490
1491 return 0;
1492}
1493
1494#if IS_BUILTIN(CONFIG_OF)
1495static const struct of_device_id mmc_omap_match[] = {
1496 { .compatible = "ti,omap2420-mmc", },
1497 { },
1498};
1499MODULE_DEVICE_TABLE(of, mmc_omap_match);
1500#endif
1501
1502static struct platform_driver mmc_omap_driver = {
1503 .probe = mmc_omap_probe,
1504 .remove = mmc_omap_remove,
1505 .driver = {
1506 .name = DRIVER_NAME,
1507 .of_match_table = of_match_ptr(mmc_omap_match),
1508 },
1509};
1510
1511module_platform_driver(mmc_omap_driver);
1512MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1513MODULE_LICENSE("GPL");
1514MODULE_ALIAS("platform:" DRIVER_NAME);
1515MODULE_AUTHOR("Juha Yrjölä");