1/*
   2 * mmc_spi.c - Access SD/MMC cards through SPI master controllers
   3 *
   4 * (C) Copyright 2005, Intec Automation,
   5 *		Mike Lavender (mike@steroidmicros)
   6 * (C) Copyright 2006-2007, David Brownell
   7 * (C) Copyright 2007, Axis Communications,
   8 *		Hans-Peter Nilsson (hp@axis.com)
   9 * (C) Copyright 2007, ATRON electronic GmbH,
  10 *		Jan Nikitenko <jan.nikitenko@gmail.com>
  11 *
  12 *
  13 * This program is free software; you can redistribute it and/or modify
  14 * it under the terms of the GNU General Public License as published by
  15 * the Free Software Foundation; either version 2 of the License, or
  16 * (at your option) any later version.
  17 *
  18 * This program is distributed in the hope that it will be useful,
  19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 * GNU General Public License for more details.
  22 *
  23 * You should have received a copy of the GNU General Public License
  24 * along with this program; if not, write to the Free Software
  25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26 */
  27#include <linux/sched.h>
  28#include <linux/delay.h>
  29#include <linux/slab.h>
  30#include <linux/module.h>
  31#include <linux/bio.h>
  32#include <linux/dma-mapping.h>
  33#include <linux/crc7.h>
  34#include <linux/crc-itu-t.h>
  35#include <linux/scatterlist.h>
  36
  37#include <linux/mmc/host.h>
  38#include <linux/mmc/mmc.h>		/* for R1_SPI_* bit values */
  39#include <linux/mmc/slot-gpio.h>
  40
  41#include <linux/spi/spi.h>
  42#include <linux/spi/mmc_spi.h>
  43
  44#include <asm/unaligned.h>
  45
  46
  47/* NOTES:
  48 *
  49 * - For now, we won't try to interoperate with a real mmc/sd/sdio
  50 *   controller, although some of them do have hardware support for
  51 *   SPI protocol.  The main reason for such configs would be mmc-ish
  52 *   cards like DataFlash, which don't support that "native" protocol.
  53 *
  54 *   We don't have a "DataFlash/MMC/SD/SDIO card slot" abstraction to
  55 *   switch between driver stacks, and in any case if "native" mode
  56 *   is available, it will be faster and hence preferable.
  57 *
  58 * - MMC depends on a different chipselect management policy than the
  59 *   SPI interface currently supports for shared bus segments:  it needs
  60 *   to issue multiple spi_message requests with the chipselect active,
  61 *   using the results of one message to decide the next one to issue.
  62 *
  63 *   Pending updates to the programming interface, this driver expects
  64 *   that it not share the bus with other drivers (precluding conflicts).
  65 *
  66 * - We tell the controller to keep the chipselect active from the
  67 *   beginning of an mmc_host_ops.request until the end.  So beware
  68 *   of SPI controller drivers that mis-handle the cs_change flag!
  69 *
  70 *   However, many cards seem OK with chipselect flapping up/down
  71 *   during that time ... at least on unshared bus segments.
  72 */
  73
  74
  75/*
  76 * Local protocol constants, internal to data block protocols.
  77 */
  78
  79/* Response tokens used to ack each block written: */
  80#define SPI_MMC_RESPONSE_CODE(x)	((x) & 0x1f)
  81#define SPI_RESPONSE_ACCEPTED		((2 << 1)|1)
  82#define SPI_RESPONSE_CRC_ERR		((5 << 1)|1)
  83#define SPI_RESPONSE_WRITE_ERR		((6 << 1)|1)
  84
  85/* Read and write blocks start with these tokens and end with crc;
  86 * on error, read tokens act like a subset of R2_SPI_* values.
  87 */
  88#define SPI_TOKEN_SINGLE	0xfe	/* single block r/w, multiblock read */
  89#define SPI_TOKEN_MULTI_WRITE	0xfc	/* multiblock write */
  90#define SPI_TOKEN_STOP_TRAN	0xfd	/* terminate multiblock write */
  91
  92#define MMC_SPI_BLOCKSIZE	512
  93
  94
  95/* These fixed timeouts come from the latest SD specs, which say to ignore
  96 * the CSD values.  The R1B value is for card erase (e.g. the "I forgot the
  97 * card's password" scenario); it's mostly applied to STOP_TRANSMISSION after
  98 * reads which takes nowhere near that long.  Older cards may be able to use
  99 * shorter timeouts ... but why bother?
 100 */
 101#define r1b_timeout		(HZ * 3)
 102
 103/* One of the critical speed parameters is the amount of data which may
 104 * be transferred in one command. If this value is too low, the SD card
 105 * controller has to do multiple partial block writes (argggh!). With
 106 * today (2008) SD cards there is little speed gain if we transfer more
 107 * than 64 KBytes at a time. So use this value until there is any indication
 108 * that we should do more here.
 109 */
 110#define MMC_SPI_BLOCKSATONCE	128
 111
 112/****************************************************************************/
 113
 114/*
 115 * Local Data Structures
 116 */
 117
 118/* "scratch" is per-{command,block} data exchanged with the card */
 119struct scratch {
 120	u8			status[29];
 121	u8			data_token;
 122	__be16			crc_val;
 123};
 124
 125struct mmc_spi_host {
 126	struct mmc_host		*mmc;
 127	struct spi_device	*spi;
 128
 129	unsigned char		power_mode;
 130	u16			powerup_msecs;
 131
 132	struct mmc_spi_platform_data	*pdata;
 133
 134	/* for bulk data transfers */
 135	struct spi_transfer	token, t, crc, early_status;
 136	struct spi_message	m;
 137
 138	/* for status readback */
 139	struct spi_transfer	status;
 140	struct spi_message	readback;
 141
 142	/* underlying DMA-aware controller, or null */
 143	struct device		*dma_dev;
 144
 145	/* buffer used for commands and for message "overhead" */
 146	struct scratch		*data;
 147	dma_addr_t		data_dma;
 148
 149	/* Specs say to write ones most of the time, even when the card
 150	 * has no need to read its input data; and many cards won't care.
 151	 * This is our source of those ones.
 152	 */
 153	void			*ones;
 154	dma_addr_t		ones_dma;
 155};
 156
 157
 158/****************************************************************************/
 159
 160/*
 161 * MMC-over-SPI protocol glue, used by the MMC stack interface
 162 */
 163
 164static inline int mmc_cs_off(struct mmc_spi_host *host)
 165{
 166	/* chipselect will always be inactive after setup() */
 167	return spi_setup(host->spi);
 168}
 169
 170static int
 171mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len)
 172{
 173	int status;
 174
 175	if (len > sizeof(*host->data)) {
 176		WARN_ON(1);
 177		return -EIO;
 178	}
 179
 180	host->status.len = len;
 181
 182	if (host->dma_dev)
 183		dma_sync_single_for_device(host->dma_dev,
 184				host->data_dma, sizeof(*host->data),
 185				DMA_FROM_DEVICE);
 186
 187	status = spi_sync_locked(host->spi, &host->readback);
 188
 189	if (host->dma_dev)
 190		dma_sync_single_for_cpu(host->dma_dev,
 191				host->data_dma, sizeof(*host->data),
 192				DMA_FROM_DEVICE);
 193
 194	return status;
 195}
 196
 197static int mmc_spi_skip(struct mmc_spi_host *host, unsigned long timeout,
 198			unsigned n, u8 byte)
 199{
 200	u8		*cp = host->data->status;
 201	unsigned long start = jiffies;
 202
 203	while (1) {
 204		int		status;
 205		unsigned	i;
 206
 207		status = mmc_spi_readbytes(host, n);
 208		if (status < 0)
 209			return status;
 210
 211		for (i = 0; i < n; i++) {
 212			if (cp[i] != byte)
 213				return cp[i];
 214		}
 215
 216		if (time_is_before_jiffies(start + timeout))
 217			break;
 218
 219		/* If we need long timeouts, we may release the CPU.
 220		 * We use jiffies here because we want to have a relation
 221		 * between elapsed time and the blocking of the scheduler.
 222		 */
 223		if (time_is_before_jiffies(start+1))
 224			schedule();
 225	}
 226	return -ETIMEDOUT;
 227}
 228
 229static inline int
 230mmc_spi_wait_unbusy(struct mmc_spi_host *host, unsigned long timeout)
 231{
 232	return mmc_spi_skip(host, timeout, sizeof(host->data->status), 0);
 233}
 234
 235static int mmc_spi_readtoken(struct mmc_spi_host *host, unsigned long timeout)
 236{
 237	return mmc_spi_skip(host, timeout, 1, 0xff);
 238}
 239
 240
 241/*
 242 * Note that for SPI, cmd->resp[0] is not the same data as "native" protocol
 243 * hosts return!  The low byte holds R1_SPI bits.  The next byte may hold
 244 * R2_SPI bits ... for SEND_STATUS, or after data read errors.
 245 *
 246 * cmd->resp[1] holds any four-byte response, for R3 (READ_OCR) and on
 247 * newer cards R7 (IF_COND).
 248 */
 249
 250static char *maptype(struct mmc_command *cmd)
 251{
 252	switch (mmc_spi_resp_type(cmd)) {
 253	case MMC_RSP_SPI_R1:	return "R1";
 254	case MMC_RSP_SPI_R1B:	return "R1B";
 255	case MMC_RSP_SPI_R2:	return "R2/R5";
 256	case MMC_RSP_SPI_R3:	return "R3/R4/R7";
 257	default:		return "?";
 258	}
 259}
 260
 261/* return zero, else negative errno after setting cmd->error */
 262static int mmc_spi_response_get(struct mmc_spi_host *host,
 263		struct mmc_command *cmd, int cs_on)
 264{
 
 265	u8	*cp = host->data->status;
 266	u8	*end = cp + host->t.len;
 267	int	value = 0;
 268	int	bitshift;
 269	u8 	leftover = 0;
 270	unsigned short rotator;
 271	int 	i;
 272	char	tag[32];
 273
 274	snprintf(tag, sizeof(tag), "  ... CMD%d response SPI_%s",
 275		cmd->opcode, maptype(cmd));
 276
 277	/* Except for data block reads, the whole response will already
 278	 * be stored in the scratch buffer.  It's somewhere after the
 279	 * command and the first byte we read after it.  We ignore that
 280	 * first byte.  After STOP_TRANSMISSION command it may include
 281	 * two data bits, but otherwise it's all ones.
 282	 */
 283	cp += 8;
 284	while (cp < end && *cp == 0xff)
 285		cp++;
 286
 287	/* Data block reads (R1 response types) may need more data... */
 288	if (cp == end) {
 289		cp = host->data->status;
 290		end = cp+1;
 291
 292		/* Card sends N(CR) (== 1..8) bytes of all-ones then one
 293		 * status byte ... and we already scanned 2 bytes.
 294		 *
 295		 * REVISIT block read paths use nasty byte-at-a-time I/O
 296		 * so it can always DMA directly into the target buffer.
 297		 * It'd probably be better to memcpy() the first chunk and
 298		 * avoid extra i/o calls...
 299		 *
 300		 * Note we check for more than 8 bytes, because in practice,
 301		 * some SD cards are slow...
 302		 */
 303		for (i = 2; i < 16; i++) {
 304			value = mmc_spi_readbytes(host, 1);
 305			if (value < 0)
 306				goto done;
 307			if (*cp != 0xff)
 308				goto checkstatus;
 309		}
 310		value = -ETIMEDOUT;
 311		goto done;
 312	}
 313
 314checkstatus:
 315	bitshift = 0;
 316	if (*cp & 0x80)	{
 317		/* Houston, we have an ugly card with a bit-shifted response */
 318		rotator = *cp++ << 8;
 319		/* read the next byte */
 320		if (cp == end) {
 321			value = mmc_spi_readbytes(host, 1);
 322			if (value < 0)
 323				goto done;
 324			cp = host->data->status;
 325			end = cp+1;
 326		}
 327		rotator |= *cp++;
 328		while (rotator & 0x8000) {
 329			bitshift++;
 330			rotator <<= 1;
 331		}
 332		cmd->resp[0] = rotator >> 8;
 333		leftover = rotator;
 334	} else {
 335		cmd->resp[0] = *cp++;
 336	}
 337	cmd->error = 0;
 338
 339	/* Status byte: the entire seven-bit R1 response.  */
 340	if (cmd->resp[0] != 0) {
 341		if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS)
 342				& cmd->resp[0])
 343			value = -EFAULT; /* Bad address */
 344		else if (R1_SPI_ILLEGAL_COMMAND & cmd->resp[0])
 345			value = -ENOSYS; /* Function not implemented */
 346		else if (R1_SPI_COM_CRC & cmd->resp[0])
 347			value = -EILSEQ; /* Illegal byte sequence */
 348		else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET)
 349				& cmd->resp[0])
 350			value = -EIO;    /* I/O error */
 351		/* else R1_SPI_IDLE, "it's resetting" */
 352	}
 353
 354	switch (mmc_spi_resp_type(cmd)) {
 355
 356	/* SPI R1B == R1 + busy; STOP_TRANSMISSION (for multiblock reads)
 357	 * and less-common stuff like various erase operations.
 358	 */
 359	case MMC_RSP_SPI_R1B:
 360		/* maybe we read all the busy tokens already */
 361		while (cp < end && *cp == 0)
 362			cp++;
 363		if (cp == end)
 364			mmc_spi_wait_unbusy(host, r1b_timeout);
 
 
 
 365		break;
 366
 367	/* SPI R2 == R1 + second status byte; SEND_STATUS
 368	 * SPI R5 == R1 + data byte; IO_RW_DIRECT
 369	 */
 370	case MMC_RSP_SPI_R2:
 371		/* read the next byte */
 372		if (cp == end) {
 373			value = mmc_spi_readbytes(host, 1);
 374			if (value < 0)
 375				goto done;
 376			cp = host->data->status;
 377			end = cp+1;
 378		}
 379		if (bitshift) {
 380			rotator = leftover << 8;
 381			rotator |= *cp << bitshift;
 382			cmd->resp[0] |= (rotator & 0xFF00);
 383		} else {
 384			cmd->resp[0] |= *cp << 8;
 385		}
 386		break;
 387
 388	/* SPI R3, R4, or R7 == R1 + 4 bytes */
 389	case MMC_RSP_SPI_R3:
 390		rotator = leftover << 8;
 391		cmd->resp[1] = 0;
 392		for (i = 0; i < 4; i++) {
 393			cmd->resp[1] <<= 8;
 394			/* read the next byte */
 395			if (cp == end) {
 396				value = mmc_spi_readbytes(host, 1);
 397				if (value < 0)
 398					goto done;
 399				cp = host->data->status;
 400				end = cp+1;
 401			}
 402			if (bitshift) {
 403				rotator |= *cp++ << bitshift;
 404				cmd->resp[1] |= (rotator >> 8);
 405				rotator <<= 8;
 406			} else {
 407				cmd->resp[1] |= *cp++;
 408			}
 409		}
 410		break;
 411
 412	/* SPI R1 == just one status byte */
 413	case MMC_RSP_SPI_R1:
 414		break;
 415
 416	default:
 417		dev_dbg(&host->spi->dev, "bad response type %04x\n",
 418				mmc_spi_resp_type(cmd));
 419		if (value >= 0)
 420			value = -EINVAL;
 421		goto done;
 422	}
 423
 424	if (value < 0)
 425		dev_dbg(&host->spi->dev, "%s: resp %04x %08x\n",
 426			tag, cmd->resp[0], cmd->resp[1]);
 427
 428	/* disable chipselect on errors and some success cases */
 429	if (value >= 0 && cs_on)
 430		return value;
 431done:
 432	if (value < 0)
 433		cmd->error = value;
 434	mmc_cs_off(host);
 435	return value;
 436}
 437
 438/* Issue command and read its response.
 439 * Returns zero on success, negative for error.
 440 *
 441 * On error, caller must cope with mmc core retry mechanism.  That
 442 * means immediate low-level resubmit, which affects the bus lock...
 443 */
 444static int
 445mmc_spi_command_send(struct mmc_spi_host *host,
 446		struct mmc_request *mrq,
 447		struct mmc_command *cmd, int cs_on)
 448{
 449	struct scratch		*data = host->data;
 450	u8			*cp = data->status;
 451	u32			arg = cmd->arg;
 452	int			status;
 453	struct spi_transfer	*t;
 454
 455	/* We can handle most commands (except block reads) in one full
 456	 * duplex I/O operation before either starting the next transfer
 457	 * (data block or command) or else deselecting the card.
 458	 *
 459	 * First, write 7 bytes:
 460	 *  - an all-ones byte to ensure the card is ready
 461	 *  - opcode byte (plus start and transmission bits)
 462	 *  - four bytes of big-endian argument
 463	 *  - crc7 (plus end bit) ... always computed, it's cheap
 464	 *
 465	 * We init the whole buffer to all-ones, which is what we need
 466	 * to write while we're reading (later) response data.
 467	 */
 468	memset(cp++, 0xff, sizeof(data->status));
 469
 470	*cp++ = 0x40 | cmd->opcode;
 471	*cp++ = (u8)(arg >> 24);
 472	*cp++ = (u8)(arg >> 16);
 473	*cp++ = (u8)(arg >> 8);
 474	*cp++ = (u8)arg;
 475	*cp++ = (crc7(0, &data->status[1], 5) << 1) | 0x01;
 476
 477	/* Then, read up to 13 bytes (while writing all-ones):
 478	 *  - N(CR) (== 1..8) bytes of all-ones
 479	 *  - status byte (for all response types)
 480	 *  - the rest of the response, either:
 481	 *      + nothing, for R1 or R1B responses
 482	 *	+ second status byte, for R2 responses
 483	 *	+ four data bytes, for R3 and R7 responses
 484	 *
 485	 * Finally, read some more bytes ... in the nice cases we know in
 486	 * advance how many, and reading 1 more is always OK:
 487	 *  - N(EC) (== 0..N) bytes of all-ones, before deselect/finish
 488	 *  - N(RC) (== 1..N) bytes of all-ones, before next command
 489	 *  - N(WR) (== 1..N) bytes of all-ones, before data write
 490	 *
 491	 * So in those cases one full duplex I/O of at most 21 bytes will
 492	 * handle the whole command, leaving the card ready to receive a
 493	 * data block or new command.  We do that whenever we can, shaving
 494	 * CPU and IRQ costs (especially when using DMA or FIFOs).
 495	 *
 496	 * There are two other cases, where it's not generally practical
 497	 * to rely on a single I/O:
 498	 *
 499	 *  - R1B responses need at least N(EC) bytes of all-zeroes.
 500	 *
 501	 *    In this case we can *try* to fit it into one I/O, then
 502	 *    maybe read more data later.
 503	 *
 504	 *  - Data block reads are more troublesome, since a variable
 505	 *    number of padding bytes precede the token and data.
 506	 *      + N(CX) (== 0..8) bytes of all-ones, before CSD or CID
 507	 *      + N(AC) (== 1..many) bytes of all-ones
 508	 *
 509	 *    In this case we currently only have minimal speedups here:
 510	 *    when N(CR) == 1 we can avoid I/O in response_get().
 511	 */
 512	if (cs_on && (mrq->data->flags & MMC_DATA_READ)) {
 513		cp += 2;	/* min(N(CR)) + status */
 514		/* R1 */
 515	} else {
 516		cp += 10;	/* max(N(CR)) + status + min(N(RC),N(WR)) */
 517		if (cmd->flags & MMC_RSP_SPI_S2)	/* R2/R5 */
 518			cp++;
 519		else if (cmd->flags & MMC_RSP_SPI_B4)	/* R3/R4/R7 */
 520			cp += 4;
 521		else if (cmd->flags & MMC_RSP_BUSY)	/* R1B */
 522			cp = data->status + sizeof(data->status);
 523		/* else:  R1 (most commands) */
 524	}
 525
 526	dev_dbg(&host->spi->dev, "  mmc_spi: CMD%d, resp %s\n",
 527		cmd->opcode, maptype(cmd));
 528
 529	/* send command, leaving chipselect active */
 530	spi_message_init(&host->m);
 531
 532	t = &host->t;
 533	memset(t, 0, sizeof(*t));
 534	t->tx_buf = t->rx_buf = data->status;
 535	t->tx_dma = t->rx_dma = host->data_dma;
 536	t->len = cp - data->status;
 537	t->cs_change = 1;
 538	spi_message_add_tail(t, &host->m);
 539
 540	if (host->dma_dev) {
 541		host->m.is_dma_mapped = 1;
 542		dma_sync_single_for_device(host->dma_dev,
 543				host->data_dma, sizeof(*host->data),
 544				DMA_BIDIRECTIONAL);
 545	}
 546	status = spi_sync_locked(host->spi, &host->m);
 547
 548	if (host->dma_dev)
 549		dma_sync_single_for_cpu(host->dma_dev,
 550				host->data_dma, sizeof(*host->data),
 551				DMA_BIDIRECTIONAL);
 552	if (status < 0) {
 553		dev_dbg(&host->spi->dev, "  ... write returned %d\n", status);
 554		cmd->error = status;
 555		return status;
 556	}
 557
 558	/* after no-data commands and STOP_TRANSMISSION, chipselect off */
 559	return mmc_spi_response_get(host, cmd, cs_on);
 560}
 561
 562/* Build data message with up to four separate transfers.  For TX, we
 563 * start by writing the data token.  And in most cases, we finish with
 564 * a status transfer.
 565 *
 566 * We always provide TX data for data and CRC.  The MMC/SD protocol
 567 * requires us to write ones; but Linux defaults to writing zeroes;
 568 * so we explicitly initialize it to all ones on RX paths.
 569 *
 570 * We also handle DMA mapping, so the underlying SPI controller does
 571 * not need to (re)do it for each message.
 572 */
 573static void
 574mmc_spi_setup_data_message(
 575	struct mmc_spi_host	*host,
 576	int			multiple,
 577	enum dma_data_direction	direction)
 578{
 579	struct spi_transfer	*t;
 580	struct scratch		*scratch = host->data;
 581	dma_addr_t		dma = host->data_dma;
 582
 583	spi_message_init(&host->m);
 584	if (dma)
 585		host->m.is_dma_mapped = 1;
 586
 587	/* for reads, readblock() skips 0xff bytes before finding
 588	 * the token; for writes, this transfer issues that token.
 589	 */
 590	if (direction == DMA_TO_DEVICE) {
 591		t = &host->token;
 592		memset(t, 0, sizeof(*t));
 593		t->len = 1;
 594		if (multiple)
 595			scratch->data_token = SPI_TOKEN_MULTI_WRITE;
 596		else
 597			scratch->data_token = SPI_TOKEN_SINGLE;
 598		t->tx_buf = &scratch->data_token;
 599		if (dma)
 600			t->tx_dma = dma + offsetof(struct scratch, data_token);
 601		spi_message_add_tail(t, &host->m);
 602	}
 603
 604	/* Body of transfer is buffer, then CRC ...
 605	 * either TX-only, or RX with TX-ones.
 606	 */
 607	t = &host->t;
 608	memset(t, 0, sizeof(*t));
 609	t->tx_buf = host->ones;
 610	t->tx_dma = host->ones_dma;
 611	/* length and actual buffer info are written later */
 612	spi_message_add_tail(t, &host->m);
 613
 614	t = &host->crc;
 615	memset(t, 0, sizeof(*t));
 616	t->len = 2;
 617	if (direction == DMA_TO_DEVICE) {
 618		/* the actual CRC may get written later */
 619		t->tx_buf = &scratch->crc_val;
 620		if (dma)
 621			t->tx_dma = dma + offsetof(struct scratch, crc_val);
 622	} else {
 623		t->tx_buf = host->ones;
 624		t->tx_dma = host->ones_dma;
 625		t->rx_buf = &scratch->crc_val;
 626		if (dma)
 627			t->rx_dma = dma + offsetof(struct scratch, crc_val);
 628	}
 629	spi_message_add_tail(t, &host->m);
 630
 631	/*
 632	 * A single block read is followed by N(EC) [0+] all-ones bytes
 633	 * before deselect ... don't bother.
 634	 *
 635	 * Multiblock reads are followed by N(AC) [1+] all-ones bytes before
 636	 * the next block is read, or a STOP_TRANSMISSION is issued.  We'll
 637	 * collect that single byte, so readblock() doesn't need to.
 638	 *
 639	 * For a write, the one-byte data response follows immediately, then
 640	 * come zero or more busy bytes, then N(WR) [1+] all-ones bytes.
 641	 * Then single block reads may deselect, and multiblock ones issue
 642	 * the next token (next data block, or STOP_TRAN).  We can try to
 643	 * minimize I/O ops by using a single read to collect end-of-busy.
 644	 */
 645	if (multiple || direction == DMA_TO_DEVICE) {
 646		t = &host->early_status;
 647		memset(t, 0, sizeof(*t));
 648		t->len = (direction == DMA_TO_DEVICE)
 649				? sizeof(scratch->status)
 650				: 1;
 651		t->tx_buf = host->ones;
 652		t->tx_dma = host->ones_dma;
 653		t->rx_buf = scratch->status;
 654		if (dma)
 655			t->rx_dma = dma + offsetof(struct scratch, status);
 656		t->cs_change = 1;
 657		spi_message_add_tail(t, &host->m);
 658	}
 659}
 660
 661/*
 662 * Write one block:
 663 *  - caller handled preceding N(WR) [1+] all-ones bytes
 664 *  - data block
 665 *	+ token
 666 *	+ data bytes
 667 *	+ crc16
 668 *  - an all-ones byte ... card writes a data-response byte
 669 *  - followed by N(EC) [0+] all-ones bytes, card writes zero/'busy'
 670 *
 671 * Return negative errno, else success.
 672 */
 673static int
 674mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t,
 675	unsigned long timeout)
 676{
 677	struct spi_device	*spi = host->spi;
 678	int			status, i;
 679	struct scratch		*scratch = host->data;
 680	u32			pattern;
 681
 682	if (host->mmc->use_spi_crc)
 683		scratch->crc_val = cpu_to_be16(
 684				crc_itu_t(0, t->tx_buf, t->len));
 685	if (host->dma_dev)
 686		dma_sync_single_for_device(host->dma_dev,
 687				host->data_dma, sizeof(*scratch),
 688				DMA_BIDIRECTIONAL);
 689
 690	status = spi_sync_locked(spi, &host->m);
 691
 692	if (status != 0) {
 693		dev_dbg(&spi->dev, "write error (%d)\n", status);
 694		return status;
 695	}
 696
 697	if (host->dma_dev)
 698		dma_sync_single_for_cpu(host->dma_dev,
 699				host->data_dma, sizeof(*scratch),
 700				DMA_BIDIRECTIONAL);
 701
 702	/*
 703	 * Get the transmission data-response reply.  It must follow
 704	 * immediately after the data block we transferred.  This reply
 705	 * doesn't necessarily tell whether the write operation succeeded;
 706	 * it just says if the transmission was ok and whether *earlier*
 707	 * writes succeeded; see the standard.
 708	 *
 709	 * In practice, there are (even modern SDHC-)cards which are late
 710	 * in sending the response, and miss the time frame by a few bits,
 711	 * so we have to cope with this situation and check the response
 712	 * bit-by-bit. Arggh!!!
 713	 */
 714	pattern  = scratch->status[0] << 24;
 715	pattern |= scratch->status[1] << 16;
 716	pattern |= scratch->status[2] << 8;
 717	pattern |= scratch->status[3];
 718
 719	/* First 3 bit of pattern are undefined */
 720	pattern |= 0xE0000000;
 721
 722	/* left-adjust to leading 0 bit */
 723	while (pattern & 0x80000000)
 724		pattern <<= 1;
 725	/* right-adjust for pattern matching. Code is in bit 4..0 now. */
 726	pattern >>= 27;
 727
 728	switch (pattern) {
 729	case SPI_RESPONSE_ACCEPTED:
 730		status = 0;
 731		break;
 732	case SPI_RESPONSE_CRC_ERR:
 733		/* host shall then issue MMC_STOP_TRANSMISSION */
 734		status = -EILSEQ;
 735		break;
 736	case SPI_RESPONSE_WRITE_ERR:
 737		/* host shall then issue MMC_STOP_TRANSMISSION,
 738		 * and should MMC_SEND_STATUS to sort it out
 739		 */
 740		status = -EIO;
 741		break;
 742	default:
 743		status = -EPROTO;
 744		break;
 745	}
 746	if (status != 0) {
 747		dev_dbg(&spi->dev, "write error %02x (%d)\n",
 748			scratch->status[0], status);
 749		return status;
 750	}
 751
 752	t->tx_buf += t->len;
 753	if (host->dma_dev)
 754		t->tx_dma += t->len;
 755
 756	/* Return when not busy.  If we didn't collect that status yet,
 757	 * we'll need some more I/O.
 758	 */
 759	for (i = 4; i < sizeof(scratch->status); i++) {
 760		/* card is non-busy if the most recent bit is 1 */
 761		if (scratch->status[i] & 0x01)
 762			return 0;
 763	}
 764	return mmc_spi_wait_unbusy(host, timeout);
 765}
 766
 767/*
 768 * Read one block:
 769 *  - skip leading all-ones bytes ... either
 770 *      + N(AC) [1..f(clock,CSD)] usually, else
 771 *      + N(CX) [0..8] when reading CSD or CID
 772 *  - data block
 773 *	+ token ... if error token, no data or crc
 774 *	+ data bytes
 775 *	+ crc16
 776 *
 777 * After single block reads, we're done; N(EC) [0+] all-ones bytes follow
 778 * before dropping chipselect.
 779 *
 780 * For multiblock reads, caller either reads the next block or issues a
 781 * STOP_TRANSMISSION command.
 782 */
 783static int
 784mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t,
 785	unsigned long timeout)
 786{
 787	struct spi_device	*spi = host->spi;
 788	int			status;
 789	struct scratch		*scratch = host->data;
 790	unsigned int 		bitshift;
 791	u8			leftover;
 792
 793	/* At least one SD card sends an all-zeroes byte when N(CX)
 794	 * applies, before the all-ones bytes ... just cope with that.
 795	 */
 796	status = mmc_spi_readbytes(host, 1);
 797	if (status < 0)
 798		return status;
 799	status = scratch->status[0];
 800	if (status == 0xff || status == 0)
 801		status = mmc_spi_readtoken(host, timeout);
 802
 803	if (status < 0) {
 804		dev_dbg(&spi->dev, "read error %02x (%d)\n", status, status);
 805		return status;
 806	}
 807
 808	/* The token may be bit-shifted...
 809	 * the first 0-bit precedes the data stream.
 810	 */
 811	bitshift = 7;
 812	while (status & 0x80) {
 813		status <<= 1;
 814		bitshift--;
 815	}
 816	leftover = status << 1;
 817
 818	if (host->dma_dev) {
 819		dma_sync_single_for_device(host->dma_dev,
 820				host->data_dma, sizeof(*scratch),
 821				DMA_BIDIRECTIONAL);
 822		dma_sync_single_for_device(host->dma_dev,
 823				t->rx_dma, t->len,
 824				DMA_FROM_DEVICE);
 825	}
 826
 827	status = spi_sync_locked(spi, &host->m);
 
 
 
 
 828
 829	if (host->dma_dev) {
 830		dma_sync_single_for_cpu(host->dma_dev,
 831				host->data_dma, sizeof(*scratch),
 832				DMA_BIDIRECTIONAL);
 833		dma_sync_single_for_cpu(host->dma_dev,
 834				t->rx_dma, t->len,
 835				DMA_FROM_DEVICE);
 836	}
 837
 838	if (bitshift) {
 839		/* Walk through the data and the crc and do
 840		 * all the magic to get byte-aligned data.
 841		 */
 842		u8 *cp = t->rx_buf;
 843		unsigned int len;
 844		unsigned int bitright = 8 - bitshift;
 845		u8 temp;
 846		for (len = t->len; len; len--) {
 847			temp = *cp;
 848			*cp++ = leftover | (temp >> bitshift);
 849			leftover = temp << bitright;
 850		}
 851		cp = (u8 *) &scratch->crc_val;
 852		temp = *cp;
 853		*cp++ = leftover | (temp >> bitshift);
 854		leftover = temp << bitright;
 855		temp = *cp;
 856		*cp = leftover | (temp >> bitshift);
 857	}
 858
 859	if (host->mmc->use_spi_crc) {
 860		u16 crc = crc_itu_t(0, t->rx_buf, t->len);
 861
 862		be16_to_cpus(&scratch->crc_val);
 863		if (scratch->crc_val != crc) {
 864			dev_dbg(&spi->dev, "read - crc error: crc_val=0x%04x, "
 865					"computed=0x%04x len=%d\n",
 866					scratch->crc_val, crc, t->len);
 867			return -EILSEQ;
 868		}
 869	}
 870
 871	t->rx_buf += t->len;
 872	if (host->dma_dev)
 873		t->rx_dma += t->len;
 874
 875	return 0;
 876}
 877
 878/*
 879 * An MMC/SD data stage includes one or more blocks, optional CRCs,
 880 * and inline handshaking.  That handhaking makes it unlike most
 881 * other SPI protocol stacks.
 882 */
 883static void
 884mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd,
 885		struct mmc_data *data, u32 blk_size)
 886{
 887	struct spi_device	*spi = host->spi;
 888	struct device		*dma_dev = host->dma_dev;
 889	struct spi_transfer	*t;
 890	enum dma_data_direction	direction;
 891	struct scatterlist	*sg;
 892	unsigned		n_sg;
 893	int			multiple = (data->blocks > 1);
 894	u32			clock_rate;
 895	unsigned long		timeout;
 896
 897	if (data->flags & MMC_DATA_READ)
 898		direction = DMA_FROM_DEVICE;
 899	else
 900		direction = DMA_TO_DEVICE;
 901	mmc_spi_setup_data_message(host, multiple, direction);
 902	t = &host->t;
 903
 904	if (t->speed_hz)
 905		clock_rate = t->speed_hz;
 906	else
 907		clock_rate = spi->max_speed_hz;
 908
 909	timeout = data->timeout_ns +
 910		  data->timeout_clks * 1000000 / clock_rate;
 911	timeout = usecs_to_jiffies((unsigned int)(timeout / 1000)) + 1;
 912
 913	/* Handle scatterlist segments one at a time, with synch for
 914	 * each 512-byte block
 915	 */
 916	for (sg = data->sg, n_sg = data->sg_len; n_sg; n_sg--, sg++) {
 917		int			status = 0;
 918		dma_addr_t		dma_addr = 0;
 919		void			*kmap_addr;
 920		unsigned		length = sg->length;
 921		enum dma_data_direction	dir = direction;
 922
 923		/* set up dma mapping for controller drivers that might
 924		 * use DMA ... though they may fall back to PIO
 925		 */
 926		if (dma_dev) {
 927			/* never invalidate whole *shared* pages ... */
 928			if ((sg->offset != 0 || length != PAGE_SIZE)
 929					&& dir == DMA_FROM_DEVICE)
 930				dir = DMA_BIDIRECTIONAL;
 931
 932			dma_addr = dma_map_page(dma_dev, sg_page(sg), 0,
 933						PAGE_SIZE, dir);
 
 
 
 
 934			if (direction == DMA_TO_DEVICE)
 935				t->tx_dma = dma_addr + sg->offset;
 936			else
 937				t->rx_dma = dma_addr + sg->offset;
 938		}
 939
 940		/* allow pio too; we don't allow highmem */
 941		kmap_addr = kmap(sg_page(sg));
 942		if (direction == DMA_TO_DEVICE)
 943			t->tx_buf = kmap_addr + sg->offset;
 944		else
 945			t->rx_buf = kmap_addr + sg->offset;
 946
 947		/* transfer each block, and update request status */
 948		while (length) {
 949			t->len = min(length, blk_size);
 950
 951			dev_dbg(&host->spi->dev,
 952				"    mmc_spi: %s block, %d bytes\n",
 953				(direction == DMA_TO_DEVICE)
 954				? "write"
 955				: "read",
 956				t->len);
 957
 958			if (direction == DMA_TO_DEVICE)
 959				status = mmc_spi_writeblock(host, t, timeout);
 960			else
 961				status = mmc_spi_readblock(host, t, timeout);
 962			if (status < 0)
 963				break;
 964
 965			data->bytes_xfered += t->len;
 966			length -= t->len;
 967
 968			if (!multiple)
 969				break;
 970		}
 971
 972		/* discard mappings */
 973		if (direction == DMA_FROM_DEVICE)
 974			flush_kernel_dcache_page(sg_page(sg));
 975		kunmap(sg_page(sg));
 976		if (dma_dev)
 977			dma_unmap_page(dma_dev, dma_addr, PAGE_SIZE, dir);
 978
 979		if (status < 0) {
 980			data->error = status;
 981			dev_dbg(&spi->dev, "%s status %d\n",
 982				(direction == DMA_TO_DEVICE)
 983					? "write" : "read",
 984				status);
 985			break;
 986		}
 987	}
 988
 989	/* NOTE some docs describe an MMC-only SET_BLOCK_COUNT (CMD23) that
 990	 * can be issued before multiblock writes.  Unlike its more widely
 991	 * documented analogue for SD cards (SET_WR_BLK_ERASE_COUNT, ACMD23),
 992	 * that can affect the STOP_TRAN logic.   Complete (and current)
 993	 * MMC specs should sort that out before Linux starts using CMD23.
 994	 */
 995	if (direction == DMA_TO_DEVICE && multiple) {
 996		struct scratch	*scratch = host->data;
 997		int		tmp;
 998		const unsigned	statlen = sizeof(scratch->status);
 999
1000		dev_dbg(&spi->dev, "    mmc_spi: STOP_TRAN\n");
1001
1002		/* Tweak the per-block message we set up earlier by morphing
1003		 * it to hold single buffer with the token followed by some
1004		 * all-ones bytes ... skip N(BR) (0..1), scan the rest for
1005		 * "not busy any longer" status, and leave chip selected.
1006		 */
1007		INIT_LIST_HEAD(&host->m.transfers);
1008		list_add(&host->early_status.transfer_list,
1009				&host->m.transfers);
1010
1011		memset(scratch->status, 0xff, statlen);
1012		scratch->status[0] = SPI_TOKEN_STOP_TRAN;
1013
1014		host->early_status.tx_buf = host->early_status.rx_buf;
1015		host->early_status.tx_dma = host->early_status.rx_dma;
1016		host->early_status.len = statlen;
1017
1018		if (host->dma_dev)
1019			dma_sync_single_for_device(host->dma_dev,
1020					host->data_dma, sizeof(*scratch),
1021					DMA_BIDIRECTIONAL);
1022
1023		tmp = spi_sync_locked(spi, &host->m);
1024
1025		if (host->dma_dev)
1026			dma_sync_single_for_cpu(host->dma_dev,
1027					host->data_dma, sizeof(*scratch),
1028					DMA_BIDIRECTIONAL);
1029
1030		if (tmp < 0) {
1031			if (!data->error)
1032				data->error = tmp;
1033			return;
1034		}
1035
1036		/* Ideally we collected "not busy" status with one I/O,
1037		 * avoiding wasteful byte-at-a-time scanning... but more
1038		 * I/O is often needed.
1039		 */
1040		for (tmp = 2; tmp < statlen; tmp++) {
1041			if (scratch->status[tmp] != 0)
1042				return;
1043		}
1044		tmp = mmc_spi_wait_unbusy(host, timeout);
1045		if (tmp < 0 && !data->error)
1046			data->error = tmp;
1047	}
1048}
1049
1050/****************************************************************************/
1051
1052/*
1053 * MMC driver implementation -- the interface to the MMC stack
1054 */
1055
1056static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq)
1057{
1058	struct mmc_spi_host	*host = mmc_priv(mmc);
1059	int			status = -EINVAL;
1060	int			crc_retry = 5;
1061	struct mmc_command	stop;
1062
1063#ifdef DEBUG
1064	/* MMC core and layered drivers *MUST* issue SPI-aware commands */
1065	{
1066		struct mmc_command	*cmd;
1067		int			invalid = 0;
1068
1069		cmd = mrq->cmd;
1070		if (!mmc_spi_resp_type(cmd)) {
1071			dev_dbg(&host->spi->dev, "bogus command\n");
1072			cmd->error = -EINVAL;
1073			invalid = 1;
1074		}
1075
1076		cmd = mrq->stop;
1077		if (cmd && !mmc_spi_resp_type(cmd)) {
1078			dev_dbg(&host->spi->dev, "bogus STOP command\n");
1079			cmd->error = -EINVAL;
1080			invalid = 1;
1081		}
1082
1083		if (invalid) {
1084			dump_stack();
1085			mmc_request_done(host->mmc, mrq);
1086			return;
1087		}
1088	}
1089#endif
1090
1091	/* request exclusive bus access */
1092	spi_bus_lock(host->spi->master);
1093
1094crc_recover:
1095	/* issue command; then optionally data and stop */
1096	status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL);
1097	if (status == 0 && mrq->data) {
1098		mmc_spi_data_do(host, mrq->cmd, mrq->data, mrq->data->blksz);
1099
1100		/*
1101		 * The SPI bus is not always reliable for large data transfers.
1102		 * If an occasional crc error is reported by the SD device with
1103		 * data read/write over SPI, it may be recovered by repeating
1104		 * the last SD command again. The retry count is set to 5 to
1105		 * ensure the driver passes stress tests.
1106		 */
1107		if (mrq->data->error == -EILSEQ && crc_retry) {
1108			stop.opcode = MMC_STOP_TRANSMISSION;
1109			stop.arg = 0;
1110			stop.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
1111			status = mmc_spi_command_send(host, mrq, &stop, 0);
1112			crc_retry--;
1113			mrq->data->error = 0;
1114			goto crc_recover;
1115		}
1116
1117		if (mrq->stop)
1118			status = mmc_spi_command_send(host, mrq, mrq->stop, 0);
1119		else
1120			mmc_cs_off(host);
1121	}
1122
1123	/* release the bus */
1124	spi_bus_unlock(host->spi->master);
1125
1126	mmc_request_done(host->mmc, mrq);
1127}
1128
1129/* See Section 6.4.1, in SD "Simplified Physical Layer Specification 2.0"
1130 *
1131 * NOTE that here we can't know that the card has just been powered up;
1132 * not all MMC/SD sockets support power switching.
1133 *
1134 * FIXME when the card is still in SPI mode, e.g. from a previous kernel,
1135 * this doesn't seem to do the right thing at all...
1136 */
1137static void mmc_spi_initsequence(struct mmc_spi_host *host)
1138{
1139	/* Try to be very sure any previous command has completed;
1140	 * wait till not-busy, skip debris from any old commands.
1141	 */
1142	mmc_spi_wait_unbusy(host, r1b_timeout);
1143	mmc_spi_readbytes(host, 10);
1144
1145	/*
1146	 * Do a burst with chipselect active-high.  We need to do this to
1147	 * meet the requirement of 74 clock cycles with both chipselect
1148	 * and CMD (MOSI) high before CMD0 ... after the card has been
1149	 * powered up to Vdd(min), and so is ready to take commands.
1150	 *
1151	 * Some cards are particularly needy of this (e.g. Viking "SD256")
1152	 * while most others don't seem to care.
1153	 *
1154	 * Note that this is one of the places MMC/SD plays games with the
1155	 * SPI protocol.  Another is that when chipselect is released while
1156	 * the card returns BUSY status, the clock must issue several cycles
1157	 * with chipselect high before the card will stop driving its output.
 
 
 
 
 
1158	 */
1159	host->spi->mode |= SPI_CS_HIGH;
1160	if (spi_setup(host->spi) != 0) {
1161		/* Just warn; most cards work without it. */
1162		dev_warn(&host->spi->dev,
1163				"can't change chip-select polarity\n");
1164		host->spi->mode &= ~SPI_CS_HIGH;
1165	} else {
1166		mmc_spi_readbytes(host, 18);
1167
1168		host->spi->mode &= ~SPI_CS_HIGH;
1169		if (spi_setup(host->spi) != 0) {
1170			/* Wot, we can't get the same setup we had before? */
1171			dev_err(&host->spi->dev,
1172					"can't restore chip-select polarity\n");
1173		}
1174	}
1175}
1176
1177static char *mmc_powerstring(u8 power_mode)
1178{
1179	switch (power_mode) {
1180	case MMC_POWER_OFF: return "off";
1181	case MMC_POWER_UP:  return "up";
1182	case MMC_POWER_ON:  return "on";
1183	}
1184	return "?";
1185}
1186
1187static void mmc_spi_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1188{
1189	struct mmc_spi_host *host = mmc_priv(mmc);
1190
1191	if (host->power_mode != ios->power_mode) {
1192		int		canpower;
1193
1194		canpower = host->pdata && host->pdata->setpower;
1195
1196		dev_dbg(&host->spi->dev, "mmc_spi: power %s (%d)%s\n",
1197				mmc_powerstring(ios->power_mode),
1198				ios->vdd,
1199				canpower ? ", can switch" : "");
1200
1201		/* switch power on/off if possible, accounting for
1202		 * max 250msec powerup time if needed.
1203		 */
1204		if (canpower) {
1205			switch (ios->power_mode) {
1206			case MMC_POWER_OFF:
1207			case MMC_POWER_UP:
1208				host->pdata->setpower(&host->spi->dev,
1209						ios->vdd);
1210				if (ios->power_mode == MMC_POWER_UP)
1211					msleep(host->powerup_msecs);
1212			}
1213		}
1214
1215		/* See 6.4.1 in the simplified SD card physical spec 2.0 */
1216		if (ios->power_mode == MMC_POWER_ON)
1217			mmc_spi_initsequence(host);
1218
1219		/* If powering down, ground all card inputs to avoid power
1220		 * delivery from data lines!  On a shared SPI bus, this
1221		 * will probably be temporary; 6.4.2 of the simplified SD
1222		 * spec says this must last at least 1msec.
1223		 *
1224		 *   - Clock low means CPOL 0, e.g. mode 0
1225		 *   - MOSI low comes from writing zero
1226		 *   - Chipselect is usually active low...
1227		 */
1228		if (canpower && ios->power_mode == MMC_POWER_OFF) {
1229			int mres;
1230			u8 nullbyte = 0;
1231
1232			host->spi->mode &= ~(SPI_CPOL|SPI_CPHA);
1233			mres = spi_setup(host->spi);
1234			if (mres < 0)
1235				dev_dbg(&host->spi->dev,
1236					"switch to SPI mode 0 failed\n");
1237
1238			if (spi_write(host->spi, &nullbyte, 1) < 0)
1239				dev_dbg(&host->spi->dev,
1240					"put spi signals to low failed\n");
1241
1242			/*
1243			 * Now clock should be low due to spi mode 0;
1244			 * MOSI should be low because of written 0x00;
1245			 * chipselect should be low (it is active low)
1246			 * power supply is off, so now MMC is off too!
1247			 *
1248			 * FIXME no, chipselect can be high since the
1249			 * device is inactive and SPI_CS_HIGH is clear...
1250			 */
1251			msleep(10);
1252			if (mres == 0) {
1253				host->spi->mode |= (SPI_CPOL|SPI_CPHA);
1254				mres = spi_setup(host->spi);
1255				if (mres < 0)
1256					dev_dbg(&host->spi->dev,
1257						"switch back to SPI mode 3"
1258						" failed\n");
1259			}
1260		}
1261
1262		host->power_mode = ios->power_mode;
1263	}
1264
1265	if (host->spi->max_speed_hz != ios->clock && ios->clock != 0) {
1266		int		status;
1267
1268		host->spi->max_speed_hz = ios->clock;
1269		status = spi_setup(host->spi);
1270		dev_dbg(&host->spi->dev,
1271			"mmc_spi:  clock to %d Hz, %d\n",
1272			host->spi->max_speed_hz, status);
1273	}
1274}
1275
1276static const struct mmc_host_ops mmc_spi_ops = {
1277	.request	= mmc_spi_request,
1278	.set_ios	= mmc_spi_set_ios,
1279	.get_ro		= mmc_gpio_get_ro,
1280	.get_cd		= mmc_gpio_get_cd,
1281};
1282
1283
1284/****************************************************************************/
1285
1286/*
1287 * SPI driver implementation
1288 */
1289
1290static irqreturn_t
1291mmc_spi_detect_irq(int irq, void *mmc)
1292{
1293	struct mmc_spi_host *host = mmc_priv(mmc);
1294	u16 delay_msec = max(host->pdata->detect_delay, (u16)100);
1295
1296	mmc_detect_change(mmc, msecs_to_jiffies(delay_msec));
1297	return IRQ_HANDLED;
1298}
1299
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1300static int mmc_spi_probe(struct spi_device *spi)
1301{
1302	void			*ones;
1303	struct mmc_host		*mmc;
1304	struct mmc_spi_host	*host;
1305	int			status;
1306	bool			has_ro = false;
1307
1308	/* We rely on full duplex transfers, mostly to reduce
1309	 * per-transfer overheads (by making fewer transfers).
1310	 */
1311	if (spi->master->flags & SPI_MASTER_HALF_DUPLEX)
1312		return -EINVAL;
1313
1314	/* MMC and SD specs only seem to care that sampling is on the
1315	 * rising edge ... meaning SPI modes 0 or 3.  So either SPI mode
1316	 * should be legit.  We'll use mode 0 since the steady state is 0,
1317	 * which is appropriate for hotplugging, unless the platform data
1318	 * specify mode 3 (if hardware is not compatible to mode 0).
1319	 */
1320	if (spi->mode != SPI_MODE_3)
1321		spi->mode = SPI_MODE_0;
1322	spi->bits_per_word = 8;
1323
1324	status = spi_setup(spi);
1325	if (status < 0) {
1326		dev_dbg(&spi->dev, "needs SPI mode %02x, %d KHz; %d\n",
1327				spi->mode, spi->max_speed_hz / 1000,
1328				status);
1329		return status;
1330	}
1331
1332	/* We need a supply of ones to transmit.  This is the only time
1333	 * the CPU touches these, so cache coherency isn't a concern.
1334	 *
1335	 * NOTE if many systems use more than one MMC-over-SPI connector
1336	 * it'd save some memory to share this.  That's evidently rare.
1337	 */
1338	status = -ENOMEM;
1339	ones = kmalloc(MMC_SPI_BLOCKSIZE, GFP_KERNEL);
1340	if (!ones)
1341		goto nomem;
1342	memset(ones, 0xff, MMC_SPI_BLOCKSIZE);
1343
1344	mmc = mmc_alloc_host(sizeof(*host), &spi->dev);
1345	if (!mmc)
1346		goto nomem;
1347
1348	mmc->ops = &mmc_spi_ops;
1349	mmc->max_blk_size = MMC_SPI_BLOCKSIZE;
1350	mmc->max_segs = MMC_SPI_BLOCKSATONCE;
1351	mmc->max_req_size = MMC_SPI_BLOCKSATONCE * MMC_SPI_BLOCKSIZE;
1352	mmc->max_blk_count = MMC_SPI_BLOCKSATONCE;
1353
1354	mmc->caps = MMC_CAP_SPI;
1355
1356	/* SPI doesn't need the lowspeed device identification thing for
1357	 * MMC or SD cards, since it never comes up in open drain mode.
1358	 * That's good; some SPI masters can't handle very low speeds!
1359	 *
1360	 * However, low speed SDIO cards need not handle over 400 KHz;
1361	 * that's the only reason not to use a few MHz for f_min (until
1362	 * the upper layer reads the target frequency from the CSD).
1363	 */
1364	mmc->f_min = 400000;
1365	mmc->f_max = spi->max_speed_hz;
1366
1367	host = mmc_priv(mmc);
1368	host->mmc = mmc;
1369	host->spi = spi;
1370
1371	host->ones = ones;
1372
1373	/* Platform data is used to hook up things like card sensing
1374	 * and power switching gpios.
1375	 */
1376	host->pdata = mmc_spi_get_pdata(spi);
1377	if (host->pdata)
1378		mmc->ocr_avail = host->pdata->ocr_mask;
1379	if (!mmc->ocr_avail) {
1380		dev_warn(&spi->dev, "ASSUMING 3.2-3.4 V slot power\n");
1381		mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
1382	}
1383	if (host->pdata && host->pdata->setpower) {
1384		host->powerup_msecs = host->pdata->powerup_msecs;
1385		if (!host->powerup_msecs || host->powerup_msecs > 250)
1386			host->powerup_msecs = 250;
1387	}
1388
1389	dev_set_drvdata(&spi->dev, mmc);
1390
1391	/* preallocate dma buffers */
1392	host->data = kmalloc(sizeof(*host->data), GFP_KERNEL);
1393	if (!host->data)
1394		goto fail_nobuf1;
1395
1396	if (spi->master->dev.parent->dma_mask) {
1397		struct device	*dev = spi->master->dev.parent;
1398
1399		host->dma_dev = dev;
1400		host->ones_dma = dma_map_single(dev, ones,
1401				MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE);
1402		host->data_dma = dma_map_single(dev, host->data,
1403				sizeof(*host->data), DMA_BIDIRECTIONAL);
1404
1405		/* REVISIT in theory those map operations can fail... */
1406
1407		dma_sync_single_for_cpu(host->dma_dev,
1408				host->data_dma, sizeof(*host->data),
1409				DMA_BIDIRECTIONAL);
1410	}
1411
1412	/* setup message for status/busy readback */
1413	spi_message_init(&host->readback);
1414	host->readback.is_dma_mapped = (host->dma_dev != NULL);
1415
1416	spi_message_add_tail(&host->status, &host->readback);
1417	host->status.tx_buf = host->ones;
1418	host->status.tx_dma = host->ones_dma;
1419	host->status.rx_buf = &host->data->status;
1420	host->status.rx_dma = host->data_dma + offsetof(struct scratch, status);
1421	host->status.cs_change = 1;
1422
1423	/* register card detect irq */
1424	if (host->pdata && host->pdata->init) {
1425		status = host->pdata->init(&spi->dev, mmc_spi_detect_irq, mmc);
1426		if (status != 0)
1427			goto fail_glue_init;
1428	}
1429
1430	/* pass platform capabilities, if any */
1431	if (host->pdata) {
1432		mmc->caps |= host->pdata->caps;
1433		mmc->caps2 |= host->pdata->caps2;
1434	}
1435
1436	status = mmc_add_host(mmc);
1437	if (status != 0)
1438		goto fail_add_host;
1439
1440	if (host->pdata && host->pdata->flags & MMC_SPI_USE_CD_GPIO) {
1441		status = mmc_gpio_request_cd(mmc, host->pdata->cd_gpio,
1442					     host->pdata->cd_debounce);
1443		if (status != 0)
1444			goto fail_add_host;
 
 
 
 
 
 
 
 
 
 
1445	}
 
1446
1447	if (host->pdata && host->pdata->flags & MMC_SPI_USE_RO_GPIO) {
 
 
 
 
1448		has_ro = true;
1449		status = mmc_gpio_request_ro(mmc, host->pdata->ro_gpio);
1450		if (status != 0)
1451			goto fail_add_host;
1452	}
1453
1454	dev_info(&spi->dev, "SD/MMC host %s%s%s%s%s\n",
1455			dev_name(&mmc->class_dev),
1456			host->dma_dev ? "" : ", no DMA",
1457			has_ro ? "" : ", no WP",
1458			(host->pdata && host->pdata->setpower)
1459				? "" : ", no poweroff",
1460			(mmc->caps & MMC_CAP_NEEDS_POLL)
1461				? ", cd polling" : "");
1462	return 0;
1463
1464fail_add_host:
1465	mmc_remove_host (mmc);
1466fail_glue_init:
1467	if (host->dma_dev)
1468		dma_unmap_single(host->dma_dev, host->data_dma,
1469				sizeof(*host->data), DMA_BIDIRECTIONAL);
1470	kfree(host->data);
1471
1472fail_nobuf1:
1473	mmc_free_host(mmc);
1474	mmc_spi_put_pdata(spi);
1475	dev_set_drvdata(&spi->dev, NULL);
1476
1477nomem:
1478	kfree(ones);
1479	return status;
1480}
1481
1482
1483static int mmc_spi_remove(struct spi_device *spi)
1484{
1485	struct mmc_host		*mmc = dev_get_drvdata(&spi->dev);
1486	struct mmc_spi_host	*host;
1487
1488	if (mmc) {
1489		host = mmc_priv(mmc);
1490
1491		/* prevent new mmc_detect_change() calls */
1492		if (host->pdata && host->pdata->exit)
1493			host->pdata->exit(&spi->dev, mmc);
1494
1495		mmc_remove_host(mmc);
 
 
1496
1497		if (host->dma_dev) {
1498			dma_unmap_single(host->dma_dev, host->ones_dma,
1499				MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE);
1500			dma_unmap_single(host->dma_dev, host->data_dma,
1501				sizeof(*host->data), DMA_BIDIRECTIONAL);
1502		}
1503
1504		kfree(host->data);
1505		kfree(host->ones);
 
1506
1507		spi->max_speed_hz = mmc->f_max;
1508		mmc_free_host(mmc);
1509		mmc_spi_put_pdata(spi);
1510		dev_set_drvdata(&spi->dev, NULL);
1511	}
1512	return 0;
1513}
1514
1515static struct of_device_id mmc_spi_of_match_table[] = {
1516	{ .compatible = "mmc-spi-slot", },
1517	{},
1518};
 
1519
1520static struct spi_driver mmc_spi_driver = {
1521	.driver = {
1522		.name =		"mmc_spi",
1523		.owner =	THIS_MODULE,
1524		.of_match_table = mmc_spi_of_match_table,
1525	},
1526	.probe =	mmc_spi_probe,
1527	.remove =	mmc_spi_remove,
1528};
1529
1530module_spi_driver(mmc_spi_driver);
1531
1532MODULE_AUTHOR("Mike Lavender, David Brownell, "
1533		"Hans-Peter Nilsson, Jan Nikitenko");
1534MODULE_DESCRIPTION("SPI SD/MMC host driver");
1535MODULE_LICENSE("GPL");
1536MODULE_ALIAS("spi:mmc_spi");