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1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef _DW_MMC_H_
15#define _DW_MMC_H_
16
17#define DW_MMC_240A 0x240a
18
19#define SDMMC_CTRL 0x000
20#define SDMMC_PWREN 0x004
21#define SDMMC_CLKDIV 0x008
22#define SDMMC_CLKSRC 0x00c
23#define SDMMC_CLKENA 0x010
24#define SDMMC_TMOUT 0x014
25#define SDMMC_CTYPE 0x018
26#define SDMMC_BLKSIZ 0x01c
27#define SDMMC_BYTCNT 0x020
28#define SDMMC_INTMASK 0x024
29#define SDMMC_CMDARG 0x028
30#define SDMMC_CMD 0x02c
31#define SDMMC_RESP0 0x030
32#define SDMMC_RESP1 0x034
33#define SDMMC_RESP2 0x038
34#define SDMMC_RESP3 0x03c
35#define SDMMC_MINTSTS 0x040
36#define SDMMC_RINTSTS 0x044
37#define SDMMC_STATUS 0x048
38#define SDMMC_FIFOTH 0x04c
39#define SDMMC_CDETECT 0x050
40#define SDMMC_WRTPRT 0x054
41#define SDMMC_GPIO 0x058
42#define SDMMC_TCBCNT 0x05c
43#define SDMMC_TBBCNT 0x060
44#define SDMMC_DEBNCE 0x064
45#define SDMMC_USRID 0x068
46#define SDMMC_VERID 0x06c
47#define SDMMC_HCON 0x070
48#define SDMMC_UHS_REG 0x074
49#define SDMMC_BMOD 0x080
50#define SDMMC_PLDMND 0x084
51#define SDMMC_DBADDR 0x088
52#define SDMMC_IDSTS 0x08c
53#define SDMMC_IDINTEN 0x090
54#define SDMMC_DSCADDR 0x094
55#define SDMMC_BUFADDR 0x098
56#define SDMMC_CDTHRCTL 0x100
57#define SDMMC_DATA(x) (x)
58
59/*
60 * Data offset is difference according to Version
61 * Lower than 2.40a : data register offest is 0x100
62 */
63#define DATA_OFFSET 0x100
64#define DATA_240A_OFFSET 0x200
65
66/* shift bit field */
67#define _SBF(f, v) ((v) << (f))
68
69/* Control register defines */
70#define SDMMC_CTRL_USE_IDMAC BIT(25)
71#define SDMMC_CTRL_CEATA_INT_EN BIT(11)
72#define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
73#define SDMMC_CTRL_SEND_CCSD BIT(9)
74#define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
75#define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
76#define SDMMC_CTRL_READ_WAIT BIT(6)
77#define SDMMC_CTRL_DMA_ENABLE BIT(5)
78#define SDMMC_CTRL_INT_ENABLE BIT(4)
79#define SDMMC_CTRL_DMA_RESET BIT(2)
80#define SDMMC_CTRL_FIFO_RESET BIT(1)
81#define SDMMC_CTRL_RESET BIT(0)
82/* Clock Enable register defines */
83#define SDMMC_CLKEN_LOW_PWR BIT(16)
84#define SDMMC_CLKEN_ENABLE BIT(0)
85/* time-out register defines */
86#define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
87#define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
88#define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
89#define SDMMC_TMOUT_RESP_MSK 0xFF
90/* card-type register defines */
91#define SDMMC_CTYPE_8BIT BIT(16)
92#define SDMMC_CTYPE_4BIT BIT(0)
93#define SDMMC_CTYPE_1BIT 0
94/* Interrupt status & mask register defines */
95#define SDMMC_INT_SDIO(n) BIT(16 + (n))
96#define SDMMC_INT_EBE BIT(15)
97#define SDMMC_INT_ACD BIT(14)
98#define SDMMC_INT_SBE BIT(13)
99#define SDMMC_INT_HLE BIT(12)
100#define SDMMC_INT_FRUN BIT(11)
101#define SDMMC_INT_HTO BIT(10)
102#define SDMMC_INT_DRTO BIT(9)
103#define SDMMC_INT_RTO BIT(8)
104#define SDMMC_INT_DCRC BIT(7)
105#define SDMMC_INT_RCRC BIT(6)
106#define SDMMC_INT_RXDR BIT(5)
107#define SDMMC_INT_TXDR BIT(4)
108#define SDMMC_INT_DATA_OVER BIT(3)
109#define SDMMC_INT_CMD_DONE BIT(2)
110#define SDMMC_INT_RESP_ERR BIT(1)
111#define SDMMC_INT_CD BIT(0)
112#define SDMMC_INT_ERROR 0xbfc2
113/* Command register defines */
114#define SDMMC_CMD_START BIT(31)
115#define SDMMC_CMD_USE_HOLD_REG BIT(29)
116#define SDMMC_CMD_CCS_EXP BIT(23)
117#define SDMMC_CMD_CEATA_RD BIT(22)
118#define SDMMC_CMD_UPD_CLK BIT(21)
119#define SDMMC_CMD_INIT BIT(15)
120#define SDMMC_CMD_STOP BIT(14)
121#define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
122#define SDMMC_CMD_SEND_STOP BIT(12)
123#define SDMMC_CMD_STRM_MODE BIT(11)
124#define SDMMC_CMD_DAT_WR BIT(10)
125#define SDMMC_CMD_DAT_EXP BIT(9)
126#define SDMMC_CMD_RESP_CRC BIT(8)
127#define SDMMC_CMD_RESP_LONG BIT(7)
128#define SDMMC_CMD_RESP_EXP BIT(6)
129#define SDMMC_CMD_INDX(n) ((n) & 0x1F)
130/* Status register defines */
131#define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
132/* FIFOTH register defines */
133#define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
134 ((r) & 0xFFF) << 16 | \
135 ((t) & 0xFFF))
136/* Internal DMAC interrupt defines */
137#define SDMMC_IDMAC_INT_AI BIT(9)
138#define SDMMC_IDMAC_INT_NI BIT(8)
139#define SDMMC_IDMAC_INT_CES BIT(5)
140#define SDMMC_IDMAC_INT_DU BIT(4)
141#define SDMMC_IDMAC_INT_FBE BIT(2)
142#define SDMMC_IDMAC_INT_RI BIT(1)
143#define SDMMC_IDMAC_INT_TI BIT(0)
144/* Internal DMAC bus mode bits */
145#define SDMMC_IDMAC_ENABLE BIT(7)
146#define SDMMC_IDMAC_FB BIT(1)
147#define SDMMC_IDMAC_SWRESET BIT(0)
148/* Version ID register define */
149#define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
150/* Card read threshold */
151#define SDMMC_SET_RD_THLD(v, x) (((v) & 0x1FFF) << 16 | (x))
152
153/* Register access macros */
154#define mci_readl(dev, reg) \
155 __raw_readl((dev)->regs + SDMMC_##reg)
156#define mci_writel(dev, reg, value) \
157 __raw_writel((value), (dev)->regs + SDMMC_##reg)
158
159/* 16-bit FIFO access macros */
160#define mci_readw(dev, reg) \
161 __raw_readw((dev)->regs + SDMMC_##reg)
162#define mci_writew(dev, reg, value) \
163 __raw_writew((value), (dev)->regs + SDMMC_##reg)
164
165/* 64-bit FIFO access macros */
166#ifdef readq
167#define mci_readq(dev, reg) \
168 __raw_readq((dev)->regs + SDMMC_##reg)
169#define mci_writeq(dev, reg, value) \
170 __raw_writeq((value), (dev)->regs + SDMMC_##reg)
171#else
172/*
173 * Dummy readq implementation for architectures that don't define it.
174 *
175 * We would assume that none of these architectures would configure
176 * the IP block with a 64bit FIFO width, so this code will never be
177 * executed on those machines. Defining these macros here keeps the
178 * rest of the code free from ifdefs.
179 */
180#define mci_readq(dev, reg) \
181 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
182#define mci_writeq(dev, reg, value) \
183 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
184#endif
185
186extern int dw_mci_probe(struct dw_mci *host);
187extern void dw_mci_remove(struct dw_mci *host);
188#ifdef CONFIG_PM_SLEEP
189extern int dw_mci_suspend(struct dw_mci *host);
190extern int dw_mci_resume(struct dw_mci *host);
191#endif
192
193/**
194 * struct dw_mci_slot - MMC slot state
195 * @mmc: The mmc_host representing this slot.
196 * @host: The MMC controller this slot is using.
197 * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX)
198 * @wp_gpio: If gpio_is_valid() we'll use this to read write protect.
199 * @ctype: Card type for this slot.
200 * @mrq: mmc_request currently being processed or waiting to be
201 * processed, or NULL when the slot is idle.
202 * @queue_node: List node for placing this node in the @queue list of
203 * &struct dw_mci.
204 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
205 * @__clk_old: The last updated clock with reflecting clock divider.
206 * Keeping track of this helps us to avoid spamming the console
207 * with CONFIG_MMC_CLKGATE.
208 * @flags: Random state bits associated with the slot.
209 * @id: Number of this slot.
210 * @last_detect_state: Most recently observed card detect state.
211 */
212struct dw_mci_slot {
213 struct mmc_host *mmc;
214 struct dw_mci *host;
215
216 int quirks;
217 int wp_gpio;
218
219 u32 ctype;
220
221 struct mmc_request *mrq;
222 struct list_head queue_node;
223
224 unsigned int clock;
225 unsigned int __clk_old;
226
227 unsigned long flags;
228#define DW_MMC_CARD_PRESENT 0
229#define DW_MMC_CARD_NEED_INIT 1
230 int id;
231 int last_detect_state;
232};
233
234struct dw_mci_tuning_data {
235 const u8 *blk_pattern;
236 unsigned int blksz;
237};
238
239/**
240 * dw_mci driver data - dw-mshc implementation specific driver data.
241 * @caps: mmc subsystem specified capabilities of the controller(s).
242 * @init: early implementation specific initialization.
243 * @setup_clock: implementation specific clock configuration.
244 * @prepare_command: handle CMD register extensions.
245 * @set_ios: handle bus specific extensions.
246 * @parse_dt: parse implementation specific device tree properties.
247 * @execute_tuning: implementation specific tuning procedure.
248 *
249 * Provide controller implementation specific extensions. The usage of this
250 * data structure is fully optional and usage of each member in this structure
251 * is optional as well.
252 */
253struct dw_mci_drv_data {
254 unsigned long *caps;
255 int (*init)(struct dw_mci *host);
256 int (*setup_clock)(struct dw_mci *host);
257 void (*prepare_command)(struct dw_mci *host, u32 *cmdr);
258 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
259 int (*parse_dt)(struct dw_mci *host);
260 int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode,
261 struct dw_mci_tuning_data *tuning_data);
262};
263#endif /* _DW_MMC_H_ */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Synopsys DesignWare Multimedia Card Interface driver
4 * (Based on NXP driver for lpc 31xx)
5 *
6 * Copyright (C) 2009 NXP Semiconductors
7 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 */
9
10#ifndef _DW_MMC_H_
11#define _DW_MMC_H_
12
13#include <linux/scatterlist.h>
14#include <linux/mmc/core.h>
15#include <linux/dmaengine.h>
16#include <linux/reset.h>
17#include <linux/interrupt.h>
18
19enum dw_mci_state {
20 STATE_IDLE = 0,
21 STATE_SENDING_CMD,
22 STATE_SENDING_DATA,
23 STATE_DATA_BUSY,
24 STATE_SENDING_STOP,
25 STATE_DATA_ERROR,
26 STATE_SENDING_CMD11,
27 STATE_WAITING_CMD11_DONE,
28};
29
30enum {
31 EVENT_CMD_COMPLETE = 0,
32 EVENT_XFER_COMPLETE,
33 EVENT_DATA_COMPLETE,
34 EVENT_DATA_ERROR,
35};
36
37enum dw_mci_cookie {
38 COOKIE_UNMAPPED,
39 COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */
40 COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */
41};
42
43struct mmc_data;
44
45enum {
46 TRANS_MODE_PIO = 0,
47 TRANS_MODE_IDMAC,
48 TRANS_MODE_EDMAC
49};
50
51struct dw_mci_dma_slave {
52 struct dma_chan *ch;
53 enum dma_transfer_direction direction;
54};
55
56/**
57 * struct dw_mci - MMC controller state shared between all slots
58 * @lock: Spinlock protecting the queue and associated data.
59 * @irq_lock: Spinlock protecting the INTMASK setting.
60 * @regs: Pointer to MMIO registers.
61 * @fifo_reg: Pointer to MMIO registers for data FIFO
62 * @sg: Scatterlist entry currently being processed by PIO code, if any.
63 * @sg_miter: PIO mapping scatterlist iterator.
64 * @mrq: The request currently being processed on @slot,
65 * or NULL if the controller is idle.
66 * @cmd: The command currently being sent to the card, or NULL.
67 * @data: The data currently being transferred, or NULL if no data
68 * transfer is in progress.
69 * @stop_abort: The command currently prepared for stoping transfer.
70 * @prev_blksz: The former transfer blksz record.
71 * @timing: Record of current ios timing.
72 * @use_dma: Which DMA channel is in use for the current transfer, zero
73 * denotes PIO mode.
74 * @using_dma: Whether DMA is in use for the current transfer.
75 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
76 * @sg_dma: Bus address of DMA buffer.
77 * @sg_cpu: Virtual address of DMA buffer.
78 * @dma_ops: Pointer to platform-specific DMA callbacks.
79 * @cmd_status: Snapshot of SR taken upon completion of the current
80 * @ring_size: Buffer size for idma descriptors.
81 * command. Only valid when EVENT_CMD_COMPLETE is pending.
82 * @dms: structure of slave-dma private data.
83 * @phy_regs: physical address of controller's register map
84 * @data_status: Snapshot of SR taken upon completion of the current
85 * data transfer. Only valid when EVENT_DATA_COMPLETE or
86 * EVENT_DATA_ERROR is pending.
87 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
88 * to be sent.
89 * @dir_status: Direction of current transfer.
90 * @tasklet: Tasklet running the request state machine.
91 * @pending_events: Bitmask of events flagged by the interrupt handler
92 * to be processed by the tasklet.
93 * @completed_events: Bitmask of events which the state machine has
94 * processed.
95 * @state: Tasklet state.
96 * @queue: List of slots waiting for access to the controller.
97 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
98 * rate and timeout calculations.
99 * @current_speed: Configured rate of the controller.
100 * @fifoth_val: The value of FIFOTH register.
101 * @verid: Denote Version ID.
102 * @dev: Device associated with the MMC controller.
103 * @pdata: Platform data associated with the MMC controller.
104 * @drv_data: Driver specific data for identified variant of the controller
105 * @priv: Implementation defined private data.
106 * @biu_clk: Pointer to bus interface unit clock instance.
107 * @ciu_clk: Pointer to card interface unit clock instance.
108 * @slot: Slots sharing this MMC controller.
109 * @fifo_depth: depth of FIFO.
110 * @data_addr_override: override fifo reg offset with this value.
111 * @wm_aligned: force fifo watermark equal with data length in PIO mode.
112 * Set as true if alignment is needed.
113 * @data_shift: log2 of FIFO item size.
114 * @part_buf_start: Start index in part_buf.
115 * @part_buf_count: Bytes of partial data in part_buf.
116 * @part_buf: Simple buffer for partial fifo reads/writes.
117 * @push_data: Pointer to FIFO push function.
118 * @pull_data: Pointer to FIFO pull function.
119 * @vqmmc_enabled: Status of vqmmc, should be true or false.
120 * @irq_flags: The flags to be passed to request_irq.
121 * @irq: The irq value to be passed to request_irq.
122 * @sdio_id0: Number of slot0 in the SDIO interrupt registers.
123 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
124 * @cto_timer: Timer for broken command transfer over scheme.
125 * @dto_timer: Timer for broken data transfer over scheme.
126 *
127 * Locking
128 * =======
129 *
130 * @lock is a softirq-safe spinlock protecting @queue as well as
131 * @slot, @mrq and @state. These must always be updated
132 * at the same time while holding @lock.
133 * The @mrq field of struct dw_mci_slot is also protected by @lock,
134 * and must always be written at the same time as the slot is added to
135 * @queue.
136 *
137 * @irq_lock is an irq-safe spinlock protecting the INTMASK register
138 * to allow the interrupt handler to modify it directly. Held for only long
139 * enough to read-modify-write INTMASK and no other locks are grabbed when
140 * holding this one.
141 *
142 * @pending_events and @completed_events are accessed using atomic bit
143 * operations, so they don't need any locking.
144 *
145 * None of the fields touched by the interrupt handler need any
146 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
147 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
148 * interrupts must be disabled and @data_status updated with a
149 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
150 * CMDRDY interrupt must be disabled and @cmd_status updated with a
151 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
152 * bytes_xfered field of @data must be written. This is ensured by
153 * using barriers.
154 */
155struct dw_mci {
156 spinlock_t lock;
157 spinlock_t irq_lock;
158 void __iomem *regs;
159 void __iomem *fifo_reg;
160 u32 data_addr_override;
161 bool wm_aligned;
162
163 struct scatterlist *sg;
164 struct sg_mapping_iter sg_miter;
165
166 struct mmc_request *mrq;
167 struct mmc_command *cmd;
168 struct mmc_data *data;
169 struct mmc_command stop_abort;
170 unsigned int prev_blksz;
171 unsigned char timing;
172
173 /* DMA interface members*/
174 int use_dma;
175 int using_dma;
176 int dma_64bit_address;
177
178 dma_addr_t sg_dma;
179 void *sg_cpu;
180 const struct dw_mci_dma_ops *dma_ops;
181 /* For idmac */
182 unsigned int ring_size;
183
184 /* For edmac */
185 struct dw_mci_dma_slave *dms;
186 /* Registers's physical base address */
187 resource_size_t phy_regs;
188
189 u32 cmd_status;
190 u32 data_status;
191 u32 stop_cmdr;
192 u32 dir_status;
193 struct tasklet_struct tasklet;
194 unsigned long pending_events;
195 unsigned long completed_events;
196 enum dw_mci_state state;
197 struct list_head queue;
198
199 u32 bus_hz;
200 u32 current_speed;
201 u32 fifoth_val;
202 u16 verid;
203 struct device *dev;
204 struct dw_mci_board *pdata;
205 const struct dw_mci_drv_data *drv_data;
206 void *priv;
207 struct clk *biu_clk;
208 struct clk *ciu_clk;
209 struct dw_mci_slot *slot;
210
211 /* FIFO push and pull */
212 int fifo_depth;
213 int data_shift;
214 u8 part_buf_start;
215 u8 part_buf_count;
216 union {
217 u16 part_buf16;
218 u32 part_buf32;
219 u64 part_buf;
220 };
221 void (*push_data)(struct dw_mci *host, void *buf, int cnt);
222 void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
223
224 bool vqmmc_enabled;
225 unsigned long irq_flags; /* IRQ flags */
226 int irq;
227
228 int sdio_id0;
229
230 struct timer_list cmd11_timer;
231 struct timer_list cto_timer;
232 struct timer_list dto_timer;
233};
234
235/* DMA ops for Internal/External DMAC interface */
236struct dw_mci_dma_ops {
237 /* DMA Ops */
238 int (*init)(struct dw_mci *host);
239 int (*start)(struct dw_mci *host, unsigned int sg_len);
240 void (*complete)(void *host);
241 void (*stop)(struct dw_mci *host);
242 void (*cleanup)(struct dw_mci *host);
243 void (*exit)(struct dw_mci *host);
244};
245
246struct dma_pdata;
247
248/* Board platform data */
249struct dw_mci_board {
250 unsigned int bus_hz; /* Clock speed at the cclk_in pad */
251
252 u32 caps; /* Capabilities */
253 u32 caps2; /* More capabilities */
254 u32 pm_caps; /* PM capabilities */
255 /*
256 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
257 * but note that this may not be reliable after a bootloader has used
258 * it.
259 */
260 unsigned int fifo_depth;
261
262 /* delay in mS before detecting cards after interrupt */
263 u32 detect_delay_ms;
264
265 struct reset_control *rstc;
266 struct dw_mci_dma_ops *dma_ops;
267 struct dma_pdata *data;
268};
269
270#define DW_MMC_240A 0x240a
271#define DW_MMC_280A 0x280a
272
273#define SDMMC_CTRL 0x000
274#define SDMMC_PWREN 0x004
275#define SDMMC_CLKDIV 0x008
276#define SDMMC_CLKSRC 0x00c
277#define SDMMC_CLKENA 0x010
278#define SDMMC_TMOUT 0x014
279#define SDMMC_CTYPE 0x018
280#define SDMMC_BLKSIZ 0x01c
281#define SDMMC_BYTCNT 0x020
282#define SDMMC_INTMASK 0x024
283#define SDMMC_CMDARG 0x028
284#define SDMMC_CMD 0x02c
285#define SDMMC_RESP0 0x030
286#define SDMMC_RESP1 0x034
287#define SDMMC_RESP2 0x038
288#define SDMMC_RESP3 0x03c
289#define SDMMC_MINTSTS 0x040
290#define SDMMC_RINTSTS 0x044
291#define SDMMC_STATUS 0x048
292#define SDMMC_FIFOTH 0x04c
293#define SDMMC_CDETECT 0x050
294#define SDMMC_WRTPRT 0x054
295#define SDMMC_GPIO 0x058
296#define SDMMC_TCBCNT 0x05c
297#define SDMMC_TBBCNT 0x060
298#define SDMMC_DEBNCE 0x064
299#define SDMMC_USRID 0x068
300#define SDMMC_VERID 0x06c
301#define SDMMC_HCON 0x070
302#define SDMMC_UHS_REG 0x074
303#define SDMMC_RST_N 0x078
304#define SDMMC_BMOD 0x080
305#define SDMMC_PLDMND 0x084
306#define SDMMC_DBADDR 0x088
307#define SDMMC_IDSTS 0x08c
308#define SDMMC_IDINTEN 0x090
309#define SDMMC_DSCADDR 0x094
310#define SDMMC_BUFADDR 0x098
311#define SDMMC_CDTHRCTL 0x100
312#define SDMMC_UHS_REG_EXT 0x108
313#define SDMMC_DDR_REG 0x10c
314#define SDMMC_ENABLE_SHIFT 0x110
315#define SDMMC_DATA(x) (x)
316/*
317 * Registers to support idmac 64-bit address mode
318 */
319#define SDMMC_DBADDRL 0x088
320#define SDMMC_DBADDRU 0x08c
321#define SDMMC_IDSTS64 0x090
322#define SDMMC_IDINTEN64 0x094
323#define SDMMC_DSCADDRL 0x098
324#define SDMMC_DSCADDRU 0x09c
325#define SDMMC_BUFADDRL 0x0A0
326#define SDMMC_BUFADDRU 0x0A4
327
328/*
329 * Data offset is difference according to Version
330 * Lower than 2.40a : data register offest is 0x100
331 */
332#define DATA_OFFSET 0x100
333#define DATA_240A_OFFSET 0x200
334
335/* shift bit field */
336#define _SBF(f, v) ((v) << (f))
337
338/* Control register defines */
339#define SDMMC_CTRL_USE_IDMAC BIT(25)
340#define SDMMC_CTRL_CEATA_INT_EN BIT(11)
341#define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
342#define SDMMC_CTRL_SEND_CCSD BIT(9)
343#define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
344#define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
345#define SDMMC_CTRL_READ_WAIT BIT(6)
346#define SDMMC_CTRL_DMA_ENABLE BIT(5)
347#define SDMMC_CTRL_INT_ENABLE BIT(4)
348#define SDMMC_CTRL_DMA_RESET BIT(2)
349#define SDMMC_CTRL_FIFO_RESET BIT(1)
350#define SDMMC_CTRL_RESET BIT(0)
351/* Clock Enable register defines */
352#define SDMMC_CLKEN_LOW_PWR BIT(16)
353#define SDMMC_CLKEN_ENABLE BIT(0)
354/* time-out register defines */
355#define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
356#define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
357#define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
358#define SDMMC_TMOUT_RESP_MSK 0xFF
359/* card-type register defines */
360#define SDMMC_CTYPE_8BIT BIT(16)
361#define SDMMC_CTYPE_4BIT BIT(0)
362#define SDMMC_CTYPE_1BIT 0
363/* Interrupt status & mask register defines */
364#define SDMMC_INT_SDIO(n) BIT(16 + (n))
365#define SDMMC_INT_EBE BIT(15)
366#define SDMMC_INT_ACD BIT(14)
367#define SDMMC_INT_SBE BIT(13)
368#define SDMMC_INT_HLE BIT(12)
369#define SDMMC_INT_FRUN BIT(11)
370#define SDMMC_INT_HTO BIT(10)
371#define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */
372#define SDMMC_INT_DRTO BIT(9)
373#define SDMMC_INT_RTO BIT(8)
374#define SDMMC_INT_DCRC BIT(7)
375#define SDMMC_INT_RCRC BIT(6)
376#define SDMMC_INT_RXDR BIT(5)
377#define SDMMC_INT_TXDR BIT(4)
378#define SDMMC_INT_DATA_OVER BIT(3)
379#define SDMMC_INT_CMD_DONE BIT(2)
380#define SDMMC_INT_RESP_ERR BIT(1)
381#define SDMMC_INT_CD BIT(0)
382#define SDMMC_INT_ERROR 0xbfc2
383/* Command register defines */
384#define SDMMC_CMD_START BIT(31)
385#define SDMMC_CMD_USE_HOLD_REG BIT(29)
386#define SDMMC_CMD_VOLT_SWITCH BIT(28)
387#define SDMMC_CMD_CCS_EXP BIT(23)
388#define SDMMC_CMD_CEATA_RD BIT(22)
389#define SDMMC_CMD_UPD_CLK BIT(21)
390#define SDMMC_CMD_INIT BIT(15)
391#define SDMMC_CMD_STOP BIT(14)
392#define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
393#define SDMMC_CMD_SEND_STOP BIT(12)
394#define SDMMC_CMD_STRM_MODE BIT(11)
395#define SDMMC_CMD_DAT_WR BIT(10)
396#define SDMMC_CMD_DAT_EXP BIT(9)
397#define SDMMC_CMD_RESP_CRC BIT(8)
398#define SDMMC_CMD_RESP_LONG BIT(7)
399#define SDMMC_CMD_RESP_EXP BIT(6)
400#define SDMMC_CMD_INDX(n) ((n) & 0x1F)
401/* Status register defines */
402#define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
403#define SDMMC_STATUS_DMA_REQ BIT(31)
404#define SDMMC_STATUS_BUSY BIT(9)
405/* FIFOTH register defines */
406#define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
407 ((r) & 0xFFF) << 16 | \
408 ((t) & 0xFFF))
409/* HCON register defines */
410#define DMA_INTERFACE_IDMA (0x0)
411#define DMA_INTERFACE_DWDMA (0x1)
412#define DMA_INTERFACE_GDMA (0x2)
413#define DMA_INTERFACE_NODMA (0x3)
414#define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
415#define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
416#define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
417#define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
418/* Internal DMAC interrupt defines */
419#define SDMMC_IDMAC_INT_AI BIT(9)
420#define SDMMC_IDMAC_INT_NI BIT(8)
421#define SDMMC_IDMAC_INT_CES BIT(5)
422#define SDMMC_IDMAC_INT_DU BIT(4)
423#define SDMMC_IDMAC_INT_FBE BIT(2)
424#define SDMMC_IDMAC_INT_RI BIT(1)
425#define SDMMC_IDMAC_INT_TI BIT(0)
426/* Internal DMAC bus mode bits */
427#define SDMMC_IDMAC_ENABLE BIT(7)
428#define SDMMC_IDMAC_FB BIT(1)
429#define SDMMC_IDMAC_SWRESET BIT(0)
430/* H/W reset */
431#define SDMMC_RST_HWACTIVE 0x1
432/* Version ID register define */
433#define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
434/* Card read threshold */
435#define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x))
436#define SDMMC_CARD_WR_THR_EN BIT(2)
437#define SDMMC_CARD_RD_THR_EN BIT(0)
438/* UHS-1 register defines */
439#define SDMMC_UHS_DDR BIT(16)
440#define SDMMC_UHS_18V BIT(0)
441/* DDR register defines */
442#define SDMMC_DDR_HS400 BIT(31)
443/* Enable shift register defines */
444#define SDMMC_ENABLE_PHASE BIT(0)
445/* All ctrl reset bits */
446#define SDMMC_CTRL_ALL_RESET_FLAGS \
447 (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
448
449/* FIFO register access macros. These should not change the data endian-ness
450 * as they are written to memory to be dealt with by the upper layers
451 */
452#define mci_fifo_readw(__reg) __raw_readw(__reg)
453#define mci_fifo_readl(__reg) __raw_readl(__reg)
454#define mci_fifo_readq(__reg) __raw_readq(__reg)
455
456#define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
457#define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
458#define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value)
459
460/* Register access macros */
461#define mci_readl(dev, reg) \
462 readl_relaxed((dev)->regs + SDMMC_##reg)
463#define mci_writel(dev, reg, value) \
464 writel_relaxed((value), (dev)->regs + SDMMC_##reg)
465
466/* 16-bit FIFO access macros */
467#define mci_readw(dev, reg) \
468 readw_relaxed((dev)->regs + SDMMC_##reg)
469#define mci_writew(dev, reg, value) \
470 writew_relaxed((value), (dev)->regs + SDMMC_##reg)
471
472/* 64-bit FIFO access macros */
473#ifdef readq
474#define mci_readq(dev, reg) \
475 readq_relaxed((dev)->regs + SDMMC_##reg)
476#define mci_writeq(dev, reg, value) \
477 writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
478#else
479/*
480 * Dummy readq implementation for architectures that don't define it.
481 *
482 * We would assume that none of these architectures would configure
483 * the IP block with a 64bit FIFO width, so this code will never be
484 * executed on those machines. Defining these macros here keeps the
485 * rest of the code free from ifdefs.
486 */
487#define mci_readq(dev, reg) \
488 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
489#define mci_writeq(dev, reg, value) \
490 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
491
492#define __raw_writeq(__value, __reg) \
493 (*(volatile u64 __force *)(__reg) = (__value))
494#define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
495#endif
496
497extern int dw_mci_probe(struct dw_mci *host);
498extern void dw_mci_remove(struct dw_mci *host);
499#ifdef CONFIG_PM
500extern int dw_mci_runtime_suspend(struct device *device);
501extern int dw_mci_runtime_resume(struct device *device);
502#endif
503
504/**
505 * struct dw_mci_slot - MMC slot state
506 * @mmc: The mmc_host representing this slot.
507 * @host: The MMC controller this slot is using.
508 * @ctype: Card type for this slot.
509 * @mrq: mmc_request currently being processed or waiting to be
510 * processed, or NULL when the slot is idle.
511 * @queue_node: List node for placing this node in the @queue list of
512 * &struct dw_mci.
513 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
514 * @__clk_old: The last clock value that was requested from core.
515 * Keeping track of this helps us to avoid spamming the console.
516 * @flags: Random state bits associated with the slot.
517 * @id: Number of this slot.
518 * @sdio_id: Number of this slot in the SDIO interrupt registers.
519 */
520struct dw_mci_slot {
521 struct mmc_host *mmc;
522 struct dw_mci *host;
523
524 u32 ctype;
525
526 struct mmc_request *mrq;
527 struct list_head queue_node;
528
529 unsigned int clock;
530 unsigned int __clk_old;
531
532 unsigned long flags;
533#define DW_MMC_CARD_PRESENT 0
534#define DW_MMC_CARD_NEED_INIT 1
535#define DW_MMC_CARD_NO_LOW_PWR 2
536#define DW_MMC_CARD_NO_USE_HOLD 3
537#define DW_MMC_CARD_NEEDS_POLL 4
538 int id;
539 int sdio_id;
540};
541
542/**
543 * dw_mci driver data - dw-mshc implementation specific driver data.
544 * @caps: mmc subsystem specified capabilities of the controller(s).
545 * @num_caps: number of capabilities specified by @caps.
546 * @init: early implementation specific initialization.
547 * @set_ios: handle bus specific extensions.
548 * @parse_dt: parse implementation specific device tree properties.
549 * @execute_tuning: implementation specific tuning procedure.
550 *
551 * Provide controller implementation specific extensions. The usage of this
552 * data structure is fully optional and usage of each member in this structure
553 * is optional as well.
554 */
555struct dw_mci_drv_data {
556 unsigned long *caps;
557 u32 num_caps;
558 int (*init)(struct dw_mci *host);
559 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
560 int (*parse_dt)(struct dw_mci *host);
561 int (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode);
562 int (*prepare_hs400_tuning)(struct dw_mci *host,
563 struct mmc_ios *ios);
564 int (*switch_voltage)(struct mmc_host *mmc,
565 struct mmc_ios *ios);
566};
567#endif /* _DW_MMC_H_ */