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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_DRV_H__
19#define __MSM_DRV_H__
20
21#include <linux/kernel.h>
22#include <linux/clk.h>
23#include <linux/cpufreq.h>
24#include <linux/module.h>
25#include <linux/component.h>
26#include <linux/platform_device.h>
27#include <linux/pm.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/list.h>
31#include <linux/iommu.h>
32#include <linux/types.h>
33#include <asm/sizes.h>
34
35
36#if defined(CONFIG_COMPILE_TEST) && !defined(CONFIG_ARCH_MSM)
37/* stubs we need for compile-test: */
38static inline struct device *msm_iommu_get_ctx(const char *ctx_name)
39{
40 return NULL;
41}
42#endif
43
44#ifndef CONFIG_OF
45#include <mach/board.h>
46#include <mach/socinfo.h>
47#include <mach/iommu_domains.h>
48#endif
49
50#include <drm/drmP.h>
51#include <drm/drm_crtc_helper.h>
52#include <drm/drm_fb_helper.h>
53#include <drm/msm_drm.h>
54
55struct msm_kms;
56struct msm_gpu;
57struct msm_mmu;
58
59#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
60
61struct msm_file_private {
62 /* currently we don't do anything useful with this.. but when
63 * per-context address spaces are supported we'd keep track of
64 * the context's page-tables here.
65 */
66 int dummy;
67};
68
69struct msm_drm_private {
70
71 struct msm_kms *kms;
72
73 /* subordinate devices, if present: */
74 struct platform_device *hdmi_pdev, *gpu_pdev;
75
76 /* when we have more than one 'msm_gpu' these need to be an array: */
77 struct msm_gpu *gpu;
78 struct msm_file_private *lastctx;
79
80 struct drm_fb_helper *fbdev;
81
82 uint32_t next_fence, completed_fence;
83 wait_queue_head_t fence_event;
84
85 /* list of GEM objects: */
86 struct list_head inactive_list;
87
88 struct workqueue_struct *wq;
89
90 /* callbacks deferred until bo is inactive: */
91 struct list_head fence_cbs;
92
93 /* registered MMUs: */
94 unsigned int num_mmus;
95 struct msm_mmu *mmus[NUM_DOMAINS];
96
97 unsigned int num_planes;
98 struct drm_plane *planes[8];
99
100 unsigned int num_crtcs;
101 struct drm_crtc *crtcs[8];
102
103 unsigned int num_encoders;
104 struct drm_encoder *encoders[8];
105
106 unsigned int num_bridges;
107 struct drm_bridge *bridges[8];
108
109 unsigned int num_connectors;
110 struct drm_connector *connectors[8];
111
112 /* VRAM carveout, used when no IOMMU: */
113 struct {
114 unsigned long size;
115 dma_addr_t paddr;
116 /* NOTE: mm managed at the page level, size is in # of pages
117 * and position mm_node->start is in # of pages:
118 */
119 struct drm_mm mm;
120 } vram;
121};
122
123struct msm_format {
124 uint32_t pixel_format;
125};
126
127/* callback from wq once fence has passed: */
128struct msm_fence_cb {
129 struct work_struct work;
130 uint32_t fence;
131 void (*func)(struct msm_fence_cb *cb);
132};
133
134void __msm_fence_worker(struct work_struct *work);
135
136#define INIT_FENCE_CB(_cb, _func) do { \
137 INIT_WORK(&(_cb)->work, __msm_fence_worker); \
138 (_cb)->func = _func; \
139 } while (0)
140
141int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
142
143int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
144 struct timespec *timeout);
145void msm_update_fence(struct drm_device *dev, uint32_t fence);
146
147int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
148 struct drm_file *file);
149
150int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
151int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
152uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
153int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
154 uint32_t *iova);
155int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
156struct page **msm_gem_get_pages(struct drm_gem_object *obj);
157void msm_gem_put_pages(struct drm_gem_object *obj);
158void msm_gem_put_iova(struct drm_gem_object *obj, int id);
159int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
160 struct drm_mode_create_dumb *args);
161int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
162 uint32_t handle, uint64_t *offset);
163struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
164void *msm_gem_prime_vmap(struct drm_gem_object *obj);
165void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
166struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
167 size_t size, struct sg_table *sg);
168int msm_gem_prime_pin(struct drm_gem_object *obj);
169void msm_gem_prime_unpin(struct drm_gem_object *obj);
170void *msm_gem_vaddr_locked(struct drm_gem_object *obj);
171void *msm_gem_vaddr(struct drm_gem_object *obj);
172int msm_gem_queue_inactive_cb(struct drm_gem_object *obj,
173 struct msm_fence_cb *cb);
174void msm_gem_move_to_active(struct drm_gem_object *obj,
175 struct msm_gpu *gpu, bool write, uint32_t fence);
176void msm_gem_move_to_inactive(struct drm_gem_object *obj);
177int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op,
178 struct timespec *timeout);
179int msm_gem_cpu_fini(struct drm_gem_object *obj);
180void msm_gem_free_object(struct drm_gem_object *obj);
181int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
182 uint32_t size, uint32_t flags, uint32_t *handle);
183struct drm_gem_object *msm_gem_new(struct drm_device *dev,
184 uint32_t size, uint32_t flags);
185struct drm_gem_object *msm_gem_import(struct drm_device *dev,
186 uint32_t size, struct sg_table *sgt);
187
188struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
189const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
190struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
191 struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
192struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
193 struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd);
194
195struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
196
197struct hdmi;
198struct hdmi *hdmi_init(struct drm_device *dev, struct drm_encoder *encoder);
199irqreturn_t hdmi_irq(int irq, void *dev_id);
200void __init hdmi_register(void);
201void __exit hdmi_unregister(void);
202
203#ifdef CONFIG_DEBUG_FS
204void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
205void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
206void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
207#endif
208
209void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
210 const char *dbgname);
211void msm_writel(u32 data, void __iomem *addr);
212u32 msm_readl(const void __iomem *addr);
213
214#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
215#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
216
217static inline bool fence_completed(struct drm_device *dev, uint32_t fence)
218{
219 struct msm_drm_private *priv = dev->dev_private;
220 return priv->completed_fence >= fence;
221}
222
223static inline int align_pitch(int width, int bpp)
224{
225 int bytespp = (bpp + 7) / 8;
226 /* adreno needs pitch aligned to 32 pixels: */
227 return bytespp * ALIGN(width, 32);
228}
229
230/* for the generated headers: */
231#define INVALID_IDX(idx) ({BUG(); 0;})
232#define fui(x) ({BUG(); 0;})
233#define util_float_to_half(x) ({BUG(); 0;})
234
235
236#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
237
238/* for conditionally setting boolean flag(s): */
239#define COND(bool, val) ((bool) ? (val) : 0)
240
241
242#endif /* __MSM_DRV_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#ifndef __MSM_DRV_H__
9#define __MSM_DRV_H__
10
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/cpufreq.h>
14#include <linux/module.h>
15#include <linux/component.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/pm_runtime.h>
19#include <linux/slab.h>
20#include <linux/list.h>
21#include <linux/iommu.h>
22#include <linux/types.h>
23#include <linux/of_graph.h>
24#include <linux/of_device.h>
25#include <linux/sizes.h>
26#include <linux/kthread.h>
27
28#include <drm/drm_atomic.h>
29#include <drm/drm_atomic_helper.h>
30#include <drm/drm_plane_helper.h>
31#include <drm/drm_probe_helper.h>
32#include <drm/drm_fb_helper.h>
33#include <drm/msm_drm.h>
34#include <drm/drm_gem.h>
35
36struct msm_kms;
37struct msm_gpu;
38struct msm_mmu;
39struct msm_mdss;
40struct msm_rd_state;
41struct msm_perf_state;
42struct msm_gem_submit;
43struct msm_fence_context;
44struct msm_gem_address_space;
45struct msm_gem_vma;
46
47#define MAX_CRTCS 8
48#define MAX_PLANES 20
49#define MAX_ENCODERS 8
50#define MAX_BRIDGES 8
51#define MAX_CONNECTORS 8
52
53#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
54
55struct msm_file_private {
56 rwlock_t queuelock;
57 struct list_head submitqueues;
58 int queueid;
59 struct msm_gem_address_space *aspace;
60};
61
62enum msm_mdp_plane_property {
63 PLANE_PROP_ZPOS,
64 PLANE_PROP_ALPHA,
65 PLANE_PROP_PREMULTIPLIED,
66 PLANE_PROP_MAX_NUM
67};
68
69#define MSM_GPU_MAX_RINGS 4
70#define MAX_H_TILES_PER_DISPLAY 2
71
72/**
73 * enum msm_display_caps - features/capabilities supported by displays
74 * @MSM_DISPLAY_CAP_VID_MODE: Video or "active" mode supported
75 * @MSM_DISPLAY_CAP_CMD_MODE: Command mode supported
76 * @MSM_DISPLAY_CAP_HOT_PLUG: Hot plug detection supported
77 * @MSM_DISPLAY_CAP_EDID: EDID supported
78 */
79enum msm_display_caps {
80 MSM_DISPLAY_CAP_VID_MODE = BIT(0),
81 MSM_DISPLAY_CAP_CMD_MODE = BIT(1),
82 MSM_DISPLAY_CAP_HOT_PLUG = BIT(2),
83 MSM_DISPLAY_CAP_EDID = BIT(3),
84};
85
86/**
87 * enum msm_event_wait - type of HW events to wait for
88 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW
89 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel
90 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters)
91 */
92enum msm_event_wait {
93 MSM_ENC_COMMIT_DONE = 0,
94 MSM_ENC_TX_COMPLETE,
95 MSM_ENC_VBLANK,
96};
97
98/**
99 * struct msm_display_topology - defines a display topology pipeline
100 * @num_lm: number of layer mixers used
101 * @num_enc: number of compression encoder blocks used
102 * @num_intf: number of interfaces the panel is mounted on
103 */
104struct msm_display_topology {
105 u32 num_lm;
106 u32 num_enc;
107 u32 num_intf;
108 u32 num_dspp;
109};
110
111/**
112 * struct msm_display_info - defines display properties
113 * @intf_type: DRM_MODE_ENCODER_ type
114 * @capabilities: Bitmask of display flags
115 * @num_of_h_tiles: Number of horizontal tiles in case of split interface
116 * @h_tile_instance: Controller instance used per tile. Number of elements is
117 * based on num_of_h_tiles
118 * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
119 * used instead of panel TE in cmd mode panels
120 */
121struct msm_display_info {
122 int intf_type;
123 uint32_t capabilities;
124 uint32_t num_of_h_tiles;
125 uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
126 bool is_te_using_watchdog_timer;
127};
128
129/* Commit/Event thread specific structure */
130struct msm_drm_thread {
131 struct drm_device *dev;
132 unsigned int crtc_id;
133 struct kthread_worker *worker;
134};
135
136struct msm_drm_private {
137
138 struct drm_device *dev;
139
140 struct msm_kms *kms;
141
142 /* subordinate devices, if present: */
143 struct platform_device *gpu_pdev;
144
145 /* top level MDSS wrapper device (for MDP5/DPU only) */
146 struct msm_mdss *mdss;
147
148 /* possibly this should be in the kms component, but it is
149 * shared by both mdp4 and mdp5..
150 */
151 struct hdmi *hdmi;
152
153 /* eDP is for mdp5 only, but kms has not been created
154 * when edp_bind() and edp_init() are called. Here is the only
155 * place to keep the edp instance.
156 */
157 struct msm_edp *edp;
158
159 /* DSI is shared by mdp4 and mdp5 */
160 struct msm_dsi *dsi[2];
161
162 /* when we have more than one 'msm_gpu' these need to be an array: */
163 struct msm_gpu *gpu;
164 struct msm_file_private *lastctx;
165 /* gpu is only set on open(), but we need this info earlier */
166 bool is_a2xx;
167
168 struct drm_fb_helper *fbdev;
169
170 struct msm_rd_state *rd; /* debugfs to dump all submits */
171 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */
172 struct msm_perf_state *perf;
173
174 /* list of GEM objects: */
175 struct list_head inactive_list;
176
177 /* worker for delayed free of objects: */
178 struct work_struct free_work;
179 struct llist_head free_list;
180
181 struct workqueue_struct *wq;
182
183 unsigned int num_planes;
184 struct drm_plane *planes[MAX_PLANES];
185
186 unsigned int num_crtcs;
187 struct drm_crtc *crtcs[MAX_CRTCS];
188
189 struct msm_drm_thread event_thread[MAX_CRTCS];
190
191 unsigned int num_encoders;
192 struct drm_encoder *encoders[MAX_ENCODERS];
193
194 unsigned int num_bridges;
195 struct drm_bridge *bridges[MAX_BRIDGES];
196
197 unsigned int num_connectors;
198 struct drm_connector *connectors[MAX_CONNECTORS];
199
200 /* Properties */
201 struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
202
203 /* VRAM carveout, used when no IOMMU: */
204 struct {
205 unsigned long size;
206 dma_addr_t paddr;
207 /* NOTE: mm managed at the page level, size is in # of pages
208 * and position mm_node->start is in # of pages:
209 */
210 struct drm_mm mm;
211 spinlock_t lock; /* Protects drm_mm node allocation/removal */
212 } vram;
213
214 struct notifier_block vmap_notifier;
215 struct shrinker shrinker;
216
217 struct drm_atomic_state *pm_state;
218};
219
220struct msm_format {
221 uint32_t pixel_format;
222};
223
224struct msm_pending_timer;
225
226int msm_atomic_prepare_fb(struct drm_plane *plane,
227 struct drm_plane_state *new_state);
228void msm_atomic_init_pending_timer(struct msm_pending_timer *timer,
229 struct msm_kms *kms, int crtc_idx);
230void msm_atomic_commit_tail(struct drm_atomic_state *state);
231struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev);
232void msm_atomic_state_clear(struct drm_atomic_state *state);
233void msm_atomic_state_free(struct drm_atomic_state *state);
234
235int msm_crtc_enable_vblank(struct drm_crtc *crtc);
236void msm_crtc_disable_vblank(struct drm_crtc *crtc);
237
238int msm_gem_init_vma(struct msm_gem_address_space *aspace,
239 struct msm_gem_vma *vma, int npages,
240 u64 range_start, u64 range_end);
241void msm_gem_purge_vma(struct msm_gem_address_space *aspace,
242 struct msm_gem_vma *vma);
243void msm_gem_unmap_vma(struct msm_gem_address_space *aspace,
244 struct msm_gem_vma *vma);
245int msm_gem_map_vma(struct msm_gem_address_space *aspace,
246 struct msm_gem_vma *vma, int prot,
247 struct sg_table *sgt, int npages);
248void msm_gem_close_vma(struct msm_gem_address_space *aspace,
249 struct msm_gem_vma *vma);
250
251void msm_gem_address_space_put(struct msm_gem_address_space *aspace);
252
253struct msm_gem_address_space *
254msm_gem_address_space_create(struct msm_mmu *mmu, const char *name,
255 u64 va_start, u64 size);
256
257int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);
258void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu);
259
260bool msm_use_mmu(struct drm_device *dev);
261
262void msm_gem_submit_free(struct msm_gem_submit *submit);
263int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
264 struct drm_file *file);
265
266void msm_gem_shrinker_init(struct drm_device *dev);
267void msm_gem_shrinker_cleanup(struct drm_device *dev);
268
269int msm_gem_mmap_obj(struct drm_gem_object *obj,
270 struct vm_area_struct *vma);
271int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
272vm_fault_t msm_gem_fault(struct vm_fault *vmf);
273uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
274int msm_gem_get_iova(struct drm_gem_object *obj,
275 struct msm_gem_address_space *aspace, uint64_t *iova);
276int msm_gem_get_and_pin_iova_range(struct drm_gem_object *obj,
277 struct msm_gem_address_space *aspace, uint64_t *iova,
278 u64 range_start, u64 range_end);
279int msm_gem_get_and_pin_iova(struct drm_gem_object *obj,
280 struct msm_gem_address_space *aspace, uint64_t *iova);
281uint64_t msm_gem_iova(struct drm_gem_object *obj,
282 struct msm_gem_address_space *aspace);
283void msm_gem_unpin_iova(struct drm_gem_object *obj,
284 struct msm_gem_address_space *aspace);
285struct page **msm_gem_get_pages(struct drm_gem_object *obj);
286void msm_gem_put_pages(struct drm_gem_object *obj);
287int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
288 struct drm_mode_create_dumb *args);
289int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
290 uint32_t handle, uint64_t *offset);
291struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
292void *msm_gem_prime_vmap(struct drm_gem_object *obj);
293void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
294int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
295struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
296 struct dma_buf_attachment *attach, struct sg_table *sg);
297int msm_gem_prime_pin(struct drm_gem_object *obj);
298void msm_gem_prime_unpin(struct drm_gem_object *obj);
299void *msm_gem_get_vaddr(struct drm_gem_object *obj);
300void *msm_gem_get_vaddr_active(struct drm_gem_object *obj);
301void msm_gem_put_vaddr(struct drm_gem_object *obj);
302int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
303int msm_gem_sync_object(struct drm_gem_object *obj,
304 struct msm_fence_context *fctx, bool exclusive);
305void msm_gem_move_to_active(struct drm_gem_object *obj,
306 struct msm_gpu *gpu, bool exclusive, struct dma_fence *fence);
307void msm_gem_move_to_inactive(struct drm_gem_object *obj);
308int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
309int msm_gem_cpu_fini(struct drm_gem_object *obj);
310void msm_gem_free_object(struct drm_gem_object *obj);
311int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
312 uint32_t size, uint32_t flags, uint32_t *handle, char *name);
313struct drm_gem_object *msm_gem_new(struct drm_device *dev,
314 uint32_t size, uint32_t flags);
315struct drm_gem_object *msm_gem_new_locked(struct drm_device *dev,
316 uint32_t size, uint32_t flags);
317void *msm_gem_kernel_new(struct drm_device *dev, uint32_t size,
318 uint32_t flags, struct msm_gem_address_space *aspace,
319 struct drm_gem_object **bo, uint64_t *iova);
320void *msm_gem_kernel_new_locked(struct drm_device *dev, uint32_t size,
321 uint32_t flags, struct msm_gem_address_space *aspace,
322 struct drm_gem_object **bo, uint64_t *iova);
323void msm_gem_kernel_put(struct drm_gem_object *bo,
324 struct msm_gem_address_space *aspace, bool locked);
325struct drm_gem_object *msm_gem_import(struct drm_device *dev,
326 struct dma_buf *dmabuf, struct sg_table *sgt);
327void msm_gem_free_work(struct work_struct *work);
328
329__printf(2, 3)
330void msm_gem_object_set_name(struct drm_gem_object *bo, const char *fmt, ...);
331
332int msm_framebuffer_prepare(struct drm_framebuffer *fb,
333 struct msm_gem_address_space *aspace);
334void msm_framebuffer_cleanup(struct drm_framebuffer *fb,
335 struct msm_gem_address_space *aspace);
336uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb,
337 struct msm_gem_address_space *aspace, int plane);
338struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
339const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
340struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
341 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);
342struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev,
343 int w, int h, int p, uint32_t format);
344
345struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
346void msm_fbdev_free(struct drm_device *dev);
347
348struct hdmi;
349int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
350 struct drm_encoder *encoder);
351void __init msm_hdmi_register(void);
352void __exit msm_hdmi_unregister(void);
353
354struct msm_edp;
355void __init msm_edp_register(void);
356void __exit msm_edp_unregister(void);
357int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
358 struct drm_encoder *encoder);
359
360struct msm_dsi;
361#ifdef CONFIG_DRM_MSM_DSI
362void __init msm_dsi_register(void);
363void __exit msm_dsi_unregister(void);
364int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
365 struct drm_encoder *encoder);
366#else
367static inline void __init msm_dsi_register(void)
368{
369}
370static inline void __exit msm_dsi_unregister(void)
371{
372}
373static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
374 struct drm_device *dev,
375 struct drm_encoder *encoder)
376{
377 return -EINVAL;
378}
379#endif
380
381void __init msm_mdp_register(void);
382void __exit msm_mdp_unregister(void);
383void __init msm_dpu_register(void);
384void __exit msm_dpu_unregister(void);
385
386#ifdef CONFIG_DEBUG_FS
387void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
388void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
389void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
390int msm_debugfs_late_init(struct drm_device *dev);
391int msm_rd_debugfs_init(struct drm_minor *minor);
392void msm_rd_debugfs_cleanup(struct msm_drm_private *priv);
393__printf(3, 4)
394void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
395 const char *fmt, ...);
396int msm_perf_debugfs_init(struct drm_minor *minor);
397void msm_perf_debugfs_cleanup(struct msm_drm_private *priv);
398#else
399static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
400__printf(3, 4)
401static inline void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
402 const char *fmt, ...) {}
403static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {}
404static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {}
405#endif
406
407struct clk *msm_clk_get(struct platform_device *pdev, const char *name);
408
409struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
410 const char *name);
411void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
412 const char *dbgname);
413void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
414 const char *dbgname);
415void msm_writel(u32 data, void __iomem *addr);
416u32 msm_readl(const void __iomem *addr);
417
418struct msm_gpu_submitqueue;
419int msm_submitqueue_init(struct drm_device *drm, struct msm_file_private *ctx);
420struct msm_gpu_submitqueue *msm_submitqueue_get(struct msm_file_private *ctx,
421 u32 id);
422int msm_submitqueue_create(struct drm_device *drm, struct msm_file_private *ctx,
423 u32 prio, u32 flags, u32 *id);
424int msm_submitqueue_query(struct drm_device *drm, struct msm_file_private *ctx,
425 struct drm_msm_submitqueue_query *args);
426int msm_submitqueue_remove(struct msm_file_private *ctx, u32 id);
427void msm_submitqueue_close(struct msm_file_private *ctx);
428
429void msm_submitqueue_destroy(struct kref *kref);
430
431
432#define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
433#define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__)
434
435static inline int align_pitch(int width, int bpp)
436{
437 int bytespp = (bpp + 7) / 8;
438 /* adreno needs pitch aligned to 32 pixels: */
439 return bytespp * ALIGN(width, 32);
440}
441
442/* for the generated headers: */
443#define INVALID_IDX(idx) ({BUG(); 0;})
444#define fui(x) ({BUG(); 0;})
445#define util_float_to_half(x) ({BUG(); 0;})
446
447
448#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
449
450/* for conditionally setting boolean flag(s): */
451#define COND(bool, val) ((bool) ? (val) : 0)
452
453static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
454{
455 ktime_t now = ktime_get();
456 unsigned long remaining_jiffies;
457
458 if (ktime_compare(*timeout, now) < 0) {
459 remaining_jiffies = 0;
460 } else {
461 ktime_t rem = ktime_sub(*timeout, now);
462 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ);
463 }
464
465 return remaining_jiffies;
466}
467
468#endif /* __MSM_DRV_H__ */