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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2016,2017 IBM Corporation.
4 */
5
6#define pr_fmt(fmt) "xive: " fmt
7
8#include <linux/types.h>
9#include <linux/threads.h>
10#include <linux/kernel.h>
11#include <linux/irq.h>
12#include <linux/debugfs.h>
13#include <linux/smp.h>
14#include <linux/interrupt.h>
15#include <linux/seq_file.h>
16#include <linux/init.h>
17#include <linux/cpu.h>
18#include <linux/of.h>
19#include <linux/slab.h>
20#include <linux/spinlock.h>
21#include <linux/msi.h>
22#include <linux/vmalloc.h>
23
24#include <asm/debugfs.h>
25#include <asm/prom.h>
26#include <asm/io.h>
27#include <asm/smp.h>
28#include <asm/machdep.h>
29#include <asm/irq.h>
30#include <asm/errno.h>
31#include <asm/xive.h>
32#include <asm/xive-regs.h>
33#include <asm/xmon.h>
34
35#include "xive-internal.h"
36
37#undef DEBUG_FLUSH
38#undef DEBUG_ALL
39
40#ifdef DEBUG_ALL
41#define DBG_VERBOSE(fmt, ...) pr_devel("cpu %d - " fmt, \
42 smp_processor_id(), ## __VA_ARGS__)
43#else
44#define DBG_VERBOSE(fmt...) do { } while(0)
45#endif
46
47bool __xive_enabled;
48EXPORT_SYMBOL_GPL(__xive_enabled);
49bool xive_cmdline_disabled;
50
51/* We use only one priority for now */
52static u8 xive_irq_priority;
53
54/* TIMA exported to KVM */
55void __iomem *xive_tima;
56EXPORT_SYMBOL_GPL(xive_tima);
57u32 xive_tima_offset;
58
59/* Backend ops */
60static const struct xive_ops *xive_ops;
61
62/* Our global interrupt domain */
63static struct irq_domain *xive_irq_domain;
64
65#ifdef CONFIG_SMP
66/* The IPIs all use the same logical irq number */
67static u32 xive_ipi_irq;
68#endif
69
70/* Xive state for each CPU */
71static DEFINE_PER_CPU(struct xive_cpu *, xive_cpu);
72
73/* An invalid CPU target */
74#define XIVE_INVALID_TARGET (-1)
75
76/*
77 * Read the next entry in a queue, return its content if it's valid
78 * or 0 if there is no new entry.
79 *
80 * The queue pointer is moved forward unless "just_peek" is set
81 */
82static u32 xive_read_eq(struct xive_q *q, bool just_peek)
83{
84 u32 cur;
85
86 if (!q->qpage)
87 return 0;
88 cur = be32_to_cpup(q->qpage + q->idx);
89
90 /* Check valid bit (31) vs current toggle polarity */
91 if ((cur >> 31) == q->toggle)
92 return 0;
93
94 /* If consuming from the queue ... */
95 if (!just_peek) {
96 /* Next entry */
97 q->idx = (q->idx + 1) & q->msk;
98
99 /* Wrap around: flip valid toggle */
100 if (q->idx == 0)
101 q->toggle ^= 1;
102 }
103 /* Mask out the valid bit (31) */
104 return cur & 0x7fffffff;
105}
106
107/*
108 * Scans all the queue that may have interrupts in them
109 * (based on "pending_prio") in priority order until an
110 * interrupt is found or all the queues are empty.
111 *
112 * Then updates the CPPR (Current Processor Priority
113 * Register) based on the most favored interrupt found
114 * (0xff if none) and return what was found (0 if none).
115 *
116 * If just_peek is set, return the most favored pending
117 * interrupt if any but don't update the queue pointers.
118 *
119 * Note: This function can operate generically on any number
120 * of queues (up to 8). The current implementation of the XIVE
121 * driver only uses a single queue however.
122 *
123 * Note2: This will also "flush" "the pending_count" of a queue
124 * into the "count" when that queue is observed to be empty.
125 * This is used to keep track of the amount of interrupts
126 * targetting a queue. When an interrupt is moved away from
127 * a queue, we only decrement that queue count once the queue
128 * has been observed empty to avoid races.
129 */
130static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek)
131{
132 u32 irq = 0;
133 u8 prio = 0;
134
135 /* Find highest pending priority */
136 while (xc->pending_prio != 0) {
137 struct xive_q *q;
138
139 prio = ffs(xc->pending_prio) - 1;
140 DBG_VERBOSE("scan_irq: trying prio %d\n", prio);
141
142 /* Try to fetch */
143 irq = xive_read_eq(&xc->queue[prio], just_peek);
144
145 /* Found something ? That's it */
146 if (irq) {
147 if (just_peek || irq_to_desc(irq))
148 break;
149 /*
150 * We should never get here; if we do then we must
151 * have failed to synchronize the interrupt properly
152 * when shutting it down.
153 */
154 pr_crit("xive: got interrupt %d without descriptor, dropping\n",
155 irq);
156 WARN_ON(1);
157 continue;
158 }
159
160 /* Clear pending bits */
161 xc->pending_prio &= ~(1 << prio);
162
163 /*
164 * Check if the queue count needs adjusting due to
165 * interrupts being moved away. See description of
166 * xive_dec_target_count()
167 */
168 q = &xc->queue[prio];
169 if (atomic_read(&q->pending_count)) {
170 int p = atomic_xchg(&q->pending_count, 0);
171 if (p) {
172 WARN_ON(p > atomic_read(&q->count));
173 atomic_sub(p, &q->count);
174 }
175 }
176 }
177
178 /* If nothing was found, set CPPR to 0xff */
179 if (irq == 0)
180 prio = 0xff;
181
182 /* Update HW CPPR to match if necessary */
183 if (prio != xc->cppr) {
184 DBG_VERBOSE("scan_irq: adjusting CPPR to %d\n", prio);
185 xc->cppr = prio;
186 out_8(xive_tima + xive_tima_offset + TM_CPPR, prio);
187 }
188
189 return irq;
190}
191
192/*
193 * This is used to perform the magic loads from an ESB
194 * described in xive-regs.h
195 */
196static notrace u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)
197{
198 u64 val;
199
200 if (offset == XIVE_ESB_SET_PQ_10 && xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
201 offset |= XIVE_ESB_LD_ST_MO;
202
203 /* Handle HW errata */
204 if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
205 offset |= offset << 4;
206
207 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
208 val = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);
209 else
210 val = in_be64(xd->eoi_mmio + offset);
211
212 return (u8)val;
213}
214
215static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)
216{
217 /* Handle HW errata */
218 if (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)
219 offset |= offset << 4;
220
221 if ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)
222 xive_ops->esb_rw(xd->hw_irq, offset, data, 1);
223 else
224 out_be64(xd->eoi_mmio + offset, data);
225}
226
227#ifdef CONFIG_XMON
228static notrace void xive_dump_eq(const char *name, struct xive_q *q)
229{
230 u32 i0, i1, idx;
231
232 if (!q->qpage)
233 return;
234 idx = q->idx;
235 i0 = be32_to_cpup(q->qpage + idx);
236 idx = (idx + 1) & q->msk;
237 i1 = be32_to_cpup(q->qpage + idx);
238 xmon_printf("%s idx=%d T=%d %08x %08x ...", name,
239 q->idx, q->toggle, i0, i1);
240}
241
242notrace void xmon_xive_do_dump(int cpu)
243{
244 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
245
246 xmon_printf("CPU %d:", cpu);
247 if (xc) {
248 xmon_printf("pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr);
249
250#ifdef CONFIG_SMP
251 {
252 u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET);
253
254 xmon_printf("IPI=0x%08x PQ=%c%c ", xc->hw_ipi,
255 val & XIVE_ESB_VAL_P ? 'P' : '-',
256 val & XIVE_ESB_VAL_Q ? 'Q' : '-');
257 }
258#endif
259 xive_dump_eq("EQ", &xc->queue[xive_irq_priority]);
260 }
261 xmon_printf("\n");
262}
263
264int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d)
265{
266 struct irq_chip *chip = irq_data_get_irq_chip(d);
267 int rc;
268 u32 target;
269 u8 prio;
270 u32 lirq;
271
272 if (!is_xive_irq(chip))
273 return -EINVAL;
274
275 rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
276 if (rc) {
277 xmon_printf("IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);
278 return rc;
279 }
280
281 xmon_printf("IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",
282 hw_irq, target, prio, lirq);
283
284 if (d) {
285 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
286 u64 val = xive_esb_read(xd, XIVE_ESB_GET);
287
288 xmon_printf("flags=%c%c%c PQ=%c%c",
289 xd->flags & XIVE_IRQ_FLAG_STORE_EOI ? 'S' : ' ',
290 xd->flags & XIVE_IRQ_FLAG_LSI ? 'L' : ' ',
291 xd->flags & XIVE_IRQ_FLAG_H_INT_ESB ? 'H' : ' ',
292 val & XIVE_ESB_VAL_P ? 'P' : '-',
293 val & XIVE_ESB_VAL_Q ? 'Q' : '-');
294 }
295
296 xmon_printf("\n");
297 return 0;
298}
299
300#endif /* CONFIG_XMON */
301
302static unsigned int xive_get_irq(void)
303{
304 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
305 u32 irq;
306
307 /*
308 * This can be called either as a result of a HW interrupt or
309 * as a "replay" because EOI decided there was still something
310 * in one of the queues.
311 *
312 * First we perform an ACK cycle in order to update our mask
313 * of pending priorities. This will also have the effect of
314 * updating the CPPR to the most favored pending interrupts.
315 *
316 * In the future, if we have a way to differentiate a first
317 * entry (on HW interrupt) from a replay triggered by EOI,
318 * we could skip this on replays unless we soft-mask tells us
319 * that a new HW interrupt occurred.
320 */
321 xive_ops->update_pending(xc);
322
323 DBG_VERBOSE("get_irq: pending=%02x\n", xc->pending_prio);
324
325 /* Scan our queue(s) for interrupts */
326 irq = xive_scan_interrupts(xc, false);
327
328 DBG_VERBOSE("get_irq: got irq 0x%x, new pending=0x%02x\n",
329 irq, xc->pending_prio);
330
331 /* Return pending interrupt if any */
332 if (irq == XIVE_BAD_IRQ)
333 return 0;
334 return irq;
335}
336
337/*
338 * After EOI'ing an interrupt, we need to re-check the queue
339 * to see if another interrupt is pending since multiple
340 * interrupts can coalesce into a single notification to the
341 * CPU.
342 *
343 * If we find that there is indeed more in there, we call
344 * force_external_irq_replay() to make Linux synthetize an
345 * external interrupt on the next call to local_irq_restore().
346 */
347static void xive_do_queue_eoi(struct xive_cpu *xc)
348{
349 if (xive_scan_interrupts(xc, true) != 0) {
350 DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio);
351 force_external_irq_replay();
352 }
353}
354
355/*
356 * EOI an interrupt at the source. There are several methods
357 * to do this depending on the HW version and source type
358 */
359static void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd)
360{
361 xd->stale_p = false;
362 /* If the XIVE supports the new "store EOI facility, use it */
363 if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
364 xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);
365 else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) {
366 /*
367 * The FW told us to call it. This happens for some
368 * interrupt sources that need additional HW whacking
369 * beyond the ESB manipulation. For example LPC interrupts
370 * on P9 DD1.0 needed a latch to be clared in the LPC bridge
371 * itself. The Firmware will take care of it.
372 */
373 if (WARN_ON_ONCE(!xive_ops->eoi))
374 return;
375 xive_ops->eoi(hw_irq);
376 } else {
377 u8 eoi_val;
378
379 /*
380 * Otherwise for EOI, we use the special MMIO that does
381 * a clear of both P and Q and returns the old Q,
382 * except for LSIs where we use the "EOI cycle" special
383 * load.
384 *
385 * This allows us to then do a re-trigger if Q was set
386 * rather than synthesizing an interrupt in software
387 *
388 * For LSIs the HW EOI cycle is used rather than PQ bits,
389 * as they are automatically re-triggred in HW when still
390 * pending.
391 */
392 if (xd->flags & XIVE_IRQ_FLAG_LSI)
393 xive_esb_read(xd, XIVE_ESB_LOAD_EOI);
394 else {
395 eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
396 DBG_VERBOSE("eoi_val=%x\n", eoi_val);
397
398 /* Re-trigger if needed */
399 if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio)
400 out_be64(xd->trig_mmio, 0);
401 }
402 }
403}
404
405/* irq_chip eoi callback, called with irq descriptor lock held */
406static void xive_irq_eoi(struct irq_data *d)
407{
408 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
409 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
410
411 DBG_VERBOSE("eoi_irq: irq=%d [0x%lx] pending=%02x\n",
412 d->irq, irqd_to_hwirq(d), xc->pending_prio);
413
414 /*
415 * EOI the source if it hasn't been disabled and hasn't
416 * been passed-through to a KVM guest
417 */
418 if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d) &&
419 !(xd->flags & XIVE_IRQ_NO_EOI))
420 xive_do_source_eoi(irqd_to_hwirq(d), xd);
421 else
422 xd->stale_p = true;
423
424 /*
425 * Clear saved_p to indicate that it's no longer occupying
426 * a queue slot on the target queue
427 */
428 xd->saved_p = false;
429
430 /* Check for more work in the queue */
431 xive_do_queue_eoi(xc);
432}
433
434/*
435 * Helper used to mask and unmask an interrupt source. This
436 * is only called for normal interrupts that do not require
437 * masking/unmasking via firmware.
438 */
439static void xive_do_source_set_mask(struct xive_irq_data *xd,
440 bool mask)
441{
442 u64 val;
443
444 /*
445 * If the interrupt had P set, it may be in a queue.
446 *
447 * We need to make sure we don't re-enable it until it
448 * has been fetched from that queue and EOId. We keep
449 * a copy of that P state and use it to restore the
450 * ESB accordingly on unmask.
451 */
452 if (mask) {
453 val = xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
454 if (!xd->stale_p && !!(val & XIVE_ESB_VAL_P))
455 xd->saved_p = true;
456 xd->stale_p = false;
457 } else if (xd->saved_p) {
458 xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
459 xd->saved_p = false;
460 } else {
461 xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
462 xd->stale_p = false;
463 }
464}
465
466/*
467 * Try to chose "cpu" as a new interrupt target. Increments
468 * the queue accounting for that target if it's not already
469 * full.
470 */
471static bool xive_try_pick_target(int cpu)
472{
473 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
474 struct xive_q *q = &xc->queue[xive_irq_priority];
475 int max;
476
477 /*
478 * Calculate max number of interrupts in that queue.
479 *
480 * We leave a gap of 1 just in case...
481 */
482 max = (q->msk + 1) - 1;
483 return !!atomic_add_unless(&q->count, 1, max);
484}
485
486/*
487 * Un-account an interrupt for a target CPU. We don't directly
488 * decrement q->count since the interrupt might still be present
489 * in the queue.
490 *
491 * Instead increment a separate counter "pending_count" which
492 * will be substracted from "count" later when that CPU observes
493 * the queue to be empty.
494 */
495static void xive_dec_target_count(int cpu)
496{
497 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
498 struct xive_q *q = &xc->queue[xive_irq_priority];
499
500 if (WARN_ON(cpu < 0 || !xc)) {
501 pr_err("%s: cpu=%d xc=%p\n", __func__, cpu, xc);
502 return;
503 }
504
505 /*
506 * We increment the "pending count" which will be used
507 * to decrement the target queue count whenever it's next
508 * processed and found empty. This ensure that we don't
509 * decrement while we still have the interrupt there
510 * occupying a slot.
511 */
512 atomic_inc(&q->pending_count);
513}
514
515/* Find a tentative CPU target in a CPU mask */
516static int xive_find_target_in_mask(const struct cpumask *mask,
517 unsigned int fuzz)
518{
519 int cpu, first, num, i;
520
521 /* Pick up a starting point CPU in the mask based on fuzz */
522 num = min_t(int, cpumask_weight(mask), nr_cpu_ids);
523 first = fuzz % num;
524
525 /* Locate it */
526 cpu = cpumask_first(mask);
527 for (i = 0; i < first && cpu < nr_cpu_ids; i++)
528 cpu = cpumask_next(cpu, mask);
529
530 /* Sanity check */
531 if (WARN_ON(cpu >= nr_cpu_ids))
532 cpu = cpumask_first(cpu_online_mask);
533
534 /* Remember first one to handle wrap-around */
535 first = cpu;
536
537 /*
538 * Now go through the entire mask until we find a valid
539 * target.
540 */
541 do {
542 /*
543 * We re-check online as the fallback case passes us
544 * an untested affinity mask
545 */
546 if (cpu_online(cpu) && xive_try_pick_target(cpu))
547 return cpu;
548 cpu = cpumask_next(cpu, mask);
549 /* Wrap around */
550 if (cpu >= nr_cpu_ids)
551 cpu = cpumask_first(mask);
552 } while (cpu != first);
553
554 return -1;
555}
556
557/*
558 * Pick a target CPU for an interrupt. This is done at
559 * startup or if the affinity is changed in a way that
560 * invalidates the current target.
561 */
562static int xive_pick_irq_target(struct irq_data *d,
563 const struct cpumask *affinity)
564{
565 static unsigned int fuzz;
566 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
567 cpumask_var_t mask;
568 int cpu = -1;
569
570 /*
571 * If we have chip IDs, first we try to build a mask of
572 * CPUs matching the CPU and find a target in there
573 */
574 if (xd->src_chip != XIVE_INVALID_CHIP_ID &&
575 zalloc_cpumask_var(&mask, GFP_ATOMIC)) {
576 /* Build a mask of matching chip IDs */
577 for_each_cpu_and(cpu, affinity, cpu_online_mask) {
578 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
579 if (xc->chip_id == xd->src_chip)
580 cpumask_set_cpu(cpu, mask);
581 }
582 /* Try to find a target */
583 if (cpumask_empty(mask))
584 cpu = -1;
585 else
586 cpu = xive_find_target_in_mask(mask, fuzz++);
587 free_cpumask_var(mask);
588 if (cpu >= 0)
589 return cpu;
590 fuzz--;
591 }
592
593 /* No chip IDs, fallback to using the affinity mask */
594 return xive_find_target_in_mask(affinity, fuzz++);
595}
596
597static unsigned int xive_irq_startup(struct irq_data *d)
598{
599 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
600 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
601 int target, rc;
602
603 xd->saved_p = false;
604 xd->stale_p = false;
605 pr_devel("xive_irq_startup: irq %d [0x%x] data @%p\n",
606 d->irq, hw_irq, d);
607
608#ifdef CONFIG_PCI_MSI
609 /*
610 * The generic MSI code returns with the interrupt disabled on the
611 * card, using the MSI mask bits. Firmware doesn't appear to unmask
612 * at that level, so we do it here by hand.
613 */
614 if (irq_data_get_msi_desc(d))
615 pci_msi_unmask_irq(d);
616#endif
617
618 /* Pick a target */
619 target = xive_pick_irq_target(d, irq_data_get_affinity_mask(d));
620 if (target == XIVE_INVALID_TARGET) {
621 /* Try again breaking affinity */
622 target = xive_pick_irq_target(d, cpu_online_mask);
623 if (target == XIVE_INVALID_TARGET)
624 return -ENXIO;
625 pr_warn("irq %d started with broken affinity\n", d->irq);
626 }
627
628 /* Sanity check */
629 if (WARN_ON(target == XIVE_INVALID_TARGET ||
630 target >= nr_cpu_ids))
631 target = smp_processor_id();
632
633 xd->target = target;
634
635 /*
636 * Configure the logical number to be the Linux IRQ number
637 * and set the target queue
638 */
639 rc = xive_ops->configure_irq(hw_irq,
640 get_hard_smp_processor_id(target),
641 xive_irq_priority, d->irq);
642 if (rc)
643 return rc;
644
645 /* Unmask the ESB */
646 xive_do_source_set_mask(xd, false);
647
648 return 0;
649}
650
651/* called with irq descriptor lock held */
652static void xive_irq_shutdown(struct irq_data *d)
653{
654 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
655 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
656
657 pr_devel("xive_irq_shutdown: irq %d [0x%x] data @%p\n",
658 d->irq, hw_irq, d);
659
660 if (WARN_ON(xd->target == XIVE_INVALID_TARGET))
661 return;
662
663 /* Mask the interrupt at the source */
664 xive_do_source_set_mask(xd, true);
665
666 /*
667 * Mask the interrupt in HW in the IVT/EAS and set the number
668 * to be the "bad" IRQ number
669 */
670 xive_ops->configure_irq(hw_irq,
671 get_hard_smp_processor_id(xd->target),
672 0xff, XIVE_BAD_IRQ);
673
674 xive_dec_target_count(xd->target);
675 xd->target = XIVE_INVALID_TARGET;
676}
677
678static void xive_irq_unmask(struct irq_data *d)
679{
680 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
681
682 pr_devel("xive_irq_unmask: irq %d data @%p\n", d->irq, xd);
683
684 /*
685 * This is a workaround for PCI LSI problems on P9, for
686 * these, we call FW to set the mask. The problems might
687 * be fixed by P9 DD2.0, if that is the case, firmware
688 * will no longer set that flag.
689 */
690 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) {
691 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
692 xive_ops->configure_irq(hw_irq,
693 get_hard_smp_processor_id(xd->target),
694 xive_irq_priority, d->irq);
695 return;
696 }
697
698 xive_do_source_set_mask(xd, false);
699}
700
701static void xive_irq_mask(struct irq_data *d)
702{
703 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
704
705 pr_devel("xive_irq_mask: irq %d data @%p\n", d->irq, xd);
706
707 /*
708 * This is a workaround for PCI LSI problems on P9, for
709 * these, we call OPAL to set the mask. The problems might
710 * be fixed by P9 DD2.0, if that is the case, firmware
711 * will no longer set that flag.
712 */
713 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) {
714 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
715 xive_ops->configure_irq(hw_irq,
716 get_hard_smp_processor_id(xd->target),
717 0xff, d->irq);
718 return;
719 }
720
721 xive_do_source_set_mask(xd, true);
722}
723
724static int xive_irq_set_affinity(struct irq_data *d,
725 const struct cpumask *cpumask,
726 bool force)
727{
728 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
729 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
730 u32 target, old_target;
731 int rc = 0;
732
733 pr_devel("xive_irq_set_affinity: irq %d\n", d->irq);
734
735 /* Is this valid ? */
736 if (cpumask_any_and(cpumask, cpu_online_mask) >= nr_cpu_ids)
737 return -EINVAL;
738
739 /* Don't do anything if the interrupt isn't started */
740 if (!irqd_is_started(d))
741 return IRQ_SET_MASK_OK;
742
743 /*
744 * If existing target is already in the new mask, and is
745 * online then do nothing.
746 */
747 if (xd->target != XIVE_INVALID_TARGET &&
748 cpu_online(xd->target) &&
749 cpumask_test_cpu(xd->target, cpumask))
750 return IRQ_SET_MASK_OK;
751
752 /* Pick a new target */
753 target = xive_pick_irq_target(d, cpumask);
754
755 /* No target found */
756 if (target == XIVE_INVALID_TARGET)
757 return -ENXIO;
758
759 /* Sanity check */
760 if (WARN_ON(target >= nr_cpu_ids))
761 target = smp_processor_id();
762
763 old_target = xd->target;
764
765 /*
766 * Only configure the irq if it's not currently passed-through to
767 * a KVM guest
768 */
769 if (!irqd_is_forwarded_to_vcpu(d))
770 rc = xive_ops->configure_irq(hw_irq,
771 get_hard_smp_processor_id(target),
772 xive_irq_priority, d->irq);
773 if (rc < 0) {
774 pr_err("Error %d reconfiguring irq %d\n", rc, d->irq);
775 return rc;
776 }
777
778 pr_devel(" target: 0x%x\n", target);
779 xd->target = target;
780
781 /* Give up previous target */
782 if (old_target != XIVE_INVALID_TARGET)
783 xive_dec_target_count(old_target);
784
785 return IRQ_SET_MASK_OK;
786}
787
788static int xive_irq_set_type(struct irq_data *d, unsigned int flow_type)
789{
790 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
791
792 /*
793 * We only support these. This has really no effect other than setting
794 * the corresponding descriptor bits mind you but those will in turn
795 * affect the resend function when re-enabling an edge interrupt.
796 *
797 * Set set the default to edge as explained in map().
798 */
799 if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE)
800 flow_type = IRQ_TYPE_EDGE_RISING;
801
802 if (flow_type != IRQ_TYPE_EDGE_RISING &&
803 flow_type != IRQ_TYPE_LEVEL_LOW)
804 return -EINVAL;
805
806 irqd_set_trigger_type(d, flow_type);
807
808 /*
809 * Double check it matches what the FW thinks
810 *
811 * NOTE: We don't know yet if the PAPR interface will provide
812 * the LSI vs MSI information apart from the device-tree so
813 * this check might have to move into an optional backend call
814 * that is specific to the native backend
815 */
816 if ((flow_type == IRQ_TYPE_LEVEL_LOW) !=
817 !!(xd->flags & XIVE_IRQ_FLAG_LSI)) {
818 pr_warn("Interrupt %d (HW 0x%x) type mismatch, Linux says %s, FW says %s\n",
819 d->irq, (u32)irqd_to_hwirq(d),
820 (flow_type == IRQ_TYPE_LEVEL_LOW) ? "Level" : "Edge",
821 (xd->flags & XIVE_IRQ_FLAG_LSI) ? "Level" : "Edge");
822 }
823
824 return IRQ_SET_MASK_OK_NOCOPY;
825}
826
827static int xive_irq_retrigger(struct irq_data *d)
828{
829 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
830
831 /* This should be only for MSIs */
832 if (WARN_ON(xd->flags & XIVE_IRQ_FLAG_LSI))
833 return 0;
834
835 /*
836 * To perform a retrigger, we first set the PQ bits to
837 * 11, then perform an EOI.
838 */
839 xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
840
841 /*
842 * Note: We pass "0" to the hw_irq argument in order to
843 * avoid calling into the backend EOI code which we don't
844 * want to do in the case of a re-trigger. Backends typically
845 * only do EOI for LSIs anyway.
846 */
847 xive_do_source_eoi(0, xd);
848
849 return 1;
850}
851
852/*
853 * Caller holds the irq descriptor lock, so this won't be called
854 * concurrently with xive_get_irqchip_state on the same interrupt.
855 */
856static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state)
857{
858 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
859 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
860 int rc;
861 u8 pq;
862
863 /*
864 * We only support this on interrupts that do not require
865 * firmware calls for masking and unmasking
866 */
867 if (xd->flags & XIVE_IRQ_FLAG_MASK_FW)
868 return -EIO;
869
870 /*
871 * This is called by KVM with state non-NULL for enabling
872 * pass-through or NULL for disabling it
873 */
874 if (state) {
875 irqd_set_forwarded_to_vcpu(d);
876
877 /* Set it to PQ=10 state to prevent further sends */
878 pq = xive_esb_read(xd, XIVE_ESB_SET_PQ_10);
879 if (!xd->stale_p) {
880 xd->saved_p = !!(pq & XIVE_ESB_VAL_P);
881 xd->stale_p = !xd->saved_p;
882 }
883
884 /* No target ? nothing to do */
885 if (xd->target == XIVE_INVALID_TARGET) {
886 /*
887 * An untargetted interrupt should have been
888 * also masked at the source
889 */
890 WARN_ON(xd->saved_p);
891
892 return 0;
893 }
894
895 /*
896 * If P was set, adjust state to PQ=11 to indicate
897 * that a resend is needed for the interrupt to reach
898 * the guest. Also remember the value of P.
899 *
900 * This also tells us that it's in flight to a host queue
901 * or has already been fetched but hasn't been EOIed yet
902 * by the host. This it's potentially using up a host
903 * queue slot. This is important to know because as long
904 * as this is the case, we must not hard-unmask it when
905 * "returning" that interrupt to the host.
906 *
907 * This saved_p is cleared by the host EOI, when we know
908 * for sure the queue slot is no longer in use.
909 */
910 if (xd->saved_p) {
911 xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
912
913 /*
914 * Sync the XIVE source HW to ensure the interrupt
915 * has gone through the EAS before we change its
916 * target to the guest. That should guarantee us
917 * that we *will* eventually get an EOI for it on
918 * the host. Otherwise there would be a small window
919 * for P to be seen here but the interrupt going
920 * to the guest queue.
921 */
922 if (xive_ops->sync_source)
923 xive_ops->sync_source(hw_irq);
924 }
925 } else {
926 irqd_clr_forwarded_to_vcpu(d);
927
928 /* No host target ? hard mask and return */
929 if (xd->target == XIVE_INVALID_TARGET) {
930 xive_do_source_set_mask(xd, true);
931 return 0;
932 }
933
934 /*
935 * Sync the XIVE source HW to ensure the interrupt
936 * has gone through the EAS before we change its
937 * target to the host.
938 */
939 if (xive_ops->sync_source)
940 xive_ops->sync_source(hw_irq);
941
942 /*
943 * By convention we are called with the interrupt in
944 * a PQ=10 or PQ=11 state, ie, it won't fire and will
945 * have latched in Q whether there's a pending HW
946 * interrupt or not.
947 *
948 * First reconfigure the target.
949 */
950 rc = xive_ops->configure_irq(hw_irq,
951 get_hard_smp_processor_id(xd->target),
952 xive_irq_priority, d->irq);
953 if (rc)
954 return rc;
955
956 /*
957 * Then if saved_p is not set, effectively re-enable the
958 * interrupt with an EOI. If it is set, we know there is
959 * still a message in a host queue somewhere that will be
960 * EOId eventually.
961 *
962 * Note: We don't check irqd_irq_disabled(). Effectively,
963 * we *will* let the irq get through even if masked if the
964 * HW is still firing it in order to deal with the whole
965 * saved_p business properly. If the interrupt triggers
966 * while masked, the generic code will re-mask it anyway.
967 */
968 if (!xd->saved_p)
969 xive_do_source_eoi(hw_irq, xd);
970
971 }
972 return 0;
973}
974
975/* Called with irq descriptor lock held. */
976static int xive_get_irqchip_state(struct irq_data *data,
977 enum irqchip_irq_state which, bool *state)
978{
979 struct xive_irq_data *xd = irq_data_get_irq_handler_data(data);
980 u8 pq;
981
982 switch (which) {
983 case IRQCHIP_STATE_ACTIVE:
984 pq = xive_esb_read(xd, XIVE_ESB_GET);
985
986 /*
987 * The esb value being all 1's means we couldn't get
988 * the PQ state of the interrupt through mmio. It may
989 * happen, for example when querying a PHB interrupt
990 * while the PHB is in an error state. We consider the
991 * interrupt to be inactive in that case.
992 */
993 *state = (pq != XIVE_ESB_INVALID) && !xd->stale_p &&
994 (xd->saved_p || !!(pq & XIVE_ESB_VAL_P));
995 return 0;
996 default:
997 return -EINVAL;
998 }
999}
1000
1001static struct irq_chip xive_irq_chip = {
1002 .name = "XIVE-IRQ",
1003 .irq_startup = xive_irq_startup,
1004 .irq_shutdown = xive_irq_shutdown,
1005 .irq_eoi = xive_irq_eoi,
1006 .irq_mask = xive_irq_mask,
1007 .irq_unmask = xive_irq_unmask,
1008 .irq_set_affinity = xive_irq_set_affinity,
1009 .irq_set_type = xive_irq_set_type,
1010 .irq_retrigger = xive_irq_retrigger,
1011 .irq_set_vcpu_affinity = xive_irq_set_vcpu_affinity,
1012 .irq_get_irqchip_state = xive_get_irqchip_state,
1013};
1014
1015bool is_xive_irq(struct irq_chip *chip)
1016{
1017 return chip == &xive_irq_chip;
1018}
1019EXPORT_SYMBOL_GPL(is_xive_irq);
1020
1021void xive_cleanup_irq_data(struct xive_irq_data *xd)
1022{
1023 if (xd->eoi_mmio) {
1024 unmap_kernel_range((unsigned long)xd->eoi_mmio,
1025 1u << xd->esb_shift);
1026 iounmap(xd->eoi_mmio);
1027 if (xd->eoi_mmio == xd->trig_mmio)
1028 xd->trig_mmio = NULL;
1029 xd->eoi_mmio = NULL;
1030 }
1031 if (xd->trig_mmio) {
1032 unmap_kernel_range((unsigned long)xd->trig_mmio,
1033 1u << xd->esb_shift);
1034 iounmap(xd->trig_mmio);
1035 xd->trig_mmio = NULL;
1036 }
1037}
1038EXPORT_SYMBOL_GPL(xive_cleanup_irq_data);
1039
1040static int xive_irq_alloc_data(unsigned int virq, irq_hw_number_t hw)
1041{
1042 struct xive_irq_data *xd;
1043 int rc;
1044
1045 xd = kzalloc(sizeof(struct xive_irq_data), GFP_KERNEL);
1046 if (!xd)
1047 return -ENOMEM;
1048 rc = xive_ops->populate_irq_data(hw, xd);
1049 if (rc) {
1050 kfree(xd);
1051 return rc;
1052 }
1053 xd->target = XIVE_INVALID_TARGET;
1054 irq_set_handler_data(virq, xd);
1055
1056 /*
1057 * Turn OFF by default the interrupt being mapped. A side
1058 * effect of this check is the mapping the ESB page of the
1059 * interrupt in the Linux address space. This prevents page
1060 * fault issues in the crash handler which masks all
1061 * interrupts.
1062 */
1063 xive_esb_read(xd, XIVE_ESB_SET_PQ_01);
1064
1065 return 0;
1066}
1067
1068static void xive_irq_free_data(unsigned int virq)
1069{
1070 struct xive_irq_data *xd = irq_get_handler_data(virq);
1071
1072 if (!xd)
1073 return;
1074 irq_set_handler_data(virq, NULL);
1075 xive_cleanup_irq_data(xd);
1076 kfree(xd);
1077}
1078
1079#ifdef CONFIG_SMP
1080
1081static void xive_cause_ipi(int cpu)
1082{
1083 struct xive_cpu *xc;
1084 struct xive_irq_data *xd;
1085
1086 xc = per_cpu(xive_cpu, cpu);
1087
1088 DBG_VERBOSE("IPI CPU %d -> %d (HW IRQ 0x%x)\n",
1089 smp_processor_id(), cpu, xc->hw_ipi);
1090
1091 xd = &xc->ipi_data;
1092 if (WARN_ON(!xd->trig_mmio))
1093 return;
1094 out_be64(xd->trig_mmio, 0);
1095}
1096
1097static irqreturn_t xive_muxed_ipi_action(int irq, void *dev_id)
1098{
1099 return smp_ipi_demux();
1100}
1101
1102static void xive_ipi_eoi(struct irq_data *d)
1103{
1104 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1105
1106 /* Handle possible race with unplug and drop stale IPIs */
1107 if (!xc)
1108 return;
1109
1110 DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n",
1111 d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio);
1112
1113 xive_do_source_eoi(xc->hw_ipi, &xc->ipi_data);
1114 xive_do_queue_eoi(xc);
1115}
1116
1117static void xive_ipi_do_nothing(struct irq_data *d)
1118{
1119 /*
1120 * Nothing to do, we never mask/unmask IPIs, but the callback
1121 * has to exist for the struct irq_chip.
1122 */
1123}
1124
1125static struct irq_chip xive_ipi_chip = {
1126 .name = "XIVE-IPI",
1127 .irq_eoi = xive_ipi_eoi,
1128 .irq_mask = xive_ipi_do_nothing,
1129 .irq_unmask = xive_ipi_do_nothing,
1130};
1131
1132static void __init xive_request_ipi(void)
1133{
1134 unsigned int virq;
1135
1136 /*
1137 * Initialization failed, move on, we might manage to
1138 * reach the point where we display our errors before
1139 * the system falls appart
1140 */
1141 if (!xive_irq_domain)
1142 return;
1143
1144 /* Initialize it */
1145 virq = irq_create_mapping(xive_irq_domain, 0);
1146 xive_ipi_irq = virq;
1147
1148 WARN_ON(request_irq(virq, xive_muxed_ipi_action,
1149 IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL));
1150}
1151
1152static int xive_setup_cpu_ipi(unsigned int cpu)
1153{
1154 struct xive_cpu *xc;
1155 int rc;
1156
1157 pr_debug("Setting up IPI for CPU %d\n", cpu);
1158
1159 xc = per_cpu(xive_cpu, cpu);
1160
1161 /* Check if we are already setup */
1162 if (xc->hw_ipi != XIVE_BAD_IRQ)
1163 return 0;
1164
1165 /* Grab an IPI from the backend, this will populate xc->hw_ipi */
1166 if (xive_ops->get_ipi(cpu, xc))
1167 return -EIO;
1168
1169 /*
1170 * Populate the IRQ data in the xive_cpu structure and
1171 * configure the HW / enable the IPIs.
1172 */
1173 rc = xive_ops->populate_irq_data(xc->hw_ipi, &xc->ipi_data);
1174 if (rc) {
1175 pr_err("Failed to populate IPI data on CPU %d\n", cpu);
1176 return -EIO;
1177 }
1178 rc = xive_ops->configure_irq(xc->hw_ipi,
1179 get_hard_smp_processor_id(cpu),
1180 xive_irq_priority, xive_ipi_irq);
1181 if (rc) {
1182 pr_err("Failed to map IPI CPU %d\n", cpu);
1183 return -EIO;
1184 }
1185 pr_devel("CPU %d HW IPI %x, virq %d, trig_mmio=%p\n", cpu,
1186 xc->hw_ipi, xive_ipi_irq, xc->ipi_data.trig_mmio);
1187
1188 /* Unmask it */
1189 xive_do_source_set_mask(&xc->ipi_data, false);
1190
1191 return 0;
1192}
1193
1194static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc)
1195{
1196 /* Disable the IPI and free the IRQ data */
1197
1198 /* Already cleaned up ? */
1199 if (xc->hw_ipi == XIVE_BAD_IRQ)
1200 return;
1201
1202 /* Mask the IPI */
1203 xive_do_source_set_mask(&xc->ipi_data, true);
1204
1205 /*
1206 * Note: We don't call xive_cleanup_irq_data() to free
1207 * the mappings as this is called from an IPI on kexec
1208 * which is not a safe environment to call iounmap()
1209 */
1210
1211 /* Deconfigure/mask in the backend */
1212 xive_ops->configure_irq(xc->hw_ipi, hard_smp_processor_id(),
1213 0xff, xive_ipi_irq);
1214
1215 /* Free the IPIs in the backend */
1216 xive_ops->put_ipi(cpu, xc);
1217}
1218
1219void __init xive_smp_probe(void)
1220{
1221 smp_ops->cause_ipi = xive_cause_ipi;
1222
1223 /* Register the IPI */
1224 xive_request_ipi();
1225
1226 /* Allocate and setup IPI for the boot CPU */
1227 xive_setup_cpu_ipi(smp_processor_id());
1228}
1229
1230#endif /* CONFIG_SMP */
1231
1232static int xive_irq_domain_map(struct irq_domain *h, unsigned int virq,
1233 irq_hw_number_t hw)
1234{
1235 int rc;
1236
1237 /*
1238 * Mark interrupts as edge sensitive by default so that resend
1239 * actually works. Will fix that up below if needed.
1240 */
1241 irq_clear_status_flags(virq, IRQ_LEVEL);
1242
1243#ifdef CONFIG_SMP
1244 /* IPIs are special and come up with HW number 0 */
1245 if (hw == 0) {
1246 /*
1247 * IPIs are marked per-cpu. We use separate HW interrupts under
1248 * the hood but associated with the same "linux" interrupt
1249 */
1250 irq_set_chip_and_handler(virq, &xive_ipi_chip,
1251 handle_percpu_irq);
1252 return 0;
1253 }
1254#endif
1255
1256 rc = xive_irq_alloc_data(virq, hw);
1257 if (rc)
1258 return rc;
1259
1260 irq_set_chip_and_handler(virq, &xive_irq_chip, handle_fasteoi_irq);
1261
1262 return 0;
1263}
1264
1265static void xive_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
1266{
1267 struct irq_data *data = irq_get_irq_data(virq);
1268 unsigned int hw_irq;
1269
1270 /* XXX Assign BAD number */
1271 if (!data)
1272 return;
1273 hw_irq = (unsigned int)irqd_to_hwirq(data);
1274 if (hw_irq)
1275 xive_irq_free_data(virq);
1276}
1277
1278static int xive_irq_domain_xlate(struct irq_domain *h, struct device_node *ct,
1279 const u32 *intspec, unsigned int intsize,
1280 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1281
1282{
1283 *out_hwirq = intspec[0];
1284
1285 /*
1286 * If intsize is at least 2, we look for the type in the second cell,
1287 * we assume the LSB indicates a level interrupt.
1288 */
1289 if (intsize > 1) {
1290 if (intspec[1] & 1)
1291 *out_flags = IRQ_TYPE_LEVEL_LOW;
1292 else
1293 *out_flags = IRQ_TYPE_EDGE_RISING;
1294 } else
1295 *out_flags = IRQ_TYPE_LEVEL_LOW;
1296
1297 return 0;
1298}
1299
1300static int xive_irq_domain_match(struct irq_domain *h, struct device_node *node,
1301 enum irq_domain_bus_token bus_token)
1302{
1303 return xive_ops->match(node);
1304}
1305
1306static const struct irq_domain_ops xive_irq_domain_ops = {
1307 .match = xive_irq_domain_match,
1308 .map = xive_irq_domain_map,
1309 .unmap = xive_irq_domain_unmap,
1310 .xlate = xive_irq_domain_xlate,
1311};
1312
1313static void __init xive_init_host(void)
1314{
1315 xive_irq_domain = irq_domain_add_nomap(NULL, XIVE_MAX_IRQ,
1316 &xive_irq_domain_ops, NULL);
1317 if (WARN_ON(xive_irq_domain == NULL))
1318 return;
1319 irq_set_default_host(xive_irq_domain);
1320}
1321
1322static void xive_cleanup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1323{
1324 if (xc->queue[xive_irq_priority].qpage)
1325 xive_ops->cleanup_queue(cpu, xc, xive_irq_priority);
1326}
1327
1328static int xive_setup_cpu_queues(unsigned int cpu, struct xive_cpu *xc)
1329{
1330 int rc = 0;
1331
1332 /* We setup 1 queues for now with a 64k page */
1333 if (!xc->queue[xive_irq_priority].qpage)
1334 rc = xive_ops->setup_queue(cpu, xc, xive_irq_priority);
1335
1336 return rc;
1337}
1338
1339static int xive_prepare_cpu(unsigned int cpu)
1340{
1341 struct xive_cpu *xc;
1342
1343 xc = per_cpu(xive_cpu, cpu);
1344 if (!xc) {
1345 struct device_node *np;
1346
1347 xc = kzalloc_node(sizeof(struct xive_cpu),
1348 GFP_KERNEL, cpu_to_node(cpu));
1349 if (!xc)
1350 return -ENOMEM;
1351 np = of_get_cpu_node(cpu, NULL);
1352 if (np)
1353 xc->chip_id = of_get_ibm_chip_id(np);
1354 of_node_put(np);
1355 xc->hw_ipi = XIVE_BAD_IRQ;
1356
1357 per_cpu(xive_cpu, cpu) = xc;
1358 }
1359
1360 /* Setup EQs if not already */
1361 return xive_setup_cpu_queues(cpu, xc);
1362}
1363
1364static void xive_setup_cpu(void)
1365{
1366 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1367
1368 /* The backend might have additional things to do */
1369 if (xive_ops->setup_cpu)
1370 xive_ops->setup_cpu(smp_processor_id(), xc);
1371
1372 /* Set CPPR to 0xff to enable flow of interrupts */
1373 xc->cppr = 0xff;
1374 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1375}
1376
1377#ifdef CONFIG_SMP
1378void xive_smp_setup_cpu(void)
1379{
1380 pr_devel("SMP setup CPU %d\n", smp_processor_id());
1381
1382 /* This will have already been done on the boot CPU */
1383 if (smp_processor_id() != boot_cpuid)
1384 xive_setup_cpu();
1385
1386}
1387
1388int xive_smp_prepare_cpu(unsigned int cpu)
1389{
1390 int rc;
1391
1392 /* Allocate per-CPU data and queues */
1393 rc = xive_prepare_cpu(cpu);
1394 if (rc)
1395 return rc;
1396
1397 /* Allocate and setup IPI for the new CPU */
1398 return xive_setup_cpu_ipi(cpu);
1399}
1400
1401#ifdef CONFIG_HOTPLUG_CPU
1402static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc)
1403{
1404 u32 irq;
1405
1406 /* We assume local irqs are disabled */
1407 WARN_ON(!irqs_disabled());
1408
1409 /* Check what's already in the CPU queue */
1410 while ((irq = xive_scan_interrupts(xc, false)) != 0) {
1411 /*
1412 * We need to re-route that interrupt to its new destination.
1413 * First get and lock the descriptor
1414 */
1415 struct irq_desc *desc = irq_to_desc(irq);
1416 struct irq_data *d = irq_desc_get_irq_data(desc);
1417 struct xive_irq_data *xd;
1418 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
1419
1420 /*
1421 * Ignore anything that isn't a XIVE irq and ignore
1422 * IPIs, so can just be dropped.
1423 */
1424 if (d->domain != xive_irq_domain || hw_irq == 0)
1425 continue;
1426
1427 /*
1428 * The IRQ should have already been re-routed, it's just a
1429 * stale in the old queue, so re-trigger it in order to make
1430 * it reach is new destination.
1431 */
1432#ifdef DEBUG_FLUSH
1433 pr_info("CPU %d: Got irq %d while offline, re-sending...\n",
1434 cpu, irq);
1435#endif
1436 raw_spin_lock(&desc->lock);
1437 xd = irq_desc_get_handler_data(desc);
1438
1439 /*
1440 * Clear saved_p to indicate that it's no longer pending
1441 */
1442 xd->saved_p = false;
1443
1444 /*
1445 * For LSIs, we EOI, this will cause a resend if it's
1446 * still asserted. Otherwise do an MSI retrigger.
1447 */
1448 if (xd->flags & XIVE_IRQ_FLAG_LSI)
1449 xive_do_source_eoi(irqd_to_hwirq(d), xd);
1450 else
1451 xive_irq_retrigger(d);
1452
1453 raw_spin_unlock(&desc->lock);
1454 }
1455}
1456
1457void xive_smp_disable_cpu(void)
1458{
1459 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1460 unsigned int cpu = smp_processor_id();
1461
1462 /* Migrate interrupts away from the CPU */
1463 irq_migrate_all_off_this_cpu();
1464
1465 /* Set CPPR to 0 to disable flow of interrupts */
1466 xc->cppr = 0;
1467 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1468
1469 /* Flush everything still in the queue */
1470 xive_flush_cpu_queue(cpu, xc);
1471
1472 /* Re-enable CPPR */
1473 xc->cppr = 0xff;
1474 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff);
1475}
1476
1477void xive_flush_interrupt(void)
1478{
1479 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1480 unsigned int cpu = smp_processor_id();
1481
1482 /* Called if an interrupt occurs while the CPU is hot unplugged */
1483 xive_flush_cpu_queue(cpu, xc);
1484}
1485
1486#endif /* CONFIG_HOTPLUG_CPU */
1487
1488#endif /* CONFIG_SMP */
1489
1490void xive_teardown_cpu(void)
1491{
1492 struct xive_cpu *xc = __this_cpu_read(xive_cpu);
1493 unsigned int cpu = smp_processor_id();
1494
1495 /* Set CPPR to 0 to disable flow of interrupts */
1496 xc->cppr = 0;
1497 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0);
1498
1499 if (xive_ops->teardown_cpu)
1500 xive_ops->teardown_cpu(cpu, xc);
1501
1502#ifdef CONFIG_SMP
1503 /* Get rid of IPI */
1504 xive_cleanup_cpu_ipi(cpu, xc);
1505#endif
1506
1507 /* Disable and free the queues */
1508 xive_cleanup_cpu_queues(cpu, xc);
1509}
1510
1511void xive_shutdown(void)
1512{
1513 xive_ops->shutdown();
1514}
1515
1516bool __init xive_core_init(const struct xive_ops *ops, void __iomem *area, u32 offset,
1517 u8 max_prio)
1518{
1519 xive_tima = area;
1520 xive_tima_offset = offset;
1521 xive_ops = ops;
1522 xive_irq_priority = max_prio;
1523
1524 ppc_md.get_irq = xive_get_irq;
1525 __xive_enabled = true;
1526
1527 pr_devel("Initializing host..\n");
1528 xive_init_host();
1529
1530 pr_devel("Initializing boot CPU..\n");
1531
1532 /* Allocate per-CPU data and queues */
1533 xive_prepare_cpu(smp_processor_id());
1534
1535 /* Get ready for interrupts */
1536 xive_setup_cpu();
1537
1538 pr_info("Interrupt handling initialized with %s backend\n",
1539 xive_ops->name);
1540 pr_info("Using priority %d for all interrupts\n", max_prio);
1541
1542 return true;
1543}
1544
1545__be32 *xive_queue_page_alloc(unsigned int cpu, u32 queue_shift)
1546{
1547 unsigned int alloc_order;
1548 struct page *pages;
1549 __be32 *qpage;
1550
1551 alloc_order = xive_alloc_order(queue_shift);
1552 pages = alloc_pages_node(cpu_to_node(cpu), GFP_KERNEL, alloc_order);
1553 if (!pages)
1554 return ERR_PTR(-ENOMEM);
1555 qpage = (__be32 *)page_address(pages);
1556 memset(qpage, 0, 1 << queue_shift);
1557
1558 return qpage;
1559}
1560
1561static int __init xive_off(char *arg)
1562{
1563 xive_cmdline_disabled = true;
1564 return 0;
1565}
1566__setup("xive=off", xive_off);
1567
1568void xive_debug_show_cpu(struct seq_file *m, int cpu)
1569{
1570 struct xive_cpu *xc = per_cpu(xive_cpu, cpu);
1571
1572 seq_printf(m, "CPU %d:", cpu);
1573 if (xc) {
1574 seq_printf(m, "pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr);
1575
1576#ifdef CONFIG_SMP
1577 {
1578 u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET);
1579
1580 seq_printf(m, "IPI=0x%08x PQ=%c%c ", xc->hw_ipi,
1581 val & XIVE_ESB_VAL_P ? 'P' : '-',
1582 val & XIVE_ESB_VAL_Q ? 'Q' : '-');
1583 }
1584#endif
1585 {
1586 struct xive_q *q = &xc->queue[xive_irq_priority];
1587 u32 i0, i1, idx;
1588
1589 if (q->qpage) {
1590 idx = q->idx;
1591 i0 = be32_to_cpup(q->qpage + idx);
1592 idx = (idx + 1) & q->msk;
1593 i1 = be32_to_cpup(q->qpage + idx);
1594 seq_printf(m, "EQ idx=%d T=%d %08x %08x ...",
1595 q->idx, q->toggle, i0, i1);
1596 }
1597 }
1598 }
1599 seq_puts(m, "\n");
1600}
1601
1602void xive_debug_show_irq(struct seq_file *m, u32 hw_irq, struct irq_data *d)
1603{
1604 struct irq_chip *chip = irq_data_get_irq_chip(d);
1605 int rc;
1606 u32 target;
1607 u8 prio;
1608 u32 lirq;
1609
1610 if (!is_xive_irq(chip))
1611 return;
1612
1613 rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
1614 if (rc) {
1615 seq_printf(m, "IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);
1616 return;
1617 }
1618
1619 seq_printf(m, "IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",
1620 hw_irq, target, prio, lirq);
1621
1622 if (d) {
1623 struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
1624 u64 val = xive_esb_read(xd, XIVE_ESB_GET);
1625
1626 seq_printf(m, "flags=%c%c%c PQ=%c%c",
1627 xd->flags & XIVE_IRQ_FLAG_STORE_EOI ? 'S' : ' ',
1628 xd->flags & XIVE_IRQ_FLAG_LSI ? 'L' : ' ',
1629 xd->flags & XIVE_IRQ_FLAG_H_INT_ESB ? 'H' : ' ',
1630 val & XIVE_ESB_VAL_P ? 'P' : '-',
1631 val & XIVE_ESB_VAL_Q ? 'Q' : '-');
1632 }
1633 seq_puts(m, "\n");
1634}
1635
1636static int xive_core_debug_show(struct seq_file *m, void *private)
1637{
1638 unsigned int i;
1639 struct irq_desc *desc;
1640 int cpu;
1641
1642 if (xive_ops->debug_show)
1643 xive_ops->debug_show(m, private);
1644
1645 for_each_possible_cpu(cpu)
1646 xive_debug_show_cpu(m, cpu);
1647
1648 for_each_irq_desc(i, desc) {
1649 struct irq_data *d = irq_desc_get_irq_data(desc);
1650 unsigned int hw_irq;
1651
1652 if (!d)
1653 continue;
1654
1655 hw_irq = (unsigned int)irqd_to_hwirq(d);
1656
1657 /* IPIs are special (HW number 0) */
1658 if (hw_irq)
1659 xive_debug_show_irq(m, hw_irq, d);
1660 }
1661 return 0;
1662}
1663DEFINE_SHOW_ATTRIBUTE(xive_core_debug);
1664
1665int xive_core_debug_init(void)
1666{
1667 if (xive_enabled())
1668 debugfs_create_file("xive", 0400, powerpc_debugfs_root,
1669 NULL, &xive_core_debug_fops);
1670 return 0;
1671}