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1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
8 */
9
10#include <linux/io.h>
11#include <linux/bitops.h>
12#include <linux/of_platform.h>
13#include <linux/of_address.h>
14#include <linux/of_irq.h>
15#include <linux/irqdomain.h>
16#include <linux/interrupt.h>
17
18#include <asm/irq_cpu.h>
19#include <asm/mipsregs.h>
20
21#include "common.h"
22
23/* INTC register offsets */
24#define INTC_REG_STATUS0 0x00
25#define INTC_REG_STATUS1 0x04
26#define INTC_REG_TYPE 0x20
27#define INTC_REG_RAW_STATUS 0x30
28#define INTC_REG_ENABLE 0x34
29#define INTC_REG_DISABLE 0x38
30
31#define INTC_INT_GLOBAL BIT(31)
32
33#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
34#define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4)
35#define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
36#define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
37#define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
38
39/* we have a cascade of 8 irqs */
40#define RALINK_INTC_IRQ_BASE 8
41
42/* we have 32 SoC irqs */
43#define RALINK_INTC_IRQ_COUNT 32
44
45#define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9)
46
47static void __iomem *rt_intc_membase;
48
49static inline void rt_intc_w32(u32 val, unsigned reg)
50{
51 __raw_writel(val, rt_intc_membase + reg);
52}
53
54static inline u32 rt_intc_r32(unsigned reg)
55{
56 return __raw_readl(rt_intc_membase + reg);
57}
58
59static void ralink_intc_irq_unmask(struct irq_data *d)
60{
61 rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE);
62}
63
64static void ralink_intc_irq_mask(struct irq_data *d)
65{
66 rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE);
67}
68
69static struct irq_chip ralink_intc_irq_chip = {
70 .name = "INTC",
71 .irq_unmask = ralink_intc_irq_unmask,
72 .irq_mask = ralink_intc_irq_mask,
73 .irq_mask_ack = ralink_intc_irq_mask,
74};
75
76unsigned int get_c0_compare_int(void)
77{
78 return CP0_LEGACY_COMPARE_IRQ;
79}
80
81static void ralink_intc_irq_handler(unsigned int irq, struct irq_desc *desc)
82{
83 u32 pending = rt_intc_r32(INTC_REG_STATUS0);
84
85 if (pending) {
86 struct irq_domain *domain = irq_get_handler_data(irq);
87 generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
88 } else {
89 spurious_interrupt();
90 }
91}
92
93asmlinkage void plat_irq_dispatch(void)
94{
95 unsigned long pending;
96
97 pending = read_c0_status() & read_c0_cause() & ST0_IM;
98
99 if (pending & STATUSF_IP7)
100 do_IRQ(RALINK_CPU_IRQ_COUNTER);
101
102 else if (pending & STATUSF_IP5)
103 do_IRQ(RALINK_CPU_IRQ_FE);
104
105 else if (pending & STATUSF_IP6)
106 do_IRQ(RALINK_CPU_IRQ_WIFI);
107
108 else if (pending & STATUSF_IP4)
109 do_IRQ(RALINK_CPU_IRQ_PCI);
110
111 else if (pending & STATUSF_IP2)
112 do_IRQ(RALINK_CPU_IRQ_INTC);
113
114 else
115 spurious_interrupt();
116}
117
118static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
119{
120 irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq);
121
122 return 0;
123}
124
125static const struct irq_domain_ops irq_domain_ops = {
126 .xlate = irq_domain_xlate_onecell,
127 .map = intc_map,
128};
129
130static int __init intc_of_init(struct device_node *node,
131 struct device_node *parent)
132{
133 struct resource res;
134 struct irq_domain *domain;
135 int irq;
136
137 irq = irq_of_parse_and_map(node, 0);
138 if (!irq)
139 panic("Failed to get INTC IRQ");
140
141 if (of_address_to_resource(node, 0, &res))
142 panic("Failed to get intc memory range");
143
144 if (request_mem_region(res.start, resource_size(&res),
145 res.name) < 0)
146 pr_err("Failed to request intc memory");
147
148 rt_intc_membase = ioremap_nocache(res.start,
149 resource_size(&res));
150 if (!rt_intc_membase)
151 panic("Failed to remap intc memory");
152
153 /* disable all interrupts */
154 rt_intc_w32(~0, INTC_REG_DISABLE);
155
156 /* route all INTC interrupts to MIPS HW0 interrupt */
157 rt_intc_w32(0, INTC_REG_TYPE);
158
159 domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT,
160 RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL);
161 if (!domain)
162 panic("Failed to add irqdomain");
163
164 rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
165
166 irq_set_chained_handler(irq, ralink_intc_irq_handler);
167 irq_set_handler_data(irq, domain);
168
169 /* tell the kernel which irq is used for performance monitoring */
170 cp0_perfcount_irq = irq_create_mapping(domain, 9);
171
172 return 0;
173}
174
175static struct of_device_id __initdata of_irq_ids[] = {
176 { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
177 { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
178 {},
179};
180
181void __init arch_init_irq(void)
182{
183 of_irq_init(of_irq_ids);
184}
185
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2013 John Crispin <john@phrozen.org>
6 */
7
8#include <linux/io.h>
9#include <linux/bitops.h>
10#include <linux/of_platform.h>
11#include <linux/of_address.h>
12#include <linux/of_irq.h>
13#include <linux/irqdomain.h>
14#include <linux/interrupt.h>
15
16#include <asm/irq_cpu.h>
17#include <asm/mipsregs.h>
18
19#include "common.h"
20
21#define INTC_INT_GLOBAL BIT(31)
22
23#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
24#define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4)
25#define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
26#define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
27#define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
28
29/* we have a cascade of 8 irqs */
30#define RALINK_INTC_IRQ_BASE 8
31
32/* we have 32 SoC irqs */
33#define RALINK_INTC_IRQ_COUNT 32
34
35#define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9)
36
37enum rt_intc_regs_enum {
38 INTC_REG_STATUS0 = 0,
39 INTC_REG_STATUS1,
40 INTC_REG_TYPE,
41 INTC_REG_RAW_STATUS,
42 INTC_REG_ENABLE,
43 INTC_REG_DISABLE,
44};
45
46static u32 rt_intc_regs[] = {
47 [INTC_REG_STATUS0] = 0x00,
48 [INTC_REG_STATUS1] = 0x04,
49 [INTC_REG_TYPE] = 0x20,
50 [INTC_REG_RAW_STATUS] = 0x30,
51 [INTC_REG_ENABLE] = 0x34,
52 [INTC_REG_DISABLE] = 0x38,
53};
54
55static void __iomem *rt_intc_membase;
56
57static int rt_perfcount_irq;
58
59static inline void rt_intc_w32(u32 val, unsigned reg)
60{
61 __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]);
62}
63
64static inline u32 rt_intc_r32(unsigned reg)
65{
66 return __raw_readl(rt_intc_membase + rt_intc_regs[reg]);
67}
68
69static void ralink_intc_irq_unmask(struct irq_data *d)
70{
71 rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE);
72}
73
74static void ralink_intc_irq_mask(struct irq_data *d)
75{
76 rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE);
77}
78
79static struct irq_chip ralink_intc_irq_chip = {
80 .name = "INTC",
81 .irq_unmask = ralink_intc_irq_unmask,
82 .irq_mask = ralink_intc_irq_mask,
83 .irq_mask_ack = ralink_intc_irq_mask,
84};
85
86int get_c0_perfcount_int(void)
87{
88 return rt_perfcount_irq;
89}
90EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
91
92unsigned int get_c0_compare_int(void)
93{
94 return CP0_LEGACY_COMPARE_IRQ;
95}
96
97static void ralink_intc_irq_handler(struct irq_desc *desc)
98{
99 u32 pending = rt_intc_r32(INTC_REG_STATUS0);
100
101 if (pending) {
102 struct irq_domain *domain = irq_desc_get_handler_data(desc);
103 generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
104 } else {
105 spurious_interrupt();
106 }
107}
108
109asmlinkage void plat_irq_dispatch(void)
110{
111 unsigned long pending;
112
113 pending = read_c0_status() & read_c0_cause() & ST0_IM;
114
115 if (pending & STATUSF_IP7)
116 do_IRQ(RALINK_CPU_IRQ_COUNTER);
117
118 else if (pending & STATUSF_IP5)
119 do_IRQ(RALINK_CPU_IRQ_FE);
120
121 else if (pending & STATUSF_IP6)
122 do_IRQ(RALINK_CPU_IRQ_WIFI);
123
124 else if (pending & STATUSF_IP4)
125 do_IRQ(RALINK_CPU_IRQ_PCI);
126
127 else if (pending & STATUSF_IP2)
128 do_IRQ(RALINK_CPU_IRQ_INTC);
129
130 else
131 spurious_interrupt();
132}
133
134static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
135{
136 irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq);
137
138 return 0;
139}
140
141static const struct irq_domain_ops irq_domain_ops = {
142 .xlate = irq_domain_xlate_onecell,
143 .map = intc_map,
144};
145
146static int __init intc_of_init(struct device_node *node,
147 struct device_node *parent)
148{
149 struct resource res;
150 struct irq_domain *domain;
151 int irq;
152
153 if (!of_property_read_u32_array(node, "ralink,intc-registers",
154 rt_intc_regs, 6))
155 pr_info("intc: using register map from devicetree\n");
156
157 irq = irq_of_parse_and_map(node, 0);
158 if (!irq)
159 panic("Failed to get INTC IRQ");
160
161 if (of_address_to_resource(node, 0, &res))
162 panic("Failed to get intc memory range");
163
164 if (!request_mem_region(res.start, resource_size(&res),
165 res.name))
166 pr_err("Failed to request intc memory");
167
168 rt_intc_membase = ioremap(res.start,
169 resource_size(&res));
170 if (!rt_intc_membase)
171 panic("Failed to remap intc memory");
172
173 /* disable all interrupts */
174 rt_intc_w32(~0, INTC_REG_DISABLE);
175
176 /* route all INTC interrupts to MIPS HW0 interrupt */
177 rt_intc_w32(0, INTC_REG_TYPE);
178
179 domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT,
180 RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL);
181 if (!domain)
182 panic("Failed to add irqdomain");
183
184 rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
185
186 irq_set_chained_handler_and_data(irq, ralink_intc_irq_handler, domain);
187
188 /* tell the kernel which irq is used for performance monitoring */
189 rt_perfcount_irq = irq_create_mapping(domain, 9);
190
191 return 0;
192}
193
194static struct of_device_id __initdata of_irq_ids[] = {
195 { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
196 { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
197 {},
198};
199
200void __init arch_init_irq(void)
201{
202 of_irq_init(of_irq_ids);
203}
204