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1/*
2 * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
3 * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/irq.h>
23
24#include <asm/irq_cpu.h>
25#include <asm/mipsregs.h>
26#include <asm/mach-ar7/ar7.h>
27
28#define EXCEPT_OFFSET 0x80
29#define PACE_OFFSET 0xA0
30#define CHNLS_OFFSET 0x200
31
32#define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
33#define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
34#define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */
35#define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
36#define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */
37#define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
38#define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */
39#define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
40#define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */
41#define PIR_OFFSET (0x40)
42#define MSR_OFFSET (0x44)
43#define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
44#define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
45
46#define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
47
48#define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
49
50static int ar7_irq_base;
51
52static void ar7_unmask_irq(struct irq_data *d)
53{
54 writel(1 << ((d->irq - ar7_irq_base) % 32),
55 REG(ESR_OFFSET(d->irq - ar7_irq_base)));
56}
57
58static void ar7_mask_irq(struct irq_data *d)
59{
60 writel(1 << ((d->irq - ar7_irq_base) % 32),
61 REG(ECR_OFFSET(d->irq - ar7_irq_base)));
62}
63
64static void ar7_ack_irq(struct irq_data *d)
65{
66 writel(1 << ((d->irq - ar7_irq_base) % 32),
67 REG(CR_OFFSET(d->irq - ar7_irq_base)));
68}
69
70static void ar7_unmask_sec_irq(struct irq_data *d)
71{
72 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
73}
74
75static void ar7_mask_sec_irq(struct irq_data *d)
76{
77 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
78}
79
80static void ar7_ack_sec_irq(struct irq_data *d)
81{
82 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
83}
84
85static struct irq_chip ar7_irq_type = {
86 .name = "AR7",
87 .irq_unmask = ar7_unmask_irq,
88 .irq_mask = ar7_mask_irq,
89 .irq_ack = ar7_ack_irq
90};
91
92static struct irq_chip ar7_sec_irq_type = {
93 .name = "AR7",
94 .irq_unmask = ar7_unmask_sec_irq,
95 .irq_mask = ar7_mask_sec_irq,
96 .irq_ack = ar7_ack_sec_irq,
97};
98
99static struct irqaction ar7_cascade_action = {
100 .handler = no_action,
101 .name = "AR7 cascade interrupt",
102 .flags = IRQF_NO_THREAD,
103};
104
105static void __init ar7_irq_init(int base)
106{
107 int i;
108 /*
109 * Disable interrupts and clear pending
110 */
111 writel(0xffffffff, REG(ECR_OFFSET(0)));
112 writel(0xff, REG(ECR_OFFSET(32)));
113 writel(0xffffffff, REG(SEC_ECR_OFFSET));
114 writel(0xffffffff, REG(CR_OFFSET(0)));
115 writel(0xff, REG(CR_OFFSET(32)));
116 writel(0xffffffff, REG(SEC_CR_OFFSET));
117
118 ar7_irq_base = base;
119
120 for (i = 0; i < 40; i++) {
121 writel(i, REG(CHNL_OFFSET(i)));
122 /* Primary IRQ's */
123 irq_set_chip_and_handler(base + i, &ar7_irq_type,
124 handle_level_irq);
125 /* Secondary IRQ's */
126 if (i < 32)
127 irq_set_chip_and_handler(base + i + 40,
128 &ar7_sec_irq_type,
129 handle_level_irq);
130 }
131
132 setup_irq(2, &ar7_cascade_action);
133 setup_irq(ar7_irq_base, &ar7_cascade_action);
134 set_c0_status(IE_IRQ0);
135}
136
137void __init arch_init_irq(void)
138{
139 mips_cpu_irq_init();
140 ar7_irq_init(8);
141}
142
143static void ar7_cascade(void)
144{
145 u32 status;
146 int i, irq;
147
148 /* Primary IRQ's */
149 irq = readl(REG(PIR_OFFSET)) & 0x3f;
150 if (irq) {
151 do_IRQ(ar7_irq_base + irq);
152 return;
153 }
154
155 /* Secondary IRQ's are cascaded through primary '0' */
156 writel(1, REG(CR_OFFSET(irq)));
157 status = readl(REG(SEC_SR_OFFSET));
158 for (i = 0; i < 32; i++) {
159 if (status & 1) {
160 do_IRQ(ar7_irq_base + i + 40);
161 return;
162 }
163 status >>= 1;
164 }
165
166 spurious_interrupt();
167}
168
169asmlinkage void plat_irq_dispatch(void)
170{
171 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
172 if (pending & STATUSF_IP7) /* cpu timer */
173 do_IRQ(7);
174 else if (pending & STATUSF_IP2) /* int0 hardware line */
175 ar7_cascade();
176 else
177 spurious_interrupt();
178}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
4 * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
5 */
6
7#include <linux/interrupt.h>
8#include <linux/io.h>
9#include <linux/irq.h>
10
11#include <asm/irq_cpu.h>
12#include <asm/mipsregs.h>
13#include <asm/mach-ar7/ar7.h>
14
15#define EXCEPT_OFFSET 0x80
16#define PACE_OFFSET 0xA0
17#define CHNLS_OFFSET 0x200
18
19#define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
20#define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
21#define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */
22#define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
23#define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */
24#define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
25#define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */
26#define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
27#define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */
28#define PIR_OFFSET (0x40)
29#define MSR_OFFSET (0x44)
30#define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
31#define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
32
33#define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
34
35#define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
36
37static int ar7_irq_base;
38
39static void ar7_unmask_irq(struct irq_data *d)
40{
41 writel(1 << ((d->irq - ar7_irq_base) % 32),
42 REG(ESR_OFFSET(d->irq - ar7_irq_base)));
43}
44
45static void ar7_mask_irq(struct irq_data *d)
46{
47 writel(1 << ((d->irq - ar7_irq_base) % 32),
48 REG(ECR_OFFSET(d->irq - ar7_irq_base)));
49}
50
51static void ar7_ack_irq(struct irq_data *d)
52{
53 writel(1 << ((d->irq - ar7_irq_base) % 32),
54 REG(CR_OFFSET(d->irq - ar7_irq_base)));
55}
56
57static void ar7_unmask_sec_irq(struct irq_data *d)
58{
59 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
60}
61
62static void ar7_mask_sec_irq(struct irq_data *d)
63{
64 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
65}
66
67static void ar7_ack_sec_irq(struct irq_data *d)
68{
69 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
70}
71
72static struct irq_chip ar7_irq_type = {
73 .name = "AR7",
74 .irq_unmask = ar7_unmask_irq,
75 .irq_mask = ar7_mask_irq,
76 .irq_ack = ar7_ack_irq
77};
78
79static struct irq_chip ar7_sec_irq_type = {
80 .name = "AR7",
81 .irq_unmask = ar7_unmask_sec_irq,
82 .irq_mask = ar7_mask_sec_irq,
83 .irq_ack = ar7_ack_sec_irq,
84};
85
86static void __init ar7_irq_init(int base)
87{
88 int i;
89 /*
90 * Disable interrupts and clear pending
91 */
92 writel(0xffffffff, REG(ECR_OFFSET(0)));
93 writel(0xff, REG(ECR_OFFSET(32)));
94 writel(0xffffffff, REG(SEC_ECR_OFFSET));
95 writel(0xffffffff, REG(CR_OFFSET(0)));
96 writel(0xff, REG(CR_OFFSET(32)));
97 writel(0xffffffff, REG(SEC_CR_OFFSET));
98
99 ar7_irq_base = base;
100
101 for (i = 0; i < 40; i++) {
102 writel(i, REG(CHNL_OFFSET(i)));
103 /* Primary IRQ's */
104 irq_set_chip_and_handler(base + i, &ar7_irq_type,
105 handle_level_irq);
106 /* Secondary IRQ's */
107 if (i < 32)
108 irq_set_chip_and_handler(base + i + 40,
109 &ar7_sec_irq_type,
110 handle_level_irq);
111 }
112
113 if (request_irq(2, no_action, IRQF_NO_THREAD, "AR7 cascade interrupt",
114 NULL))
115 pr_err("Failed to request irq 2 (AR7 cascade interrupt)\n");
116 if (request_irq(ar7_irq_base, no_action, IRQF_NO_THREAD,
117 "AR7 cascade interrupt", NULL)) {
118 pr_err("Failed to request irq %d (AR7 cascade interrupt)\n",
119 ar7_irq_base);
120 }
121 set_c0_status(IE_IRQ0);
122}
123
124void __init arch_init_irq(void)
125{
126 mips_cpu_irq_init();
127 ar7_irq_init(8);
128}
129
130static void ar7_cascade(void)
131{
132 u32 status;
133 int i, irq;
134
135 /* Primary IRQ's */
136 irq = readl(REG(PIR_OFFSET)) & 0x3f;
137 if (irq) {
138 do_IRQ(ar7_irq_base + irq);
139 return;
140 }
141
142 /* Secondary IRQ's are cascaded through primary '0' */
143 writel(1, REG(CR_OFFSET(irq)));
144 status = readl(REG(SEC_SR_OFFSET));
145 for (i = 0; i < 32; i++) {
146 if (status & 1) {
147 do_IRQ(ar7_irq_base + i + 40);
148 return;
149 }
150 status >>= 1;
151 }
152
153 spurious_interrupt();
154}
155
156asmlinkage void plat_irq_dispatch(void)
157{
158 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
159 if (pending & STATUSF_IP7) /* cpu timer */
160 do_IRQ(7);
161 else if (pending & STATUSF_IP2) /* int0 hardware line */
162 ar7_cascade();
163 else
164 spurious_interrupt();
165}